A cache management method, a storage array controller, an apparatus, a device and a medium

Abstract

The application relates to the technical field of storage, in particular to a cache management method, a storage array controller, an apparatus, a device and a medium. The method comprises the following steps: according to a namespace to be accessed by an access command, allocating a cache region for the access command in a static cache subspace; based on the access command, receiving target data of the storage array for reading and writing, and caching the target data to the cache region; wherein the static cache subspace is obtained by dividing a static cache space in the controller memory according to the namespace. Therefore, the application can effectively solve the problem of low data reading and writing efficiency of the storage array data caused by unreasonable cache space allocation.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a cache management method, storage array controller, device, equipment and medium. Background Art

[0002] Independent Redundant Storage Arrays (RSA) combine multiple physical hard drives into a single logical drive, providing higher storage performance than a single hard drive by accessing multiple physical drives in parallel. Furthermore, the storage array provides data redundancy protection by encoding write data using redundant computation units to generate redundant checksum information. This information is then stored in the storage array along with the original write data, enabling data recovery after a failure.

[0003] In the existing technology, the execution logic of the NVMe master is not designed based on the redundant storage array, but is only managed by a remote host. As a result, the entire data end cannot take advantage of the independent redundant storage array, resulting in a time-consuming processing process and low data processing efficiency. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a cache management method, storage array controller, apparatus, device, and medium, which can effectively solve the problem of low efficiency in reading and writing data in the storage array due to unreasonable cache space allocation.

[0005] In a first aspect, an embodiment of the present application provides a namespace-based cache management method, which is applied to a storage array controller, wherein the storage array controller includes a storage interface control module, a redundancy module, a controller memory, and a non-volatile storage control module. The method includes:

[0006] Allocating a cache area for the access command in the static cache subspace according to the namespace to be accessed by the access command;

[0007] receiving target data for reading and writing the storage array based on the access command, and caching the target data in the cache area;

[0008] The static cache subspace is obtained by dividing the static cache space in the controller memory according to the namespace.

[0009] In some embodiments, allocating a cache area for the access command in a static cache subspace according to a namespace to be accessed by the access command includes:

[0010] Obtaining a virtual logical address subspace according to the namespace matching;

[0011] assigning a target virtual logical address to the access command from the virtual logical address subspace;

[0012] The cache area is allocated to the target virtual logical address from the static cache subspace uniquely corresponding to the namespace.

[0013] In some embodiments, the static cache subspace is obtained by the following partitioning method:

[0014] The static cache space is divided according to the number of namespaces using a preset capacity allocation rule to obtain static cache subspaces corresponding to each namespace.

[0015] In some embodiments, the virtual logical address subspace is obtained by the following division method:

[0016] Mapping the storage array into a virtual logical address space according to each of the namespaces;

[0017] The virtual logical address space is divided according to the number of namespaces to obtain virtual logical address subspaces corresponding to each namespace.

[0018] In some embodiments, allocating a target virtual logical address for the access command from the virtual logical address subspace includes:

[0019] When the access command is to access any virtual logical address in a stripe, the stripe is assigned to the access command as the target virtual logical address;

[0020] The stripes are divided by the following method:

[0021] Dividing the virtual logical address subspace into a namespace array according to a redundancy mode of the storage array, wherein a row of virtual logical addresses in the namespace array serves as a stripe;

[0022] Allocating the cache area for the target virtual logical address from the static cache subspace uniquely corresponding to the namespace includes:

[0023] If the cache area is not matched according to the stripe, a cache area is allocated to the stripe from the static cache subspace corresponding to the namespace according to the capacity of the stripe.

[0024] In some embodiments, the controller memory further includes a dynamic shared cache space;

[0025] The method further comprises:

[0026] When the static cache subspace corresponding to the namespace is full, a storage area of ​​preset capacity is requested from the dynamic shared cache space for the namespace.

[0027] In some embodiments, the method further comprises:

[0028] Determining whether to approve the application based on the current capacity of the space, the current capacity of the space group, and preset space capacity thresholds and space group capacity thresholds;

[0029] The current capacity of the space is the current capacity of the static cache subspace obtained by the namespace; the current capacity of the space group is the sum of the current capacities of the static cache subspaces obtained by each namespace included in the namespace group.

[0030] In some embodiments, the method further comprises:

[0031] When the static cache subspace is full, if it is determined that the application is not approved, the write data and / or pre-read data in the static cache subspace corresponding to the namespace is cleared.

[0032] In some embodiments, if the access command is a read command for reading a first virtual logical address, the stripe in which the first virtual logical address is located is determined according to the first virtual logical address;

[0033] Reading the read data corresponding to the stripe in the storage array;

[0034] The read data is cached in a cache area corresponding to the stripe to serve as pre-read data for subsequent reading of other addresses in the stripe except the first virtual logical address.

[0035] In some embodiments, the use of a preset capacity allocation rule to divide the static cache space according to the number of namespaces includes:

[0036] Dividing the static cache space evenly according to the number of namespaces;

[0037] Alternatively, the namespaces may be divided according to a preset capacity ratio of each namespace.

[0038] In some embodiments, allocating a cache area for the access command in a static cache subspace according to a namespace to be accessed by the access command includes:

[0039] Execute access commands in different namespace groups in parallel, and allocate cache areas for corresponding access commands in corresponding static cache subspaces according to the namespaces to be accessed;

[0040] The namespace group is divided in the following manner: each namespace in the hard disk group of the storage array is divided into a namespace group.

[0041] In a second aspect, an embodiment of the present application provides a storage array controller, comprising a storage interface control module, a redundancy module, a controller memory, and a non-volatile storage control module;

[0042] The redundancy module is respectively connected to the storage interface control module, the non-volatile storage control module and the controller memory;

[0043] The redundancy module is used to implement a namespace-based cache management method provided in the first aspect of this application.

[0044] In a third aspect, an embodiment of the present application provides a namespace-based cache management device, which is applied to a storage array controller, wherein the storage array controller includes a storage interface control module, a redundancy module, a controller memory, and a non-volatile storage control module, and the device includes: a cache area allocation module and a data cache module;

[0045] a cache area allocation module, configured to allocate a cache area for an access command in a static cache subspace according to a namespace to be accessed by the access command;

[0046] A data cache module, configured to receive target data to be read from or written to the storage array based on the access command, and cache the data in the cache area;

[0047] The static cache subspace is obtained by dividing the static cache space in the controller memory according to the namespace.

[0048] In a fourth aspect, an embodiment of the present application provides a terminal device, which includes a processor and a memory, the memory storing a computer program, and the processor being used to execute the computer program to implement a namespace-based cache management method provided in the first aspect of the present application.

[0049] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium storing a computer program. When the computer program is executed on a processor, it implements a namespace-based cache management method provided in the first aspect of the present application.

[0050] The embodiments of the present application have the following beneficial effects:

[0051] The present application allocates a cache area for the access command in the static cache subspace according to the namespace to be accessed by the access command; receives the target data of reading and writing the storage array based on the access command, and caches it in the cache area; wherein, the static cache subspace is obtained by dividing the static cache space in the controller memory according to the namespace. The present application divides the static cache space in the controller memory into multiple static cache subspaces according to the namespace; when the remote host accesses the storage array according to the namespace, the redundancy module of the present application first allocates a cache area for storing read and write data in the corresponding static cache subspace for the access command. In the present application, each namespace has a corresponding static cache subspace, ensuring that each namespace is accessed in a timely manner, and the static cache space in the controller memory is not occupied by one access command, causing other commands to queue up. Therefore, the present application can effectively solve the problem of low efficiency in reading and writing data in the storage array due to unreasonable cache space allocation. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0053] Figure 1 A structural block diagram of a storage array controller according to an embodiment of the present application is shown;

[0054] Figure 2 Another structural block diagram of a storage array controller according to an embodiment of the present application is shown;

[0055] Figure 3 A flowchart of a namespace-based cache management method according to an embodiment of the present application is shown;

[0056] Figure 4 A schematic diagram of a namespace array in a namespace-based cache management method according to an embodiment of the present application is shown;

[0057] Figure 5 A schematic diagram of a namespace group in a namespace-based cache management method according to an embodiment of the present application is shown;

[0058] Figure 6 A schematic diagram showing a partitioning of controller memory in a namespace-based cache management method according to an embodiment of the present application is shown;

[0059] Figure 7Another flowchart of the namespace-based cache management method according to an embodiment of the present application is shown;

[0060] Figure 8 A schematic structural diagram of a namespace-based cache management device according to an embodiment of the present application is shown;

[0061] Figure 9 A schematic diagram of a redundancy group in a cache management method of a storage array according to an embodiment of the present application is shown;

[0062] Figure 10 A schematic diagram of a namespace array in a cache management method for a storage array according to an embodiment of the present application is shown;

[0063] Figure 11 A schematic diagram showing a LBAG to be cleared with all active factor flag bits being 0 in a cache management method for a storage array according to an embodiment of the present application is shown;

[0064] Figure 12 A schematic diagram of stripes in the storage array data reading and writing method according to an embodiment of the present application is shown.

[0065] Description of main component symbols:

[0066] 100 - storage array controller; 200 - non-volatile storage array; 300 - remote host; 110 - storage interface control module; 111 - message parsing module; 112 - command queue processing module; 113 - processor; 120 - redundancy module; 130 - non-volatile storage control module; 140 - controller memory; 150 - protocol offload engine; 810 - cache area allocation module; 820 - data cache module. DETAILED DESCRIPTION

[0067] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0068] The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but rather merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort are within the scope of protection of the present application.

[0069] Hereinafter, the terms "including", "having" and their cognates used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the aforementioned items, and should not be understood as excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the aforementioned items or adding the possibility of one or more features, numbers, steps, operations, elements, components or combinations of the aforementioned items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and should not be understood as indicating or implying relative importance.

[0070] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as in the context of the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present application.

[0071] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0072] The following first introduces the keywords involved in this application:

[0073] PCIe: peripheral component interconnect express, a high-speed serial computer expansion bus standard.

[0074] NVMe: non volatile memory express, non-volatile high-speed transmission bus.

[0075] NVMe oF specification: the non-volatile memory express over fabrics (NVMe oF) specification is a storage network protocol. At present, the storage device based on NVMe oF usually adopts a multi-node architecture (the node can also be understood as a kind of controller) to realize the access of the host to the storage device, so as to improve the reliability and continuity of the storage service. The NVMe oF specification is a high-speed storage protocol based on the NVMe protocol, and NVMe oF is used to access NVMe storage media across a network. NVMe oF adds fabric-related commands based on NVMe, so that the application scenario of NVMe is not limited to one device, but can be extended to cross-network communication. Wherein, the so-called "fabric" refers to the network between the host and the storage medium. The typical form of fabric is, for example, Ethernet, fiber channel, InfiniBand (IB), direct memory access RDMA, etc.

[0076] SSD: Solid State Drive, solid state drive.

[0077] HBM: High Bandwidth Memory, high bandwidth memory.

[0078] The storage array in the present application includes a non-volatile storage array, and the present application is introduced based on the non-volatile storage array.

[0079] Figure 1 A structural block diagram of a storage array controller of an embodiment of the present application is shown. Exemplarily, the storage array controller 100 includes a storage interface control module 110, a redundancy module 120, a non-volatile storage control module 130 and a controller memory 140.

[0080] The redundancy module 120 is connected to the storage interface control module 110, the non-volatile storage control module 130 and the controller memory 140 respectively. The controller memory 140 can adopt HBM.

[0081] The storage interface control module 110 is in communication connection with a remote host 300, and is used to receive and analyze the message data sent by the remote host 300 to obtain an operation command, and transmit the operation command to the redundancy module 120 after scheduling management based on a namespace.

[0082] Further, as Figure 2As shown, the storage array controller 100 further includes a protocol offload engine 150 , and the storage interface control module 110 includes a message parsing module 111 , a command queue processing module 112 and a processor 113 .

[0083] The protocol offload engine 150 is configured to receive a protocol message of a preset protocol type sent by the remote host 300 , parse the protocol message, and send the message data obtained by parsing to the message parsing module 111 in the storage interface control module 110 .

[0084] The processor 113 is connected to both the command queue processing module 112 and the message parsing module 111 .

[0085] The message parsing module 111 is used to receive and parse the message data sent by the remote host 300, obtain operation commands, and send data transmission type operation commands to the command queue processing module 112, and send non-data transmission type operation commands to the processor 113.

[0086] The processor 113 is configured to establish a connection with the remote host 300 according to the operation command, and to configure and manage the scheduling function parameters of the command queue processing module 112 .

[0087] The command queue processing module 112 is configured to store the operation command into a corresponding namespace command queue according to the accessed target namespace for scheduling management, and transmit the operation command to the redundancy module 120 in sequence.

[0088] The redundancy module 120 is configured to perform redundancy calculation on the data and then write the data into the controller memory 140 , and to manage the logical address space of the non-volatile storage array 200 and the controller memory 140 based on the namespace.

[0089] The non-volatile storage control module 130 is in communication with the non-volatile storage array 200 and, in response to a data transfer request from the redundancy module 120, maps the controller memory 140 to implement data exchange with the non-volatile storage array 200. The non-volatile storage control module 130 interacts with the non-volatile storage array 200 to read or write data via DMA (Direct Memory Access).

[0090] By way of example, the storage array controller 100 of an embodiment of the present application is described, taking a write command as an example. In this example, the storage interface control module 110 uses an NVMe-oF controller, the non-volatile storage control module 130 uses an NVMe-PCIe host, the protocol offload engine 150 uses a TOE module (TCP / IP Offload Engine), and the controller memory 140 uses HBM. The specific processing process of the storage array controller 100 includes the following steps:

[0091] S111: The TOE module receives a protocol message of a preset protocol type sent by the remote host 300, parses the protocol message, and sends the message data obtained by parsing to the NVMe-oF controller. The protocol message of the preset protocol type may be a TCP / IP / Ethernet message, and the message data may be the data portion of the TCP / IP / Ethernet message.

[0092] S112: The message parsing module 111 in the NVMe-oF controller receives and parses the message data sent by the remote host 300, obtains an operation command, and sends the data transmission type operation command to the IOQ processing module. The operation command includes a PDU (Protocol Data Unit), and the operation command is determined to be a data transmission type based on the PDU, that is, the operation command is a write operation command.

[0093] S113: The IOQ processing module stores the write operation command in the corresponding namespace command queue based on the target namespace being accessed for scheduling and management, and sequentially transmits the write operation command to the redundancy module 120. Alternatively, the write operation command may be added to a read / write command queue, a priority command queue, or other queues. When the IOQ processing module receives a write operation command to write data, it sends an indication command to the redundancy module 120, instructing it to prepare an idle first cache subspace to receive the data to be written.

[0094] S114 , the redundancy module 120 queries the cache status table to determine whether there is sufficient cache space in the controller memory 140 to receive the data to be written.

[0095] Redundancy module 120 needs to determine whether controller memory 140 has address space for the corresponding LBA block. If so, but the LBA block is in an uncompleted state from a previous command, processing of the write command is suspended until the corresponding LBA block is unlocked. If controller memory 140 does not have address space for the corresponding LBA block, an idle first cache subspace is allocated in controller memory 140. If the controller memory has address space for the corresponding LBA block, the LBA block is unlocked, and there is sufficient space to write the command data, an R2T command is sent back to remote host 300, instructing remote host 300 to send the data to be written.

[0096] If there is not enough cache space, the data in the corresponding namespace will be actively written to disk to free up cache space.

[0097] S115, after receiving the R2T command, the remote host 300 sends the data to be written in the form of a TCP / IP / Ethernet message, which is then parsed by the TOE module and the message parsing module 111 and sent to the redundancy module 120 via the IOQ processing module.

[0098] S116 , the redundancy module 120 divides the data blocks and calculates the check blocks according to the current redundancy mode of the non-volatile storage array 200 .

[0099] First, the redundancy module 120 needs to perform a data integrity check on the data to be written, and check whether the data is consistent based on the DIF (Data Integrity Field) of the data.

[0100] After the integrity check is passed, redundancy calculation is performed. If the current redundancy mode is k+m, the data is divided into k parts, and m parts of verification data are obtained based on the encoding of the k parts of data. The k+m parts of data obtained after the redundancy calculation are written into the controller memory 140.

[0101] The CQ (Completion Queque) corresponding to the data write completion is sent to the remote host 300 to notify the remote host 300 that the data write is complete. Since the redundancy module 120 has completed the data integrity check, ensuring the reliability of the data to be written in the cache, the remote host 300 can be directly notified that the data write is complete without waiting for the data to be actually written to the non-volatile storage array 200 (NVME hard drive). If an integrity check error occurs at the non-volatile storage array 200 during the subsequent disk write process, the data can be read again from the controller memory 140.

[0102] S117, the redundancy module 120 generates a disk write command to inform the NVMe-PCIe host of the cache address of k+m copies of data (data to be written and verification data after redundancy calculation).

[0103] S118, the NVMe-PCIe host maps the corresponding first cache subspace to the memory of the NVME-PCIe host.

[0104] For example, the cache address of k+m copies of data is A1-A5. The NVME-PCIe host writes the first address A1 and the data length into the DMA register of the corresponding namespace in the NVMe hard disk. Each namespace corresponds to a register. The register address is exchanged when the NVMe-PCIe host and the NVME hard disk initialize and establish a DMA connection.

[0105] When a DMA register in the NVMe hard drive is enabled, the NVMe hard drive can directly read k+m copies of data from the cache mapped by the corresponding NVMe-PCIe host by writing the first address A1 and data length of the register through the NVMe-PCIe host.

[0106] After the data is read, the NVMe hard drive writes the DMA completion flag into the DMA register of the NVMe-PCIe host.

[0107] S119, the NVMe-PCIe host sends a disk write completion notification in response to the DMA completion to notify the redundancy module 120 that the cache space A1-A5 has been released, and the cache space can be continued to be used by the redundancy module 120.

[0108] By way of example, the storage array controller 100 of the embodiment of the present application is introduced below based on a read command as an example. The specific processing process of the storage array controller 100 includes the following steps:

[0109] S121, the TOE module parses the received TCP / IP / Ethernet message and sends the parsed message data (data part) to the NVMe-oF controller.

[0110] S122, the message parsing module 111 in the NVMe-oF controller decapsulates the message data to obtain an operation command, which includes a PDU (Protocol Data Unit). According to the PDU, the operation command is determined to be a data transmission type (read operation command), and then the read operation command is sent to the IOQ processing module (command queue processing module 112).

[0111] S123, the IOQ processing module adds the received read operation command to a command queue for management and scheduling, such as a read / write command queue, a priority command queue, or an NS (NameSpace) command queue.

[0112] When the read operation command is executed, an indication command is sent to the redundant module 120 to instruct the redundant module 120 to check whether there is an address space of the corresponding LBA block in the controller memory 140. If so, and it is not in a locked state, the data is read directly from the address space of the corresponding LBA block in the controller memory 140; if so, and the corresponding LBA block is in a locked state, the execution of the command is temporarily suspended; if there is no address space of the corresponding LBA block in the controller memory 140, the second cache subspace is prepared and the relevant data is read.

[0113] At the same time, the IOQ processing module generates a command for reading consecutive addresses in the same namespace and transmits it to the redundancy module 120 .

[0114] S124, the redundancy module 120 queries the cache status table to see if there is enough cache space to receive the data to be read. If so, it instructs the NVMe-PCIe host to read the data from the NVMe hard disk, and informs the address of the second cache subspace for receiving the data and the target address of the data to be read.

[0115] If there is not enough cache space, the data in the corresponding namespace will be sent to the remote host 300 first to free up cache space.

[0116] S125, the NVMe-PCIe host sends a data read command to the NVMe hard disk, and maps the cache space to the memory of the NVMe-PCIe host to receive the data to be read.

[0117] S126, after the NVMe hard disk prepares the data to be read, it writes the first address and length of the data into the DMA register of the NVMe-PCIe host.

[0118] S127, the NVMe-PCIe host responds to the DMA register enable, directly reads data from the memory of the NVMe hard disk according to the data address and data length written by the NVMe hard disk, and notifies the redundancy module 120 to release the relevant cache after reading.

[0119] S128 , the redundancy module 120 merges the data blocks or recovers the data according to the redundancy mode of the current array, and sends the data to the remote host 300 .

[0120] In order to improve the management efficiency of the controller memory 140 by the redundancy module 120, the present application further provides a cache management method, storage array controller, apparatus, device and medium. In the embodiment of the present application, the redundancy module 120 implements a namespace-based cache management method of the present application.

[0121] In the namespace-based cache management method of an embodiment of the present application, for simplicity, the cache in redundancy module 120 does not have separate read and write cache spaces. Data in the cache space may originate from a remote host 300 or a non-volatile storage array 200. The cache is internally divided and managed solely by namespace, with each namespace allocated a separate cache for data storage. Namespaces belonging to different hard drives can write data in parallel. Independent namespace caching prevents data from a single namespace from occupying the entire cache and slowing down overall read and write speeds.

[0122] The namespace-based cache management method is described below with reference to some specific embodiments.

[0123] Figure 3 A flowchart of a namespace-based cache management method according to an embodiment of the present application is shown. In the embodiment of the present application, the redundancy module 120 performs cache management on the controller memory 140 (hereinafter referred to as cache) according to the current redundancy mode and the number of NS (Namespace). Exemplarily, the namespace-based cache management method includes the following steps:

[0124] S210 , allocating a cache area for the access command in a static cache subspace according to the namespace to be accessed by the access command.

[0125] The controller memory 140 in the embodiment of the present application includes a static cache space. It can be understood that the present application utilizes a preset capacity allocation rule to divide the static cache space according to the number of namespaces, and obtains static cache subspaces corresponding to each of the namespaces, as shown in Table 1. Thus, a static cache subspace is obtained. For example, a device supports i NS (NameSpace), and the static cache space is divided into i NS, as shown in Table 1. Each namespace corresponds to a static cache subspace. Thus, it is ensured that each NS has a certain amount of cache space. Once a read or write operation command accesses the NS, the remote host 300 can be immediately notified that there is enough cache space to instruct the remote host 300 to send write data; the cache space will not be used up by other NSs and cannot respond to the command.

[0126] Table 1 Correspondence between namespace and static cache subspace

[0127] Namespace Static cache space <![CDATA[NS1]]> Static cache subspace 1 <![CDATA[NS2]]> Static cache subspace 2 … … <![CDATA[NS i ]]> Static cache subspace i

[0128] Furthermore, the static cache space is divided according to the number of namespaces using a preset capacity allocation rule, including:

[0129] The static cache space is evenly divided according to the number of namespaces to obtain various static cache subspaces, and the static cache subspaces are fixed.

[0130] Alternatively, the namespaces can be divided based on a preset capacity ratio. For example, a ratio of static cache space occupied by each namespace can be set, and fixed static cache subspaces can be divided for each namespace based on the ratio. However, once a static cache subspace is divided, its capacity is fixed and will not be adjusted based on actual cache usage or the validity of the NS.

[0131] Furthermore, the nonvolatile storage array 200 is mapped into a virtual logical address space based on each of the namespaces. All logical addresses of the nonvolatile storage array 200 are mapped to equal sizes to obtain a virtual logical address space. The virtual logical address space includes virtual logical addresses (referred to as VIR_LBA addresses) that correspond one-to-one with each logical address (referred to as LBA addresses) in the nonvolatile storage array 200, as shown in Table 2.

[0132] Table 2 Mapping relationship between VIR_LBA address and LBA address in non-volatile storage array

[0133] VIR_LBA address LBA address in the storage array VIR_LBA0 LBA0 VIR_LBA1 LBA1 … … VIR_LBAi LbI

[0134] The virtual logical address space is divided according to the number of namespaces to obtain virtual logical address subspaces corresponding to each namespace. Thus, each virtual logical address subspace is obtained. The virtual logical address subspace includes multiple virtual logical addresses, as shown in Table 3.

[0135] Table 3 Correspondence between namespace and virtual logical address subspace

[0136] Namespace Virtual logical address subspace NS1 VIR_LBA0-VIR_LBA99 NS2 VIR_LBA100-VIR_LBA249 … … NSi VIR_LBAm-VIR_LBAn

[0137] Furthermore, allocating a cache area for the access command in the static cache subspace according to the namespace to be accessed by the access command includes:

[0138] S211: Obtain a virtual logical address subspace according to the namespace matching.

[0139] S212: Allocate a target virtual logical address for the access command from the virtual logical address subspace.

[0140] S213: Allocate the cache area for the target virtual logical address from the static cache subspace uniquely corresponding to the namespace.

[0141] To improve performance and facilitate management, the allocation granularity of the virtual logical address subspace corresponding to NS is set according to the redundancy mode of the SSD hard disk (non-volatile storage array 200). The virtual logical address subspace is divided into multiple stripes according to the number of members in the redundancy group of the SSD hard disk. Specifically, according to the redundancy mode of the non-volatile storage array 200, the virtual logical address subspace is divided into a namespace array. A row of virtual logical addresses in the namespace array is regarded as a stripe, such as Figure 4 As shown (namespace array corresponding to NS1).

[0142] Furthermore, in step S212, allocating a target virtual logical address for the access command from the virtual logical address subspace includes:

[0143] When the access command is to access any virtual logical address in the stripe, the stripe is assigned to the access command as the target virtual logical address. It can be understood that when an access command accesses any virtual logical address in a stripe, the entire stripe where the virtual logical address is located will be allocated to the access command, and a cache area of ​​the entire stripe size will be requested from the corresponding static cache subspace. Therefore, the static cache subspace should be set to an integer multiple of the stripe length. If a read command is received for NS1 to read the data corresponding to VIR_LBA3, it is necessary to request a corresponding cache area from the static cache subspace in NS1 for the entire stripe where VIR_LBA3 is located.

[0144] In step S213, allocating the cache area for the target virtual logical address from the static cache subspace uniquely corresponding to the namespace includes:

[0145] If the cache area is not matched according to the stripe, a cache area is allocated to the stripe from the static cache subspace corresponding to the namespace according to the capacity of the stripe.

[0146] In one embodiment, to improve data processing speed, the method of the embodiment of the present application further includes: dividing each namespace within the hard disk group of the non-volatile storage array 200 into a namespace group. Allocating a cache area for the access command in the static cache subspace based on the namespace to be accessed by the access command includes:

[0147] Access commands in different namespace groups are executed in parallel, and cache areas are allocated for corresponding access commands in corresponding static cache subspaces according to the namespaces to be accessed. Figure 5The figure shows a schematic diagram of an NS Group, where NameSpace1, NameSpace2, and NameSpace3 belong to NS Group1, and NameSpace4, NameSpace5, and NameSpace6 belong to NS Group2. Different namespace groups can be accessed in parallel without affecting each other because they store different hard disk groups. Therefore, limiting the dynamic space usage of a single namespace group is beneficial to improving the overall processing efficiency of the array system.

[0148] S220: Receive target data for reading and writing the non-volatile storage array 200 based on the access command, and cache the data in the cache area. The static cache subspace is obtained by dividing the static cache space in the controller memory 140 according to the namespace.

[0149] In one embodiment, in order to increase the speed of reading data, the present application also supports pre-reading data. The method further includes:

[0150] S310: If the access command is a read command for reading a first virtual logical address, determine the stripe in which the first virtual logical address is located according to the first virtual logical address.

[0151] S320, reading the read data corresponding to the stripes in the non-volatile storage array 200; mapping the logical address of the non-volatile storage array 200 according to the virtual logical addresses corresponding to the stripes, and reading the read data in the non-volatile storage array 200 according to the logical address of the non-volatile storage array 200.

[0152] S330: Cache the read data in a cache area corresponding to the stripe to serve as pre-read data for subsequent reading of other addresses in the stripe except the first virtual logical address.

[0153] For example, if a read command is received from NS1 to read data corresponding to VIR_LBA3, a corresponding cache area must be allocated from the static cache subspace in NS1 for the entire stripe containing VIR_LBA3. Alternatively, only the data corresponding to VIR_LBA3 can be read, or a pre-read operation can be performed to read all the data corresponding to the entire stripe from the non-volatile storage array 200 into the corresponding cache area. A subsequent command to read data corresponding to VIR_LBA4 in the stripe can then be read directly from the cache area, thereby improving data reading efficiency.

[0154] In one embodiment, the controller memory 140 also includes a dynamic shared cache space, such as Figure 6 shown.

[0155] The method further comprises:

[0156] When the static cache subspace corresponding to the namespace is full, a storage area of ​​preset capacity is requested from the dynamic shared cache space for the namespace.

[0157] Furthermore, the method further comprises:

[0158] Whether the application is approved is determined based on the current space capacity, the current space group capacity, and preset space capacity thresholds and space group capacity thresholds. The current space capacity is the current capacity of the static cache subspace already obtained by the namespace; the current space group capacity is the sum of the current capacities of the static cache subspaces obtained by each namespace contained in the namespace group.

[0159] Exemplarily, if the current capacity of the space group corresponding to the namespace group does not reach the space group capacity threshold, and the current capacity of the space corresponding to the namespace does not reach the space capacity threshold, then the application is determined to be approved, that is, the storage area is allowed to be allocated from the dynamic shared cache space, otherwise the application is rejected.

[0160] In other words, in order to prevent a certain NS from occupying a large amount of dynamic space and affecting the use of other NSs, the embodiment of the present application sets a watermark for the dynamic space that can be applied for for each NS and the namespace group in which the NS is located. The application of dynamic space for all namespaces belonging to the same namespace group is limited by the watermark of the namespace itself and the namespace group to which it belongs (i.e., the threshold). When a namespace applies for dynamic space and touches any of the above watermarks, no more dynamic space will be allocated to it.

[0161] Furthermore, the method further comprises:

[0162] If the static cache subspace is full and the request is rejected, the write data and pre-read data in the static cache subspace corresponding to the namespace are cleared. To execute commands, the namespace needs to free up cache space occupied by completed commands. For write command caches, this triggers the backend to flush data to disk as quickly as possible; for read command caches, pre-read data is cleared.

[0163] The following describes the namespace-based cache management method of the embodiment of the present application with an example of a write command. Figure 7 As shown, the specific steps include:

[0164] S401 , the redundancy module 120 receives a write command, and allocates an idle virtual logical address VIR_LBA according to the namespace accessed by the current write command and the length of the data to be written, and records it as a first address.

[0165] S402: The redundancy module 120 determines whether the stripe to which the first address belongs has been allocated a cache area according to the cache status table. If the stripe has been allocated a cache area, step S403 is executed; if not, step S404 is executed.

[0166] S403 , the redundancy module 120 sends an R2T (Ready to Transfer, indicating that the cache area is ready) to the remote host 300 to instruct the remote host 300 to send the data to be written.

[0167] S404: The redundancy module 120 determines whether there is any free cache area in the static cache sub-area of ​​the namespace corresponding to the stripe. If there is a free cache area, step S405 is executed; otherwise, step S406 is executed.

[0168] S405 , the redundancy module 120 allocates an available fixed cache area to the stripe from the static cache sub-area corresponding to the namespace.

[0169] S406, the redundancy module 120 determines whether the dynamic shared cache space applied for by the currently accessed NS triggers the preset watermark (including the space capacity threshold and the space group capacity threshold). If triggered, cache cleaning is performed and the released cache space is allocated to the stripe. If not triggered, the corresponding shared cache area is allocated from the dynamic shared cache space to the stripe.

[0170] S407, sends R2T (Ready to Transfer, indicating that the cache area is ready) to the remote host 300 to instruct the remote host 300 to send the data to be written, and stores the received data to be written into the second address (physical address of the cache space) corresponding to the first address (VIR_LBA of NS) in the allocated cache area.

[0171] The present application divides the static cache space in the controller memory 140 into a plurality of static cache subspaces according to the namespace; and divides the virtual logical address subspace corresponding to the namespace into a plurality of stripes.

[0172] When the remote host 300 accesses the non-volatile storage array 200 according to a virtual logical address in the namespace, the redundancy module 120 of the present application first allocates a cache area for storing read and write data to the stripe in the static cache subspace corresponding to the namespace according to the stripe where the virtual logical address is located. In addition, if the static cache subspace corresponding to the namespace has been allocated, a dynamic cache area is allocated to the stripe from the dynamic shared cache space according to the set threshold. In the present application, each namespace has a corresponding static cache subspace. If the static cache subspace is used up, a dynamic cache area is allocated from the dynamic shared cache space. The present application ensures that each namespace is accessed in a timely manner from all aspects, so that the static cache space in the controller memory 140 is not occupied by one access command, causing other commands to queue up. Therefore, the present application can effectively solve the problem of low efficiency in reading and writing data in the non-volatile storage array 200 due to unreasonable cache space allocation.

[0173] Figure 8 A schematic diagram of the structure of a namespace-based cache management device according to an embodiment of the present application is shown. Exemplarily, the namespace-based cache management device includes: a cache area allocation module 810 and a data cache module 820.

[0174] The cache area allocation module 810 is configured to allocate a cache area to an access command in a static cache subspace according to a namespace to be accessed by the access command.

[0175] The data cache module 820 is configured to receive target data for reading and writing the non-volatile storage array 200 based on the access command, and cache the target data in the cache area.

[0176] The static cache subspace is obtained by dividing the static cache space in the controller memory 140 according to the namespace.

[0177] It can be understood that the device of this embodiment corresponds to the namespace-based cache management method of the above embodiment, and the options in the above embodiment are also applicable to this embodiment, so they will not be described again here.

[0178] In order to improve the efficiency of the redundancy module in processing data on the controller memory based on the namespace, the present invention also provides a cache management method, device, controller and medium for a storage array. In the embodiment of the present invention, the redundancy module implements a cache management method for a storage array provided by the present invention.

[0179] The cache management method of the storage array is described below with reference to some specific embodiments.

[0180] In the embodiment of the present application, the redundancy module 120 performs cache management on the controller memory 140 (hereinafter referred to as cache) according to the current redundancy mode and the number of NS (Namespace). Exemplarily, the cache management method of the storage array includes the following steps:

[0181] S2210, map the non-volatile storage array 200 to a virtual logical address space according to the namespace, and divide the virtual logical address space into virtual logical address groups. Map the logical addresses of the non-volatile storage array 200 one by one to obtain a virtual logical address space, which includes virtual logical addresses (also known as VIR_LBA addresses) corresponding to all logical addresses (also known as LBA addresses, logical block addresses, Logical Block Address) in the non-volatile storage array 200. There is a mapping relationship between the VIR_LBA address in the embodiment of the present application and the LBA address of the non-volatile storage array 200, and the relationship between the LBA address and the PBA address (Physics Block Address) in the non-volatile storage array 200 is processed by the controller in the non-volatile storage array 200 after the disk is written, and is not limited in comparison with the present application. The storage array controller 100 of the present application is an external controller of the non-volatile storage array 200.

[0182] In one embodiment, the present application supports HMB (Host Memory Buffer) technology, where the memory of the storage array controller 100 is open to the controller of the non-volatile storage array 200 to store the FTL (Flash Translation Layer) table. When the non-volatile storage array 200 is a DRAM-less hard disk, enabling this function can significantly improve the performance of the storage array.

[0183] Furthermore, dividing the virtual logical address space into virtual logical address groups includes:

[0184] The virtual logical address space is divided according to a preset number of namespaces to obtain virtual logical address subspaces of a number equal to the preset number.

[0185] That is, the redundancy module 120 allocates a fixed VIR_LBA address space (virtual logical address subspace) to each namespace, as shown in Table 2-1.

[0186] Table 2-1 Namespace and VIR_LBA address space

[0187] Namespace VIR_LBA address NameSpace1 VIR_LBA0-VIR_LBA99 NameSpace2 VIR_LBA100-VIR_LBA249 … … NameSpacex VIR_LBAm-VIR_LBAn

[0188] A fixed mapping is established between each VIR_LBA address in each namespace and the LBA address of the non-volatile storage array 200. As shown in Table 2-2, the LBA addresses of NS1 in the non-volatile storage array 200 are LBA1050-LBA1149.

[0189] Table 2-2 Mapping relationship between VIR_LBA address and LBA address in non-volatile storage array

[0190]

[0191]

[0192] For example, when a write data command for NS1 is received, the write data size is 10, and a virtual logical address of VIR_LBA0-VIR_LBA9 is assigned to the write data command, and sufficient cache space is requested from the controller memory 140 (e.g., HBM High Bandwidth Memory) for VIR_LBA0-VIR_LBA9 to prepare for receiving the write data. VIR_LBA0-VIR_LBA9 is mapped to the logical addresses LBA1050-LBA1059 of the non-volatile storage array 200 (e.g., SSD hard disk). Furthermore, each continuous logical address block in the virtual logical address subspace is divided into a namespace array according to the redundancy mode of the non-volatile storage array 200; a row of the logical address blocks in the namespace array is regarded as a stripe, wherein the number of logical address blocks in the stripe is the same as the number of redundant group members in the non-volatile storage array 200, and the namespace array is divided into multiple virtual logical address groups, each of which includes one or more stripes.

[0193] If the current redundancy mode is k+m, that is, there are k+m i members in a redundancy group, such as Figure 9 As shown, SSD1-SSDi is a redundant group.

[0194] To improve performance, this embodiment of the application divides the namespace array into multiple virtual logical address groups. Specifically, the contiguous VIR_LBA address space within a namespace is defined as a VIR_LBA group, denoted as a VIR_LBAG. When the array is redundant, each VIR_LBAG is further divided into arrays based on the current redundancy mode.

[0195] Divide the cache array according to the current redundancy mode Figure 10(A namespace array divided by a virtual logical address group in a namespace under a redundancy group), each row in the NS array (namespace array) is a stripe, and the number of LBA_BLOCKs (logical address blocks) in the stripe is determined by the number of redundant group members. The VIR_LBA address of the namespace corresponds one-to-one to the LBA address of the SSD disk. The number of LBA_BLOCK blocks in each column is related to the total VIR_LBA capacity allocated to the current NS, the overall cache capacity, and the actual storage business characteristics. For example, a certain NS may be mainly small random IO, then the number of LBA_BLOCK blocks in the array can be designed to be very small, and the same cache space can be divided into more VIR_LBAGs. For devices that support redundancy features, the VIR_LBAG in its cache is at least one stripe ( Figure 10 In other cases, multiple stripes can be divided into one VIR_LBAG for management and operation as needed.

[0196] The space size of a VIR_LBAG and the number of LBA_BLOCKs remain unchanged when the redundancy group configuration remains unchanged. This also applies if individual members of the redundancy group fail (for example, an SSD member is damaged and cannot be used, but the entire redundancy group can still recover data normally).

[0197] S2220: Determine the activity level of cached data in the virtual logical address group according to the storage status corresponding to the virtual logical address group.

[0198] S2230: Determine a target virtual logical address group that needs to be stored in the non-volatile storage array 200 according to the activity level.

[0199] In order to ensure that there is enough free space in the cache space, the present application writes data with low activity levels to the disk. It can be understood that the target virtual logical address group that needs to be stored in the non-volatile storage array 200 according to the activity level includes:

[0200] The virtual logical address group with a low activity level is determined as the target virtual logical address group.

[0201] When the cache space is full, the virtual logical address group at the intermediate activity level may also be determined as the target virtual logical address group.

[0202] Furthermore, the determining of the target virtual logical address group to be stored in the non-volatile storage array 200 according to the activity level includes:

[0203] The target cache data that needs to be stored in the non-volatile storage array 200 in the target virtual logical address group is determined according to the storage status.

[0204] Furthermore, the determining of the target virtual logical address group to be stored in the non-volatile storage array 200 according to the activity level includes:

[0205] The target logical address for storing the target cache data in the non-volatile storage array 200 is determined according to the virtual logical address group and the preset logical address mapping relationship.

[0206] The target cache data is written into the non-volatile storage array 200 according to the target logical address.

[0207] In one embodiment, the storage status includes a read / write status flag corresponding one-to-one to each logical address block in the virtual logical address group.

[0208] Exemplarily, in an embodiment of the present application, an LBAG status table (also known as a virtual logical address group status table) is used to record the allocation and usage of VIR_LBAG in each namespace. That is, the storage status is stored in the LBAG status table. The activity level of the cached data in the virtual logical address group is determined based on the storage status recorded in the LBAG status table. The LBAG status table includes read-write status flags that correspond one-to-one to each logical address block (LBA_BLOCK) in the virtual logical address group. Multiple read-write status flags are required depending on the number of LBA_BLOCKs in the current virtual logical address group, and each LBA_BLOCK corresponds to a 1-bit read-write status flag, as shown in Table 2-3.

[0209] Table 2-3LBAG status table 1

[0210]

[0211] The step of determining target cache data in the target virtual logical address group that needs to be stored in the non-volatile storage array 200 according to the storage state includes:

[0212] The cached data in the logical address block corresponding to the read / write status flag in the target virtual logical address group is determined as the target cached data. That is, within the target virtual logical address group, the logical address block corresponding to the read / write status flag in the write state is first determined to obtain the target logical address block, and the cached data in the target logical address block is determined as the target cached data. The target cached data is stored in the non-volatile storage array 200 to complete the write to disk.

[0213] Furthermore, the method further includes: updating the corresponding storage status according to the read and write operations on the virtual logical address groups corresponding to the namespaces in the cache, specifically including:

[0214] If the data stored in the cache by the logical address block is first data, a read-write state flag corresponding to the logical address block is set to a write state, the first data being write data sent by the remote host 300. For example, if the data in the logical address block is write data from the NVMe-oF controller, the read-write state flag corresponding to the logical address block is set to 1, indicating a write state. Therefore, when the current virtual logical address group needs to be flushed, the data in the logical address block with the read-write state flag set to 1 must be flushed.

[0215] If the data stored in the cache by the logical address block is second data, a read-write state flag corresponding to the logical address block is set to a read state; the second data being empty data or read data read from the non-volatile storage array 200. For example, if the data in the logical address block is read data from the SSD or the logical address block is currently not written with data, the read-write state flag corresponding to the logical address block is set to 0, indicating a read state. Therefore, when the current virtual logical address group needs to be flushed, the data in the logical address block with the read-write state flag set to 0 is not flushed.

[0216] Further, the method further comprises:

[0217] When the target cache data is written into the non-volatile storage array 200, redundant calculation is performed on the cache data in each logical address block in the stripe to obtain check data and write the check data into a check block in the stripe; and a read-write state flag corresponding to the check block is set to the write state.

[0218] In the redundancy mode, when the IOQ processing module transmits write data to the redundancy module 120, the write data is only divided according to the current redundancy mode and stored in the corresponding data block cache, and the check calculation is not performed at present, the corresponding check block is empty, and the check data is calculated and filled into the corresponding check block when it needs to be flushed, the read-write state flag corresponding to the check block for storing the check data is forcibly set to 1 to indicate that the LBA_BLOCK needs to be flushed. For example, the current redundancy mode is k+m, the write data is stored in k data LBA_BLOCKs in a stripe, and the read-write state flag is set to 1, m check blocks are temporarily empty and the check data does not come from the NVMe-oF controller, but the check data is calculated when it needs to be flushed, written into the check block, and the corresponding read-write state flag is set to 1, indicating that the LBA_BLOCK needs to be flushed.

[0219] In an embodiment, the storage state comprises a full-write flag corresponding to each virtual logical address group. One virtual logical address group corresponds to one full-write flag. The full-write flag is stored by using 1 bit.

[0220] The method further comprises:

[0221] Determine whether each read / write status flag corresponding to each logical address block in the virtual logical address group is in the write state, and obtain the number of logical address blocks whose read / write status flag is in the write state. If the number of blocks is greater than a preset threshold, determine that the full flag corresponding to the virtual logical address group is in the full state. For example, in the write state, the full flag is set to 1, indicating that the cache space corresponding to the virtual logical address group is full or about to be full.

[0222] The method further includes: using the virtual logical address group corresponding to the full state of the write flag as the target virtual logical address group, that is, the virtual logical address group that needs to be written to the disk, and then determining the target cache data that needs to be written to the disk according to the read-write status identification bit.

[0223] Exemplarily, the number of 1s in each read / write status flag within a virtual logical address group is counted. When this number exceeds a preset threshold (e.g., 2 / 3 of the logical address block), the full flag is set to 1 to indicate that the virtual logical address group is full, as a condition for flushing to disk. In one embodiment, the storage status includes a number of activity factor flags corresponding to each virtual logical address group. Each virtual logical address group corresponds to one activity factor flag, and the activity factor flag has a size of 1 to n bits.

[0224] The method further includes: updating corresponding storage states according to read and write operation commands of the virtual logical address groups corresponding to each namespace in the cache, specifically including:

[0225] The activity factor flag value corresponding to the virtual logical address group is set according to the frequency of the read and write operation commands received for the virtual logical address group. The greater the frequency of the read and write operations, the more active the virtual logical address group is.

[0226] Furthermore, setting the corresponding activity factor flag value according to the frequency of the read and write operation commands received by the virtual logical address group includes:

[0227] Counting objects based on the virtual logical address group according to a preset frequency and counting period;

[0228] During the counting period, the activity factor flag value is updated according to a preset updating rule based on whether the virtual logical address group receives a read or write operation command.

[0229] Furthermore, the activity factor flag value is updated according to a preset update rule based on whether the virtual logical address group receives a read or write operation command within the counting period, including:

[0230] If the read / write operation command is not received within the counting period, the respective digits of the activity factor flag value are retrieved in a set digit order, and the second state value is updated and written to the digit corresponding to the first first state value; wherein, in the initial state, the values ​​of the respective digits of the activity factor flag value are all the first state values.

[0231] If the read / write operation command is received within the counting cycle, the respective digits of the activity factor flag value are retrieved in the reverse order of the set digits, and the first state value is updated and written to the digit corresponding to the first second state value.

[0232] For example, once a virtual logical address group is allocated, the activity factor flag value of the activity factor flag bit defaults to all 1s. Whether the individual bits in the activity factor flag value are set to 0 depends on a counter that continuously accumulates naturally, and the operating frequency of the counter (i.e., the speed of counting) can be set. A certain technical cycle is set based on the counter. If no read or write operation is received for the current virtual logical address group when the counter overflows, one of the bits of the activity factor flag value is set to 0; if a read or write operation is received for the current virtual logical address group within one counting cycle of the counter, the counter is reset to zero and the count is restarted, and a 0-bit bit of the activity factor flag value is flipped to 1.

[0233] For example, if a 3-bit liveness factor flag is set, and the counter's counting period is t, the counter will naturally increment from 0. After counting period t, the counter reaches its maximum value and overflows. After the current virtual logical address group is allocated, the liveness factor flag value is 111, and the counter begins counting. If no read / write operation is received for the current virtual logical address group after counting period t, the liveness factor rolls over to 110. The counter resets to zero and counts again. If no read / write operation is received for the current virtual logical address group after counting period t, the liveness factor flag value rolls over to 100. If the counter resets to zero and counts again but receives a read / write operation for the current virtual logical address group before the end of the counting period, the liveness factor flag value rolls over to 110, and so on. That is, if the liveness factor flag value receives a read or write command within the counting period, the value of the 0 digit rolls over to 1, and so on. When the liveness factor flag value is all 1, there is no overflow and it remains all 1. If no read or write operation command is received during the counting cycle, the value of the 1 digit is flipped to 0, and so on; when the activity factor flag value is all 0, it does not overflow and remains all 0.

[0234] Furthermore, determining the activity level of cached data in the virtual logical address group according to the storage state corresponding to the virtual logical address group includes:

[0235] If the numbers on each digit of the activity factor flag value corresponding to the virtual logical address group are all the second state values, the activity level of the cached data in the virtual logical address group is determined to be a low activity level.

[0236] If the numbers on each digit of the activity factor flag value corresponding to the virtual logical address group are all the first state values, the activity level of the cache data in the virtual logical address group is determined to be a high activity level.

[0237] Counting the number of digits of each digit of the activity factor flag value that are the first state value;

[0238] If the number of digits is greater than a preset number, the activity level of the cached data in the virtual logical address group is determined to be an intermediate activity level.

[0239] The activity factor flag value represents the activity of the virtual logical address group, that is, the hotness or coldness of the data. A larger activity factor flag value indicates a more active virtual logical address group. Active data is kept in the cache as much as possible. An activity factor flag value of all 0 indicates that the virtual logical address group is no longer active and requires a write command to the SSD. If cache space is insufficient, cached data in virtual logical address groups with intermediate activity (non-all 0 values) can be written to disk based on activity.

[0240] In this embodiment, an activity factor flag value is used to represent the activity level of the data in the current virtual logical address group. Retaining highly active data in the cache reduces frequent operations on the SSD after the active data is written to disk, thereby reducing wear on the SSD and extending its lifespan. This also reduces the bandwidth requirements of the backend PCIe channel, significantly improving the I / O command performance of active data.

[0241] In one embodiment, the virtual logical address group is the granularity of read and write operation commands.

[0242] The storage state includes a number of lock flag bits equal to the number of virtual logical address groups. One virtual logical address group corresponds to one lock flag bit, for example, the size of the lock flag bit is 1 bit.

[0243] The method further comprises:

[0244] When operating the current virtual logical address group according to the read / write operation command, the lock flag corresponding to the current virtual logical address group is set to a locked state; and the read / write operation command accessing the virtual logical address group in the locked state is delayed. That is, after a read / write operation command operates the current virtual logical address group, the virtual logical address group is in a locked state before the read / write operation command is completed. For example, the lock flag is set to 1 to indicate a locked state. When a subsequent read / write operation command accessing the virtual logical address group in the locked state is received, the subsequent read / write operation command is delayed to prevent the two previous read / write operation commands from conflicting with each other, thereby causing confusion in the data of the virtual logical address group.

[0245] Each read or write command operates at the virtual logical address group granularity. Even if the currently requested cache space only covers one logical address block within a virtual logical address group, the entire virtual logical address group is locked until the current command completes. Only then can the next read or write command targeting the current virtual logical address group be executed. This reduces I / O execution speed somewhat, but it reduces repeated and frequent redundant calculations and wear and tear on the SSD.

[0246] The following describes the cache management method of the non-volatile storage array 200 according to an embodiment of the present application with reference to an example. In this example, the storage status includes a read / write status flag, a full flag, an activity factor flag, and a lock flag, as shown in Table 2-4.

[0247] Table 2-4LBAG status table 2

[0248]

[0249] The activity factor flag bits of the current virtual logical address group are all 0, indicating that the current virtual logical address group has been inactive for a long time and needs to be cleared. The specific steps include:

[0250] S2301: The redundancy module 120 checks the activity factor flag bits of the virtual logical address group and finds that the flag bits are all 0, and determines that the virtual logical address group is of low activity level.

[0251] S2302: For the virtual logical address group of the low activity level, the redundancy module 120 calculates redundant check data based on the data of each LBA_BLOCK in the stripe and writes the redundant check data into the LBA_BLOCK corresponding to the check block, and sets the read / write status flag of the LBA_BLOCK corresponding to the check block to 1.

[0252] S2303, for the virtual logical address group with low activity level, the redundant module 120 uses the cache data in the LBA_BLOCK with the read / write status flag position 1 as the target cache data, submits the write operation instruction to the SSD disk, and writes the target cache data to the disk. After writing to the disk, the target cache data needs to be cleared and the read / write status flag position is set to 0.

[0253] For example, if the current redundancy mode is 4+2, with 4 data blocks and 2 redundancy check blocks, and the number of members in a stripe in the namespace is 6, then the number of members in a stripe in the corresponding virtual logical address group is also 6.

[0254] like Figure 11 As shown, for a virtual logical address group with all activity factor flags set to zero, redundancy calculation is performed based on the data in the logical address blocks LBA_BLOCK5, LBA_BLOCK2, LBA_BLOCK1, and LBA_BLOCK0. The calculated parity data is written to the parity blocks LBA_BLOCK4 and LBA_BLOCK3, and the read / write flags of LBA_BLOCK4 and LBA_BLOCK3 are set to 1. This changes the current read / write flags from 100001 to 111001. An SSD write operation instruction is then issued based on the read / write flags, writing the data in LBA_BLOCK5, LBA_BLOCK4, LBA_BLOCK3, and LBA_BLOCK0 (with the read / write flags set to 1) to the SSD. After the write is complete, the cache occupied by the virtual logical address group is released.

[0255] The following describes the cache management method of the non-volatile storage array 200 according to an embodiment of the present application with reference to another example. In this example, when the cache space corresponding to the current namespace is insufficient, it is necessary to quickly organize virtual logical address groups that can be cleared to free up cache space for storing data for other read / write commands. The specific steps are as follows:

[0256] S2401: The redundancy module 120 detects that the cache space corresponding to the current namespace is insufficient.

[0257] S2402 , the redundancy module 120 checks the full flag corresponding to each virtual logical address group in the LBAG status table, and uses the virtual logical address group with the full flag set to 1 as the target virtual logical address group that needs to be written to disk.

[0258] S2403 , the redundancy module 120 checks the activity factor flag value of the activity factor flag corresponding to the target virtual logical address group, determines the activity level of the target virtual logical address group according to the activity factor flag value, and selects a target virtual logical address group with a low activity level.

[0259] S2404: For the target virtual logical address group with low activity level, the redundancy module 120 calculates redundant check data based on the data of each LBA_BLOCK of the stripe and writes the check data into the LBA_BLOCK corresponding to the check block.

[0260] At S2405, for the target virtual logical address group with a low activity level, the redundancy module 120 sets the cached data in the LBA_BLOCK with the read / write status flag set to 1 as the target cached data, submits a write instruction to the SSD, and writes the target cached data to the SSD. After writing to the SSD, the target cached data is cleared. Furthermore, after sending the data read from the non-volatile storage array 200 to the remote host 300, the cached data in the LBA_BLOCK with the read / write status flag set to 0 is also cleared.

[0261] To increase the speed of data read and write processing for a storage array, for example, to increase the speed of determining a first cache subspace and a second cache subspace in a controller memory, the present application further provides a storage array data read and write method. The redundancy module in the present application implements a storage array data read and write method of the present application.

[0262] The storage array data reading and writing method is described below with reference to some specific embodiments.

[0263] In the embodiment of the present application, the redundancy module 120 performs cache management on the controller memory 140 (hereinafter referred to as cache) according to the current redundancy mode and the number of NS (Namespace). Exemplarily, the storage array data reading and writing method includes the following steps:

[0264] S3210: Determine a corresponding cache address space in a cache space management table according to an index of a target address stripe in a command to access the storage array.

[0265] Furthermore, in the embodiment of the present application, the non-volatile storage array 200 is mapped into a virtual logical address space based on each namespace. For each logical address in the non-volatile storage array 200, there is a unique virtual logical address (Vir_LBA) corresponding to it in the virtual logical address space. The virtual logical address is used to determine the logical address in the non-volatile storage array 200 to be accessed.

[0266] The virtual logical address space is divided according to the number of each namespace to obtain virtual logical address subspaces corresponding to each namespace one by one. Thus, the virtual logical address subspaces are obtained by division, as shown in Table 3-1.

[0267] Table 3-1 Correspondence between namespace and virtual logical address subspace

[0268] Namespace Virtual logical address subspace NameSpace 1 VIR_LBA0-VIR_LBA99 NameSpace 1 VIR_LBA100-VIR_LBA249 … … NameSpace x VIR_LBAm-VIR_LBAn

[0269] Furthermore, in order to improve performance and facilitate management, the virtual logical address subspace corresponding to the namespace is divided into a namespace array according to the redundancy mode of the non-volatile storage array 200. A row of virtual logical addresses in the namespace array is regarded as a stripe, thereby obtaining the target address stripe. That is, the allocation granularity of the VIR_LBA in the NS is set according to the redundancy mode of the SSD hard disk (the SSD hard disk in the non-volatile storage array 200), and the VIR_LBA in the NS is divided into LBA stripes according to the number of members in the redundancy group of the SSD hard disk, such as Figure 12 shown.

[0270] Furthermore, determining the corresponding cache address space in the cache space management table according to the index of the target address stripe includes:

[0271] S3211: Determine a target namespace and a target virtual logical address to be accessed according to an access command to the non-volatile storage array 200. The access command includes the target namespace and the target virtual logical address.

[0272] S3212: Determine the target address stripe according to the target namespace and the target virtual logical address.

[0273] In one embodiment, determining the corresponding cache address space in the cache space management table according to the index of the target address stripe includes:

[0274] Matching the cache address space in the cache space management table according to the index;

[0275] If the match fails, the cache address space is obtained by partitioning the target address stripe from the controller memory 140 ;

[0276] If the match is successful, the index is obtained, and the corresponding cache address space in the cache space management table is obtained.

[0277] Furthermore, to facilitate cache space management, in an embodiment of the present application, a cache space management table is established based on the index of the stripe. It is understandable that the method further includes: storing the divided cache address space into the cache space management table based on the sequence number of the target address stripe. After allocating cache space (cache address space) from the controller memory for a stripe, the address of the cache space is written into the cache space management table. As shown in Table 3-2, the cache space management table records the physical address (Physics Block Address, PBA) of the controller memory corresponding to each stripe.

[0278] Table 3-2 Cache space management table

[0279]

[0280] When a cache search is needed, the index of the stripe mapped to the virtual logical address corresponding to the access command is first determined. Then, based on the stripe index, the cache space management table is checked to see if cache space is allocated for that stripe. This application uses NS as the management unit, the index of the stripe where the virtual logical address is located as the KEY, and the Value of each physical address bit allocated to the stripe to construct a key-value pair. When read or write commands need to search for data stored in the cache space, they can quickly hit the target.

[0281] S3220 , cache the read and write data determined based on the access command to the non-volatile storage array 200 in the controller memory 140 according to the cache address space.

[0282] When any VIR_LBA within a stripe is used, the virtual logical address of the entire stripe in which the VIR_LBA is located is allocated, and cache space for the entire stripe is requested. For example, if a write data command for NS1 is received with a data length of 5, virtual logical addresses VIR_LBA0-VIR_LBA4 are assigned. Since VIR_LBAs are allocated and managed on a stripe-by-strip basis, stripe 1 is assigned to the current write data command, and sufficient cache space is requested from controller memory 140 for this stripe to cache the incoming write data. The received write data is cached in the cache space corresponding to LBA0-LBA4.

[0283] S3230: If the access command is a read command, read the target data and pre-read data according to the target address stripe and cache them in the controller memory.

[0284] In one embodiment, in order to significantly reduce the latency of read commands, the present application supports pre-reading data. It can be understood that the cache address space is used to cache the read and write data determined based on the access command to the non-volatile storage array 200 to the controller memory 140, including:

[0285] If the access command is a read command, obtaining the virtual logical address segment of the target data and the continuous virtual logical address segments adjacent thereto according to the target address stripe;

[0286] Target data and pre-read data are read from the non-volatile storage array 200 according to the virtual logical address segment and cached into the controller memory.

[0287] S3240: Send the target data.

[0288] The target data requested by the read command is sent to the host, and then the target data and the pre-read data are retained in the controller memory 140 so as to be directly read from the controller memory 140 by subsequent access commands related to the virtual logical address segment.

[0289] For example, when a read command is received, a command to read the relevant continuous addresses is generated based on the target access address of the read command and passed to the redundancy module 120 (EC / RAID). The redundancy module 120 reads data from the non-volatile storage array 200 based on the relevant continuous addresses and caches the read data in the controller memory. When the IOQ processor 113 subsequently receives a command to access the relevant continuous addresses, it can quickly retrieve the above data from the controller memory, thereby significantly reducing the latency of the read command.

[0290] In one embodiment, the method further comprises:

[0291] If the access command is a read command, determining the target address stripe to which the virtual logical address segment to be accessed by the read command belongs according to the virtual logical address segment to be accessed;

[0292] Matching a target cache address space in the cache space management table according to the index of the target address stripe;

[0293] If the match is successful, the pre-read data is read from the target cache address space according to the cache address to be accessed by the read command.

[0294] In one embodiment, the present application not only supports write termination, greatly reduces write latency, but also identifies the activity level of data in the controller memory to reduce wear on the SSD hard drive. Understandably, the method further comprises: writing write data cached in the controller memory 140 to the non-volatile storage array 200 according to the activity level of the data. Under the premise of the write termination mechanism, the present application enables the redundancy module 120 to identify the activity level of data in the controller memory, temporarily store active data in the cache space, and not perform disk landing. When subsequent write commands update the data, they can be directly completed in the cache space, reducing wear on the SSD hard drive.

[0295] In one embodiment, the present application supports write summary function. When the redundancy module 120 writes data corresponding to the write command to the controller memory 140 managed by the redundancy module, it can send command completion information CQ to the remote host 300, without waiting for the data to be truly written to the SSD disk, thus greatly reducing the write latency. Understandably, in step S220, the caching of read-write data determined based on access commands to the non-volatile storage array 200 to the controller memory 140 according to the cache address space comprises:

[0296] If the read-write data is write data, after caching the write data to the controller memory 140, the command completion information is sent to the remote host 300.

[0297] Further, if the read-write data is write data, after caching the write data to the controller memory 140, the command completion information is sent to the remote host 300, comprising:

[0298] Performing integrity check on the write data.

[0299] If the check fails, sending a prompt message of data write error to the remote host 300;

[0300] If the check passes, sending command completion information to the remote host 300.

[0301] In one embodiment, the present application not only supports write termination, greatly reduces write latency, but also identifies the activity level of data in the controller memory 140 to reduce wear on the SSD hard drive. Understandably, the method further comprises: writing write data cached in the controller memory 140 to the non-volatile storage array 200 according to the activity level of the data. Under the premise of the write termination mechanism, the present application enables the redundancy module 120 to identify the activity level of data in the controller memory 140, temporarily store active data in the cache space, and not perform disk landing. When subsequent write commands update the data, they can be directly completed in the cache space, reducing wear on the SSD hard drive.

[0302] The following describes the storage array data reading and writing method according to an embodiment of the present application with reference to an example of a write command, which specifically includes the following steps:

[0303] S3301: The redundancy module 120 receives a write command and determines the stripe to which it is mapped based on the namespace and target virtual logical address accessed by the current write command.

[0304] S3302: Based on the stripe's index, the established cache space management table is checked to see if the stripe is in the cache. If the stripe is in the cache, indicating that a cache address space (e.g., PBAx-PBAy) has been allocated for the stripe, then step S3304 is executed. If not, indicating that no cache address space has been allocated for the stripe, then step S3303 is executed.

[0305] S3303: Apply for a cache address space in the controller memory 140 for the stripe, for example, PBAx-PBAy.

[0306] S3304, sending R2T (Ready to Transfer, indicating that the cache address space is ready) to the host to instruct the remote host 300 to send the data to be written.

[0307] In step S3305, the redundancy module 120 performs an integrity check on the data to be written. If the check fails, a CQ with an error message is sent to the remote host 300; if the check passes, a CQ with a completion status (corresponding to command completion information) is sent and step S3306 is executed.

[0308] S3306: Store the data to be written after integrity verification into the allocated cache address space.

[0309] The following describes the storage array data reading and writing method according to an embodiment of the present application with reference to an example of a read command, which specifically includes the following steps:

[0310] S3401: The redundancy module 120 receives a read command and determines the mapped stripe according to the namespace and target virtual logical address accessed by the current read command.

[0311] S3402: Query the cache space management table based on the index of the stripe to see if the stripe is in the cache. If the stripe is in the cache, execute step S3404; if not, execute step S3403.

[0312] S3403: Apply for a cache address space, such as PBAm-PBAn, in the controller memory 140 for the stripe.

[0313] S3404, determine whether the physical address corresponding to the virtual logical address of the stripe is used; if it is used, it means that pre-read data already exists, and then directly read the pre-read data cached at the physical address and use the pre-read data as the read data.

[0314] If it is not in use, a pre-read command is initiated to the SSD hard disk to read the data corresponding to the entire stripe, and the pre-read data read is stored in the allocated cache address space.

[0315] S3405, returning the read data in the physical address corresponding to the target virtual logical address to the remote host 300.

[0316] The present application also provides a terminal device. Exemplarily, the terminal device includes a processor and a memory, wherein the memory stores a computer program, and the processor runs the computer program to enable the terminal device to execute the functions of the above-mentioned namespace-based cache management method or the various modules in the above-mentioned namespace-based cache management device.

[0317] Among them, the processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including a central processing unit (CPU), a graphics processing unit (GPU) and a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or at least one of other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc., which can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present application.

[0318] The memory may be, but is not limited to, a random access memory (RAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc. The memory is used to store a computer program, and the processor may execute the computer program accordingly after receiving an execution instruction.

[0319] The present application also provides a computer-readable storage medium for storing the computer program used in the terminal device. For example, the computer-readable storage medium may include, but is not limited to, various media capable of storing program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0320] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or flowchart, and the combination of boxes in the structure diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0321] In addition, the functional modules or units in the various embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0322] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a smart phone, personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application.

[0323] The above is only a specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the scope of protection of the present application.

Claims

1. A namespace-based cache management method, characterized in that: Applied to a storage array controller, the storage array controller being an external controller of a storage array, the storage array controller comprising a storage interface control module, a redundancy module, a controller memory, and a non-volatile storage control module, wherein the redundancy module is respectively connected to the storage interface control module, the non-volatile storage control module, and the controller memory, the method comprising: Allocating a cache area for the access command in a static cache subspace according to a namespace to be accessed by the access command, specifically comprising: obtaining a virtual logical address subspace according to the namespace matching; allocating a target virtual logical address for the access command from the virtual logical address subspace; and allocating the cache area for the target virtual logical address from a static cache subspace uniquely corresponding to the namespace; receiving target data for reading and writing the storage array based on the access command, and caching the target data in the cache area; The static cache subspace is obtained by dividing the static cache space in the controller memory according to the namespace; The virtual logical address subspace is obtained by the following division method: Mapping the storage array into a virtual logical address space according to each of the namespaces; The virtual logical address space is divided according to the number of namespaces to obtain virtual logical address subspaces corresponding to each namespace.

2. The namespace-based cache management method according to claim 1, characterized in that: The static cache subspace is obtained by the following division method: The static cache space is divided according to the number of the namespaces using a preset capacity allocation rule to obtain static cache subspaces corresponding to the respective namespaces.

3. The namespace-based cache management method according to claim 1, characterized in that: The allocating a target virtual logical address for the access command from the virtual logical address subspace includes: When the access command is to access any virtual logical address in a stripe, the stripe is assigned to the access command as the target virtual logical address; The stripes are divided by the following method: Dividing the virtual logical address subspace into a namespace array according to a redundancy mode of the storage array, wherein a row of virtual logical addresses in the namespace array serves as a stripe; Allocating the cache area for the target virtual logical address from the static cache subspace uniquely corresponding to the namespace includes: If the cache area is not matched according to the stripe, a cache area is allocated to the stripe from the static cache subspace corresponding to the namespace according to the capacity of the stripe.

4. The namespace-based cache management method according to claim 1, characterized in that: The controller memory also includes a dynamic shared cache space; The method further comprises: When the static cache subspace corresponding to the namespace is full, a storage area of ​​preset capacity is requested from the dynamic shared cache space for the namespace.

5. The namespace-based cache management method according to claim 4, characterized in that: Also includes: Determining whether to approve the application based on the current capacity of the space, the current capacity of the space group, and preset space capacity thresholds and space group capacity thresholds; The current capacity of the space is the current capacity of the static cache subspace obtained by the namespace; the current capacity of the space group is the sum of the current capacities of the static cache subspaces obtained by each namespace included in the namespace group.

6. The namespace-based cache management method according to claim 4, characterized in that: The method further comprises: When the static cache subspace is full, if it is determined that the application is not approved, the write data and / or pre-read data in the static cache subspace corresponding to the namespace is cleared.

7. The namespace-based cache management method according to claim 3, characterized in that: If the access command is a read command for reading a first virtual logical address, determining the stripe in which the first virtual logical address is located according to the first virtual logical address; Reading the read data corresponding to the stripe in the storage array; The read data is cached in a cache area corresponding to the stripe to serve as pre-read data for subsequent reading of other addresses in the stripe except the first virtual logical address.

8. The namespace-based cache management method according to claim 2, characterized in that: The utilizing a preset capacity allocation rule to divide the static cache space according to the number of namespaces includes: Dividing the static cache space evenly according to the number of namespaces; Alternatively, the namespaces may be divided according to a preset capacity ratio of each namespace.

9. The namespace-based cache management method according to claim 5, characterized in that: Allocating a cache area for the access command in the static cache subspace according to the namespace to be accessed by the access command includes: Execute access commands in different namespace groups in parallel, and allocate cache areas for corresponding access commands in corresponding static cache subspaces according to the namespaces to be accessed; The namespace group is divided in the following manner: each namespace in the hard disk group of the storage array is divided into a namespace group.

10. A storage array controller, characterized in that: It includes a storage interface control module, a redundancy module, a controller memory and a non-volatile storage control module; The redundancy module is respectively connected to the storage interface control module, the non-volatile storage control module and the controller memory; The redundancy module is used to implement the namespace-based cache management method according to any one of claims 1 to 9.

11. A cache management device based on namespace, characterized in that: Applied to a storage array controller, the storage array controller is an external controller of a storage array, the storage array controller includes a storage interface control module, a redundancy module, a controller memory, and a non-volatile storage control module, the redundancy module is respectively connected to the storage interface control module, the non-volatile storage control module, and the controller memory, the device includes: a cache area allocation module and a data cache module; A cache area allocation module is configured to allocate a cache area in a static cache subspace to an access command based on a namespace to be accessed by the access command. The cache area allocation module is specifically configured to: obtain a virtual logical address subspace based on the namespace matching; allocate a target virtual logical address to the access command from the virtual logical address subspace; and allocate the cache area to the target virtual logical address from the static cache subspace uniquely corresponding to the namespace. The virtual logical address subspace is obtained by the following division method: mapping the storage array into a virtual logical address space based on each of the namespaces; and dividing the virtual logical address space based on the number of namespaces to obtain virtual logical address subspaces corresponding to each of the namespaces. a data cache module, configured to receive target data to be read or written from the storage array based on the access command, and cache the data in the cache area; The static cache subspace is obtained by dividing the static cache space in the controller memory according to the namespace.

12. A terminal device, characterized in that: The terminal device includes a processor and a memory, the memory stores a computer program, and the processor is configured to execute the computer program to implement the namespace-based cache management method according to any one of claims 1 to 9.

13. A computer-readable storage medium, characterized in that The computer program is stored therein, and when the computer program is executed on a processor, the namespace-based cache management method according to any one of claims 1 to 9 is implemented.

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