Method, system, device and storage medium for high-speed communication between dual-core processors

Abstract

The application discloses a high-speed communication method, system and device between dual-core processors and a storage medium, and relates to the technical field of communication. The method comprises the following steps: allocating a shared area in a memory and establishing a communication channel; a processor divides a piece of memory managed by the processor into memory blocks with a fixed size, and forms a memory pool by using memory block pointers; obtaining a memory block pointer from the memory pool, and managing the pointer by using a ring buffer structure; a data writing end obtains a memory block pointer pointed by a writing pointer from a ring buffer managed by a data reading end, and writes data into the memory block pointed by the writing pointer; the data reading end obtains and uses the memory block pointer according to a reading pointer; a new memory block pointer is obtained from the memory pool to replace the read memory block pointer; and the data reading end returns the used memory block pointer to the memory pool. The method uses a memory block pointer as a communication medium to avoid direct data copying, improves data transmission efficiency and reduces delay, and is suitable for high real-time application scenarios.

Description

Technical Field

[0001] This invention belongs to the field of dual-core communication technology, specifically relating to a high-speed communication method, system, computer device, and storage medium between dual-core processors. Background Technology

[0002] With the rapid development of computer communication technology, the demand for data transmission between processors is constantly increasing, especially in multi-core processor systems, where the communication efficiency between processors directly affects the overall system performance and real-time performance. However, existing inter-processor communication methods mainly rely on data copying and transmission using buffers, which shows significant shortcomings in scenarios involving large amounts of data or high real-time requirements.

[0003] Frequent data copying operations significantly reduce communication efficiency and introduce additional latency. As the amount of data increases, the system's communication overhead rises significantly, impacting the overall processing speed.

[0004] Therefore, existing technologies still have unresolved issues regarding high-speed, low-latency communication between processors. A new inter-processor communication method is needed to address these problems. Summary of the Invention

[0005] The main objective of this invention is to overcome the shortcomings and deficiencies of the prior art and provide a high-speed communication method, system, computer device, and storage medium between dual-core processors.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] In a first aspect, the present invention provides a high-speed communication method between dual-core processors, applied to dual-core processors, wherein the dual-core processors are respectively connected to memory, and the high-speed communication method includes the following steps:

[0008] S1. Allocate a shared area in memory and establish a communication channel;

[0009] S2. The dual-core processor divides the memory it manages into fixed-size memory blocks and uses the memory block pointers to form a memory pool.

[0010] S3. Obtain memory block pointers from the memory pool and manage the memory block pointers using a circular buffer structure;

[0011] S4. The data writing end obtains the memory block pointer pointed to by the write pointer from the circular buffer managed by the data reading end, and writes the data into the memory block pointed to by the memory block pointer.

[0012] S5. The data reading end obtains and uses the memory block pointer based on the read pointer;

[0013] S6. The data reading end obtains a new memory block pointer from the memory pool to replace the already read memory block pointer;

[0014] S7. After the data reading end is finished, the memory block pointer will be returned to the memory pool.

[0015] Further, step S1 specifically includes:

[0016] A region is allocated in memory as a shared area for the dual-core processors. The size of this shared area is determined by actual needs, and it allows both processors to access it simultaneously. The shared area is divided into four parts: a channel information area, a circular buffer structure area, a memory block area, and an idle area. The channel information area stores the channel name, the base address of the circular buffer for processor 0, the base address of the circular buffer for processor 1, the number of buffer units N, the memory block size, and the base addresses of the memory block areas for processor 0 and processor 1. This area provides channel information to the processors and ensures consistency in the channel information obtained by the two processors. The circular buffer structure area stores the circular buffers managed by the two processors. The memory block area is used by the processors to partition the memory into memory pools. The idle area represents unused remaining memory, which can be allocated according to actual needs.

[0017] Furthermore, in step S2, each processor divides the portion of the memory block region it manages, as follows:

[0018] S2.1 The two processors obtain the memory block size from the channel information area, and divide the memory block from the portion managed by each processor in the memory block area according to the predefined memory pool size.

[0019] S2.2 Each processor creates a queue to store pointers, placing pointers to memory blocks into the pointer queue to form a memory pool. Establishing a memory pool facilitates processor management of memory blocks, and this memory pool allows processors to obtain pointers to memory blocks.

[0020] Furthermore, in step S3, memory block pointers are obtained from the memory pool, and a circular buffer structure is used to manage the pointers. The specific steps are as follows:

[0021] The processor obtains the base address and the number of buffer units N of the corresponding circular buffer from the channel information region. Starting at the base address, a circular buffer structure is created. This circular buffer structure includes a buffer header and N buffer units. The buffer header contains information such as the buffer write pointer, read pointer, and the number of buffer units. The buffer header allows simultaneous access by two processors; the data reading end is only allowed to modify the read pointer, and the data writing end is only allowed to modify the write pointer. Each buffer unit contains a memory block pointer and the length of the stored data. The processor extracts N memory block pointers from the memory pool to fill an equal number of buffer units to initialize the circular buffer. The memory block pointers within the buffer units serve as a communication medium between the two processors; the read and write pointers enable the processor to locate the memory block pointers within the corresponding buffer units.

[0022] Furthermore, step S4 specifically involves the following steps:

[0023] S4.1 The data writing end obtains the base address of the circular buffer of the data reading end from the channel information area, and finds the buffer table head through the base address of the circular buffer to obtain the write pointer.

[0024] S4.2. The data writing end obtains a memory block pointer based on the buffer unit pointed to by the write pointer, copies the data to be written into the memory block, and sets the length of the stored data in the buffer unit to that data length. The length of the data to be written should be less than or equal to the size of the memory block to avoid memory overflow issues.

[0025] S4.3 After the write operation is completed, the write pointer moves one position to the right. If it reaches the end of the circular buffer, it will point to the beginning of the circular buffer again.

[0026] Furthermore, step S5 specifically involves the following steps:

[0027] S5.1 The data reading end obtains its own ring buffer base address from the channel information area, and finds the buffer table head through the ring buffer base address to obtain the read pointer;

[0028] S5.2 The data reading end retrieves the memory block pointer and the length of the stored data based on the buffer unit pointed to by the read pointer. After retrieving the memory block pointer, the data reading end can read the corresponding data from that memory block according to the length of the stored data.

[0029] Further, step S6 specifically includes the following steps:

[0030] S6.1 After retrieving the memory block pointer, the data reading end obtains a new memory block pointer from the local memory pool to replace the original pointer. This is done to prevent the retrieved memory block pointer from being repeatedly written by the data writing end, thereby allowing the data reading end to arbitrarily control the memory block pointer it retrieves;

[0031] S6.2 After the replacement operation is completed, the read pointer moves one position to the right. If it reaches the end of the circular buffer, it will point to the beginning of the circular buffer again.

[0032] Further, step S7 specifically includes:

[0033] After the data reading end finishes using the memory block pointer retrieved in step S5.2 at any location, it must put the memory block pointer back into the memory pool so that the memory block pointer can be reassigned and used in subsequent operations, thereby ensuring that the pointers in the memory pool are effectively managed and recycled.

[0034] In a second aspect, the present invention provides a high-speed communication system between dual-core processors for executing the above-described high-speed communication method between dual-core processors, the high-speed communication system comprising:

[0035] The communication channel establishment module is used to allocate a shared area in memory and establish a communication channel.

[0036] The memory partitioning module is used by dual-core processors to partition the memory they each manage into fixed-size memory blocks and to form a memory pool by arranging the memory block pointers.

[0037] The memory block pointer management module is used to obtain memory block pointers from the memory pool and manage the memory block pointers using a circular buffer structure.

[0038] The data writing module is used by the data writing end to obtain the memory block pointer pointed to by the write pointer from the circular buffer managed by the data reading end, and write the data into the memory block pointed to by the memory block pointer.

[0039] The first data reading module is used by the data reading end to obtain and use the memory block pointer according to the read pointer;

[0040] The second data reading module is used by the data reading end to obtain a new memory block pointer from the memory pool to replace the already read memory block pointer;

[0041] The third data reading module is used by the data reading end to return the memory block pointers to the memory pool after use.

[0042] Thirdly, the present invention provides a computer device including a processor and a memory for storing processor-executable programs, wherein when the processor executes the program stored in the memory, it implements the above-described high-speed communication method between dual-core processors.

[0043] Fourthly, the present invention provides a storage medium storing a program, which, when executed by a processor, implements the above-described high-speed communication method between dual-core processors.

[0044] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0045] 1. This invention employs a shared memory and circular buffer design, utilizing memory block pointers as a communication medium. On one hand, using memory block pointers as a communication medium allows the processor to manage memory more flexibly. On the other hand, this method effectively reduces frequent data copy operations, significantly improving data transmission efficiency and reducing communication latency.

[0046] 2. This invention has excellent scalability. By simply modifying the channel configuration within the channel information area, this invention can be easily expanded to adapt to different communication scenarios. Users can flexibly adjust it according to actual application scenarios, ensuring the system's scalability.

[0047] 3. This invention supports the instantiation of multiple channels. By adding new channel information in the channel information area, multiple communication channels can be constructed and managed in parallel. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a flowchart of the steps of a high-speed communication method between dual-core processors disclosed in Embodiment 1 of the present invention;

[0050] Figure 2 This is a high-speed channel flowchart of a high-speed communication method between dual-core processors disclosed in Embodiment 1 of the present invention;

[0051] Figure 3 This is a memory space allocation diagram of a high-speed communication method between dual-core processors disclosed in Embodiment 1 of the present invention;

[0052] Figure 4 This is a structural block diagram of a dual-core, dual-system data communication example in Embodiment 1 of the present invention;

[0053] Figure 5 This is a schematic diagram of the channel information area in Embodiment 2 of the present invention;

[0054] Figure 6 This is a structural block diagram of a high-speed communication system between dual-core processors according to Embodiment 4 of the present invention;

[0055] Figure 7 This is a structural block diagram of the computer device in Embodiment 5 of the present invention. Detailed Implementation

[0056] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort are within the scope of protection of the present application.

[0057] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application can be combined with other embodiments.

[0058] Example 1

[0059] refer to Figure 4 This embodiment provides a high-speed communication system between dual-core processors. The system has one memory and two processors. The two processors run different operating systems: a Linux system and a bare kernel. Within the Linux system, the application is responsible for sending data to and receiving data from the high-speed channel, while the kernel driver maintains the high-speed channel. The bare kernel program within the bare kernel is responsible for maintaining the high-speed channel and also for sending and receiving data. The specific steps are as follows:

[0060] S1. Allocate a shared area in memory and establish a communication channel;

[0061] S2. The dual-core processor divides the memory it manages into fixed-size memory blocks and uses the memory block pointers to form a memory pool.

[0062] S3. Obtain memory block pointers from the memory pool and manage the pointers using a circular buffer structure;

[0063] S4. The data writing end obtains the memory block pointer pointed to by the write pointer from the circular buffer managed by the data reading end, and writes the data to the memory block pointed to by the pointer.

[0064] S5. The data reading end obtains and uses the memory block pointer based on the read pointer;

[0065] S6. The data reading end obtains a new memory block pointer from the memory pool to replace the already read memory block pointer;

[0066] S7. After the data reading end is finished, the memory block pointer will be returned to the memory pool.

[0067] In this embodiment, step S1 specifically involves: allocating a region in memory as a shared region for the two processors. For example... Figure 3 As shown. The size of the shared region is determined by actual needs, and this region allows two processors to access it simultaneously. The shared region is divided into four parts: a channel information region, a ring buffer structure region, a memory block region, and an idle region. The channel information region stores the channel name, the base address of the ring buffer for processor 0, the base address of the ring buffer for processor 1, the number of buffer units N, the memory block size, the base address of the memory block region for processor 0, and the base address of the memory block region for processor 1. The ring buffer structure region stores the ring buffers managed by the two processors. The memory block region is used for processors to partition the memory to form a memory pool. The idle region represents unused remaining memory, which can be allocated according to actual needs. The channel information region is detailed as follows... Figure 5 As shown.

[0068] like Figure 3 The diagram illustrates the memory space allocation for a high-speed inter-core communication method, where the entire memory space is divided into three parts: processor 0's running memory, processor 1's running memory, and shared memory. The shared memory includes channel information, a circular buffer structure for processor 0, a circular buffer structure for processor 1, a memory block area for processor 0, a memory block area for processor 1, and an idle area. In this embodiment, processor 0 runs a Linux system, while processor 1 does not run an operating system and is a bare-core processor.

[0069] In this embodiment, in step S2, each processor divides the portion of the memory block region it manages. The specific steps are as follows:

[0070] S2.1 The processor obtains the memory block size from the channel information area and divides the memory block area into memory blocks according to the predefined memory pool size.

[0071] In the Linux processor kernel driver, the address of the predefined memory region is found. Figure 3The channel information area shown indicates that the memory block size B is read. Then, the base address of the processor 0 memory block region is located, which is the base address of the memory block region managed by the Linux system processor. Starting from this base address, the processor 0 memory block region is divided into P memory blocks of size B, where the memory pool size is set during program initialization. Similarly, in the bare-core program of the bare-core processor, the memory block size is obtained according to the pre-defined memory region address, and then the processor 1 memory block region is divided according to the memory pool size.

[0072] S2.2 After the segmentation, the pointers to each memory block are stored in a pointer queue to form a memory pool.

[0073] In the Linux processor kernel driver, a queue q is created to store pointers; this queue is initialized to empty. After the memory pool region is divided, the memory block pointers corresponding to P memory blocks are placed into the queue. Similarly, the bare-metal processor also needs to create a queue q to store pointers and place the memory block pointers corresponding to memory blocks into the queue.

[0074] In this embodiment, step S3 involves obtaining memory block pointers from the memory pool and managing the pointers using a circular buffer structure, as detailed below:

[0075] In the Linux processor's kernel driver, the base address of the processor 0 circular buffer and the number of buffer units N are obtained from the channel information region. Starting at the base address of the processor 0 circular buffer, a circular buffer structure is created. This circular buffer structure contains a buffer header and N buffer units. The buffer header contains information such as buffer write pointers, read pointers, and the number of buffer units. Each buffer unit contains a memory block pointer and the length of the stored data. The processor retrieves N memory block pointers from the memory pool to fill an equal number of buffer units to initialize the circular buffer.

[0076] In the bare-core program of the bare-core processor, the base address of the processor 1 ring buffer and the number of buffer units N are obtained from the channel information region. Similar to the above operation, a ring buffer structure is created starting at the processor ring buffer base address.

[0077] In this embodiment, step S4 is specifically as follows:

[0078] S4.1 The data writing end obtains the base address of the circular buffer of the data reading end from the channel information area, and finds the buffer table head through the base address of the circular buffer to obtain the write pointer.

[0079] refer to Figure 2In this example, the bare-core processor, i.e., processor 1, is the data writing end. In the bare-core program, the bare-core processor first finds the base address of the ring buffer managed by the Linux processor 0 through the channel information area, and then finds the buffer table head under that base address to obtain the write pointer.

[0080] S4.2. The data writing end obtains the memory block pointer based on the buffer unit pointed to by the write pointer, copies the data to be written into the memory block, and sets the length of the stored data in the buffer unit to the data length.

[0081] The bare-core processor obtains a memory block pointer p2 from the buffer cell pointed to by the write pointer. This pointer indicates the memory block where data can currently be written. The data to be written is copied to the memory block pointed to by memory block pointer p2, and the length l2 of the data stored in the buffer cell is set to the length of the data to be written. This length must not exceed the memory block size B; otherwise, a memory out-of-bounds error will occur.

[0082] S4.3 After the write operation is completed, the write pointer moves one position to the right. If it reaches the end of the circular buffer, it will point to the beginning of the circular buffer again.

[0083] After a write operation is complete, the bare-core processor needs to modify the write pointer information at the head of the buffer table, moving its position to point to the next buffer cell. If the currently pointed-to buffer cell is already the last one, it is moved to point to the first buffer cell.

[0084] In this embodiment, step S5 is specifically as follows:

[0085] S5.1 The data reading end obtains its own ring buffer base address from the channel information area, and finds the buffer table head through the ring buffer base address to obtain the read pointer;

[0086] refer to Figure 2 In this example, the Linux processor, specifically processor 0, is the data read end. The Linux processor first locates the base address of the processor 0 circular buffer through the channel information region in the kernel driver, and then finds the buffer table head at that base address to obtain the read pointer.

[0087] S5.2 The data reading end retrieves the memory block pointer and the length of the stored data based on the buffer unit pointed to by the read pointer. The data reading end can then read the corresponding data from that memory block according to the length of the stored data.

[0088] In the Linux kernel driver, the processor retrieves the memory block pointer p1 and the data length l1 from the buffer cell pointed to by the read pointer. After retrieving the memory block pointer p1 and the data length l1, the processor delivers the data to the application in the Linux processor at the memory block pointed to by the memory block pointer p1, according to the data length l1.

[0089] In this embodiment, step S6 is specifically as follows:

[0090] S6.1 After retrieving the memory block pointer, the data reading end needs to obtain a new memory block pointer from the local memory pool of the data reading end to replace the above memory block pointer;

[0091] refer to Figure 2 After retrieving the memory block pointer p1 from the Linux processor (processor 0), it needs to obtain a new memory block pointer p from the pointer queue q (processor 0's memory pool) described in S2.2. new And put it back into the buffer cell where the memory block pointer p1 is located.

[0092] S6.2 After the replacement operation is completed, the pointer moves one position to the right. If it reaches the end of the circular buffer, it will point to the beginning of the circular buffer again.

[0093] After the above replacement operation is completed, the Linux processor modifies the read pointer information of the buffer table header, moving its position to point to the next buffer cell. If the currently pointed-to buffer cell is already the last one, it is moved to point to the first buffer cell.

[0094] In this embodiment, step S7 involves the data reading end returning the memory block pointer to the memory pool after use, specifically as follows:

[0095] After the Linux processor passes the data stored in memory block pointer p1 to the application in the kernel driver, it needs to put the memory block pointer p1 back into the pointer queue q, i.e., the processor 0 memory pool.

[0096] Example 2

[0097] refer to Figure 4 This embodiment provides a set of experimental data, which is based on the high-speed communication method disclosed in Embodiment 1. The experimental content is as follows:

[0098] Run a test program on a Linux processor. Its function is to generate test data, with the data size randomly generated between 50 and 1600 bytes, which is consistent with the size of an Ethernet packet. Send the test data to the bare kernel through a high-speed channel maintained by the kernel driver. Obtain the data sent by the bare kernel through the high-speed channel through the kernel driver. Compare whether the sent data and the received data are the same. Measure the time difference between sending and receiving the data. Repeat the above steps 50,000 times and sum and average the time differences.

[0099] Set the bare-core program of the bare-core processor as a test program, whose functions include receiving data from the Linux processor through the high-speed channel; and sending the data received from the high-speed channel to the Linux processor through the high-speed channel.

[0100] The high-speed communication method between dual-core processors includes the following steps:

[0101] S1. Allocate a shared area in memory and establish a communication channel;

[0102] S2. The dual-core processor divides the memory it manages into fixed-size memory blocks and uses the memory block pointers to form a memory pool.

[0103] S3. Obtain memory block pointers from the memory pool and manage the pointers using a circular buffer structure;

[0104] S4. The data writing end obtains the memory block pointer pointed to by the write pointer from the circular buffer managed by the data reading end, and writes the data to the memory block pointed to by the pointer.

[0105] S5. The data reading end obtains and uses the memory block pointer based on the read pointer;

[0106] S6. The data reading end obtains a new memory block pointer from the memory pool to replace the already read memory block pointer;

[0107] S7. After the data reading end is finished, the memory block pointer will be returned to the memory pool.

[0108] The content of the above method embodiments is applicable to this embodiment. In this embodiment, after the above tests, it was found that after 50,000 data loopback tests, the average time of this high-speed communication method was 27µs. In the same system, compared with the traditional dual-core processor communication method, the average time of the traditional method is 40µs. Therefore, this high-speed communication method can effectively improve communication efficiency.

[0109] Example 3

[0110] This embodiment provides a high-speed communication method between dual-core processors, which can be applied to, for example... Figure 4 The dual-core processor shown includes two high-speed channels, denoted as high-speed channel 0 and high-speed channel 1. In this embodiment, by creating two high-speed channels, the dual-core processor is allowed to transmit data in parallel through two different high-speed channels.

[0111] The high-speed communication method between dual-core processors includes the following steps:

[0112] S1. Allocate a shared area in memory and establish a communication channel;

[0113] S2. The dual-core processor divides the memory it manages into fixed-size memory blocks and uses the memory block pointers to form a memory pool.

[0114] S3. Obtain memory block pointers from the memory pool and manage the pointers using a circular buffer structure;

[0115] S4. The data writing end obtains the memory block pointer pointed to by the write pointer from the circular buffer managed by the data reading end, and writes the data to the memory block pointed to by the pointer.

[0116] S5. The data reading end obtains and uses the memory block pointer based on the read pointer;

[0117] S6. The data reading end obtains a new memory block pointer from the memory pool to replace the already read memory block pointer;

[0118] S7. After the data reading end is finished, the memory block pointer will be returned to the memory pool.

[0119] In this embodiment, the difference between step S1 and embodiment 1 is as follows:

[0120] refer to Figure 5 In the channel information area, the information for high-speed channel 0 is stored first, including the channel name "HSCH0", the base address of the processor 0 ring buffer (0x11100000), the base address of the processor 1 ring buffer (0x11103E90), the number of buffer units (1600), the memory block size (2000), the base address of the processor 0 memory block region (0x1150FA80), and the base address of the processor 1 memory block region (0x11CB3390). Then, the information for high-speed channel 1 is stored, including the channel name "HSCH1", the base address of the processor 0 ring buffer (0x11107D20), the base address of the processor 1 ring buffer (0x1110BBB0), the number of buffer units (2000), the memory block size (1600), the base address of the processor 0 memory block region (0x12456CA0), and the base address of the processor 1 memory block region (0x12BFA5B0).

[0121] Example 4

[0122] Reference Figure 6 This embodiment provides a high-speed communication system between dual-core processors. The high-speed communication system includes a communication channel establishment module 501, a memory partitioning module 502, a memory block pointer management module 503, a data writing module 504, a first data reading module 505, a second data reading module 506, and a third data reading module 507 connected in sequence.

[0123] The communication channel establishment module 501 is used to allocate a shared area in memory and establish a communication channel;

[0124] The memory partitioning module 502 is used by the dual-core processor to partition the memory it manages into memory blocks of fixed size and to form a memory pool by arranging the memory block pointers.

[0125] The memory block pointer management module 503 is used to obtain memory block pointers from the memory pool and manage the memory block pointers using a circular buffer structure;

[0126] The data writing module 504 is used to obtain the memory block pointer pointed to by the write pointer from the circular buffer managed by the data reading end, and write the data into the memory block pointed to by the memory block pointer.

[0127] The first data reading module 505 is used by the data reading end to obtain and use the memory block pointer according to the read pointer;

[0128] The second data reading module 506 is used by the data reading end to obtain a new memory block pointer from the memory pool to replace the already read memory block pointer;

[0129] The third data reading module 507 is used by the data reading end to return the memory block pointer to the memory pool after use.

[0130] The content of the above method embodiments is applicable to this system embodiment, and the specific functions implemented in this system embodiment are the same as those in the above method embodiments.

[0131] Example 5

[0132] This embodiment provides a computer device, which can be a computer, such as... Figure 7As shown, the processor 602, memory, input device 603, display 604, and network interface 605 are connected via system bus 601. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium 606 and internal memory 607. The non-volatile storage medium 606 stores the operating system, computer programs, and database. The internal memory 607 provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. When the processor 602 executes the computer programs stored in the memory, it implements a high-speed communication method between dual-core processors proposed in Embodiment 1. The high-speed communication method between dual-core processors includes the following steps:

[0133] S1. Allocate a shared area in memory and establish a communication channel;

[0134] S2. The dual-core processor divides the memory it manages into fixed-size memory blocks and uses the memory block pointers to form a memory pool.

[0135] S3. Obtain memory block pointers from the memory pool and manage the pointers using a circular buffer structure;

[0136] S4. The data writing end obtains the memory block pointer pointed to by the write pointer from the circular buffer managed by the data reading end, and writes the data to the memory block pointed to by the pointer.

[0137] S5. The data reading end obtains and uses the memory block pointer based on the read pointer;

[0138] S6. The data reading end obtains a new memory block pointer from the memory pool to replace the already read memory block pointer;

[0139] S7. After the data reading end is finished, the memory block pointer will be returned to the memory pool.

[0140] Example 6

[0141] This embodiment provides a storage medium, which is a computer-readable storage medium, storing a computer program. When the computer program is executed by a processor, it implements a high-speed communication method between dual-core processors proposed in Embodiment 1 above. The high-speed communication method between dual-core processors includes the following steps:

[0142] S1. Allocate a shared area in memory and establish a communication channel;

[0143] S2. The dual-core processor divides the memory it manages into fixed-size memory blocks and uses the memory block pointers to form a memory pool.

[0144] S3. Obtain memory block pointers from the memory pool and manage the pointers using a circular buffer structure;

[0145] S4. The data writing end obtains the memory block pointer pointed to by the write pointer from the circular buffer managed by the data reading end, and writes the data to the memory block pointed to by the pointer.

[0146] S5. The data reading end obtains and uses the memory block pointer based on the read pointer;

[0147] S6. The data reading end obtains a new memory block pointer from the memory pool to replace the already read memory block pointer;

[0148] S7. After the data reading end is finished, the memory block pointer will be returned to the memory pool.

[0149] The storage medium described in this embodiment can be a disk, optical disk, computer memory, random access memory (RAM), USB flash drive, portable hard drive, etc.

[0150] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

[0151] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0152] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A high-speed communication method between dual-core processors, applied to dual-core processors, wherein each dual-core processor is connected to memory, characterized in that, The high-speed communication method includes the following steps: S1. Allocate a shared area in memory and establish a communication channel. The shared area is divided into four parts, including a channel information area, a circular buffer structure area, a memory block area, and an idle area. The channel information area stores the channel name, the base address of the processor 0 circular buffer, the base address of the processor 1 circular buffer, the number of buffer units N, the memory block size, the base address of the processor 0 memory block area, and the base address of the processor 1 memory block area. The circular buffer structure area is used to store the circular buffers managed by the two processors. The memory block area is used for the processors to divide the memory to form a memory pool. The idle area represents the unused remaining memory, which can be allocated according to actual needs. S2. The dual-core processor divides its respective memory block into fixed-size memory blocks and arranges the memory block pointers into a memory pool; the process is as follows: S2.1 The processor obtains the memory block size from the channel information area and divides the memory block area into memory blocks according to the pre-set memory pool size. S2.2 After the segmentation, the pointers to each memory block are stored in a pointer queue to form a memory pool; S3. Obtain memory block pointers from the memory pool and manage the memory block pointers using a circular buffer structure; S4. The data writing end obtains the memory block pointer pointed to by the write pointer from the circular buffer managed by the data reading end, and writes the data into the memory block pointed to by the memory block pointer. S5. The data reading end obtains and uses the memory block pointer based on the read pointer; S6. The data reading end obtains a new memory block pointer from the memory pool to replace the already read memory block pointer; the process of step S6 is as follows: S6.1 After retrieving the memory block pointer, the data reading end obtains a new memory block pointer from the local memory pool of the data reading end to replace the above memory block pointer; S6.2 After the replacement operation is completed, the read pointer moves one position to the right. If it reaches the end of the circular buffer, it will point to the beginning of the circular buffer again. S7. The data reading end returns the memory block pointer to the memory pool after use.

2. The high-speed communication method according to claim 1, characterized in that, The circular buffer structure includes a buffer header and N buffer units. The buffer header contains information such as the buffer write pointer, read pointer, and number of buffer units. The buffer unit includes a memory block pointer and the length of the stored data. The processor extracts an equal number of memory block pointers from the memory pool according to the number of buffer units N to fill the buffer units in order to initialize the circular buffer.

3. The high-speed communication method according to claim 2, characterized in that, The process of step S4 is as follows: S4.1 The data writing end obtains the base address of the circular buffer of the data reading end from the channel information area, and finds the buffer table head through the base address of the circular buffer to obtain the write pointer; S4.

2. The data writing end obtains the memory block pointer based on the buffer unit pointed to by the write pointer, copies the data to be written into the memory block, and sets the length of the stored data in the buffer unit to the data length. S4.3 After the write operation is completed, the write pointer moves one position to the right. If it reaches the end of the circular buffer, it will point to the beginning of the circular buffer again.

4. The high-speed communication method according to claim 3, characterized in that, The process of step S5 is as follows: S5.1 The data reading end obtains the local ring buffer base address from the channel information area, and finds the buffer table head through the ring buffer base address to obtain the read pointer; S5.2 The data reading end retrieves the memory block pointer and the length of the stored data based on the buffer unit pointed to by the read pointer, and then reads the corresponding data at the memory block according to the length of the stored data.

5. A high-speed communication system between dual-core processors, used to execute the high-speed communication method according to any one of claims 1 to 4, characterized in that, The high-speed communication system includes: The communication channel establishment module is used to allocate a shared area in memory and establish a communication channel. The memory partitioning module is used by dual-core processors to partition the memory they each manage into fixed-size memory blocks and to form a memory pool by arranging the memory block pointers. The memory block pointer management module is used to obtain memory block pointers from the memory pool and manage the memory block pointers using a circular buffer structure. The data writing module is used by the data writing end to obtain the memory block pointer pointed to by the write pointer from the circular buffer managed by the data reading end, and write the data into the memory block pointed to by the memory block pointer. The first data reading module is used by the data reading end to obtain and use the memory block pointer according to the read pointer; The second data reading module is used by the data reading end to obtain a new memory block pointer from the memory pool to replace the already read memory block pointer; The third data reading module is used by the data reading end to return the memory block pointers to the memory pool after use.

6. A computer device comprising a processor and a memory for storing a processor-executable program, characterized in that, When the processor executes the program stored in the memory, it implements the high-speed communication method according to any one of claims 1 to 4.

7. A storage medium storing a program, characterized in that, When the program is executed by the processor, it implements the high-speed communication method according to any one of claims 1 to 4.

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