Apparatus and method for performing cloud-based artificial intelligence overclocking

Abstract

The invention discloses an apparatus and method for performing cloud-based artificial intelligence overclocking. Systems, apparatus, articles of manufacture, and methods for performing cloud-based artificial intelligence overclocking are disclosed that collect workload information representing a workload to be executed by a first computing platform; causing generation of an output from an AI model based on the workload information, the output representing an overclocking frequency value to be used for operation of the first computing platform; and performing overclocking based on the overclocking frequency value.

Description

Technical Field

[0001] The present disclosure relates generally to computer architecture, and more particularly to devices and methods for performing cloud-based artificial intelligence overclocking. Background Art

[0002] Computers operate by executing instructions at a clock frequency. Such clock frequencies are determined by the manufacturer of the computer and / or its parts. Some computers can be overclocked, which causes the instructions to be executed at a higher frequency than specified by the manufacturer. Such overclocking can improve the performance of the computer. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 is a block diagram of an example environment in which an example overclocking circuit module operates to perform overclocking based on an artificial intelligence model generated by a model generator circuit module.

[0004] Figure 2A yes Figure 1 A block diagram of an example implementation of an overclocking circuit module.

[0005] Figure 2B yes Figure 1 A block diagram of an example implementation of a model builder circuit module.

[0006] Figure 3 It is shown based on Figure 1 The overclocking circuit module collects information to generate a block diagram of one or more AI models, wherein the AI ​​model consists of Figure 1 The Model Builder circuit module is generated.

[0007] Figure 4 is a flowchart representing example machine-readable instructions and / or example operations that may be executed, instantiated, and / or performed by example programmable circuit modules to implement Figure 2A Overclocked circuit modules to generate system telemetry data.

[0008] Figure 5 is a flowchart representing example machine-readable instructions and / or example operations that may be executed, instantiated, and / or performed by example programmable circuit modules to implement Figure 2B Model Builder circuit module to train multiple AI models.

[0009] Figure 6 is a flowchart representing example machine-readable instructions and / or example operations that may be executed, instantiated, and / or performed by example programmable circuit modules to implement Figure 2A Overclocking circuit module to perform overclocking of the computing platform.

[0010] Figure 7 is a graph showing example overclocking results.

[0011] Figure 8 is a block diagram of an example processing platform including programmable circuit modules configured to run, instantiate and / or execute example machine-readable instructions, and / or perform Figure 4 and Figure 6 Example operation (to achieve Figure 2A Overclocking circuit module) and Figure 5 Example operation (to achieve Figure 2B Model Builder circuit module).

[0012] Fig. 9 yes Figure 8 A block diagram of an example implementation of a programmable circuit module.

[0013] Fig.10 yes Figure 8 A block diagram of another example implementation of a programmable circuit module.

[0014] Fig.11 is a block diagram of an example software / firmware / instruction distribution platform (e.g., one or more servers) for distributing software, instructions, and / or firmware (e.g., corresponding to Figure 4-Figure 6 The invention also provides example machine-readable instructions for distributing the invention to client devices associated with end-users and / or consumers (e.g., for licensing, sale, and / or use), retailers (e.g., for sale, resale, licensing, and / or sub-licensing), and / or original equipment manufacturers (OEMs) (e.g., for inclusion in products to be distributed to, for example, retailers and / or to other end-users such as direct purchase customers).

[0015] In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts.The drawings are not necessarily drawn to scale.

[0016] Unless otherwise specifically stated, descriptors such as "first", "second", "third", etc. are used herein without inputting or otherwise indicating any meaning of priority, physical order, arrangement in a list, and / or ordering in any manner, but are merely used as labels and / or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor "first" may be used to refer to an element in the detailed description, while the same element may be referred to by different descriptors (such as "second", "third") in the claims. In such instances, it should be understood that such descriptors are only used to distinguishably identify those elements within the context of the discussion (e.g., within the claims), where the elements may, for example, otherwise share the same name.

[0017] As used herein, "approximately" and "about" modify their subject matter / values ​​to recognize the potential for variations that occur in real-world applications. For example, as will be understood by one of ordinary skill in the art, "approximately" and "approximately" may modify dimensions that may be imprecise due to manufacturing tolerances and / or other real-world imperfections. For example, "approximately" and "approximately" may indicate that such dimensions may be within a tolerance range of + / - 10%, unless otherwise specified in the following description.

[0018] As used herein, "substantially real time" refers to occurring in a near instantaneous manner, recognizing that there may be real-world delays for computation time, transmission, etc. Thus, unless otherwise specified, "substantially real time" refers to real time + 1 second.

[0019] As used herein, the phrase "in communication" (including variations thereof) encompasses direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but instead additionally includes selective communication at periodic intervals, scheduled intervals, non-periodic intervals, and / or one-time events.

[0020] As used herein, a "programmable circuit module" is defined as including (i) one or more special-purpose electrical circuits (e.g., application-specific circuits (ASICs)) that are configured to perform (one or more) specific operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based electrical circuits that are programmable by instructions to perform (one or more) specific functions and / or (one or more) operations and include one or more semiconductor-based devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit modules include programmable microprocessors, such as a central processor unit (CPU) that can execute a first instruction to perform one or more operations and / or functions, a field programmable gate array (FPGA) that can be programmed by a second instruction so that the configuration and / or structure of the FPGA instantiates one or more operations and / or functions corresponding to the first instruction, a graphics processor unit (GPU) that can execute a first instruction to perform one or more operations and / or functions, a digital signal processor (DSP) that can execute a first instruction to perform one or more operations and / or functions, an XPU, a network processing unit (NPU), one or more microcontrollers that can execute a first instruction to perform one or more operations and / or functions, and / or integrated circuits, such as an application-specific integrated circuit (ASIC). For example, the XPU may be implemented by a heterogeneous computing system that includes multiple types of programmable circuit modules (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and / or any combination thereof), and orchestration technology (e.g., (one or more) application programming interfaces ((one or more) APIs)), which may assign (one or more) computing tasks to any (one or more) programmable circuit modules of multiple types that are suitable and available for performing the (one or more) computing tasks.

[0021] As used herein, an integrated circuit / circuit module is defined as one or more semiconductor packages that contain one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, a programmable circuit module, a semiconductor substrate coupling multiple circuit elements, a system on a chip (SoC), etc. DETAILED DESCRIPTION

[0022] When overclocking, the processor of the central processing unit (CPU) is operated at a higher clock frequency than the clock frequency specified by the manufacturer of the computing device. By increasing the clock frequency of the processor of the computing device, the computing device is able to perform additional operations per second, thereby improving the efficiency of the computing device. However, in some instances, by increasing the clock frequency of the processor of the computing device to a level higher than the manufacturer-specified clock frequency, the computing device may malfunction. Therefore, there are overclocked frequencies above the manufacturer-specified clock frequency that improve the performance of the computing device without being significantly higher than the manufacturer-specified clock frequency (which would cause the computing device to overheat and / or otherwise malfunction).

[0023] Traditional overclocking techniques utilize a trial and error approach. Traditional overclocking techniques start by increasing the CPU frequency and voltage by a small amount, and then execute a workload. If the computing device is stable, the traditional overclocking techniques further increase the CPU frequency and voltage, and execute another workload. If the computing device is unstable, the traditional overclocking techniques stop the process, and record the maximum CPU frequency when the computing device is stable as the overclocked frequency.

[0024] However, traditional overclocking techniques are time-consuming and tedious processes that require knowledge of central processing units and physics. In addition, although consumers prefer higher performance from computing devices, the higher the performance, the more consumers generally prefer stable computing devices. In other words, such consumers prefer simple, reliable, and stable overclocking techniques.

[0025] The technology disclosed herein uses an artificial intelligence model to predict overclocking frequencies for computing devices. Artificial intelligence (AI) (including machine learning (ML), deep learning (DL), and / or other artificial machine-driven logic) enables a machine (e.g., a computer, a logic circuit, etc.) to process input data using the model to generate outputs based on associations and / or patterns previously learned by the model through a training process. For example, the model can be trained with data to recognize patterns and / or associations, and follow such patterns and / or associations when processing input data, so that (one or more) other inputs cause (one or more) outputs consistent with the recognized patterns and / or associations.

[0026] In general, implementing an ML / AI system involves two phases, a learning / training phase and an inference phase. In the learning / training phase, a model is trained using a training algorithm based on, for example, training data to operate according to patterns and / or associations. In general, the model contains internal parameters that guide how input data is transformed into output data, such as through a series of nodes and connections within the model to transform input data into output data. In addition, hyperparameters are used as part of the training process to control how learning is performed (e.g., the number of layers to be used in a machine learning model, the learning rate, etc.). Hyperparameters are defined as training parameters that are determined before initiating the training process.

[0027] Different types of training can be performed based on the expected output and / or type of ML / AI model. For example, supervised training uses inputs and corresponding expected (e.g., labeled) outputs to select parameters for the ML / AI model (e.g., by iterating over combinations of selected parameters) that reduce model error. As used herein, a label refers to an expected output of a machine learning model (e.g., a classification, an expected output value, etc.). Alternatively, unsupervised training (e.g., as used in deep learning, subsets of machine learning, etc.) involves inferring patterns from inputs to select parameters for the ML / AI model (e.g., without the benefit of an expected (e.g., labeled) output).

[0028] In the examples disclosed herein, stochastic gradient descent is used to train the ML / AI model. However, any other training algorithm may be used additionally or alternatively. In the examples disclosed herein, training is performed until the performance of the ML / AI model exceeds a threshold. In some examples, training is performed until the error associated with the ML / AI model is reduced to a certain amount. In the examples disclosed herein, training is performed locally, separately, and remotely by a computing device. In some examples, training is performed remotely at a training facility (e.g., a model generator circuit module). Training is performed using hyperparameters that control how learning is performed (e.g., the number of layers to be used in the machine learning model, the learning rate, etc.).

[0029] The training is performed using training data. In examples disclosed herein, the training data originates from a computing platform. For example, the training data may be based on system telemetry data. The system telemetry data may include temperature data, voltage data, frequency data, and power data. The system telemetry data may be based on using one core of a computing platform or multiple cores of a computing platform. In some examples, the system telemetry data is based on (e.g., originates from) other computing platforms that communicate with the first computing platform.

[0030] Once training is complete, the model is deployed for use as an executable construct that processes inputs and provides outputs based on the network of connections and nodes defined in the model. The model is stored on a computing platform and / or a model generation facility. The model can then be executed by the computing platform (and / or by the model generation facility) to determine an overclocked frequency for use at the computing platform.

[0031] Once trained, the deployed model can be operated in the reasoning phase to process data. In the reasoning phase, the data to be analyzed (e.g., live data) is input into the model, and the model executes to create an output. The reasoning phase can be thought of as the AI ​​"thinking" to generate output based on what it has learned from training (e.g., by executing the model to apply the learned patterns and / or associations to live data). In some examples, the input data is pre-processed before being used as input to the machine learning model. In addition, in some examples, the output data can be post-processed after it is generated by the AI ​​model to transform the output into a useful result (e.g., a display of data, instructions to be executed by the machine, etc.).

[0032] In some examples, the output of the deployed model can be captured and provided as feedback. By analyzing the feedback, the accuracy of the deployed model can be determined. If the feedback indicates that the accuracy of the deployed model is less than a threshold or other criteria, the feedback and updated training data set, hyperparameters, etc. can be used to trigger the training of the updated model to generate an updated deployed model.

[0033] Figure 1 is a block diagram of an example environment 100, including an example model generator circuit module 102, an example computing platform 104, and an example manufacturer 108. Figure 1 In the example shown in FIG. 1 , the overclocking circuit module 110 is implemented in each computing platform 104 . Figure 1 In the example shown in , manufacturer 108 represents multiple manufacturers, including, for example, a first example manufacturer 108A (eg, OEM X) and a second example manufacturer 108B (eg, OEMY). Figure 1 In the illustrated example, the example overclocking circuit module 110 is implemented on a computing platform 104 (e.g., an end-user device, a laptop computer, a gaming desktop computer, etc.), but in some examples, the example overclocking circuit module 110 may additionally or alternatively be implemented at another location, such as, for example, by the example model generator circuit module 102.

[0034] The example model generator circuit module 102 is to design, publish, and / or generate an overclocking model for use by an overclocking circuit module implemented on a computing platform 104. Figure 1In the example of, the example model generator circuit module 102 is implemented on a server and / or multiple servers (e.g., a cloud). Such a model generator circuit module 102 can be operated by one or more entities (such as, for example, Intel Corporation) to facilitate the deployment of overclocking models. The generated overclocking model (e.g., a global overclocking model, a published overclocking model, a deployed overclocking model, a base overclocking model, etc.) is provided (e.g., accessed, retrieved, stored, downloaded) to the individual computing platform 104 before being run (e.g., executed) on the individual computing platform 104 (e.g., by the overclocking circuit module 110). The downloaded overclocking model is used by the overclocking circuit module 110 at each individual computing platform 104 (e.g., an end-user device) to determine the overclocking frequency to be used by the individual computing platform 104. For example, the overclocking circuit module 110 of the first computing platform 104 can determine that the first computing platform 104 can execute at a higher frequency, which improves the performance of the first computing platform of the computing platform 104 (e.g., compared to the second computing platform of the computing platform 104).

[0035] The example computing platform 104 (e.g., an end-user device) generates system telemetry data (e.g., voltage data, temperature data) based on the execution of various workloads. The example system telemetry data is accessed by the overclocking circuit module 110, which can use the telemetry data from the computing platform 104 in conjunction with the overclocking model received from the example model generator circuit module 102. In some examples, the overclocking circuit module 110 transmits the telemetry data to the example model generator circuit module 102 so that the example model generator circuit module 102 can update the generated overclocking model (e.g., global overclocking model, standard overclocking model, base overclocking model) before the subsequently generated overclocking model is trained with the telemetry data and deployed to each computing platform of the computing platform 104.

[0036] The example overclocking circuit module 110 is to determine a core frequency for execution on a first computing platform. The core frequency data can be transmitted to the example manufacturers 108 (e.g., a first manufacturer 108A (e.g., OEMX) and a second manufacturer 108B (e.g., OEMY)). The example manufacturers 108 can use the core frequency data to design, build, and pre-install the core frequency into the manufactured computing platform.

[0037] Figure 2A Include Figure 1 A block diagram 200 of an example implementation of an overclocking circuit module 110 for performing artificial intelligence model-based overclocking of a computing platform. Figure 2AThe example overclocking circuit module 110 can be instantiated (e.g., creating an instance thereof, generating, materializing, realizing, etc. for any length of time) by a programmable circuit module such as a central processing unit (CPU) executing a first instruction. Additionally or alternatively, Figure 2A The example overclocking circuit module 110 may be instantiated (e.g., creating an instance thereof, generating, materializing, implementing, etc., for any length of time) by (i) an application specific integrated circuit (ASIC) and / or (ii) a field programmable gate array (FPGA), which is constructed and / or configured to perform an operation corresponding to the first instruction in response to the execution of the second instruction. It should be understood that Figure 2A Some or all of the circuit modules may thus be instantiated at the same or different times. Figure 2A Some or all of the circuit modules of can be instantiated, for example, in one or more threads that are executed serially on hardware and / or simultaneously on hardware. In addition, in some examples, Figure 2A Some or all of the circuit modules may be implemented by a microprocessor circuit module executing instructions and / or an FPGA circuit module executing operations to implement one or more virtual machines and / or containers.

[0038] Figure 2A Include Figure 1 The example overclocking circuit module 110 includes an example network interface 204, an example model updater circuit module 206, an example overclocking execution circuit module 208, an example comparator circuit module 210, an example frequency generation circuit module 212, an example timer circuit module 214, an example telemetry data storage 216, and an example model data storage 218.

[0039] The example network interface 204 of the overclocking circuit module 110 transmits the system telemetry data of the corresponding computing platform to the example model generator circuit module 102 ( Figure 1 ). For example, the network interface 204 accesses system telemetry data, which is stored in the telemetry data store 216 of the computing platform 104. In some examples, the network interface 204 transmits the determined overclocked frequency to the example model generator circuit module 102 in the cloud ( Figure 1 ) and Manufacturer 108( Figure 1 The example network interface 204 may communicate with the model generator circuit module 102 (by using a Wi-Fi connection, a Bluetooth connection, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a field line wireless system, a cellular telephone system, an optical connection, etc. Figure 1 ) and / or manufacturer 108( Figure 1 ) communications to transmit system telemetry data or overclock frequency.

[0040] In some examples, network interface 204 is instantiated and / or configured to perform operations (such as by executing network interface instructions) through a programmable circuit module. Figure 4 and Figure 6 operations represented by the flowchart of FIG.

[0041] In some examples, the overclocking circuit module 110 includes a component for transmitting system telemetry data and overclocking frequency values. For example, the component for transmitting can be implemented by the network interface 204. In some examples, the network interface 204 can be implemented by a programmable circuit module (such as Figure 8 For example, the network interface 204 may be instantiated by Fig. 9 The example microprocessor 900 executes machine executable instructions (such as instructions generated by at least Figure 4 Frame 428, Figure 6 In some examples, the network interface 204 may be instantiated by a hardware logic circuit module, which may be an ASIC, XPU, or other processor configured and / or constructed to perform operations corresponding to the machine-readable instructions. Fig.10 The network interface 204 may be implemented by any other combination of hardware, software, and / or firmware. Additionally or alternatively, the network interface 204 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the network interface 204 may be implemented by at least one or more hardware circuits (e.g., processor circuit modules, discrete and / or integrated analog and / or digital circuit modules, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.), and the at least one or more hardware circuits are configured and / or constructed to execute all or some of the machine-readable instructions and / or to execute all or some of the operations corresponding to the machine-readable instructions (without executing software or firmware), but other structures are also suitable.

[0042] The example model updater circuit module 206 is to update the model generator circuit module 102 ( Figure 1 ) received. The example model updater circuit module 206 is to update the local AI model by training and / or tuning the AI ​​model with low-stress data, high-stress data, various core frequencies, and system telemetry data. The example model updater circuit module 206 may replace (e.g., update, overwrite, etc.) a first AI model with a second AI model based on the corresponding performance of the AI ​​model. The example model updater circuit module 206 may store the selected AI model in the example model data store 218. In some examples, the model generator circuit module 102 ( Figure 1 ) of an example model tuner circuit module 258 ( Figure 2B ) and model generator circuit module 102 ( Figure 1 ) of an example model trainer circuit module 256 ( Figure 2B ) is implemented by the example model updater circuit module 206.

[0043] In some examples, the model updater circuit module 206 is instantiated and / or configured to perform operations (such as by executing model updater instructions) through a programmable circuit module. Figure 4 and Figure 6 those operations represented by the flowchart of FIG.

[0044] In some examples, the overclocking circuit module 110 includes a component for updating an artificial intelligence (AI) model. For example, the component for updating the AI ​​model can be implemented by a model updater circuit module 206. In some examples, the model updater circuit module 206 can be implemented by a programmable circuit module (such as Figure 8 For example, the model updater circuit module 206 may be instantiated by Fig. 9 The example microprocessor 900 executes machine executable instructions (such as instructions generated by at least Figure 4 412, and Figure 6 In some examples, the model updater circuit module 206 may be instantiated by a hardware logic circuit module, which may be an ASIC, XPU, or other processor configured and / or constructed to perform operations corresponding to the machine-readable instructions. Fig.10 Additionally or alternatively, the model updater circuit module 206 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the model updater circuit module 206 may be implemented by at least one or more hardware circuits (e.g., processor circuit modules, discrete and / or integrated analog and / or digital circuit modules, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.), which are configured and / or constructed to execute all or some of the machine-readable instructions and / or to execute all or some of the operations corresponding to the machine-readable instructions (without executing software or firmware), but other structures are also suitable.

[0045] The example overclocking execution circuit module 208 is to perform overclocking of the individual computing platform 104. The example overclocking execution circuit module 208 is to control various hardware aspects of the computing platform 104 to perform overclocking. For example, the overclocking execution circuit module 208 can set a frequency value of the CPU, set a voltage value by using a voltage controlled oscillator (VCO), or set a temperature value by using a plurality of fans to cool the computing platform. By performing overclocking, the overclocking execution circuit module 208 can set a frequency value of the individual computing platform 104 based on the overclocked frequency determined by the frequency generation circuit module 212.

[0046] In some examples, the overclocking execution circuit module 208 runs a workload on a separate computing platform to determine system telemetry (e.g., voltage data, temperature data, power data, etc.). As used herein, a workload can be classified as a low-stress workload (e.g., a light workload, a lightweight workload) or a high-stress workload (e.g., a heavy workload, a heavyweight workload). For example, a workload can be classified based on an average amount of processor cycles associated with the workload. If a low-stress workload (e.g., a workload classified as a workload with a lower stress than a workload classified with high stress) is being executed, the separate computing platform can perform better at a first core frequency, or if a high-stress workload is being executed, the separate computing platform can perform better at a second core frequency. In addition, if multiple workloads are being executed, the core frequency can enable the separate computing platform to perform better. The example overclocking execution circuit module 208 can perform operations at different core frequencies within various amounts of time. The example overclocking execution circuit module 208 can use the example timer circuit module 214 to determine how much time has passed. In some examples, the overclocking execution circuit module 208 can be derived from the example model generator circuit module 102 ( Figure 1 ) of an example platform operator circuit module 262 ( Figure 2B ) receives instructions that cause the overclocking execution circuit module 208 to perform workload testing or overclocking (e.g., setting frequency values, voltage values, maintaining temperature, etc.).

[0047] In some examples, the overclocking execution circuit module 208 is instantiated and / or configured to perform operations (such as by executing overclocking execution instructions) by a programmable circuit module. Figure 4 and Figure 6 those operations represented by the flowchart of FIG.

[0048] In some examples, the overclocking circuit module 110 includes components for performing overclocking on the first machine. For example, the components for performing overclocking can be implemented by the overclocking execution circuit module 208. In some examples, the overclocking execution circuit module 208 can be implemented by a programmable circuit module (such as Figure 8For example, the overclocking execution circuit module 208 may be instantiated by Fig. 9 The example microprocessor 900 executes machine executable instructions (such as instructions generated by at least Figure 4 Boxes 402, 404, 406, 408, 410, 416, 420, 424, and 426, and Figure 6 In some examples, the overclocking execution circuit module 208 may be instantiated by a hardware logic circuit module, which may be an ASIC, XPU, or other processor configured and / or constructed to perform operations corresponding to the machine-readable instructions. Fig.10 The overclocking execution circuit module 208 is implemented by the FPGA circuit module 1000. Additionally or alternatively, the overclocking execution circuit module 208 can be instantiated by any other combination of hardware, software and / or firmware. For example, the overclocking execution circuit module 208 can be implemented by at least one or more hardware circuits (e.g., processor circuit modules, discrete and / or integrated analog and / or digital circuit modules, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.), and the at least one or more hardware circuits are configured and / or constructed to execute all or some of the machine-readable instructions and / or execute all or some of the operations corresponding to the machine-readable instructions (without executing software or firmware), but other structures are also suitable.

[0049] The example comparator circuit module 210 is to compare the performance corresponding to different models of the AI ​​model. In such examples, in addition to the performance of the AI ​​model, the comparator circuit module 210 can compare the features of different AI models. For example, the first AI model for predicting the overclocking frequency may have only two inputs, while the second AI model may have twenty inputs. In such examples, the comparator circuit module 210 can determine the performance of the two AI models, and if the performance of the two AI models is similar, it is determined to use the first AI model with only two inputs. In some examples, the threshold of similarity can be based on a percentage point in a balanced accuracy metric (e.g., 0.3%, 2%, 10%). In some examples, the comparator circuit module 210 compares different frequency values ​​to determine whether the second overclocking frequency (e.g., the current overclocking frequency, the new overclocking frequency) is different from the first overclocking frequency (e.g., the previous overclocking frequency, the old overclocking frequency).

[0050] In some examples, the comparator circuit module 210 is instantiated and / or configured to perform operations (such as by executing comparator instructions) through a programmable circuit module. Figure 4 those operations represented by the flowchart of FIG.

[0051] In some examples, the overclocking circuit module 110 includes a component for comparing the performance of different AI models. For example, the component for comparison can be implemented by a comparator circuit module 210. In some examples, the comparator circuit module 210 can be implemented by a programmable circuit module (such as Figure 8 For example, the comparator circuit module 210 may be instantiated by Fig. 9 The example microprocessor 900 executes machine executable instructions (such as instructions generated by at least Figure 4 In some examples, the comparator circuit module 210 may be instantiated by a hardware logic circuit module, which may be an ASIC, XPU, or other processor configured and / or constructed to perform operations corresponding to the machine-readable instructions. Fig.10 The FPGA circuit module 1000 is implemented. Additionally or alternatively, the comparator circuit module 210 can be instantiated by any other combination of hardware, software and / or firmware. For example, the comparator circuit module 210 can be implemented by at least one or more hardware circuits (e.g., processor circuit modules, discrete and / or integrated analog and / or digital circuit modules, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.), and the at least one or more hardware circuits are configured and / or constructed to execute all or some of the machine-readable instructions and / or execute all or some of the operations corresponding to the machine-readable instructions (without executing software or firmware), but other structures are also suitable.

[0052] The example frequency generation circuit module 212 is to generate (e.g., calculate) an overclocked frequency value. In some examples, the frequency generation circuit module 212 generates the overclocked frequency value by performing reasoning for predicting the overclocked frequency value. In such examples, the frequency generation circuit module 212 generates the overclocked frequency value by performing reasoning for predicting the overclocked frequency value. Figure 1 ) tuned and / or trained AI model to perform reasoning. In some examples, the frequency generation circuit module 212 transmits data to the model generator circuit module 102 ( Figure 1 ) and instructs the cloud computing circuit module 260 of the model generator circuit module 102 ( Figure 2B ) performs reasoning for predicting an overclocked frequency value. In such examples, the model generator circuit module 102 transmits the final value to the frequency generation circuit module 212 of the overclocking circuit module 110 of the computing platform 104. In some examples, the example model updater circuit module 206 updates the received AI model with telemetry data from the separate computing platform 104. In such examples, the frequency generation circuit module 212 performs reasoning with the updated model.

[0053] For example, the example frequency generation circuit module 212 can determine the overclocked frequency value to be between 5.5 GHz (five point five gigahertz) and 5.7 GHz (five point seven gigahertz). In other examples, the frequency generation circuit module 212 can determine the overclocked frequency value to be dependent on the type of workload to be executed by the individual computing platform 104 (e.g., low stress workload, high stress workload).

[0054] In some examples, the frequency generation circuit module 212 is instantiated and / or configured to perform operations (such as by executing frequency generation instructions) through a programmable circuit module. Figure 4 and Figure 6 those operations represented by the flowchart of FIG.

[0055] In some examples, the overclocking circuit module 110 includes a component for performing inference. For example, the component for performing inference can be implemented by the frequency generation circuit module 212. In some examples, the frequency generation circuit module 212 can be implemented by a programmable circuit module (such as Figure 8 For example, the frequency generation circuit module 212 can be instantiated by Fig. 9 The example microprocessor 900 executes machine executable instructions (such as instructions generated by at least Figure 6 In some examples, the frequency generation circuit module 212 may be instantiated by a hardware logic circuit module, which may be an ASIC, XPU, or other processor configured and / or constructed to perform operations corresponding to the machine-readable instructions. Fig.10 The frequency generation circuit module 212 is implemented by the FPGA circuit module 1000 of the present invention. Additionally or alternatively, the frequency generation circuit module 212 can be instantiated by any other combination of hardware, software and / or firmware. For example, the frequency generation circuit module 212 can be implemented by at least one or more hardware circuits (e.g., processor circuit modules, discrete and / or integrated analog and / or digital circuit modules, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.), and the at least one or more hardware circuits are configured and / or constructed to execute all or some of the machine-readable instructions and / or execute all or some of the operations corresponding to the machine-readable instructions (without executing software or firmware), but other structures are also suitable.

[0056] The example timer circuit module 214 determines the amount of time that has elapsed while the example overclocking execution circuit module 208 executes the workload test on the computing platform 104. For example, the timer circuit module 214 may determine that the first workload was executed by the overclocking execution circuit module 208 for a total of five seconds, while the second workload was executed by the overclocking execution circuit module 208 for a total of seven seconds.

[0057] In some examples, the timer circuit module 214 is instantiated and / or configured to perform operations (such as by executing timer instructions) through a programmable circuit module. Figure 4 those operations represented by the flowchart of FIG.

[0058] In some examples, overclocking circuit module 110 includes a component for determining the amount of time for the computing platform to execute the workload. For example, the component for determining the amount of time can be implemented by timer circuit module 214. In some examples, timer circuit module 214 can be implemented by a programmable circuit module (such as Figure 8 For example, the timer circuit module 214 can be instantiated by Fig. 9 The example microprocessor 900 executes machine executable instructions (such as instructions generated by at least Figure 4 In some examples, the timer circuit module 214 may be instantiated by a hardware logic circuit module, which may be an ASIC, XPU, or other processor configured and / or constructed to perform operations corresponding to the machine-readable instructions. Fig.10 FPGA circuit module 1000. Additionally or alternatively, timer circuit module 214 can be instantiated by any other combination of hardware, software and / or firmware. For example, timer circuit module 214 can be implemented by at least one or more hardware circuits (e.g., processor circuit modules, discrete and / or integrated analog and / or digital circuit modules, FPGA, ASIC, XPU, comparator, operational amplifier (op-amp), logic circuit, etc.), and the at least one or more hardware circuits are configured and / or constructed to execute all or some of the machine-readable instructions and / or execute all or some of the operations corresponding to the machine-readable instructions (without executing software or firmware), but other structures are also suitable.

[0059] The example telemetry data store 216 is a database containing system telemetry and overclocked frequencies. The example network interface 204 can use the overclocked frequencies stored in the telemetry data store 216 to transmit the overclocked frequencies to the example model generator circuit module 102 ( Figure 1 ). The example telemetry data store 216 stores example telemetry data (e.g., system characterization data), such as voltage values, temperature values, and power values. The telemetry data may be based on the number of cores used by the CPU in executing the workload. For example, the voltage of one core of the CPU may be a different value than the voltage of all cores of the CPU.

[0060] The example model data store 218 is a database containing multiple AI models. The example model data store 218 can store the AI ​​models from the model generator circuit module 102 ( Figure 1) generated models (e.g., global models, deployed models, live models, etc.). These example AI models can be updated by the example model updater circuit module 206. In some examples, the model updater circuit module 206 updates the stored AI models based on the metrics of the individual computing platforms 104.

[0061] Although Figure 2A The implementation is shown in Figure 1 Example of an overclocking circuit module, but Figure 2A One or more of the devices, processes and / or elements shown in the embodiment may be combined, divided, rearranged, omitted, eliminated and / or implemented in any other manner. Further, Figure 2A The example network interface 204, the example model updater circuit module 206, the example overclocking execution circuit module 208, the example comparator circuit module 210, the example frequency generation circuit module 212, and the example timer circuit module 214 and / or (more generally) the example overclocking circuit module 110 can be implemented by hardware alone, or by hardware in combination with software and / or firmware. Thus, for example, any of the example network interface 204, the example model updater circuit module 206, the example overclocking execution circuit module 208, the example comparator circuit module 210, the example frequency generation circuit module 212, and the example timer circuit module 214, and / or (more generally) the example overclocking circuit module 110 may be implemented by: a programmable circuit module in combination with machine-readable instructions (e.g., firmware or software), a processor circuit module, (one or more) analog circuits, (one or more) digital circuits, (one or more) logic circuits, (one or more) programmable processors, (one or more) programmable microcontrollers, (one or more) graphics processing units ((one or more) GPUs), (one or more) digital signal processors ((one or more) DSPs), (one or more) ASICs, (one or more) programmable logic devices ((one or more) PLDs), and / or (one or more) field programmable logic devices ((one or more) FPLDs) (such as FPGAs). Still further, Figure 2A The example overclocking circuit module 110 may include one or more elements, processes, and / or devices (except Figure 2A In addition to or in lieu of those shown in Figure 2A ), and / or may include more than one of all or any of the elements, processes and devices shown.

[0062] Figure 2B yes Figure 1 0048 ] A block diagram of an example model generator circuit module 102 for performing generation of an artificial intelligence overclocking model. Figure 2BThe example model generator circuit module 102 can be instantiated (e.g., create an instance of it, generate it for any length of time, materialize, realize it, etc.) by executing a first instruction through a programmable circuit module such as a central processing unit (CPU). Additionally or alternatively, Figure 2B The example model generator circuit module 102 may be instantiated (e.g., an instance of it is created, generated for any length of time, embodied, implemented, etc.) by (i) an application specific integrated circuit (ASIC) and / or (ii) a field programmable gate array (FPGA), which is constructed and / or configured to perform operations corresponding to the first instruction in response to the execution of the second instruction. It should be understood that Figure 2B Some or all of the circuit modules may thus be instantiated at the same or different times. Figure 2B Some or all of the circuit modules of can be instantiated, for example, in one or more threads that are executed serially on hardware and / or simultaneously on hardware. In addition, in some examples, Figure 2B Some or all of the circuit modules may be implemented by a microprocessor circuit module executing instructions and / or an FPGA circuit module executing operations to implement one or more virtual machines and / or containers.

[0063] The example model generator circuit module 102 includes an example security circuit module 252, an example network interface 254, an example model trainer circuit module 256, an example model tuner circuit module 258, an example cloud computing circuit module 260, and an example platform operator circuit module 262, an example generated model data store 264, and an example received telemetry data store 266.

[0064] The example security circuit module 252 of the model generator circuit module 102 is to perform security checks on data received from the computing platform 104. In some examples, the computing platform 104 ( Figure 1 ) may generate malicious telemetry data that is intended to negatively (e.g., disadvantageously) train the generated AI model (e.g., global AI model, live AI model, cloud-based AI model). However, the example secure circuit module 252 is to receive the data from the computing platform 104 ( Figure 1 ) is filtered out. For example, the safety circuit module 252 can determine the validity of the data after retrieving the ground truth data and system characterization data of the maximum overclocking frequency of the computing platform 104. The example safety circuit module 252 allows data that has passed the safety check to be used as input data to train the generated AI model and fine-tune the generated AI model.

[0065] In some examples, the safety circuit module 252 is instantiated and / or configured to perform operations (such as by executing safety instructions) through a programmable circuit module. Figure 5 those operations represented by the flowchart of FIG.

[0066] In some examples, model generator circuit module 102 includes a component for performing a security check. For example, the component for performing a security check can be implemented by security circuit module 252. In some examples, security circuit module 252 can be implemented by a programmable circuit module (such as Figure 8 For example, the safety circuit module 252 can be instantiated by Fig. 9 The example microprocessor 900 executes machine executable instructions (such as instructions generated by at least Figure 5 In some examples, the security circuit module 252 may be instantiated by a hardware logic circuit module, which may be an ASIC, XPU, or other processor configured and / or constructed to perform operations corresponding to the machine-readable instructions. Fig.10 FPGA circuit module 1000. Additionally or alternatively, the security circuit module 252 can be instantiated by any other combination of hardware, software and / or firmware. For example, the security circuit module 252 can be implemented by at least one or more hardware circuits (e.g., processor circuit modules, discrete and / or integrated analog and / or digital circuit modules, FPGA, ASIC, XPU, comparator, operational amplifier (op-amp), logic circuit, etc.), and the at least one or more hardware circuits are configured and / or constructed to execute all or some of the machine-readable instructions and / or execute all or some of the operations corresponding to the machine-readable instructions (without executing software or firmware), but other structures are also suitable.

[0067] The example network interface 254 of the model generator circuit module 102 receives data from multiple computing platforms 104 ( Figure 1 ) receives system telemetry data and stores the received telemetry data in the example received telemetry data store 266. In some examples, the network interface 254 transmits the generated AI model to a processor that can be used by the example manufacturer 108 ( Figure 1 ) and the example computing platform 104 ( Figure 1 ) cloud repository accessed by . In some examples, the network interface 254 transmits the generated AI model directly to the example manufacturer 108 ( Figure 1 ) and example computing platform 104 ( Figure 1 In some examples, network interface 254 transmits the determined overclocked frequency to one of computing platforms 104. Example network interface 254 may communicate with computing platform 104 (eg, a wireless network interface 254) using a Wi-Fi connection, a Bluetooth connection, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a field line wireless system, a cellular telephone system, an optical connection, etc. Figure 1 ) and Manufacturer 108( Figure 1 ) communication to transmit the generated AI model or overclocked frequency.

[0068] In some examples, network interface 254 is instantiated and / or configured to perform operations (such as by executing network interface instructions) through a programmable circuit module. Figure 5 those operations represented by the flowchart of FIG.

[0069] In some examples, the model generator circuit module 102 includes a component for transmitting system telemetry data and overclocking frequency values. For example, the component for transmitting can be implemented by the network interface 254. In some examples, the network interface 254 can be implemented by a programmable circuit module (such as Figure 8 For example, the network interface 254 may be instantiated by Fig. 9 The example microprocessor 900 executes machine executable instructions (such as instructions generated by at least Figure 5 In some examples, the network interface 254 may be instantiated by a hardware logic circuit module, which may be an ASIC, XPU, or other processor configured and / or constructed to perform operations corresponding to the machine-readable instructions. Fig.10 The network interface 254 may be implemented by any other combination of hardware, software, and / or firmware. Additionally or alternatively, the network interface 254 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the network interface 254 may be implemented by at least one or more hardware circuits (e.g., processor circuit modules, discrete and / or integrated analog and / or digital circuit modules, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.), and the at least one or more hardware circuits are configured and / or constructed to execute all or some of the machine-readable instructions and / or to execute all or some of the operations corresponding to the machine-readable instructions (without executing software or firmware), but other structures are also suitable.

[0070] The example model trainer circuit module 256 is to generate and train multiple AI models. In some examples, the model trainer circuit module 256 is to evaluate the performance of multiple AI models (e.g., prediction accuracy, prediction speed, etc.). The example model trainer circuit module 256 is to train the AI ​​model with low-stress data, high-stress data, various core frequencies, and system telemetry data. Once the example multiple AI models are fully trained by the example model trainer circuit module 256, the example model tuner circuit module 258 can perform fine-tuning of the fully trained AI model.

[0071] In some examples, the model trainer circuit module 256 is instantiated and / or configured to perform operations (such as by executing model training instructions) through a programmable circuit module. Figure 5 those operations represented by the flowchart of FIG.

[0072] In some examples, the model generator circuit module 102 includes components for training an artificial intelligence (AI) model. For example, the components for training an AI model can be implemented by the model trainer circuit module 256. In some examples, the model trainer circuit module 256 can be implemented by a programmable circuit module (such as Figure 8 For example, the model trainer circuit module 256 can be instantiated by Fig. 9 The example microprocessor 900 executes machine executable instructions (such as instructions generated by at least Figure 5 In some examples, the model trainer circuit module 256 may be instantiated by a hardware logic circuit module, which may be an ASIC, XPU, or other processor configured and / or constructed to perform operations corresponding to the machine-readable instructions. Fig.10 Additionally or alternatively, the model trainer circuit module 256 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the model trainer circuit module 256 may be implemented by at least one or more hardware circuits (e.g., processor circuit modules, discrete and / or integrated analog and / or digital circuit modules, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.), and the at least one or more hardware circuits are configured and / or constructed to execute all or some of the machine-readable instructions and / or to execute all or some of the operations corresponding to the machine-readable instructions (without executing software or firmware), but other structures are also suitable.

[0073] The example model tuner circuit module 258 is to perform fine-tuning of the AI ​​model by determining the impact of the features of the AI ​​model on the final overall performance of the AI ​​model (e.g., the overall accuracy of the AI ​​model, the overall speed of the AI ​​model). The example model tuner circuit module 258 is to minimize the number of features that contribute to the overall performance of the AI ​​model. The example model tuner circuit module 258 is to distinguish between the performance of the AI ​​models to determine which AI model has the best performance with the least number of features. For example, the first AI model may be 85.0% accurate, while the second AI model may be 83.2% accurate. The example model tuner circuit module 258 can determine that the second AI model has only five key features that lead to overall performance (while the first AI model has eight key features), and select the second AI model as the generated AI model to be deployed. Some example features of the AI ​​model include the number of CPU samples, the number of workloads, and the number of different frequencies for different types of workloads, which are all features minimized by the example model tuner circuit module 258.

[0074] In some examples, model tuner circuit module 258 is instantiated and / or configured to perform operations (such as by executing model tuner instructions) through a programmable circuit module. Figure 5 those operations represented by the flowchart of FIG.

[0075] In some examples, model generator circuit module 102 includes components for tuning an artificial intelligence (AI) model. For example, the components for tuning an AI model can be implemented by model tuner circuit module 258. In some examples, model tuner circuit module 258 can be implemented by a programmable circuit module (such as Figure 8 For example, the model tuner circuit module 258 may be instantiated by Fig. 9 The example microprocessor 900 executes machine executable instructions (such as instructions generated by at least Figure 5 In some examples, the model tuner circuit module 258 may be instantiated by a hardware logic circuit module, which may be an ASIC, XPU, or other processor configured and / or constructed to perform operations corresponding to the machine-readable instructions. Fig.10Additionally or alternatively, the model tuner circuit module 258 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the model tuner circuit module 258 may be implemented by at least one or more hardware circuits (e.g., processor circuit modules, discrete and / or integrated analog and / or digital circuit modules, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.), which are configured and / or constructed to execute all or some of the machine-readable instructions and / or to execute all or some of the operations corresponding to the machine-readable instructions (without executing software or firmware), but other structures are also suitable.

[0076] The example cloud computing circuit module 260 is to use the generated AI model to perform artificial intelligence reasoning. In the examples disclosed herein, the performance of reasoning includes the generation of outputs based on the model and input data. For example, one computing platform of the example computing platform 104 can transmit telemetry data and request to return an overclocked frequency value. The example cloud computing circuit module 260 uses the telemetry data to determine the overclocked frequency value for the one computing platform of the example computing platform 104.

[0077] In some examples, cloud computing circuit module 260 is instantiated and / or configured to perform operations (such as by executing cloud computing instructions) through a programmable circuit module. Figure 4 and 6 those operations represented by the flowchart of FIG.

[0078] In some examples, model generator circuit module 102 includes components for performing cloud computing through a cloud-based AI model. For example, the components for performing cloud computing can be implemented by cloud computing circuit module 260. In some examples, cloud computing circuit module 260 can be implemented by a programmable circuit module (such as Figure 8 For example, the cloud computing circuit module 260 can be instantiated by Fig. 9 The example microprocessor 900 executes machine executable instructions (such as instructions generated by at least Figure 4 Box 414 and Figure 6 In some examples, the cloud computing circuit module 260 may be instantiated by a hardware logic circuit module, which may be an ASIC, XPU, or other processor configured and / or constructed to perform operations corresponding to the machine-readable instructions. Fig.10The cloud computing circuit module 260 is implemented by the FPGA circuit module 1000. Additionally or alternatively, the cloud computing circuit module 260 can be instantiated by any other combination of hardware, software and / or firmware. For example, the cloud computing circuit module 260 can be implemented by at least one or more hardware circuits (e.g., processor circuit modules, discrete and / or integrated analog and / or digital circuit modules, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.), and the at least one or more hardware circuits are configured and / or constructed to execute all or some of the machine-readable instructions and / or execute all or some of the operations corresponding to the machine-readable instructions (without executing software or firmware), but other structures are also suitable.

[0079] The example platform operator circuit module 262 is to cause the remote device to perform overclocking. In some examples, the platform operator circuit module 262 causes the computing platform 104 to perform overclocking by sending instructions to the computing platform 104 (which is an end-user device). In some examples, instructions for performing overclocking can be sent to a test device for the purpose of collecting telemetry data. In such examples, collecting telemetry data does not necessarily need to be performed by an end-user device (e.g., a device operated and / or owned by a customer). Instead, a computing platform that is directed to collect telemetry and / or overclocking data (e.g., maximum frequency data) can be operated by the same entity that operates the model generator circuit module 102. In some examples, a computing platform that is directed to collect telemetry and / or overclocking data (e.g., maximum frequency data) can be operated by one of the examples of the example manufacturer 108. In other words, a computing platform directed to collect telemetry data and / or overclocking data may be operated in a non-user environment and / or may be operated for the sole purpose of collecting such telemetry data, overclocking data, and / or other operational information of an entity (e.g., an entity operating the model generator circuit module 102, a manufacturer, etc.). The example platform operator circuit module 262 may cause the example overclocking execution circuit module 208 ( Figure 2A ) adjusts the frequency, voltage, or temperature of the computing platform 104 and collects frequency information (e.g., maximum turbo frequency).

[0080] In some examples, platform operator circuit module 262 is instantiated and / or configured to perform operations (such as by executing platform operator instructions) through a programmable circuit module. Figure 6 those operations represented by the flowchart of FIG.

[0081] In some examples, the model generator circuit module 102 includes components for enabling overclocking to occur on the remote computing platform. For example, the components for enabling overclocking to occur on the remote computing platform can be implemented by the platform operator circuit module 262. In some examples, the platform operator circuit module 262 can be implemented by a programmable circuit module (such as Figure 8 For example, the platform operator circuit module 262 may be instantiated by Fig. 9 The example microprocessor 900 executes machine executable instructions (such as instructions generated by at least Figure 6 In some examples, the platform operator circuit module 262 may be instantiated by a hardware logic circuit module, which may be an ASIC, XPU, or other processor configured and / or constructed to perform operations corresponding to the machine-readable instructions. Fig.10 The platform operator circuit module 262 may be implemented by any other combination of hardware, software, and / or firmware. Additionally or alternatively, the platform operator circuit module 262 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the platform operator circuit module 262 may be implemented by at least one or more hardware circuits (e.g., processor circuit modules, discrete and / or integrated analog and / or digital circuit modules, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.), which are configured and / or constructed to execute all or some of the machine-readable instructions and / or to execute all or some of the operations corresponding to the machine-readable instructions (without executing software or firmware), but other structures are also suitable.

[0082] The example generated model data store 264 contains multiple AI models that are generated and / or trained by the example model trainer circuit module 256 and, in some examples, tuned by the example model tuner circuit module 258. The example generated model data store 264 can store generated artificial intelligence models (e.g., deployed models, global models, live models, accessible models).

[0083] An example received telemetry data store 266 is a database containing system telemetry originating from a computing platform 104. The system telemetry data may originate from an end-user device or a test device. The received telemetry data stored in the received telemetry data store 266 may include workload data, voltage data, frequency data, temperature data, and / or power data.

[0084] Although Figure 2B The implementation is shown in Figure 1 The model generation circuit module 102 is an example of a method, but Figure 2B One or more of the devices, processes and / or elements shown in the embodiment may be combined, divided, rearranged, omitted, eliminated and / or implemented in any other manner. Further, Figure 2BThe example security circuit module 252, the example network interface 254, the example model trainer circuit module 256, the example model tuner circuit module 258, the example cloud computing circuit module 260, the example platform operator circuit module 262, and / or (more generally) the example model generator circuit module 102 can be implemented by hardware alone, or by hardware in combination with software and / or firmware. Thus, for example, any of the example security circuit module 252, the example network interface 254, the example model trainer circuit module 256, the example model tuner circuit module 258, the example cloud computing circuit module 260, the example platform operator circuit module 262, and / or (more generally) the example model generator circuit module 102 may be implemented by: a programmable circuit module in combination with machine-readable instructions (e.g., firmware or software), a processor circuit module, (one or more) analog circuits, (one or more) digital circuits, (one or more) logic circuits, (one or more) programmable processors, (one or more) programmable microcontrollers, (one or more) graphics processing units ((one or more) GPUs), (one or more) digital signal processors ((one or more) DSPs), (one or more) ASICs, (one or more) programmable logic devices ((one or more) PLDs), and / or (one or more) field programmable logic devices ((one or more) FPLDs) (such as FPGAs). Still further, Figure 2B The example model generator circuit module 102 may include one or more elements, processes, and / or devices (except Figure 2B In addition to or instead of those shown in Figure 2B ), and / or may include more than one of all or any of the elements, processes and devices shown.

[0085] Figure 3 Is Figure 1 A block diagram of an example AI model generated by an overclocked circuit module in a cloud-based environment. Figure 3 In the example of , various versions of the AI ​​overclocking model are shown by dashed lines. The example model generator circuit module 102 is to generate an example trained model 302. Figure 3 In the example of , the example trained model 302 is updated to the example cloud platform 316, which is separate from the model builder facility 318 of the model builder circuit module 102. System telemetry data from the first manufacturer 108A (e.g., OEM X) and the second manufacturer 108B (e.g., OEMY) and the computing platform 104 is received at the safety check operation 304. The example safety circuit module 252 ( Figure 2B ) to perform a security check on the telemetry data to filter out any malicious data that may affect the example generated model 306. At operation 308, the example model tuner circuit module 258 ( Figure 2B ) updates the model. In some examples, the example model trainer circuit module 256 updates the model at operation 308. For example, the model tuner circuit module 258 ( Figure 2B ) tunes the model to generate a first model 310 (e.g., "Model X") for use by a first manufacturer 108A (e.g., "OEMX") and a second model 312 ("Model Y") for use by a second manufacturer 108B (e.g., "OEM Y"). The example manufacturers 108 can use the specific models 310, 312 to design the computing platform 104 and relay the results back to the example model generator circuit module 102. The example network interface 254 ( Figure 2B ) may transmit the model to a third-party monetization system 314. An example third-party monetization system 314 may be the computing platform 104 that participates with the updated model at operation 308 and provides system telemetry data to the model generator circuit module 102 to receive the model at a discount. For example, the system telemetry data may be sent to an advertising service. For example, if the temperature of the computing platform 104 is high, the example advertising service may recommend that the user of the computing platform 104 purchase a cooler to reduce the high temperature of the computing platform 104. For example, the model generator circuit module 102 may pay the user for the system telemetry data using the third-party monetization system 314. For example, if the user of the computing platform shares telemetry data with the example model generator circuit module 102, the model generator circuit module 102 may unlock a software feature of an overclocking service.

[0086] Figure 4 and Figure 6 The diagram shows that the programmable circuit module can be executed to implement and / or instantiate Figure 2A Example operations of the overclocking circuit module 110, and / or representations of what may be performed by the programmable circuit module to implement and / or instantiate Figure 2A A flow chart of example machine readable instructions of the overclocking circuit module 110 is provided. Figure 5 The diagram shows that the programmable circuit module can be executed to implement and / or instantiate Figure 2B Example operations of the model generator circuit module 102, and / or representations of the operations that may be performed by a programmable circuit module to implement and / or instantiate Figure 2B Flowchart of example machine readable instructions for the model generator circuit module 102 of the present invention. The machine readable instructions may be one or more executable programs or (one or more) parts of one or more executable programs for being executed by a programmable circuit module (such as described below in conjunction with Figure 8 The programmable circuit module 812 shown in the example processor platform 800 discussed above is executed, and / or may be executed by the following in conjunction with Fig. 9In some examples, the machine-readable instructions enable operations, tasks, etc. to be performed and / or executed in an automatic manner in the real world. As used herein, "automatic" means without human involvement.

[0087] The program may be embodied in instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media, such as cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or disks (e.g., Blu-ray disks, compact disks (CDs), digital versatile disks (DVDs), etc.), redundant arrays of independent disks (RAIDs), registers, ROMs, solid-state drives (SSDs), SSD memories, non-volatile memories (e.g., electrically erasable programmable read-only memories (EEPROMs), flash memories, etc.), volatile memories (e.g., any type of random access memories (RAMs), etc.), and / or any other storage devices or storage disks. The instructions of the non-transitory computer-readable and / or machine-readable media may be programmed and / or executed by a programmable circuit module located in one or more hardware devices, but the entire program and / or portions thereof may alternatively be instantiated and / or executed by one or more hardware devices other than the programmable circuit module, and / or embodied in dedicated hardware. The machine-readable instructions may be distributed across multiple hardware devices and / or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, the client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a human and / or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that may facilitate communication between a server and an endpoint client hardware device. Similarly, a non-transitory computer-readable storage medium may include one or more media. Further, although reference is made to Figure 4-Figure 6The (one or more) flowcharts shown in the example program describe example procedures, but many other methods of implementing the example overclocking circuit module 110 and / or the example model generator circuit module 102 may alternatively be used. For example, the execution order of the blocks of the (one or more) flowcharts may be changed, and / or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, all or any of the blocks in the flowcharts may be implemented by one or more hardware circuits (e.g., processor circuit modules, discrete and / or integrated analog and / or digital circuit modules, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.), which are configured to perform corresponding operations (without executing software or firmware). The programmable circuit modules may be distributed in different network locations and / or local to one or more hardware devices (e.g., single-core processors (e.g., single-core CPUs), multi-core processors (e.g., multi-core CPUs, XPUs, etc.)). For example, the programmable circuit module may be an FPGA and / or CPU located in the same package (e.g., the same integrated circuit (IC) package, or in two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers in a server rack, multiple processors distributed across one or more server racks, etc., and / or any combination (one or more) thereof.

[0088] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a fragmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions as described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.), etc.) or a data structure (e.g., as (one or more) parts of instructions, code, a representation of code, etc.), which may be used to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be broken up and stored on one or more storage devices, disks, and / or computing devices (e.g., servers) located at the same or different locations of a network collection or network (e.g., in the cloud, in an edge device, etc.). The machine-readable instructions may require one or more of installation, modification, adaptation, update, combination, supplementation, configuration, decryption, decompression, unpacking, distribution, reassignment, compilation, etc., so that they are directly readable, interpretable, and / or executable by a computing device and / or other machine. For example, machine-readable instructions may be stored in multiple portions that are individually compressed, encrypted, and / or stored on separate computing devices, wherein the portions, when decrypted, decompressed, and / or combined, form a set of computer-executable and / or machine-executable instructions that implement one or more functions and / or operations that may together form a program (such as the programs described herein).

[0089] In another example, the machine-readable instructions may be stored in a state where they can be read by a programmable circuit module, but require the addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application program interface (API), etc., in order to execute the machine-readable instructions on a particular computing device or other device. In another example, the machine-readable instructions may need to be configured (stored settings, data inputs, recorded network addresses, etc.) before the machine-readable instructions and / or corresponding (one or more) programs can be executed in whole or in part. Therefore, a machine-readable, computer-readable and / or machine-readable medium (as used herein) can contain instructions and / or (one or more) programs regardless of the specific format or state of the machine-readable instructions and / or (one or more) programs.

[0090] The machine-readable instructions described herein may be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, machine-readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0091] As mentioned above, the present invention may be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transitory computer-readable and / or machine-readable media. Figure 4-Figure 6 Example operation. As used herein, the term non-transient computer-readable medium, non-transient computer-readable storage medium, non-transient machine-readable medium and / or non-transient machine-readable storage medium is clearly defined to include any type of computer-readable storage device and / or storage disk, and excludes propagated signals and excludes transmission media. Examples of such non-transient computer-readable media, non-transient computer-readable storage media, non-transient machine-readable media and / or non-transient machine-readable storage media include optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, caches, any type of RAM, registers and / or any other storage devices or storage disks, wherein information is stored in any duration (e.g., in an extended period of time, permanently, in a brief instance, in a temporary buffer, and / or in a cache of information). As used herein, the terms "non-transient computer-readable storage device" and "non-transient machine-readable storage device" are defined to include any physical (mechanical, magnetic and / or electrical) hardware for retaining information over a period of time, but exclude propagated signals and exclude transmission media. Examples of non-transitory computer-readable storage devices and / or non-transitory machine-readable storage devices include any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disks, magnetic disks, disk drives, and / or redundant array of independent disks (RAID) systems. As used herein, the term "device" refers to a physical structure such as a mechanical and / or electrical device, hardware, and / or circuit module that may or may not be configured by computer-readable instructions, machine-readable instructions, etc., and / or manufactured to execute computer-readable instructions, machine-readable instructions, etc.

[0092] "Include" and "comprising" (and all forms and tenses thereof) are used herein as open-ended terms. Thus, whenever a claim employs any form of "includes" or "comprising" (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or within any type of claim recitation, it is to be understood that additional elements, terms, etc. may be present without falling outside the scope of the corresponding claim or recitation. As used herein, when the phrase "at least" is used as a transitional term, such as in the preamble of a claim, it is open-ended (in the same manner as the terms "includes" and "comprising" are open-ended). The term "and / or" when used, for example, in a form such as A, B, and / or C, refers to any combination or subset of A, B, and C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A and B" is intended to refer to implementations that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A or B" is intended to refer to implementations that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the execution or performance of steps, activities, actions, instructions, and / or processes, the phrase "at least one of A and B" is intended to refer to implementations that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the execution or performance of steps, activities, actions, instructions and / or processes, the phrase "at least one of A or B" is intended to refer to an implementation that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0093] As used herein, singular references (e.g., "a, an," "first," "second," etc.) do not exclude a plurality. The term "a or an" object (as used herein) refers to one or more of the object. The terms "a" (or "an"), "one or more," and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple components, elements, or actions may be implemented by, for example, the same entity or object. Additionally, although individual features may be included in different examples or claims, these features may possibly be combined, and the inclusion in different examples or claims does not indicate that a combination of features is not feasible and / or advantageous.

[0094] Figure 4 is a flow diagram representative of example machine-readable instructions and / or example operations 400 that may be executed, instantiated, and / or performed by a programmable circuit module to generate system telemetry data. Figure 4 The example machine readable instructions and / or example operations 400 begin at block 402, where the example. Figure 4 The example machine readable instructions and / or example operations 400 of the example overclocking execution circuit module 208 begin at block 402, where the example overclocking execution circuit module 208 determines whether to determine an overclocking frequency. For example, if the example overclocking execution circuit module 208 determines to determine an overclocking frequency (e.g., "yes"), control proceeds to block 404. Alternatively, in response to the overclocking execution circuit module 208 determining that the overclocking frequency is not determined (e.g., "no"), control returns to block 402. The example overclocking execution circuit module 208 may determine to determine an overclocking frequency based on the information from the example model generator circuit module 102 ( Figure 1 ) of an example platform operator circuit module 262 ( Figure 2B ) to determine the overclocking frequency to be determined. In some examples, the example overclocking execution circuit module 208 can determine to perform overclocking frequency determination in response to an instruction from a user.

[0095] At block 404, the example overclocking execution circuit module 208 obtains a baseline score (S) by running the benchmark for a third number of seconds (T3). 基线 ). The example overclocking execution circuit module 208 may derive the baseline score by executing the workload at a particular core frequency for a third number of seconds.

[0096] At block 406, the example overclocking execution circuit module 208 records the full core frequency as the old frequency value (F MAX_OLD ) and set the new core frequency value (F MAX_SC ) for system characterization.

[0097] At block 408, the example overclocking execution circuit module 208 collects system telemetry by executing the low stress workload for a first number of seconds (T1). The example overclocking execution circuit module 208 may record power, temperature, and / or voltage of the individual computing platforms while the low stress workload is being executed at the new core frequency value (F MAX_SC ) is processed. The example timer circuit module 214 is to determine the amount of time that has elapsed during the execution of the low stress workload. For example, the overclocking execution circuit module 208 can determine a first number of low stress workloads (e.g., five low stress workloads) and a second number of different core frequencies (e.g., a first frequency of 5 GHz, a second frequency of 5.5 GHz, a third frequency of 5.7 GHz, and a fourth frequency of 6.0 GHz). In some examples, the first number (e.g., five) of low stress workloads corresponds to the second number of frequencies (e.g., five). In such examples, for each low stress workload and core frequency combination, the example overclocking execution circuit module 208 runs the low stress workload for a third number of seconds (e.g., five seconds, ten seconds, sixty seconds, three hundred seconds, etc.).

[0098] At block 410, the example overclocking execution circuit module 208 collects system telemetry by executing the high-stress workload for a second number of seconds (T2). The example overclocking execution circuit module 208 may record power, temperature, and voltage of the individual computing platforms while the high-stress workload is being executed at the new core frequency value (F MAX_SC ) is processed. The example timer circuit module 214 is to determine the amount of time that has elapsed during the execution of the high stress workload. The example overclocking execution circuit module 208 may determine five high stress workloads (which may be a different number than the number of low stress workloads). In other examples, the overclocking execution circuit module 208 determines the same number of high stress workloads based on the number of low stress workloads. The example overclocking execution circuit module 208 runs the high stress workload for a sixth number of seconds. The example overclocking execution circuit module 208 uses the example timer circuit module 214 to determine the amount of time (e.g., a third number of seconds).

[0099] At block 412, the example model updater circuit module 206 collects telemetry data from the previous two operations. The example telemetry data can be used to train an AI model to predict the new full core frequency (F MAX_NEW ). In some examples, telemetry data is used as input to an AI model to predict and / or generate an all-core frequency.

[0100] At block 414, the example overclocking execution circuit module 208 generates a new full core frequency (F MAX_NEW). Overclocking execution circuit module 208 generates a predicted full core frequency using the fully trained model. In some examples, overclocking execution circuit module 208 uses model generator circuit module 102 ( Figure 1 ) of an example cloud computing circuit module 260 ( Figure 2B ) to predict the new all-core frequency.

[0101] At block 416, the example overclocking execution circuit module 208 operates at the predicted full core frequency (F) with overclocking thermal velocity boost (OCTVB) enabled. MAX_NEW ) The benchmark is run again for a third number of seconds (T3). The example overclocking execution circuit module 208 obtains a new score (S NEW ).

[0102] At block 418, the example comparator circuit module 210 compares the baseline score to the new score. For example, if the comparator circuit module 210 determines that the baseline score is greater than the new score (e.g., "yes"), control proceeds to block 424. Alternatively, if the comparator circuit module 210 determines that the baseline score is not greater than the new score (e.g., "no"), control proceeds to block 420. In some examples, the comparator circuit module 210 determines whether the baseline score is greater than or equal to the new score.

[0103] At block 420, the example overclocking execution circuit module 208 removes a number of hertz from the new predicted frequency. For example, if the overclocked frequency is 5.8 GHz (five point eight gigahertz), the example overclocking execution circuit module 208 may remove zero point three gigahertz (0.3 GHz) from the overclocked frequency to generate an overclocked frequency of five point five gigahertz (5.5 GHz). Control proceeds to block 422.

[0104] At block 422, the example comparator circuit module 210 compares the new overclocked frequency (F MAX_NEW ) and the recorded old overclocked frequency (F MAX_OLD ). For example, if the new overclocked frequency is less than the recorded old overclocked frequency (e.g., "yes"), control proceeds to block 424. Alternatively, if the example new overclocked frequency is not less than the recorded old overclocked frequency (e.g., "no"), control proceeds to block 416.

[0105] At block 424, the example overclocking execution circuit module 208 re-stores the old overclocking frequency value as the new overclocking frequency value. For example, if the performance of the old overclocking frequency value is better than the performance of the new overclocking frequency value, the old overclocking frequency value may be stored.

[0106] At block 426, the example overclocking execution circuit module 208 sets a new overclocked frequency value for the individual computing platform. For example, the overclocking execution circuit module 208 may report the new overclocked frequency to the user using an extreme tuning utility (XTU). In such examples, the overclocking execution circuit module 208 may wait for instructions from the user to set the frequency value for the computing platform. In some examples, the overclocking execution circuit module 208 automatically sets the overclocked frequency value without user input.

[0107] At block 428, the example network interface 204 transmits the example telemetry data and the overclocked frequency value to the example model generator circuit module 102. For example, the model generator circuit module 102 ( Figure 1 ) may be a cloud-based entity that uses the new overclocked frequency and telemetry data transmitted by network interface 204 for the generation of a model to facilitate further overclocking attempts, which may then not have to be implemented Figure 4 The process is executed.

[0108] Figure 5 is a flow chart representing example machine-readable instructions and / or example operations 500 that may be executed, instantiated, and / or performed by a programmable circuit module to implement a model generator circuit module 102 ( Figure 2B ) to generate multiple AI models. Figure 5 The example machine readable instructions and / or example operations 500 begin at block 502, where the example security circuit module 252 filters information from multiple computing platforms 104 ( Figure 1 ) received by the computing platform 104. For example, the safety circuit module 252 can remove data that is considered malicious. The removed data will not be used to modify, adjust, tune, or train the overclocking model. The example platform operator circuit module 262 can generate system telemetry data by directing the computing platform 104 to execute a workload, record temperature, voltage, and / or power while the workload is being executed, and transmit the data to the example safety circuit module 252.

[0109] At block 504 , the example model trainer circuit module 256 trains the plurality of AI models with the received system telemetry data and maximum frequency data (originating from the platform operator circuit module 262 ).

[0110] At block 506, the example model tuner circuit module 258 tunes a first AI model from the one or more AI models. For example, the model tuner circuit module 258 may tune the first AI model from the plurality of AI models by determining features of the first AI model that provide the greatest influence in the prediction scores of the AI ​​models and then minimizing those features. In some examples, the tuning of block 506 may be omitted.

[0111] At box 508, the example network interface 254 distributes the one or more AI models to the example computing platform 104. In some examples, only one model is provided to each respective computing platform based on, for example, operating parameters of the computing platform, brand of the computing platform, model of the computing platform, etc. In some examples, where the model generator circuit module 102 is implemented on the first computing platform 104, the example network interface 254 may distribute the one or more AI models to the first computing platform 104 (itself). In some examples, the network interface 254 may distribute the one or more AI models to manufacturers for deployment of their computing platforms. Instructions 500 then terminate, but may be re-executed to generate and / or distribute additional AI models.

[0112] Figure 6 is a flow diagram representative of example machine-readable instructions and / or example operations 600 that may be executed, instantiated, and / or performed by a programmable circuit module to perform overclocking of a computing platform 104 . Figure 6 The example machine readable instructions and / or example operations 600 begin at block 602, where the example network interface 204 accesses one or more artificial intelligence (AI) models. For example, the network interface 204 may access the model generator circuit module 102 ( Figure 1 ) and then downloading the one or more AI models to the example model data store 218 ( Figure 2A ).

[0113] At block 604, the example model updater circuit module 206 trains and / or tunes a first AI model of the one or more AI models on the local computing platform 104. For example, the model updater circuit module 206 may update the first AI model using local telemetry data from the example telemetry data store 216. The example updated first AI model will result in improved performance in the prediction of the overclocked frequency, which will result in improved performance of the computing platform 104. Figure 6 In the illustrated example of , block 604 is optional and may be omitted in some examples (eg, in scenarios where additional local tuning is not to be performed).

[0114] At block 605, the example frequency generation circuit module 212 collects workload information for the computing platform 104. Such workload information may indicate, for example, whether a processor of the computing platform 104 is executing a high intensity workload, a low intensity workload, etc. In some examples, the workload information represents a current workload of the computing platform 104. In some other examples, the workload information represents an expected (e.g., predicted, future) workload of the computing platform 104.

[0115] At block 606, the example frequency generation circuit module 212 generates an overclocked frequency value using the first tuned AI model and the workload information. For example, the frequency generation circuit module 212 may perform reasoning using the collected workload information through the first tuned AI model to generate an overclocked frequency value. In some examples, multiple overclocked frequency values ​​are determined based on the number and / or type of workloads. For example, if there are three workloads (e.g., a low stress workload, a first high stress workload, and a second high stress workload), the example frequency generation circuit module 212 may determine that when the processor is executing a low stress workload, the overclocked frequency is 5.0 GHz (five point five GHz). In such an example, the example frequency generation circuit module 212 may determine that if the low stress workload and the first high stress workload are to be executed at the same time, the overclocked frequency is 4.9 GHz (four point nine gigahertz). In such an example, the example frequency generation circuit module 212 may determine that if the first high stress workload is executed by the processor, the overclocked frequency is 6.0 GHz (six point zero gigahertz). In some examples, the example network interface 204 sends a request to the example cloud computing circuit module 260 of the example model generator circuit module 102 to perform inference. Such a request may include workload information identifying a workload currently executed (and / or expected to be executed) by the computing platform 104. In such an example, the cloud computing circuit module 260 transmits the overclocked frequency value back to the example network interface 204 after performing inference through the first tuned AI model specific to the local computing platform 104 or the general AI model.

[0116] At block 608, the example overclocking execution circuit module 208 performs overclocking based on the generated overclocking frequency value. For example, the separate computing platform now has a clock frequency equal to the overclocking frequency value. In some examples, the platform operator circuit module 262 of the example model generator circuit module 102 performs overclocking on a remote end-user device (e.g., a remote computing platform in the computing platform 104).

[0117] At block 610, the example network interface 204 transmits the system telemetry data and the overclocked frequency value to a cloud-based AI model generator (e.g., Figure 1 , Figure 2A and Figure 3 The example model generator circuit module 102 can use the overclocked frequency value to update or generate a cloud-based AI model (e.g., a global model, a deployed model, a generated model).

[0118] At block 615, the example frequency generation circuit module 212 determines whether the overclocked frequency should be adjusted. Such determination may be made periodically (e.g., every minute, every thirty seconds, etc.) and / or aperiodically (e.g., upon booting the computing platform 104, upon execution of a process by the computing platform 104, upon request from a user, upon detection of a change in the workload performed by the computing platform 104, etc.). If the example frequency generation circuit module 212 determines that the overclocked frequency should be adjusted (e.g., block 615 returns a result of yes), control passes to block 605, where the frequency generation circuit module 212 collects workload information.

[0119] If the example frequency generation circuit module 212 determines that the overclocked frequency is not to be adjusted (e.g., block 615 returns a result of no), the example frequency generation circuit module 212 waits (block 620) and then determines again whether to re-perform the adjustment of the overclocked frequency (block 615). Figure 6 The process may be restarted, e.g., may return to block 602, where the AI ​​model is retrieved. Such re-retrieval may be performed periodically and / or aperiodically. For example, re-retrieval of the model may be the result of detecting a fault in overclocking (e.g., a system failure due to an identified overclock frequency that is too high and crashes the system and / or other problems).

[0120] Figure 7 is an example set of overclocking results. In some examples, the example overclocking circuit module 110 generates using the example model updater circuit module 206, the example comparator circuit module 210, and the example frequency generation circuit module 212 Figure 7 In some examples, the model generator circuit module 102 generates the example model trainer circuit module 256, the example model tuner circuit module 258, and the example cloud computing circuit module 260. Figure 7 result. Figure 7 The results are shown in graph 700 . Figure 7The results of the example compare the possible overclocked frequencies of 5.5 GHz, 5.6 GHz, and 5.7 GHz along the percentage value axis 702 (e.g., vertical axis). The percentage values ​​of the percentage value axis 702 represent the accuracy of predicting the maximum frequency to be used in overclocking. The example horizontal axis shows different performance metrics 704, 706, 708, 710 (based on the three overclocked frequencies). The example first performance metric 704 shows the balanced accuracy of the three overclocked frequencies 5.5 GHz, 5.6 GHz, and 5.7 GHz. The example second performance metric 706 shows the F-1 score of the first overclocked frequency value (e.g., 5.5 GHz). The example third performance metric 708 shows the F-1 score of the second overclocked frequency value (e.g., 5.6 GHz). The example fourth performance metric 710 shows the F-1 score of the third overclocked frequency value (e.g., 5.7 GHz). The F-1 score is the harmonic average of the precision score and the recall score.

[0121] like Figure 7 As shown in the example of , the first performance metric 704 scores 90.1%, the second performance metric 706 scores 95.3%, the third performance metric 708 scores 87.6%, and the fourth performance metric 710 scores 90.5%. In some examples, the prediction of the maximum frequency value is based on performing overclocking by setting the clock frequency to 5.5 GHz, 5.6 GHz, or 5.7 GHz on a large number of computing platforms (e.g., thirty computing platforms, seventy-eight computing platforms). In other examples, different overclocking frequencies (e.g., 0.5 GHz, 3 GHz, 4 GHz, 10 GHz, 100 GHz) can be used. However, the higher the overclocking frequency, the higher the possibility of computing platform failure and / or processor overheating.

[0122] In some examples, different overclocking frequencies are selected for different workloads classified in different pressures. In other examples, a single overclocking frequency is selected regardless of the classification of the different workloads.

[0123] Figure 8 is a block diagram of an example programmable circuit module platform 800 configured to execute and / or instantiate Figure 4 and Figure 6 Example machine readable instructions and / or example operations (to implement Figure 2A Overclocking circuit module 110) and Figure 5 Example machine readable instructions and / or example operations (to implement Figure 2B The programmable circuit module platform 800 may be, for example, a server, a personal computer, a workstation, a self-learning machine (eg, a neural network), or any other type of computing and / or electronic device.

[0124] The example programmable circuit module platform 800 shown includes a programmable circuit module 812. The example programmable circuit module 812 shown is hardware. For example, the programmable circuit module 812 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers (from any desired family or manufacturer). The programmable circuit module 812 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit module 812 implements the example network interface 204, the example model updater circuit module 206, the example overclocking execution circuit module 208, the example comparator circuit module 210, the example frequency generation circuit module 212, the example timer circuit module 214, the example security circuit module 252, the example network interface 254, the example model trainer circuit module 256, the example model tuner circuit module 258, the example cloud computing circuit module 260, and the example platform operator circuit module 262.

[0125] The example programmable circuit module 812 includes a local memory 813 (e.g., cache, registers, etc.). The example programmable circuit module 812 communicates with main memories 814 and 816 via a bus 818. The main memories 814 and 816 include a volatile memory 814 and a non-volatile memory 816. The volatile memory 814 can be composed of a synchronous dynamic random access memory (SDRAM), a dynamic random access memory (DRAM), Dynamic Random Access Memory The non-volatile memory 816 may be implemented by flash memory and / or any other desired type of memory device. Access to the main memory 814, 816 of the illustrated example is controlled by a memory controller 817. In some examples, the memory controller 817 may be implemented by one or more integrated circuits, logic circuits, microcontrollers (from any desired family or manufacturer), or any other type of circuit module to manage the flow of data into and out of the main memory 814, 816.

[0126] The example programmable circuit module platform 800 shown also includes an interface circuit module 820. The interface circuit module 820 can be implemented by hardware that complies with any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, and / or a peripheral component interconnect express (PCIe) interface.

[0127] In the example shown, one or more input devices 822 are connected to the interface circuit module 820. The input device(s) 822 permit a user (e.g., a human user, a machine user, etc.) to input data and / or commands into the programmable circuit module 812. The input device(s) 822 may be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touch screen, a trackpad, a trackball, an isopoint device, and / or a voice recognition system.

[0128] One or more output devices 824 are also connected to the illustrated example interface circuit module 820. The output device(s) 824 may be implemented, for example, by a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-plane switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. Therefore, the illustrated example interface circuit module 820 typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuit module (such as a GPU).

[0129] The illustrated example interface circuit module 820 also includes a communication device, such as a transmitter, receiver, transceiver, modem, residential gateway, wireless access point, and / or network interface, which facilitates the exchange of data with an external machine (e.g., any kind of computing device) over a network 826. Communications may be through, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-sight wireless system, a line-of-sight wireless system, a cellular telephone system, an optical connection, etc.

[0130] The illustrated example programmable circuit module platform 800 also includes one or more mass storage disks or devices 828 for storing firmware, software, and / or data. Examples of such mass storage disks or devices 828 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices (such as flash memory devices and / or SSDs).

[0131] Machine readable instructions 832 (which may be Figure 4-Figure 6 The computer-readable storage medium 820 (implemented by machine-readable instructions) may be stored in mass storage device 828, in volatile memory 814, in non-volatile memory 816, and / or on at least one non-transitory computer-readable storage medium (such as a CD or DVD, which may be removable).

[0132] Fig. 9 yes Figure 8812 is a block diagram of an example implementation of a programmable circuit module 812. In this example, Figure 8 The programmable circuit module 812 is implemented by the microprocessor 900. For example, the microprocessor 900 may be a general-purpose microprocessor (eg, a general-purpose microprocessor circuit module). The microprocessor 900 executes Figure 4-Figure 6 Some or all of the machine readable instructions of the flowchart to effectively Figure 2A-2B The circuit modules of the machine readable instructions are instantiated as logic circuits to perform operations corresponding to those machine readable instructions. In some such examples, Figure 2A-2B The circuit modules are instantiated by the hardware circuits of the microprocessor 900 in combination with machine-readable instructions. For example, the microprocessor 900 may be implemented by a multi-core hardware circuit module (such as a CPU, DSP, GPU, XPU, etc.). Although it may include any number of example cores 902 (e.g., 1 core), the microprocessor 900 of this example is a multi-core semiconductor device including N cores. The cores 902 of the microprocessor 900 may operate independently or may collaborate to execute machine-readable instructions. For example, machine code corresponding to a firmware program, an embedded software program, or a software program may be executed by one of the cores in the core 902, or may be executed by multiple cores in the core 902 at the same or different times. In some examples, the machine code corresponding to the firmware program, the embedded software program, or the software program is split into threads and executed in parallel by two or more cores in the core 902. The software program may correspond to a program executed by Figure 4-Figure 6 The flowcharts represent a portion or all of machine-readable instructions and / or operations.

[0133] The core 902 can communicate via a first example bus 904. In some examples, the first bus 904 can be implemented by a communication bus to implement communications associated with the core (one or more) of the core 902. For example, the first bus 904 can be implemented by at least one of an interconnect integrated circuit (I2C) bus, a serial peripheral interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 904 can be implemented by any other type of computing or electrical bus. The core 902 can obtain data, instructions, and / or signals from one or more external devices via an example interface circuit module 906. The core 902 can output data, instructions, and / or signals to the one or more external devices via the interface circuit module 906. Although the core 902 of this example includes an example local memory 920 (e.g., a level 1 (L1) cache, which can be split into an L1 data cache and an L1 instruction cache), the microprocessor 900 also includes an example shared memory 910 (e.g., a level 2 (L2 cache)) that can be shared by the core for high-speed access to data and / or instructions. Data and / or instructions may be transferred (e.g., shared) by writing to and / or reading from the shared memory 910. The local memory 920 of each core in the core 902 and the shared memory 910 may be a plurality of levels of cache memory and main memory (e.g., Figure 8 Cache memory is part of a hierarchy of storage devices (main memory 814, 816). Generally, memory at higher levels in the hierarchy exhibits lower access times and has smaller storage capacity than memory at lower levels. Changes in the various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherence policy.

[0134] Each core 902 may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuit module. Each core 902 includes a control unit circuit module 914, an arithmetic and logic (AL) circuit module (sometimes referred to as an ALU) 916, a plurality of registers 918, a local memory 920, and a second example bus 922. Other structures may exist. For example, each core 902 may include a vector unit circuit module, a single instruction multiple data (SIMD) unit circuit module, a load / store unit (LSU) circuit module, a branch / jump unit circuit module, a floating point unit (FPU) circuit module, etc. The control unit circuit module 914 includes a semiconductor-based circuit that is configured to control (e.g., coordinate) data movement within the corresponding core 902. The AL circuit module 916 includes a semiconductor-based circuit that is configured to perform one or more mathematical and / or logical operations on data within the corresponding core 902. The AL circuit module 916 of some examples performs integer-based operations. In other examples, the AL circuit module 916 also performs floating-point operations. In still other examples, AL circuit module 916 may include a first AL circuit module that performs integer-based operations and a second AL circuit module that performs floating-point operations. In some examples, AL circuit module 916 may be referred to as an arithmetic logic unit (ALU).

[0135] Registers 918 are semiconductor-based structures for storing data and / or instructions, such as the results of one or more of the operations performed by the AL circuit module 916 of the corresponding core 902. For example, registers 918 may include vector register(s), SIMD register(s), general register(s), flag register(s), segment register(s), machine-specific register(s), instruction pointer register(s), control register(s), debug register(s), memory management register(s), machine check register(s), etc. Fig. 9 As shown in FIG. 1 , registers 918 may be arranged in a memory bank. Alternatively, registers 918 may be organized in any other arrangement, format, or structure, such as by being distributed throughout core 902 to shorten access time. Second bus 922 may be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0136] Each core 902 and / or (more generally) microprocessor 900 may include additional and / or alternative structures to those described and shown above. For example, one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHA), one or more convergence / common grid stops (CMS), one or more shifters (e.g., (one or more) barrel shifters), and / or other circuit modules may be present. Microprocessor 900 is a semiconductor device that is fabricated to include many transistors that are interconnected to implement the structures described above (in one or more integrated circuits (ICs) contained in one or more packages).

[0137] The microprocessor 900 may include and / or collaborate with one or more accelerators (e.g., acceleration circuit modules, hardware accelerators, etc.). In some examples, the accelerator is implemented by a logic circuit module to perform certain tasks faster and / or efficiently (compared to certain tasks that can be performed by a general-purpose processor). Examples of accelerators include ASICs and FPGAs, such as those discussed herein. GPUs, DSPs, and / or other programmable devices may also be accelerators. The accelerator may be mounted on the microprocessor 900, in the same chip package as the microprocessor 900, and / or in one or more packages separated from the microprocessor 900.

[0138] Fig.10 yes Figure 8 1 is a block diagram of another example implementation of a programmable circuit module 812. In this example, the programmable circuit module 812 is implemented by an FPGA circuit module 1000. For example, the FPGA circuit module 1000 can be implemented by an FPGA. The FPGA circuit module 1000 can be used, for example, to perform operations that would otherwise be performed by Fig. 9 However, once configured, the FPGA circuit module 1000 instantiates the operations and / or functions corresponding to the machine-readable instructions in hardware, and therefore, the operations / functions can generally be performed faster (compared to the corresponding software that can be executed by a general-purpose microprocessor).

[0139] More specifically, compared to the above description Fig. 9 The microprocessor 900 (which can be programmed to execute Figure 4-Figure 6 (one or more) flowcharts representing all or some of the machine-readable instructions, but once made, its interconnections and logic circuit modules are fixed), Fig.10 The example FPGA circuit module 1000 includes interconnects and logic circuit modules that can be configured, constructed, programmed, and / or interconnected in different ways after manufacture to instantiate, for example, Figure 4-Figure 6 The FPGA circuit module 1000 may be programmed to change how the logic gates are connected to each other through the interconnections, thereby effectively forming one or more dedicated logic circuits (unless and until the FPGA circuit module 1000 is reprogrammed). The configured logic circuits enable the logic gates to cooperate in different ways to perform different operations on the data received by the input circuit module. Those operations may correspond to the operations performed by the FPGA circuit module 1000. Figure 4-Figure 6 As such, the FPGA circuit module 1000 may be configured and / or constructed to effectively communicate with Figure 4-Figure 6 Some or all of the operations / functions corresponding to the machine-readable instructions of the (one or more) flowcharts are instantiated into dedicated logic circuits to perform the operations / functions corresponding to those software instructions (in a dedicated manner similar to an ASIC). Therefore, compared to a general-purpose microprocessor, it can perform the same Figure 4-Figure 6 By performing operations / functions corresponding to some or all of the machine-readable instructions, the FPGA circuit module 1000 can perform the same operations / functions faster.

[0140] exist Fig.10 In the example, the FPGA circuit module 1000 is configured and / or constructed in response to being programmed (and / or reprogrammed one or more times) based on a binary file. In some examples, the binary file can be compiled and / or generated based on instructions in a hardware description language (HDL), such as Lucid, Very High Speed ​​Integrated Circuit (VHSIC) Hardware Description Language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) can write a program or code corresponding to one or more operations / functions in the HDL; the code / program can be translated into a low-level language as needed; and the code / program (e.g., code / program in a low-level language) can be converted (e.g., by a compiler, a software application, etc.) into a binary file. In some examples, Fig.10 The FPGA circuit module 1000 can access and / or load binary files to enable Fig.10 The FPGA circuit module 1000 is configured and / or constructed to perform the one or more operations / functions. For example, a binary file may be generated by Fig.10 The FPGA circuit module 1000 can access a bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.) and / or machine-readable instructions to cause Fig.10 Configuration and / or structuring of FPGA circuit module 1000 or (one or more) parts thereof.

[0141] In some examples, the binary file is compiled, generated, transformed, and / or otherwise output from a unified software platform for programming the FPGA. For example, the unified software platform can translate a first instruction (e.g., code or program) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) into a second instruction in the HDL corresponding to the one or more operations / functions. In some such examples, the binary file is compiled, generated, and / or otherwise output from the unified software platform based on the second instruction. In some examples, Fig.10 The FPGA circuit module 1000 can access and / or load binary files to enable Fig.10 The FPGA circuit module 1000 is configured and / or constructed to perform the one or more operations / functions. For example, a binary file may be generated by Fig.10 The FPGA circuit module 1000 can access a bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.) and / or machine-readable instructions to cause Fig.10 Configuration and / or structuring of FPGA circuit module 1000 or (one or more) parts thereof.

[0142] Fig.10 FPGA circuit module 1000 includes an example input / output (I / O) circuit module 1002, which is used to obtain and / or output data from / to an example configuration circuit module 1004 and / or external hardware 1006. For example, the configuration circuit module 1004 can be implemented by an interface circuit module, which can obtain a binary file (which can be implemented by a bitstream, data and / or machine-readable instructions) to configure the FPGA circuit module 1000 or (one or more) parts thereof. In some such examples, the configuration circuit module 1004 can obtain the binary file from a user, a machine (e.g., a hardware circuit module (e.g., a programmable or dedicated circuit module) that can implement an artificial intelligence / machine learning (AI / ML) model to generate a binary file), etc. and / or any combination thereof. In some examples, the external hardware 1006 can be implemented by an external hardware circuit module. For example, the external hardware 1006 can be implemented by Fig. 9 The microprocessor 900 is implemented.

[0143] FPGA circuit module 1000 also includes an array of example logic gate circuit modules 1008, a plurality of example configurable interconnects 1010, and example storage circuit modules 1012. Logic gate circuit modules 1008 and configurable interconnects 1010 may be configured to instantiate one or more operations / functions that may correspond to Figure 4-Figure 6 At least some of the machine-readable instructions and / or other desired operations. Fig.10 The logic gate circuit module 1008 shown in is made in blocks or groups. Each block contains a semiconductor-based electrical structure that can be configured into a logic circuit. In some examples, the electrical structure contains a logic gate (e.g., an AND gate, an OR gate, a NOT gate, etc.), which provides a basic building block for a logic circuit. An electrically controllable switch (e.g., a transistor) is present in each of the logic gate circuit modules 1008 so that the configuration of the logic gate and / or the electrical structure can form a circuit to perform a desired operation / function. The logic gate circuit module 1008 may include other electrical structures, such as a lookup table (LUT), a register (e.g., a flip-flop or a latch), a multiplexer, etc.

[0144] The example configurable interconnect 1010 shown is a conductive path, trace, via, or the like, which may include an electrically controllable switch (e.g., a transistor) whose state can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more logic gate circuit modules in the logic gate circuit module 1008 to program the desired logic circuit.

[0145] The storage circuit module 1012 of the illustrated example is configured to store the result(s) of one or more operations performed by the corresponding logic gates. The storage circuit module 1012 may be implemented by a register or the like. In the illustrated example, the storage circuit module 1012 is distributed in the logic gate circuit module 1008 to facilitate access and improve execution speed.

[0146] Fig.10The example FPGA circuit module 1000 also includes an example dedicated operation circuit module 1014. In this example, the dedicated operation circuit module 1014 includes a dedicated circuit module 1016, which can be called to implement common functions to avoid the need to program those functions on site. Examples of such dedicated circuit modules 1016 include memory (e.g., DRAM) controller circuit modules, PCIe controller circuit modules, clock circuit modules, transceiver circuit modules, memory, and multiplier accumulator circuit modules. There may be other types of dedicated circuit modules. In some examples, the FPGA circuit module 1000 may also include an example general programmable circuit module 1018, such as an example CPU 1020 and / or an example DSP 1022. Additionally or alternatively, there may be other general programmable circuit modules 1018 that can be programmed to perform other operations, such as GPUs, XPUs, etc.

[0147] Although Fig. 9 and Fig.10 Show Figure 8 These are two example implementations of the programmable circuit module 812, but many other implementations are also contemplated. For example, the FPGA circuit module may include an onboard CPU, such as Fig.10 One or more of the example CPUs 1020. Thus, Figure 8 The programmable circuit module 812 may additionally be configured by combining at least Fig. 9 An example microprocessor 900 and Fig.10 In some such hybrid examples, Fig. 9 One or more cores 902 may execute Figure 4-Figure 6 The flowchart(s) represent a first portion of machine-readable instructions to perform a first operation(s) / function(s), Fig.10 The FPGA circuit module 1000 may be configured and / or constructed to perform the same as that Figure 4-Figure 6 The second portion of the machine-readable instructions represented by the flowchart corresponds to a second (one or more) operation / (one or more) functions, and / or the ASIC can be configured and / or constructed to perform the same as the second portion of the machine-readable instructions represented by the flowchart ... Figure 4-Figure 6 The third portion of the machine-readable instructions represented by the flowchart corresponds to a third (one or more) operation / (one or more) function.

[0148] It should be understood that: Figure 2A-2B Some or all of the circuit modules of can therefore be instantiated at the same or different times. For example, Fig. 9 The same and / or different (one or more) portions of the microprocessor 900 can be programmed at the same and / or different times to execute (one or more) portions of the machine-readable instructions. In some examples, Fig.10 The same and / or different (one or more) parts of the FPGA circuit module 1000 can be configured and / or constructed at the same and / or different times to perform operations / functions corresponding to (one or more) parts of the machine-readable instructions.

[0149] In some examples, Figure 2A-2B Some or all of the circuit modules of can be instantiated, for example, in one or more threads that are executed serially and / or simultaneously. Fig. 9 The microprocessor 900 can execute machine-readable instructions in one or more threads that are executed serially and / or simultaneously. In some examples, Fig.10 The FPGA circuit module 1000 can be configured and / or constructed to perform operations / functions simultaneously and / or in series. In addition, in some examples, Figure 2A-2B Some or all of the circuit modules in the circuit module can be Fig. 9 The microprocessor 900 is implemented within one or more virtual machines and / or containers.

[0150] In some examples, Figure 8 The programmable circuit module 812 can be in one or more packages. For example, Fig.10 FPGA circuit module 1000 and / or Fig. 9 The microprocessor 900 may be in one or more packages. In some examples, the XPU may be provided by Figure 8 The XPU may include a CPU in one package (e.g., Fig. 9 Microprocessor 900, Fig.10 CPU 1020, etc.), a DSP in another package (e.g. Fig.10 DSP 1022 of ), a GPU in still another package, and an FPGA in still another package (e.g., Fig.10 FPGA circuit module 1000).

[0151] Fig.11 The diagram shows a method for converting software such as Figure 8832) to other hardware devices (e.g., hardware devices operated and / or owned by third parties from the owners and / or operators of the software distribution platform). The example software distribution platform 1105 can be implemented by any computer server, data facility, cloud service, etc. that can store and transfer software to other computing devices. The third party can be a customer of the entity that owns and / or operates the software distribution platform 1105. For example, the entity that owns and / or operates the software distribution platform 1105 can be a software (such as Figure 8 The third party may be a consumer, user, retailer, OEM, etc., who purchases and / or licenses the software for use and / or resale and / or sub-licensing. In the example shown, the software distribution platform 1105 includes one or more servers and one or more storage devices. The storage device stores the machine-readable instructions 832, which may correspond to Figure 4-Figure 6 The one or more servers of the example software distribution platform 1105 communicate with the example network 1110, which may correspond to any of the example networks described above and / or any one or more networks on the Internet. In some examples, as part of a commercial transaction, the one or more servers transmit the software to the requestor in response to the request. Payment for the license, sale, and / or delivery of the software may be handled by one or more servers of the software distribution platform and / or by a third-party payment entity. The server enables purchasers and / or licensors to download machine-readable instructions 832 from the software distribution platform 1105. For example, the software (which may correspond to Figure 4-Figure 6 832 to implement the overclocking circuit module 110. In some examples, one or more servers of the software distribution platform 1105 periodically propose, transmit and / or force software updates (e.g., Figure 8 Example machine readable instructions 832) to ensure that improvements, patches, updates, etc. are distributed and applied to the software on the end-user device. Although referred to as software above, alternatively, the distributed "software" may also be firmware.

[0152] It will be appreciated from the foregoing that example systems, devices, articles, and methods for performing cloud-based artificial intelligence overclocking have been disclosed. The disclosed systems, devices, articles, and methods improve the efficiency of using computing devices by determining overclocked frequencies that allow computing devices to perform more efficiently. The disclosed systems, devices, articles, and methods improve the efficiency of using computing devices by training multiple AI models, wherein the AI ​​models are used to predict overclocked frequencies. The AI ​​model is to predict the maximum overclocked frequency based on system telemetry data, rather than the user manually determining various overclocked frequencies (which wastes processing power and computing time). The overclocked frequency can be set based on the recommendation of the AI ​​model, which improves the performance of the computing device faster than humans determine the overclocked frequency. Therefore, the disclosed systems, devices, articles, and methods relate to (one or more) improvements in the operation of machines such as computers or other electronic and / or mechanical devices.

[0153] Disclosed herein are example methods, devices, systems, and articles of manufacture for performing cloud-based artificial intelligence overclocking. Further examples and combinations thereof include the following:

[0154] Example 1 includes a device for performing cloud-based artificial intelligence (AI) overclocking, the device comprising: an interface circuit module, machine-readable instructions, and a programmable circuit module, the programmable circuit module being used to instantiate or execute at least one of the machine-readable instructions to collect workload information, the workload information representing a workload to be performed by a first computing platform; causing generation of an output from an AI model based on the workload information, the output representing an overclocked frequency value to be used for operations of the first computing platform; and performing overclocking based on the overclocked frequency value.

[0155] Example 2 includes an apparatus as described in Example 1, wherein, to cause generation of the output from the AI ​​model, the programmable circuit module is to: obtain a local copy of the AI ​​model; and execute the AI ​​model based on the workload information.

[0156] Example 3 includes an apparatus as described in Example 1, wherein, in order to cause the generation of the output from the AI ​​model, the programmable circuit module is to transmit the workload information to a model generator and request the model generator to use the workload information to generate the output.

[0157] Example 4 includes the apparatus of Example 1, wherein the workload information includes system telemetry data, the system telemetry data including at least one of voltage data, temperature data, individual core power data, and multi-core power data.

[0158] Example 5 includes a device as described in Example 1, wherein the AI ​​model is trained by a model generator circuit module separate from the device, and the programmable circuit module is to tune the AI ​​model.

[0159] Example 6 includes an apparatus as described in Example 5, wherein, in order to tune the AI ​​model, the programmable circuit module is to: determine the importance of a corresponding feature of the AI ​​model, the feature being associated with a first overclocking performance; and minimize the feature of the AI ​​model based on the importance.

[0160] Example 7 includes the apparatus of Example 1, wherein the programmable circuit module is to determine to collect subsequent workload information after performing overclocking on the first computing platform, wherein the subsequent workload information is used to adjust the overclocking frequency value.

[0161] Example 8 includes a non-transitory machine-readable storage medium comprising instructions for causing a programmable circuit module to perform at least the following operations: collect workload information, the workload information representing a workload to be executed by a first computing platform; cause generation of an output from an AI model based on the workload information, the output representing an overclocked frequency value to be used for operations of the first computing platform; and perform overclocking based on the overclocked frequency value.

[0162] Example 9 includes a non-transitory machine-readable storage medium as described in Example 8, wherein the instructions are used to cause the programmable circuit module to: obtain a local copy of the AI ​​model; and execute the AI ​​model based on the workload information.

[0163] Example 10 includes the non-transitory machine-readable storage medium of Example 8, wherein the instructions are for causing the programmable circuit module to transmit the workload information to a model generator and request the model generator to generate the output using the workload information.

[0164] Example 11 includes the non-transitory machine-readable storage medium of Example 8, wherein the workload information includes system telemetry data, the system telemetry data including at least one of voltage data, temperature data, individual core power data, and multi-core power data.

[0165] Example 12 includes a non-transitory machine-readable storage medium as described in Example 8, wherein the AI ​​model is trained by a cloud-based model generator separate from the programmable circuit module, and the instructions are used to cause the programmable circuit module to tune the AI ​​model.

[0166] Example 13 includes a non-transitory machine-readable storage medium as described in Example 12, wherein, in order to tune the AI ​​model, the instructions are used to cause the programmable circuit module to: determine the importance of a corresponding feature of the AI ​​model, the feature being associated with a first overclocking performance; and minimize the feature of the AI ​​model based on the importance.

[0167] Example 14 includes a non-transitory machine-readable storage medium as described in Example 13, wherein the instructions are used to enable the programmable circuit module to determine to collect subsequent workload information after performing overclocking on the first computing platform, and the subsequent workload information is used to adjust the overclocking frequency.

[0168] Example 15 includes a method, comprising collecting workload information by executing instructions with at least one processor, the workload information representing a workload to be performed by a first computing platform; based on the workload information, causing generation of an output from an AI model by executing instructions with the at least one processor, the output representing an overclocked frequency value to be used for operations of the first computing platform; and performing overclocking by executing instructions with the processor based on the overclocked frequency value.

[0169] Example 16 includes the method as described in Example 15, further comprising: obtaining a local copy of the AI ​​model; and executing the AI ​​model based on the workload information.

[0170] Example 17 includes the method of Example 15, further comprising: transmitting the workload information to a model generator; and requesting the model generator to generate the output using the workload information.

[0171] Example 18 includes the method of Example 15, wherein the workload information includes system telemetry data, the system telemetry data including at least one of voltage data, temperature data, individual core power data, and multi-core power data.

[0172] Example 19 includes a method as described in Example 15, wherein the AI ​​model is trained by a cloud-based model generation entity, and the method further includes tuning the AI ​​model.

[0173] Example 20 includes the method of Example 19, wherein the tuning the AI ​​model includes: determining an importance of a corresponding feature of the AI ​​model, the feature being associated with a first overclocking performance; and minimizing the feature of the AI ​​model based on the importance.

[0174] The accompanying claims are hereby incorporated into this detailed description by this reference. Although certain example systems, devices, articles, and methods have been disclosed herein, the coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, devices, articles, and methods that fully fall within the scope of the claims of this patent.

Claims

1. A device for performing cloud-based artificial intelligence (AI) overclocking, the device comprising: Interface circuit module; machine-readable instructions; as well as a programmable circuit module configured to at least one of instantiate or execute the machine-readable instructions to: collecting workload information, the workload information representing a workload to be executed by the first computing platform; causing generation of an output from an AI model based on the workload information, the output representing an overclocked frequency value to be used for operation of the first computing platform; as well as Overclocking is performed based on the overclocking frequency value.

2. The device according to claim 1, wherein: To cause generation of the output from the AI ​​model, the programmable circuit module is to: obtaining a local copy of the AI ​​model; and The AI ​​model is executed based on the workload information.

3. The device according to any one of claims 1 to 2, wherein: To cause the generation of the output from the AI ​​model, the programmable circuit module is to transmit the workload information to a model generator and request the model generator to generate the output using the workload information.

4. The device according to any one of claims 1 to 3, wherein: The workload information includes system telemetry data, and the system telemetry data includes at least one of voltage data, temperature data, individual core power data, and multi-core power data.

5. The device according to any one of claims 1 to 4, wherein: The AI ​​model is trained by a model generator circuit module separate from the device, and the programmable circuit module is to tune the AI ​​model.

6. The device of claim 5, wherein: To tune the AI ​​model, the programmable circuit module: determining an importance of a corresponding feature of the AI ​​model, the feature being associated with a first overclocking performance; and The features of the AI ​​model are minimized based on the importance.

7. The device according to any one of claims 1 to 6, wherein: The programmable circuit module is to determine and collect subsequent workload information after executing overclocking on the first computing platform, and the subsequent workload information is used to adjust the overclocking frequency value.

8. A machine-readable storage medium comprising instructions for causing a programmable circuit module to at least perform the following operations: collecting workload information, the workload information representing a workload to be executed by the first computing platform; causing generation of an output from an AI model based on the workload information, the output representing an overclocked frequency value to be used for operation of the first computing platform; as well as Overclocking is performed based on the overclocking frequency value.

9. The machine-readable storage medium of claim 8, wherein: The instructions are used to enable the programmable circuit module to: obtaining a local copy of the AI ​​model; and The AI ​​model is executed based on the workload information.

10. The machine-readable storage medium according to any one of claims 8 to 9, wherein: The instructions are for causing the programmable circuit module to transmit the workload information to a model generator and request the model generator to generate the output using the workload information.

11. The machine-readable storage medium according to any one of claims 8 to 10, wherein: The workload information includes system telemetry data, and the system telemetry data includes at least one of voltage data, temperature data, individual core power data, and multi-core power data.

12. The machine-readable storage medium according to any one of claims 8 to 11, wherein: The AI ​​model is trained by a cloud-based model generator separate from the programmable circuit module, and the instructions are used to cause the programmable circuit module to tune the AI ​​model.

13. The machine-readable storage medium of claim 12, wherein: In order to tune the AI ​​model, the instructions are used to cause the programmable circuit module to: determining an importance of a corresponding feature of the AI ​​model, the feature being associated with a first overclocking performance; and The features of the AI ​​model are minimized based on the importance.

14. The machine-readable storage medium of claim 13, wherein: The instruction is used to enable the programmable circuit module to determine and collect subsequent workload information after executing overclocking on the first computing platform, and the subsequent workload information is used to adjust the overclocking frequency.

15. A method comprising: collecting workload information, the workload information representing a workload to be executed by the first computing platform; causing generation of an output from an AI model based on the workload information, the output representing an overclocked frequency value to be used for operation of the first computing platform; as well as Based on the overclocking frequency value, overclocking is performed.

16. The method of claim 15, further comprising: obtaining a local copy of the AI ​​model; and The AI ​​model is executed based on the workload information.

17. The method of any one of claims 15-16, further comprising: transmitting the workload information to a model generator; and requesting the model generator to generate the output using the workload information.

18. The method according to any one of claims 15 to 17, wherein: The workload information includes system telemetry data, and the system telemetry data includes at least one of voltage data, temperature data, individual core power data, and multi-core power data.

19. The method according to any one of claims 15 to 18, wherein: The AI ​​model is trained by a cloud-based model generation entity, and the method also includes tuning the AI ​​model.

20. The method of claim 19, wherein: Tuning the AI ​​model includes: determining an importance of a corresponding feature of the AI ​​model, the feature being associated with a first overclocking performance; and The features of the AI ​​model are minimized based on the importance.

21. A machine-readable medium comprising code, which, when executed, causes a machine to perform the method of any one of claims 15-20.

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