Display device

Abstract

There is provided a display device including: a pixel including a light emitting element; and a data driver configured to sequentially provide a first data signal and a second data signal to the pixel in a frame period including a first period and a second period, in which the pixel is configured to emit light during the first period based on the first data signal, and to emit light during the second period based on the second data signal. And emitting light during a second period based on the second data signal, where the pixel is configured to emit light equally in the first period and the second period when the gradation value for the pixel is greater than a reference gradation value, and where the pixel is configured to emit light equally in the second period when the gradation value is less than or equal to the reference gradation value. The pixel is configured to emit light differently compared to the second period in the first period, or emit light in the first period and not emit light in the second period.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0113169 filed in the Korean Intellectual Property Office on August 28, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to display devices. Background Art

[0004] The display device includes at least one pixel, and the pixel includes a light emitting element and a driving transistor. The display device can express grayscale by controlling a driving current flowing through the light emitting element using the driving transistor.

[0005] A low grayscale corresponding to a driving current having a low intensity may not be accurately expressed due to dispersion of a driving current flowing through the light-emitting element, due to leakage current, etc. In addition, as the magnitude of the driving current is large or small, the color (or wavelength) of light emitted from the light-emitting element may shift, and a desired color may not be accurately expressed in a low grayscale area. Summary of the invention

[0006] Embodiments provide a display device capable of accurately expressing low grayscales.

[0007] According to one aspect of the present disclosure, a display device is provided, comprising: a pixel comprising a light-emitting element; and a data driver configured to sequentially provide a first data signal and a second data signal to the pixel in a frame period including a first period and a second period, wherein the pixel is configured to emit light during the first period based on the first data signal, and to emit light during the second period based on the second data signal, wherein when a grayscale value for the pixel is greater than a reference grayscale value, the pixel is configured to emit light equally in the first period and the second period, and wherein when the grayscale value is less than or equal to the reference grayscale value, the pixel is configured to emit light differently in the first period than in the second period, or to emit light in the first period and not to emit light in the second period.

[0008] The display device may further include a controller configured to generate a first data value and a second data value based on a grayscale value of the frame data, wherein the data driver is configured to generate a first data signal based on the first data value and generate a second data signal based on the second data value.

[0009] When the grayscale value is greater than a reference grayscale value, each of the first data value and the second data value may be equal to the grayscale value, wherein when the grayscale value is less than or equal to the reference grayscale value, the first data value is greater than the grayscale value and the second data value is less than the grayscale value.

[0010] When the gray value is less than or equal to a reference gray value, the pixel may be configured to emit light having a brightness higher than a target brightness corresponding to the gray value in a first period and not to emit light in a second period.

[0011] When the grayscale value is less than or equal to the reference grayscale value, the pixel may be configured to emit light having a lower brightness in the second period than in the first period.

[0012] The width of the first period may be equal to the width of the second period.

[0013] The width of the second period may be greater than the width of the first period.

[0014] The data driver may be configured to supply the first data signal to the pixel at a start time of the first cycle, and to supply the second data signal to the pixel at a start time of the second cycle.

[0015] The pixel may also include: a first transistor, the first transistor including a first electrode electrically connected to a first power line and a second electrode electrically connected to the light emitting element; a second transistor, the second transistor electrically connected between a data line and a gate electrode of the first transistor and including a gate electrode connected to a first scan line; and a first capacitor, the first capacitor electrically connected between the gate electrode of the first transistor and the second electrode of the first transistor, wherein the first data signal and the second data signal are applied to the data line.

[0016] The pixel may further include: a third transistor electrically connected between the readout line and the second electrode of the first transistor.

[0017] The light-emitting element can be electrically connected between the first transistor and the second power line, wherein the pixel also includes: a sixth transistor, which is electrically connected between the gate electrode of the first transistor and the second power line; a fourth transistor, which is electrically connected between the data line and the intermediate node and includes a gate electrode electrically connected to the second scan line; a fifth transistor, which is electrically connected between the intermediate node and the gate electrode of the sixth transistor and includes a gate electrode electrically connected to the third scan line; and a second capacitor, which is electrically connected between the intermediate node and the second power line, and wherein the first scan line, the second scan line and the third scan line are different from each other.

[0018] The display device may further include a gate driver connected to the first scan line, the second scan line, and the third scan line, configured to apply a first scan signal having an on-voltage level to the first scan line and a second scan signal having an on-voltage level to the second scan line in a first cycle, and configured to apply a third scan signal having an on-voltage level to the third scan line in a second cycle, wherein the data driver is configured to provide a first data signal to the pixel at a time corresponding to the first scan signal, and to provide a second data signal to the pixel at a time corresponding to the second scan signal.

[0019] The third scan signal having the turn-on voltage level may be applied during the entire second period.

[0020] The second data signal may have a gate-off voltage level when the gray value is greater than a reference gray value, wherein the second data signal has a gate-on voltage level when the gray value is less than or equal to the reference gray value.

[0021] When the grayscale value is less than or equal to the reference grayscale value, the pixel may be configured not to emit light in the second period.

[0022] The grayscale value may be in the range of a minimum grayscale value to a maximum grayscale value, wherein the reference grayscale value is greater than about 1 / 10 of the maximum grayscale value and less than or equal to about 1 / 2 of the maximum grayscale value.

[0023] According to another aspect of the present disclosure, a display device is provided, which includes a pixel, wherein the pixel includes: a light-emitting element electrically connected between a first power line and a second power line; a first transistor, the first transistor including a first electrode electrically connected to the first power line and a second electrode electrically connected to the light-emitting element; a second transistor, the second transistor is electrically connected between a data line and a gate electrode of the first transistor, and includes a gate electrode electrically connected to a first scan line; a first capacitor, the first capacitor is electrically connected between the gate electrode of the first transistor and the second electrode of the first transistor; a sixth transistor, the sixth transistor is electrically connected between the gate electrode of the first transistor and the second power line; a fourth transistor, the fourth transistor is electrically connected between the data line and an intermediate node, and includes a gate electrode electrically connected to the second scan line; a fifth transistor, the fifth transistor is electrically connected between the intermediate node and the gate electrode of the sixth transistor, and includes a gate electrode electrically connected to a third scan line; and a second capacitor, the second capacitor is electrically connected between the intermediate node and the second power line.

[0024] The pixel may further include: a third transistor electrically connected between the readout line and the second electrode of the first transistor.

[0025] The display device may further include: a data driver connected to the data line; and a gate driver connected to the first scan line, the second scan line and the third scan line, wherein the frame period includes a first period and a second period, wherein the gate driver is configured to apply a first scan signal having an on-voltage level to the first scan line and a second scan signal having an on-voltage level to the second scan line in the first period, and is configured to apply a third scan signal having an on-voltage level to the third scan line during the second period, and wherein the data driver is configured to apply a first data signal to a pixel through the data line at a time corresponding to the first scan signal, and to apply a second data signal different from the first data signal to the pixel through the data line at a time corresponding to the second scan signal.

[0026] The first data signal can be configured to change according to a grayscale value for a pixel, wherein, when the grayscale value is greater than a reference grayscale value, the second data signal has a gate-off voltage level at which the transistor is disconnected, and wherein, when the grayscale value is less than or equal to the reference grayscale value, the second data signal has a gate-on voltage level. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Embodiments will now be described more fully below with reference to the accompanying drawings. However, the embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the example embodiments to those skilled in the art.

[0028] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Like reference numerals refer to like elements throughout.

[0029] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0030] Figure 2 The diagram is included in Figure 1 A circuit diagram of one or more embodiments of a pixel in a display device shown in FIG.

[0031] Figure 3 is a diagram illustrating one or more embodiments of the present disclosure Figure 2 0 is a waveform diagram of the pixel operation shown in FIG.

[0032] Figure 4 The figure shows the comparative example. Figure 2 The operation of the pixel is shown in the diagram.

[0033] Figure 5 is a diagram illustrating one or more embodiments of the present disclosure Figure 2 0 is a waveform diagram of the pixel operation shown in FIG.

[0034] Figure 6 is a diagram illustrating one or more embodiments of the present disclosure Figure 2 0 is a waveform diagram of the pixel operation shown in FIG.

[0035] Figure 7 is a diagram illustrating one or more embodiments of the present disclosure Figure 2 0 is a waveform diagram of the pixel operation shown in FIG.

[0036] Figure 8 It is a graphic Figure 1 A circuit diagram of one or more embodiments of a pixel included in a display device shown in FIG.

[0037] Fig. 9 is a diagram illustrating one or more embodiments of the present disclosure Figure 8 0 is a waveform diagram of the pixel operation shown in FIG. DETAILED DESCRIPTION

[0038] By referring to the detailed description and the accompanying drawings of the embodiments, it is easier to understand the aspects of some embodiments of the present disclosure and the methods for realizing them. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments or unnecessary processes, elements and techniques for a complete understanding of the aspects of the present disclosure by those of ordinary skill in the art can be omitted. Unless otherwise noted, similar reference numerals, characters or combinations thereof represent similar elements throughout the drawings and written descriptions, and therefore their repeated descriptions can be omitted.

[0039] The described embodiments may have various modifications and may be embodied in different forms, and should not be construed as being limited to the embodiments illustrated herein. The use of "can", "may", or "may not" in describing the embodiments corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents, and alternatives within the scope of the ideas and techniques of the present disclosure. In addition, the multiple features of the various embodiments of the present disclosure may be partially or completely combined with each other, and various interlocks and drives in technology are possible. Each embodiment may be implemented independently of one another or may be implemented together in association.

[0040] For the purposes of this disclosure, expressions such as "at least one of ...," "any of ...," or "one or more of ..." when preceding a list of elements modify the entire list of elements, without modifying individual elements in the list. For example, "at least one of X, Y, and Z," "at least one of X, Y, or Z," "at least one selected from the group consisting of X, Y, and Z," and "at least one selected from the group consisting of X, Y, or Z" may be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ, or any variants thereof. Similarly, the expressions "at least one of A and B" and "at least one of A or B" may include A, B, or A and B. As used herein, "or" generally means "and / or," and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" may include A, B, or A and B. Similarly, expressions such as “at least one of,” “a plurality of,” “one of,” and other prepositional phrases when preceding a list of elements modify the entire list of elements and do not modify the individual elements of the list.

[0041] It will be understood that although the terms "first", "second", "third", etc. can be used to describe various elements, components, areas, layers and / or sections in this article, these elements, components, areas, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or superiority, and are used to distinguish an element, member, component, area, region, layer, section or part from another element, member, component, area, region, layer, section or part. Therefore, the first element, component, area, layer or section discussed below can be referred to as the second element, component, area, layer or section without departing from the spirit and scope of the present disclosure. The description of the element as the "first" element may not require or imply the existence of the second element or other elements. The terms "first", "second", etc. can also be used herein to distinguish elements of different categories or sets. For the sake of simplicity, the terms "first", "second", etc. can represent "first category (or first set)", "second category (or second set)", etc. respectively.

[0042] The terms used herein are only for the purpose of describing the embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to include the plural forms as well, and the plural forms are intended to include the singular forms, unless the context clearly indicates otherwise. It will also be understood that the terms "comprises", "comprising", "have", "having", "includes" and "including" when used in this specification specify the presence of stated features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0043] As used herein, the terms "substantially," "about," "approximately," and similar terms are used as terms of approximation rather than terms of degree, and are intended to take into account the inherent deviations in measured or calculated values ​​that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / - 5% of the corresponding value. Taking into account the errors associated with the measurements and the measurements of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately" as used herein include the value and mean within an acceptable range of deviations for a particular value as determined by those of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the value. In addition, when describing embodiments of the present disclosure, the use of "may" relates to "one or more embodiments of the present disclosure."

[0044] In some embodiments, well-known structures and devices can be described in the accompanying drawings about one or more functional blocks (e.g., block diagrams), units and / or modules to avoid unnecessary blurring of different embodiments. It will be understood by those skilled in the art that such blocks, units and / or modules are physically implemented by logic circuits, separate components, microprocessors, hard-wired circuits, memory elements, line connections and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, and can be driven by firmware and / or software, alternatively. In addition, each block, unit and / or module can be implemented by a combination of dedicated hardware or dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and related circuits) that performs functions different from the functions of the dedicated hardware. In addition, in some embodiments, blocks, units and / or modules can be physically divided into two or more interactive separate blocks, units and / or modules without departing from the scope of this disclosure. Furthermore, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0045] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and / or this specification, and should not be interpreted in an idealized or overly formal sense.

[0046] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0047] Reference Figure 1 The display device 100 (or display panel) is a device for displaying images, and can be used not only as a display screen for portable electronic devices (such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs), but also as a variety of products such as televisions, notebooks, monitors, billboards, and Internet of Things (IOT) devices.

[0048] The display device 100 may include a display 110 (or a display unit or a display panel), a gate driver 120 (or a scan driver), a data driver 130 (or a source driver), and a timing controller 140 (or a controller or a data processor).

[0049] The display 110 may display an image. The display 110 may include a gate line GL, a data line DL, a readout line RL (or a sensing line), and a pixel PXL (or a sub-pixel). The gate line GL may include a scan line SCL (or a first gate line) and a sensing scan line SSL (or a second gate line). Each of the scan line SCL, the sensing scan line SSL, the data line DL, the readout line RL, and the pixel PXL may be provided in plural.

[0050] The pixel PXL may include a light emitting element, and may be located in a region (eg, a pixel region) defined by the scan lines SCL and the data lines DL.

[0051] The pixels PXL may be connected to the scan lines SCL, the sensing scan lines SSL, the data lines DL, and the readout lines RL.

[0052] The pixel PXL may be initialized using an initialization voltage provided through the readout line RL in response to a sensing scan signal provided through the sensing scan line SSL, may store or record a data signal (or data voltage) provided through the data line DL in response to a scan signal provided through the scan line SCL, and may emit light having a brightness corresponding to the stored data signal. Figure 2 and Figure 8 The specific configuration of the pixel PXL is described.

[0053] The gate driver 120 may generate a scan signal based on a scan control signal SCS (or a gate control signal), and may provide the generated scan signal to the scan line SCL. The scan control signal SCS may include a start signal, a clock signal, etc., and may be provided to the gate driver 120 from the timing controller 140. For example, the gate driver 120 may be implemented as a shift register for outputting a scan signal by shifting the start signal in a pulse form using a clock signal. In addition, similar to the method of generating a scan signal, the gate driver 120 may generate a sensing scan signal, and may provide the generated sensing scan signal to the sensing scan line SSL.

[0054] The gate driver 120 may be formed on the display 110 together with the pixel PXL. However, the gate driver 120 is not limited thereto. For example, the gate driver 120 may be implemented as an integrated circuit mounted on a circuit film and may be connected to the timing controller 140 via at least one circuit film and a printed circuit board.

[0055] The data driver 130 may generate a data signal (or a data voltage) based on the image data DATA2 (or the second data) and the data control signal DCS provided from the timing controller 140, and may provide the generated data signal to the display 110 (or the pixel PXL) through the data line DL. The data control signal DCS is a signal for controlling the operation of the data driver 130, and may include a load signal (or a data enable signal) indicating that a valid data signal is output, a horizontal start signal, a data clock signal, etc. In addition, the data driver 130 may provide an initialization voltage to the display 110 (or the pixel PXL) through the readout line RL.

[0056] For example, the data driver 130 may include: a shift register for generating a sampling signal by shifting a horizontal start signal synchronously with a data clock signal; a latch for latching image data DATA2 in response to the sampling signal; a digital-to-analog converter (or decoder) for converting the latched image data DATA2 (e.g., data in digital form) into a data signal in analog form; and a buffer (or amplifier) ​​for outputting the data signal to the data line DL.

[0057] In addition, in a separate sensing mode or sensing cycle (e.g., in a sensing cycle allocated for sensing electrical characteristics of the pixel PXL (such as the threshold voltage and / or mobility of the driving transistor included in the pixel PXL)), the data driver 130 may provide a test signal (or test voltage) to the pixel PXL through the data line DL, and may receive a sensing signal from the pixel PXL through the readout line RL. The sensing signal may be used to compensate for the electrical characteristics (or characteristic deviation) of the pixel PXL in at least one of the data driver 130 and the timing controller 140.

[0058] In one or more embodiments, the image data DATA2 for one frame image may include two data values ​​(or grayscale values) for the pixel PXL. For example, the image data DATA2 may include a first data value V1 and a second data value V2. The data driver 130 may generate a first data signal based on the first data value V1, and may generate a second data signal based on the second data value V2. In one frame period, the data driver 130 may sequentially provide the first data signal and the second data signal to the pixel PXL through the data line DL. This will be referred to later. Figure 3 and Fig. 9 Describe this.

[0059] The timing controller 140 may receive input image data DATA1 (or frame data) and a control signal CS from an external device (e.g., a graphics processor), may generate a scan control signal SCS and a data control signal DCS based on the control signal CS, and may generate image data DATA2 by converting the input image data DATA1. The control signal CS may include a vertical synchronization signal, a horizontal synchronization signal, a reference clock signal, and the like. The vertical synchronization signal indicates the start of frame data (e.g., data corresponding to a frame period in which one frame image is displayed), and the horizontal synchronization signal may indicate the start of a data row (e.g., one data row among a plurality of data rows included in the frame data). For example, the timing controller 140 may convert the input image data DATA1 into image data DATA2 having a format corresponding to the pixel arrangement in the display 110.

[0060] In an embodiment, the timing controller 140 may generate the first data value V1 and the second data value V2 based on the gray value GRAY (or grayscale) of the pixel PXL. The gray value GRAY may be included in the input image data DATA1 (or frame data), and the first data value V1 and the second data value V2 may be included in the image data DATA2.

[0061] In one or more embodiments, the timing controller 140 may determine whether the gray value GRAY is less than or equal to the reference gray value, and may generate a first data value V1 and a second data value V2 based on the determination result. The gray value GRAY may be included in the input image data DATA1 (or frame data), and the first data value V1 and the second data value V2 may be included in the image data DATA2.

[0062] When the gray value GRAY is within the range of the minimum gray value to the maximum gray value, the reference gray value may be greater than about 1 / 10 of the maximum gray value, and may be less than or equal to about 1 / 2 of the maximum gray value. For example, when the minimum gray value is 0 and the maximum gray value is 255, the reference gray value may be greater than a gray value of about 25 and may be less than or equal to a gray value of about 128. For example, the reference gray value may be a gray value of 128, a gray value of 80, a gray value of 32, etc. among the gray values ​​of 0 to 255. When the gray value GRAY is greater than the reference gray value, this may mean that the gray value GRAY is a high gray value (or an intermediate gray value). When the gray value GRAY is less than or equal to the reference gray value, this may mean that the gray value GRAY is a low gray value. In other words, the reference gray value may be a reference value for determining whether the gray value GRAY is a low gray value (e.g., a low gray value that is difficult to express by current control).

[0063] For example, the first data value V1 and the second data value V2 may correspond to the grayscale value GRAY in the first period within the frame period and the grayscale value GRAY in the second period within the frame period. When the grayscale value GRAY is greater than the reference grayscale value, the timing controller 140 may generate the first data value V1 and the second data value V2, each of which is equal to the grayscale value GRAY. The pixel PXL may emit light equally in the first period and the second period.

[0064] When the gray value GRAY is less than or equal to the reference gray value, the timing controller 140 may generate a first data value V1 greater than the gray value GRAY (e.g., a first data value V1 that is twice the gray value GRAY), and may generate a second data value V2 less than the gray value GRAY (e.g., a gray value of 0). The pixel PXL may emit light differently in the first period and the second period, or may emit light in the first period and not emit light in the second period. For example, the pixel PXL may emit light having a brightness higher than the target brightness (e.g., the brightness corresponding to the gray value GRAY) in the first period (e.g., a brightness corresponding to a gray value greater than the gray value GRAY or the reference gray value), but may not emit light in the second period. The average brightness in both the first period and the second period may be equal to the target brightness. That is, the low grayscale is expressed using an intermediate grayscale value (or a high grayscale value) instead of a low grayscale value, so that the display device 100 can accurately express the low grayscale.

[0065] In another example, the first data value V1 may correspond to the grayscale value GRAY in the frame period, and the second data value V2 may indicate whether the pixel PXL does not emit light in the second period within the frame period. When the grayscale value GRA is greater than the reference grayscale value, the timing controller 140 may generate a first data value V1 equal to the grayscale value GRAY and a second data value V2 indicating light emission. When the grayscale value GRAY is less than or equal to the reference grayscale value, the timing controller 140 may generate a first data value V1 greater than the grayscale value GRAY (e.g., a first data value V1 that is twice the grayscale value GRAY) and a second data value V2 indicating non-light emission. This will be referred to later. Fig. 9 Describe this.

[0066] In one or more embodiments, the timing controller 140 may include a first data processor and a second data processor. For example, the first data processor may be implemented as a general timing controller for generating image data DATA2 having a format corresponding to the pixel arrangement in the display 110 based on a vertical synchronization signal, a horizontal synchronization signal, and input image data DATA1. For example, the second data processor may include a calculation circuit for comparing a gray value GRAY of the image data DATA2 with a reference gray value and for calculating a first data value V1 and a second data value V2.

[0067] In an embodiment, the display device 100 may further include a power supply. The power supply may supply a first power supply voltage and a second power supply voltage. The first power supply voltage and the second power supply voltage may be a power supply voltage suitable for the operation of the pixel PXL or a voltage of a driving power supply. In addition, the power supply may provide an initialization voltage to the data driver 130. In addition, the power supply may provide a driving voltage (e.g., a turn-on voltage and a turn-off voltage) to at least one of the gate driver 120, the data driver 130, and the timing controller 140. The power supply may be implemented as a power management IC (PMIC).

[0068] Meanwhile, each of the data driver 130 and the timing controller 140 may be implemented as a separate integrated circuit, but the present disclosure is not limited thereto. For example, the data driver 130 and the timing controller 140 may be implemented as one integrated circuit. In some embodiments, at least two of the gate driver 120, the data driver 130, and the timing controller 140 may be implemented as one integrated circuit.

[0069] Figure 2 The diagram is included in Figure 1 A circuit diagram of one or more embodiments of a pixel in a display device shown in FIG.

[0070] refer to Figure 1 and Figure 2 , the pixel PXL may be electrically connected to the data line DL, the readout line RL, the scan line SCL, and the sensing scan line SSL.

[0071] The pixel PXL may include a light emitting element LD, a first transistor T1 (driving transistor), a second transistor T2, a third transistor T3, and a first capacitor C1. Each of the first transistor T1, the second transistor T2, and the third transistor T3 may include an oxide transistor and may be an n-type transistor. However, the present disclosure is not limited thereto. For example, each of the first transistor T1, the second transistor T2, and the third transistor T3 may include a silicon semiconductor, or may be implemented as a p-type transistor.

[0072] The anode electrode of the light emitting element LD may be connected to the second node N2 (or the second electrode of the first transistor T1), and the cathode electrode of the light emitting element LD may be connected to the second power line PL2 to which the second power supply voltage VSS is applied. In the circuit diagram, "connection" may mean electrical connection. The light emitting element LD may emit light corresponding to the driving current Id (or current amount) supplied from the first transistor T1. The light emitting element LD may be an organic light emitting diode. However, the present disclosure is not limited thereto, and the light emitting element LD may include an inorganic light emitting diode.

[0073] The first electrode of the first transistor T1 may be connected to the first power line PL1 to which the first power voltage VDD is applied, and the second electrode of the first transistor T1 may be connected to the second node N2 (or the anode electrode of the light emitting element LD). The gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 may control a driving current Id flowing through the light emitting element LD corresponding to the voltage of the first node N1.

[0074] The first electrode of the second transistor T2 may be connected to the data line DL, and the second electrode of the second transistor T2 may be connected to the first node N1. The gate electrode of the second transistor T2 may be connected to the scan line SCL (or the first scan line). When the scan signal SC having the on voltage level is supplied to the scan line SCL, the second transistor T2 may be turned on. The second transistor T2 may transmit the data signal VDATA (or data voltage) from the data line DL to the first node N1. The on voltage level (or gate on voltage level) may mean the voltage level when the transistor is turned on. For example, the on voltage level of the n-type transistor may be a high level. Meanwhile, the off voltage level (or gate off voltage level) may mean the voltage level when the transistor is turned off. For example, the off voltage level of the n-type transistor may be a low level.

[0075] The first capacitor C1 may be connected or formed between the first node N1 and the second node N2 (or the anode electrode of the light emitting element LD). The first capacitor C1 may store a voltage corresponding to the voltage of the first node N1.

[0076] The third transistor T3 may be connected between the readout line RL and the second node N2 (or the second electrode of the first transistor T1). The gate electrode of the third transistor T3 may be connected to the sensing scan line SSL. When the sensing scan signal SS having a turn-on voltage level is supplied to the sensing scan line SSL, the third transistor T3 may be turned on. The third transistor T3 may connect the second node N2 and the readout line RL to each other. The initialization voltage applied to the readout line RL may be provided to the second node N2, and the pixel PXL (or the light emitting element LD) may be initialized or reset. Alternatively, a sensing signal (e.g., a sensing voltage or a sensing current) may be provided to the readout line RL from the second node N2.

[0077] At the same time, the pixel PXL is not limited to Figure 2 In the example, the pixel PXL may omit the third transistor T3. In addition, the pixel PXL may further include other circuit elements, such as a compensation transistor for compensating for the threshold voltage of the first transistor T1, an initialization transistor for initializing the voltage of the first node N1, an emission control transistor for controlling a period in which the driving current Id is supplied, and / or a boost capacitor for increasing the voltage of the first node N1.

[0078] Figure 3 is a diagram illustrating one or more embodiments of the present disclosure Figure 2 The waveform diagram of the pixel operation is shown in FIG. Figure 3 , signals for describing the operation of the pixel PXL in a frame period Frame (or display period) are illustrated. Figure 4 The figure is based on the comparative example Figure 2 The operation of the pixel is shown in the diagram.

[0079] refer to Figures 1 to 3 , the scan signal SC may be provided to the scan line SCL, and the data signal VDATA may be provided to the data line DL. The third transistor T3 may be omitted, and therefore, the sensing scan signal SS applied to the sensing scan line SSL is not particularly limited. For example, the sensing scan signal SS may be the same as the scan signal SC.

[0080] The frame period Frame may include a first period P1 and a second period P2. The first period P1 and the second period P2 do not overlap each other. The width of the first period P1 and the width of the second period P2 may be equal to each other, or may be different from each other.

[0081] The scan signal SC may have a turn-on voltage level in each of the first period P1 and the second period P2. For example, the gate driver 120 may sequentially provide the scan signal SC having the turn-on voltage level to the display 110 in the first period P1, and may sequentially provide the scan signal SC having the turn-on voltage level to the display 110 again in the second period P2.

[0082] like Figure 4 As shown in FIG. 1 , during one frame period Frame, the scan signal SC_C according to the comparative example may be applied to the pixel PXL once, and during one frame period Frame corresponding to the scan signal SC_C, the data signal VDATA_C according to the comparative example may also be applied to the pixel PXL once. Alternatively, during one frame period Frame, the scan signal SC according to an embodiment of the present disclosure may be applied to the pixel PXL twice.

[0083] When the scan signal SC having the on voltage level is applied, the data signal VDATA for the pixel PXL may be provided to the data line DL. For example, the data driver 130 may provide the first data signal VDATA1 to the pixel PXL through the data line DL at the start time of the first period P1, and may provide the second data signal VDATA2 to the pixel PXL through the data line DL at the start time of the second period P2. Figure 1 As described above, the first data signal VDATA1 may be generated based on the first data value V1, and the second data signal VDATA2 may be generated based on the second data value V2.

[0084] In one or more embodiments, when the gray value GRAY for the pixel PXL is greater than the reference gray value GRAY_REF, each of the first data signal VDATA1 and the second data signal VDATA2 may have a voltage level at which the pixel PXL emits light. On the contrary, when the gray value GRAY for the pixel PXL is less than or equal to the reference gray value GRAY_REF, the first data signal VDATA1 may have a voltage level at which the pixel PXL emits light, and the second data signal VDATA2 may have a voltage level at which the pixel PXL does not emit light. As described above, the reference gray value GRAY_REF may be a reference value for determining whether the gray value GRAY is a low gray value (e.g., a low gray value that is difficult to express by current control). For example, the reference gray value GRAY_REF may be a gray value of 128, a gray value of 80, a gray value of 32, etc. among the gray values ​​of 0 to 255.

[0085] For example, Figure 3As shown in , with respect to a first gray value GRAY1 (e.g., a high gray value or an intermediate gray value) greater than a reference gray value GRAY_REF, each of the first data signal VDATA1 and the second data signal VDATA2 may have a voltage level at which the first transistor T1 is turned on. For example, each of the first data value V1 and the second data value V2 generated in the timing controller 140 may be equal to the first gray value GRAY1, and the first data signal VDATA1 according to the first data value V1 and the second data signal VDATA2 according to the second data value V2 may have the same voltage level. Therefore, in the first period P1 and the second period P2 except for the period in which the scan signal SC is applied, the driving current Id may flow through the pixel PXL, and the pixel PXL may emit light.

[0086] Alternatively, with respect to a second gray value GRAY2 (e.g., a low gray value) less than or equal to the reference gray value GRAY_REF, the first data signal VDATA1 may have a voltage level at which the first transistor T1 is turned on, and the second data signal VDATA2 may have a voltage level at which the first transistor T1 is turned off. For example, the first data value V1 generated in the timing controller 140 may be greater than the first gray value GRAY1, and the second data value V2 generated in the timing controller 140 may be equal to the minimum gray value (e.g., a gray value of 0). Therefore, in the first period P1, the drive current Id may flow through the pixel PXL, and the pixel PXL may emit light. In the second period P2, the drive current Id may not flow through the pixel PXL, and the pixel PXL may not emit light.

[0087] At the same time, with respect to the entire frame period Frame, the pixel PXL will emit light with a target brightness corresponding to the second gray value GRAY2 on average. In addition, the pixel PXL does not emit light in the second period. Therefore, the pixel PXL can emit light with a brightness higher than the target brightness in the first period P1. For example, when the width of the first period P1 and the width of the second period P2 are the same, the pixel PXL can emit light with a brightness twice the target brightness in the first period P1. To this end, the voltage level of the first data signal VDATA1 can be higher than the reference voltage level VREF (for example, the voltage level of the data signal for emitting light with the target brightness). The range of the driving current Id for the second gray value GRAY2 (for example, low gray) can be substantially equal to the range of the driving current Id for the first gray value GRAY1 (for example, high gray or middle gray), or can overlap with the range of the driving current Id for the first gray value GRAY1 (for example, high gray or middle gray). That is, the driving current Id for the second gray value GRAY2 (for example, low gray) can be a high current.

[0088] Due to the dispersion of the driving current Id, the leakage current, etc., it may be difficult to accurately express the grayscale corresponding to the driving current Id with low intensity. Therefore, in the present disclosure, the intensity of the driving current Id for a low grayscale value (e.g., the second grayscale value GRAY2) less than or equal to the reference grayscale value GRAY_REF is increased, and the emission duty cycle (or emission time) of the pixel PXL is reduced, thereby accurately expressing the low grayscale. In addition, because the range of the driving current ID is reduced as the low current is excluded, the color shift according to the change of the driving current Id can also be reduced or minimized.

[0089] As the second gray value GRAY2 changes (e.g., increases or decreases), the voltage level of the first data signal VDATA1 may also change. For example, the voltage level of the first data signal VDATA1 for the second gray value GRAY2 of 64 may be different from the voltage level of the first data signal VDATA1 for the second gray value GRAY2 of 10. For example, the voltage level of the first data signal VDATA1 for the second gray value GRAY2 of 64 may be higher than the voltage level of the first data signal VDATA1 for the second gray value GRAY2 of 10.

[0090] At the same time, regardless of whether the second gray value GRAY2 changes (e.g., increases or decreases), the width of each of the first period P1 and the second period P2 or the emission duty cycle of the pixel PXL may be constant or fixed. For example, the emission duty cycle of 64 for the second gray value GRAY2 and the emission duty cycle of 10 for the second gray value GRAY2 may be the same.

[0091] As described above, the display device 100 may divide one frame period Frame into two periods (e.g., a first period P1 and a second period P2), and may provide a data signal (e.g., a first data signal VDATA1 and a second data signal VDATA2) twice to the pixel PXL. With respect to a second gray value GRAY2 (or low gray) less than or equal to a reference gray value GRAY_REF, the display device 100 may sequentially provide the pixel PXL with a first data signal VDATA1 having a voltage level higher than a reference voltage level VREF corresponding to the first gray value GRAY1 and a second data signal VDATA2 having a voltage level lower than the reference voltage level VREF, so that the pixel PXL emits light in the first period P1 and does not emit light in the second period P2. The driving current Id flowing through the pixel PXL in the first period P1 may have a higher intensity corresponding to the first data signal VDATA1 (e.g., a first data signal VDATA1 having a voltage level higher than the reference voltage level VREF corresponding to the first gray value GRAY1). Therefore, the pixel PXL and the display device 100 including the same can express the low gray more accurately.

[0092] Figure 5 is a diagram illustrating one or more embodiments of the present disclosure Figure 2 The waveform diagram of the pixel operation is shown in FIG. Figure 5 , signals for describing the operation of the pixel PXL in the sensing period Sensing Period are illustrated.

[0093] refer to Figure 2 and Figure 5 , the scan signal SC may be provided to the scan line SCL, the sensing scan signal SS may be provided to the sensing scan line SSL, and the data signal VDATA may be provided to the data line DL. The second node voltage V_N2 may be a voltage in the second node N2, and the readout voltage V_RL may be a voltage in the readout line RL.

[0094] The sensing period is a period in which the characteristics of the pixel PXL (eg, the first transistor T1 or the light emitting element LD) are sensed, and may be related to the Figure 3 For example, the sensing period Sensing Period may be allocated separately from the frame period Frame (or display period). The pixel PXL may not emit light during the sensing period Sensing Period.

[0095] The sensing period Sensing Period may include a third period P3, a fourth period P4, a fifth period P5, and a sixth period P6.

[0096] In the third period P3 , the scan signal SC may have an on voltage level, and the sensing scan signal SS may have an on voltage level.

[0097] The second transistor T2 may be turned on in response to a scan signal SC having a turn-on voltage level, and a data signal VDATA (or a test signal, for example, about 10V) may be applied to the first node N1 through the data line DL. In addition, the third transistor T3 may be turned on in response to a sensing scan signal SS having a turn-on voltage level, and an initialization voltage (for example, about 2V) may be applied to the second node N2 through the readout line RL. The second node voltage V_N2 may be equal to the readout voltage V_RL. The initialization voltage has a voltage level lower than the operating point (or threshold voltage) of the light emitting element LD, and therefore, the light emitting element LD may not emit light.

[0098] Thereafter, in the fourth period P4, the sensing scan signal SS may have an off voltage level. The third transistor T3 may be turned off in response to the sensing scan signal SS having the off voltage level, and the second node N2 of the pixel PXL may be in a floating state.

[0099] During the fourth period P4, the first transistor T1 supplies current to the second node N2 in response to the data signal VDATA, and thus, the second node voltage V_N2 may be changed. For example, when the parasitic capacitance of the light emitting element LD is charged, the second node voltage V_N2 may be increased to the operating point of the light emitting element LD, and a voltage corresponding to the operating point of the light emitting element LD may be stored in the first capacitor C1.

[0100] Thereafter, in the fifth period P5, the scan signal SC may have a turn-off voltage level. The second transistor T2 may be turned off, and the first node N1 may be in a floating state. The node voltage of the first node N1 may be changed by the first capacitor C1 to correspond to the second node voltage V_N2.

[0101] In the fifth period P5, the sensing scan signal SS may have a turn-on voltage level. The third transistor T3 may be turned on, and the second node N2 may be connected to the readout line RL. The readout voltage V_RL is in a state where the readout voltage V_RL is maintained as an initialization voltage, and the second node voltage V_N2 may be changed to be equal to the readout voltage V_RL.

[0102] Thereafter, in the sixth period P6, the initialization voltage may not be supplied to the readout line RL.

[0103] The first transistor T1 can supply a current corresponding to the gate-source voltage (or the voltage stored in the first capacitor C1, such as a voltage corresponding to the operating point of the light emitting element LD) to the second node N2, and therefore, the second node voltage V_N2 and the read voltage V_RL can increase linearly. Therefore, it is possible to obtain information about the characteristics of the light emitting element LD based on the read voltage V_RL.

[0104] Figure 6 is a diagram illustrating one or more embodiments of the present disclosure Figure 2 The waveform diagram of the pixel operation is shown in FIG. Figure 6 In FIG. 1 , the driving current Id flowing through the pixel PXL for each grayscale is shown. Figure 6 The left side of FIG. 1 illustrates a case where the width of the first period P1 and the width of the second period P2 are substantially the same, and Figure 6 The right side of shows a case where the width of the second period P2 is greater than the width of the first period P1.

[0105] refer to Figure 2 , Figure 3 and Figure 6 , the period during which the scan signal having the on voltage level is applied to the pixel PXL in one frame period Frame is very small, and therefore, for ease of description, Figure 6 The period in which the scan signal SC is applied is omitted.

[0106] Each of the third grayscale value GRAY3 and the fourth grayscale value GRAY4 may be greater than the reference grayscale value GRAY_REF, and each of the fifth grayscale value GRAY5, the sixth grayscale value GRAY6, and the seventh grayscale value GRAY7 may be less than or equal to the reference grayscale value GRAY_REF. For example, in a grayscale range of 0 to 255, the reference grayscale value GRAY_REF may be 128, the third grayscale value GRAY3 may be 256, the fourth grayscale value GRAY4 may be 200, the fifth grayscale value GRAY5 may be 128, the sixth grayscale value GRAY6 may be 64, and the seventh grayscale value GRAY7 may be 10.

[0107] Regardless of the width of the first period P1 and / or the width of the second period P2, the driving current Id or Id_1 for the third grayscale value GRAY3 or the fourth grayscale value GRAY4 greater than the reference grayscale value GRAY_REF can be constant. This is because the driving current Id or Id_1 flows through the pixel PXL throughout one frame period Frame with respect to the third grayscale value GRAY3 or the fourth grayscale value GRAY4 greater than the reference grayscale value GRAY_REF.

[0108] As the width (or emission duty cycle) of the first period P1 becomes smaller, the driving current Id or Id_1 for the fifth gray value GRAY5, the sixth gray value GRAY6, or the seventh gray value GRAY7 that is less than or equal to the reference gray value GRAY_REF may increase. Figure 6 As shown in , the driving current Id_1 for the fifth gray value GRAY5 in the case where the width of the first period P1 is relatively small may be greater than the driving current Id_1 for the fifth gray value GRAY5 in the case where the width of the first period P1 and the width of the second period P2 are the same.

[0109] At the same time, if Figure 6 As shown in , as the gray value changes (e.g., increases or decreases), the intensity of the driving current Id or Id_1 may also change. For example, the driving current Id or Id_1 for the seventh gray value GRAY7 may be less than the driving current Id or Id_1 for the sixth gray value GRAY6. In addition, regardless of how the gray value changes (e.g., increases or decreases), the width of each of the first period P1 and the second period P2 or the emission duty cycle of the pixel PXL may be constant or fixed. For example, the emission duty cycle for the sixth gray value GRAY6 and the emission duty cycle for the seventh gray value GRAY7 may be the same.

[0110] As described above, as the width (or emission duty cycle) of the first period P1 becomes smaller, the driving current Id or Id_1 for the fifth gray value GRAY5, the sixth gray value GRAY6, or the seventh gray value GRAY7 that is less than or equal to the reference gray value GRAY_REF may increase. By taking this into consideration, the range of the driving current Id or Id_1 and the emission duty cycle (the width of the first period P1 and / or the width of the second period P2 corresponding thereto) may be appropriately set.

[0111] Figure 7 is a diagram illustrating one or more embodiments of the present disclosure Figure 2 0 is a waveform diagram of the pixel operation shown in FIG.

[0112] refer to Figures 1 to 3 and Figure 7 In addition to the second data signal VDATA2 for the second gray value GRAY2 (eg, the data signal VDATA in the second period P2) and the driving current Id corresponding thereto (eg, the driving current Id in the second period P2), Figure 7 The waveforms shown in Figure 3 The waveform diagrams shown in FIG. 1 are substantially the same or similar. Therefore, the overlapping descriptions will not be repeated.

[0113] In one or more embodiments, with respect to a second gray value GRAY2 less than or equal to a reference gray value GRAY_REF, the first data signal VDATA1 may have a voltage level higher than a reference voltage level VREF, and the second data signal VDATA2 may have a voltage level lower than the reference voltage level VREF. Figure 3 Corresponding to one or more embodiments, the second data signal VDATA2 may have a voltage level at which the pixel PXL emits light. Therefore, with respect to the second gray value GRAY2, the pixel PXL may emit light having a brightness in the second period P2 lower than that in the first period P1.

[0114] Regardless of the gray value (or the second gray value GRAY2), the second data signal VDATA2 may be fixed or may be changed according to the gray value (or the second gray value GRAY2). For example, the second data signal VDATA2 may be set to have a voltage level corresponding to the minimum current in the range of the driving current Id other than the low current, but the present disclosure is not limited thereto. In another example, similar to the first data signal VDATA1, the second data signal VDATA2 may be set to correspond to the second gray value GRAY2 or may be proportional to the second gray value GRAY2.

[0115] As described above, the pixel PXL may emit light with low brightness in the second period P2 relative to the second gray value GRAY2 (or low gray) less than or equal to the reference gray value GRAY_REF. Therefore, in the first period P1, the low gray can be relatively accurately expressed using a high current.

[0116] Figure 8 It is a graphic Figure 1 A circuit diagram of one or more embodiments of a pixel included in a display device shown in FIG.

[0117] refer to Figure 1 , Figure 2 and Figure 8 , the pixel PXL_1 may be electrically connected to the data line DL, the readout line RL, the scan line SCL, and the sensing scan line SSL. The scan line SCL may include a first scan line SCL1, a second scan line SCL2, and a third scan line SCL3 that are different from each other. The gate electrode of the second transistor T2 may be connected to the first scan line SCL1. The gate driver 120 may apply a first scan signal SC1, a second scan signal SC2, and a third scan signal SC3 to the first scan line SCL1, the second scan line SCL2, and the third scan line SCL3, respectively.

[0118] and Figure 2 The pixel PXL shown in Figure 2 is compared to Figure 8The pixel PXL_1 shown in FIG. 1 may further include a fourth transistor T4, a second capacitor C2, a fifth transistor T5, and a sixth transistor T6. The pixel PXL_1 may adjust the emission duty ratio using the fourth transistor T4, the second capacitor C2, the fifth transistor T5, and the sixth transistor T6.

[0119] A first electrode of the fourth transistor T4 may be connected to the data line DL, and a second electrode of the fourth transistor T4 may be connected to the third node N3. A gate electrode of the fourth transistor T4 may be connected to the second scan line SCL2. When a second scan signal SC2 having a turn-on voltage level is supplied to the second scan line SCL2, the fourth transistor T4 may be turned on. The fourth transistor T4 may transmit a data signal VDATA (or data voltage) from the data line DL to the third node N3.

[0120] The second capacitor C2 may be connected or formed between the third node N3 and the second power line PL2. The second capacitor C2 may store a voltage corresponding to the voltage of the third node N3. Although a case where one electrode of the second capacitor C2 is connected to the second power line PL2 is described, the present disclosure is not limited thereto. One electrode of the second capacitor C2 may be connected to another constant voltage line (e.g., the first power line PL1).

[0121] A first electrode of the fifth transistor T5 may be connected to the third node N3, and a second electrode of the fifth transistor T5 may be connected to a gate electrode of the sixth transistor T6. The gate electrode of the fifth transistor T5 may be connected to the third scan line SCL3. When a third scan signal SC3 having a turn-on voltage level is supplied to the third scan line SCL3, the fifth transistor T5 may be turned on. The fifth transistor T5 may electrically connect the third node N3 and the gate electrode of the sixth transistor T6 to each other.

[0122] A first electrode of the sixth transistor T6 may be connected to the first node N1, and a second electrode of the sixth transistor T6 may be connected to the second power line PL2. A gate electrode of the sixth transistor T6 may be connected to the second electrode of the fifth transistor T5. The sixth transistor T6 may electrically connect the first node N1 to the second power line PL2 or separate the first node N1 from the second power line PL2 corresponding to a voltage of the third node N3.

[0123] Fig. 9 is a diagram illustrating one or more embodiments of the present disclosure Figure 8 The waveform diagram of the pixel operation is shown in FIG. Fig. 9 , signals for describing the operation of the pixel PXL_1 in a frame period Frame (or display period) are illustrated.

[0124] The frame period Frame may include a first period P1 and a second period P2. The first period P1 and the second period P2 may not overlap with each other. The width of the first period P1 and the width of the second period P2 may be the same as or different from each other (see Figure 6 ).

[0125] In the first period P1, the first scan signal SC1 may have an on voltage level. When the first scan signal SC1 having the on voltage level is applied, the first data signal VDATA1 for the pixel PXL_1 may be provided to the data line DL. The first data signal VDATA1 may be applied to the first node N1 through the second transistor T2 turned on in response to the first scan signal SC1 having the on voltage level, a driving current Id corresponding to the first data signal VDATA1 may flow through the pixel PXL_1 during the first period P1, and the pixel PXL_1 may emit light having a brightness corresponding to the driving current Id.

[0126] In the first period P1, after the first scan signal SC1 changes to the off voltage level, the second scan signal SC2 may have the on voltage level. When the second scan signal SC2 having the on voltage level is applied, the second data signal VDATA2 for the pixel PXL_1 may be provided to the data line DL. The second data signal VDATA2 may be applied to the third node N3 through the fourth transistor T4 turned on in response to the second scan signal SC2 having the on voltage level, and a voltage corresponding to the second data signal VDATA2 may be stored in the second capacitor C2.

[0127] Afterwards, in the second period P2, the third scan signal SC3 may have a turn-on voltage level. The width of the second period P2 may be equal to the width of the third scan signal SC3 having the turn-on voltage level. That is, the second period P2 may be defined as a period in which the third scan signal SC3 having the turn-on voltage level is applied.

[0128] The voltage of the third node N3 (or the voltage stored in the second capacitor C2) can be provided to the gate electrode of the sixth transistor T6 through the fifth transistor T5 turned on in response to the third scan signal SC3 having the on voltage level, and the sixth transistor T6 can be turned on or off in response to the voltage. When the sixth transistor T6 is turned off, the voltage of the first node N1 does not change, and the pixel PXL_1 can emit light in the second period P2 that is the same as the first period P1. Alternatively, when the sixth transistor T6 is turned on, the first node N1 can be connected to the second power line PL2, the first transistor T1 can be disconnected by the second power supply voltage VSS of the second power line PL2, and the pixel PXL_1 can not emit light in the second period P2. That is, the voltage corresponding to the second data signal VDATA2 stored in the second capacitor C2 indicates whether the pixel PXL_1 does not emit light in the second period P2. When the second data signal VDATA2 has a disconnection voltage level, the pixel PXL_1 can emit light. When the second data signal VDATA2 has a turn-on voltage level, the pixel PXL_1 can not emit light. The turn-on voltage level may be higher than the voltage level of the first data signal VDATA1 .

[0129] In one or more embodiments, when the gray value GRAY for the pixel PXL_1 is greater than the reference gray value GRAY_REF, the second data signal VDATA2 may have a disconnect voltage level. For example, with respect to the first gray value GRAY1 greater than the reference gray value GRAY_REF, the second data signal VDATA2 may have a disconnect voltage level. The pixel PXL_1 may emit light equally in the first period P1 and the second period P2. To this end, the first data value V1 (see Figure 1 ) may be equal to the first gray value GRAY1. The first data signal VDATA1 may be set to change according to the first gray value GRAY1 (or gray value GRAY).

[0130] In one or more embodiments, when the gray value GRAY for the pixel PXL_1 is less than or equal to the reference gray value GRAY_REF, the second data signal VDATA2 may have a turn-on voltage level. For example, with respect to the second gray value GRAY2 that is less than or equal to the reference gray value GRAY_REF, the second data signal VDATA2 may have a turn-on voltage level. The pixel PXL_1 may not emit light in the second period P2. Because the pixel PXL_1 emits light in the first period P1, the drive current Id in the first period P1 may be set to a relatively high current, and the first data value V1 (see FIG. 1 ) as a basis for generating the first data signal VDATA1 may be set to a relatively high current. Figure 1 ) can be greater than the second grayscale value GRAY2.

[0131] The intensity of the driving current ID for the second gray value GRAY2 less than or equal to the low gray value (eg, reference gray value GRAY_REF) increases, and the emission duty (or emission time) of the pixel PXL_1 decreases, so that the low gray can be accurately expressed.

[0132] At the same time, the operation of the pixel PXL_1 in the sensing period can be compared with the reference Figure 5 In other words, Figure 5 One or more corresponding embodiments may be applied to Figure 8 The pixel PXL_1 is shown in FIG.

[0133] In the display device according to the present disclosure, one frame period may be divided into two periods (e.g., a first period P1 and a second period P2), and a data signal may be provided to a pixel twice (e.g., a first data signal and a second data signal may be provided to a pixel). Relative to a grayscale value less than a reference grayscale value (e.g., relative to a low grayscale), the pixel may emit light based on a high current corresponding to the first data signal in the first period, and may not emit light corresponding to the second data signal in the second period. Therefore, it is possible to accurately express a low grayscale using a high current instead of a low current.

[0134] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art at the time of filing this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically indicated. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims, including functional equivalents thereof.

Claims

1. A display device, comprising: A pixel, wherein the pixel includes a light-emitting element; as well as a data driver configured to sequentially provide a first data signal and a second data signal to the pixel in a frame period including a first period and a second period, wherein the pixel is configured to emit light during the first period based on the first data signal, and to emit light during the second period based on the second data signal, wherein when the grayscale value for the pixel is greater than the reference grayscale value, the pixel is configured to emit light equally in the first period and the second period, and Wherein, when the grayscale value is less than or equal to the reference grayscale value, the pixel is configured to emit light differently in the first period than in the second period, or to emit light in the first period but not in the second period.

2. The display device according to claim 1, further comprising: a controller configured to generate a first data value and a second data value based on the grayscale value of the frame data, The data driver is configured to generate the first data signal based on the first data value, and to generate the second data signal based on the second data value.

3. The display device according to claim 2, wherein: When the grayscale value is greater than the reference grayscale value, each of the first data value and the second data value is equal to the grayscale value, and When the grayscale value is less than or equal to the reference grayscale value, the first data value is greater than the grayscale value, and the second data value is less than the grayscale value.

4. The display device according to claim 1, wherein: When the grayscale value is less than or equal to the reference grayscale value, the pixel is configured to emit light having a brightness higher than a target brightness corresponding to the grayscale value in the first period and not to emit light in the second period.

5. The display device according to claim 1, wherein: When the grayscale value is less than or equal to the reference grayscale value, the pixel is configured to emit light having a brightness lower than that in the first period in the second period.

6. The display device according to claim 1, wherein: The width of the first period is equal to the width of the second period.

7. The display device according to claim 1, wherein: The width of the second period is greater than the width of the first period.

8. The display device according to claim 1, wherein: The data driver is configured to provide the first data signal to the pixel at a start time of the first cycle, and to provide the second data signal to the pixel at a start time of the second cycle.

9. The display device according to claim 1, wherein: The pixel also includes: a first transistor including a first electrode electrically connected to a first power line and a second electrode electrically connected to the light emitting element; a second transistor electrically connected between the data line and the gate electrode of the first transistor and including a gate electrode connected to the first scan line; and a first capacitor electrically connected between the gate electrode of the first transistor and the second electrode of the first transistor, and The first data signal and the second data signal are applied to the data line.

10. The display device according to claim 9, wherein: The pixel also includes: A third transistor is electrically connected between a readout line and the second electrode of the first transistor.

11. The display device according to claim 9, wherein: The light emitting element is electrically connected between the first transistor and the second power line. Wherein, the pixel further includes: a sixth transistor electrically connected between the gate electrode of the first transistor and the second power line; a fourth transistor electrically connected between the data line and the intermediate node and including a gate electrode electrically connected to the second scan line; a fifth transistor electrically connected between the intermediate node and the gate electrode of the sixth transistor and including a gate electrode electrically connected to a third scan line; and a second capacitor electrically connected between the intermediate node and the second power line, and The first scan line, the second scan line and the third scan line are different from each other.

12. The display device according to claim 11, further comprising: a gate driver connected to the first scan line, the second scan line, and the third scan line, configured to apply a first scan signal having a turn-on voltage level to the first scan line and a second scan signal having the turn-on voltage level to the second scan line in the first period, and configured to apply a third scan signal having the turn-on voltage level to the third scan line in the second period, and The data driver is configured to provide the first data signal to the pixel at a time corresponding to the first scan signal, and to provide the second data signal to the pixel at a time corresponding to the second scan signal.

13. The display device according to claim 12, wherein: The third scan signal having the turn-on voltage level is applied during the entire second period.

14. The display device according to claim 12, wherein: When the grayscale value is greater than the reference grayscale value, the second data signal has a gate-off voltage level, and When the grayscale value is less than or equal to the reference grayscale value, the second data signal has the turn-on voltage level.

15. The display device according to claim 14, wherein: When the grayscale value is less than or equal to the reference grayscale value, the pixel is configured not to emit light in the second period.

16. The display device according to claim 1, wherein: The grayscale value is within the range of a minimum grayscale value to a maximum grayscale value, and The reference grayscale value is greater than 1 / 10 of the maximum grayscale value and less than or equal to 1 / 2 of the maximum grayscale value.

17. A display device, comprising a pixel, wherein the pixel comprises: a light emitting element, the light emitting element being electrically connected between the first power line and the second power line; a first transistor including a first electrode electrically connected to the first power line and a second electrode electrically connected to the light emitting element; a second transistor electrically connected between the data line and the gate electrode of the first transistor and including a gate electrode electrically connected to the first scan line; a first capacitor electrically connected between the gate electrode of the first transistor and the second electrode of the first transistor; a sixth transistor electrically connected between the gate electrode of the first transistor and the second power line; a fourth transistor electrically connected between the data line and the intermediate node and including a gate electrode electrically connected to the second scan line; a fifth transistor electrically connected between the intermediate node and the gate electrode of the sixth transistor and including a gate electrode electrically connected to a third scan line; as well as A second capacitor is electrically connected between the intermediate node and the second power line.

18. The display device according to claim 17, wherein: The pixel also includes: A third transistor is electrically connected between a readout line and the second electrode of the first transistor.

19. The display device according to claim 17, further comprising: a data driver connected to the data line; as well as a gate driver connected to the first scan line, the second scan line and the third scan line, The frame period includes a first period and a second period. wherein the gate driver is configured to apply a first scan signal having a turn-on voltage level to the first scan line and a second scan signal having the turn-on voltage level to the second scan line in the first period, and is configured to apply a third scan signal having the turn-on voltage level to the third scan line during the second period, and The data driver is configured to apply a first data signal to the pixel through the data line at a time corresponding to the first scan signal, and to apply a second data signal different from the first data signal to the pixel through the data line at a time corresponding to the second scan signal.

20. The display device according to claim 19, wherein: The first data signal is configured to change according to a grayscale value for the pixel, Wherein, when the grayscale value is greater than the reference grayscale value, the second data signal has a gate-off voltage level at which the transistor is turned off, and When the grayscale value is less than or equal to the reference grayscale value, the second data signal has the turn-on voltage level.

Images