Display panel and display device

Abstract

The application discloses a display panel and a display device, and relates to the technical field of display panels, and discloses a display panel and a display device, which comprises a first area comprising a plurality of pixel circuits, a second area comprising a first start control line, a first driving circuit and a plurality of clock signal lines, the first start control line being electrically connected to the first driving circuit, and the first driving circuit comprising a plurality of shift register units; in the shift register units, a plurality of clock terminals are respectively electrically connected to the plurality of clock signal lines, and N shift output terminals are respectively electrically connected to N adjacent rows of pixel circuits; in a first working mode, the plurality of clock terminals in the shift register units receive different clock signals, so that the N shift output terminals output gate driving signals in time; and in a second working mode, two clock terminals in the shift register units receive the same clock signal, so that the N shift output terminals output gate driving signals at the same time. In the application, the display panel adopts the second working mode, so that the charging time of each row of pixel circuits can be increased, or the refresh rate can be improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the rapid development of display technology, monitors can switch between high resolution and low resolution.

[0003] In a monitor, the driving circuitry located in the non-display area is an indispensable circuit structure, used to realize the display panel's display, touch, and other functions. Currently, the switching between high and low resolutions in a monitor mainly involves pattern changes, and the operation of the driving circuitry in the non-display area remains unchanged.

[0004] Therefore, existing displays are no longer able to meet the demand for higher refresh rates. Summary of the Invention

[0005] This invention provides a display panel and display device to solve the problem that displays cannot meet the requirements for higher refresh rates.

[0006] According to one aspect of the present invention, a display panel is provided, comprising: a first area and a second area;

[0007] The first area includes multiple rows of pixel circuits;

[0008] The second region includes a first start control line, a first drive circuit, and multiple clock signal lines. The first start control line is electrically connected to the first drive circuit, which includes a multi-stage shift register unit. Each shift register unit includes multiple clock terminals and N shift output terminals. The multiple clock terminals are electrically connected to the multiple clock signal lines, and the N shift output terminals are electrically connected to N adjacent rows of pixel circuits, where N ≥ 2.

[0009] The display panel includes a first working mode and a second working mode;

[0010] In the first working mode, the multiple clock terminals in the shift register unit receive different clock signals provided by multiple clock signal lines, so that the N shift output terminals of the shift register unit output gate drive signals in a time-division manner.

[0011] In the second operating mode, the shift register unit has two clock terminals that receive the same clock signal provided by the two clock signal lines, so that the N shift output terminals of the shift register unit simultaneously output gate drive signals.

[0012] According to another aspect of the present invention, a display device is provided, comprising: a display panel as described above.

[0013] In this invention, the N shift output terminals of the shift register unit are electrically connected to N adjacent rows of pixel circuits. In the first operating mode, multiple clock signal lines provide different clock signals, causing the N shift output terminals of the shift register unit to output gate drive signals in a time-division manner, thus scanning each row of pixel circuits in the first region sequentially. In the second operating mode, two clock terminals in the shift register unit receive the same clock signal provided by two clock signal lines, causing the N shift output terminals of the shift register unit to simultaneously output gate drive signals, thus scanning the corresponding N rows of pixel circuits electrically connected to the shift register unit simultaneously. Based on this, regardless of the resolution of the display panel, using the second operating mode can increase the charging time of each row of pixel circuits, which is beneficial for improving the pixel charging rate and reducing the power consumption of the display panel; or, using the second operating mode can help improve the refresh rate of the display panel, enabling the display panel to be compatible with higher refresh rates at lower resolutions.

[0014] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention;

[0017] Figure 2 yes Figure 1 A timing diagram of the display panel shown;

[0018] Figure 3 This is a schematic diagram of a shift register unit provided in an embodiment of the present invention;

[0019] Figure 4 yes Figure 3 A timing diagram of a shift register unit is shown.

[0020] Figure 5 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0021] Figure 6 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0022] Figure 7 yes Figure 6 The diagram shown is a timing schematic of the display panel in the first operating mode.

[0023] Figure 8 yes Figure 6 The diagram shows the timing of the display panel in the second operating mode.

[0024] Figure 9 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0025] Figure 10 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0026] Figure 11 yes Figure 10 The diagram shown is a timing schematic of the display panel in the first operating mode.

[0027] Figure 12 yes Figure 10 The diagram shows the timing of the display panel in the second operating mode.

[0028] Figure 13 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0029] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0031] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 1The display panel shown includes: a first area 101 and a second area 102; the first area 101 includes a multi-row pixel circuit 103; the second area 102 includes a first start control line STV, a first drive circuit 104, and multiple clock signal lines CKL. The first start control line STV is electrically connected to the first drive circuit 104. The first drive circuit 104 includes a multi-stage shift register unit 105; the shift register unit 105 includes multiple clock terminals CK and N shift output terminals Gout. The multiple clock terminals CK are electrically connected to multiple clock signal lines CKL, and the N shift output terminals Gout are electrically connected to multiple clock signal lines CKL. The adjacent N rows of pixel circuits 103, where N≥2; the display panel includes a first operating mode and a second operating mode; in the first operating mode, multiple clock terminals CK in the shift register unit 105 receive different clock signals provided by multiple clock signal lines CKL, causing the N shift output terminals Gout of the shift register unit 105 to output gate drive signals in a time-division manner; in the second operating mode, two clock terminals CK in the shift register unit 105 receive the same clock signals provided by two clock signal lines CKL, causing the N shift output terminals Gout of the shift register unit 105 to output gate drive signals simultaneously.

[0032] In this embodiment, the display panel can be a liquid crystal display panel, an organic light-emitting diode display panel, a micro light-emitting diode display panel, a quantum dot light-emitting diode display panel, etc. The display panel can be a 2D display panel or a 3D display panel. The present invention does not limit the light emission type and structure of the display panel. The display panel includes a first area 101 and a second area 102. Optionally, the first area 101 is the display area of ​​the display panel, and the second area 102 is the non-display area surrounding the display area.

[0033] The first region 101 is used for display. Accordingly, the first region 101 includes multiple pixel circuits 103. The pixel circuits 103 are electrically connected to light-emitting elements or display electrodes (not shown) to drive the light-emitting elements or display electrodes and ensure the display of the light-emitting elements or display electrodes. Optionally, the multiple pixel circuits 103 in the first region 101 can be arranged in a row to form a row of pixel circuits 103, or arranged in a column to form a column of pixel circuits 103. However, the arrangement of the pixel circuits in the first region can also be other arrangements, not limited to an array arrangement. The light-emitting elements in the first region 101 can be organic light-emitting display units, micro light-emitting diode display units, or other types of display units, without specific limitations.

[0034] The second region 102 includes a circuit structure for driving the pixel circuits 103 in the first region 101. Specifically, the second region 102 includes at least a first driving circuit 104. The first driving circuit 104 is used to drive the light-emitting elements or display electrodes by driving the pixel circuits 103 in the first region 101, thereby enabling the first region 101 to display. The first driving circuit 104 in the second region 102 is used to control the scanning of the multi-row pixel circuits 103 in the first region 101.

[0035] The second zone 102 also includes multiple signal lines, which are electrically connected to the first drive circuit 104. Among the multiple signal lines electrically connected to the first drive circuit 104 are at least a first start control line STV and multiple clock signal lines CKL. Figure 1 The diagram shows that the second region 102 includes at least four clock signal lines CKL, labeled as CKL1 (first clock signal line), CKL2 (second clock signal line), CKL3 (third clock signal line), and CKL4 (fourth clock signal line). A first start control line STV is electrically connected to a first drive circuit 104, providing a start control signal to trigger its operation. Clock signal lines CKL are also electrically connected to the first drive circuit 104, providing clock signals. Specifically, the first drive circuit 104, in response to the start control signal provided by the first start control line STV and the clock signals provided by the multiple clock signal lines CKL, scans and drives the pixel circuits 103 in each row of the first region 101. The start control signal provided by the first start control line STV controls the start time of the first drive circuit 104, and the clock signals provided by each clock signal line CKL control the scanning and driving mode of the pixel circuits 103 in each row of the first region 101.

[0036] The first driving circuit 104 includes a multi-level shift register unit 105; the shift register unit 105 includes multiple clock terminals CK and N shift output terminals Gout, the multiple clock terminals CK are electrically connected to multiple clock signal lines CKL respectively, and the N shift output terminals Gout are electrically connected to adjacent N rows of pixel circuits 103 respectively, where N≥2. Figure 1 The diagram shows that the shift register unit 105 includes four clock terminals CK, which are labeled as clock terminal CK1, clock terminal CK2, clock terminal CK3, and clock terminal CK4, respectively. Figure 1The diagram shows a shift register unit 105 including two shift output terminals Gout, labeled Gout1 and Gout2 respectively. One clock terminal CK in the shift register unit 105 is connected to one clock signal line CKL to receive the clock signal. The two clock signal lines CKL connected to the same clock terminal CK (e.g., CK1) in two different shift register units 105 may be the same or different. Under the premise of ensuring normal product operation, the connection relationship between the clock terminal CK and the clock signal line CKL in the shift register unit 105 can be reasonably designed to meet product requirements.

[0037] The N shift output terminals Gout of the shift register unit 105 are electrically connected to the adjacent N rows of pixel circuits 103, where N ≥ 2. For example, the first driving circuit 104 includes a first-stage shift register unit VSR(1), a second-stage shift register unit VSR(2), ... arranged sequentially along the column direction, and the first region 101 includes a first-row pixel circuit 131, a second-row pixel circuit 132, a third-row pixel circuit 133, a fourth-row pixel circuit 134, ... arranged sequentially along the column direction. The first start control line STV is electrically connected to the first-stage shift register unit VSR(1) and is used to provide a start control signal to the first-stage shift register unit VSR(1) to trigger the first driving circuit 104 to operate. The two shift output terminals Gout of the first-stage shift register unit VSR(1) are electrically connected to the adjacent first row pixel circuit 131 and second row pixel circuit 132, respectively. Among them, shift output terminal Gout1 is electrically connected to the first row pixel circuit 131 and shift output terminal Gout2 is electrically connected to the second row pixel circuit 132. The two shift output terminals Gout of the second-stage shift register unit VSR(2) are electrically connected to the adjacent third row pixel circuit 133 and fourth row pixel circuit 134, respectively. Among them, shift output terminal Gout1 is electrically connected to the third row pixel circuit 133 and shift output terminal Gout2 is electrically connected to the fourth row pixel circuit 134. And so on. In other embodiments, depending on the structure of different shift register units, the number of clock terminals of the shift register unit is not limited to 4, and the number of shift output terminals of the shift register unit is not limited to 2; depending on the display requirements of the display panel, the N rows of pixel circuits electrically connected to the N shift output terminals of the shift register unit can be adjacent N rows or have intervals; there are no specific limitations.

[0038] Based on the structure of the display panel described above, the display panel includes two different operating modes: a first operating mode and a second operating mode. The operating mode of the display panel can be set independently by controlling the timing of multiple clock signal lines in the second zone 102.

[0039] In the first operating mode, the multiple clock terminals CK in the shift register unit 105 receive different clock signals from multiple clock signal lines CKL, causing the N shift output terminals Gout of the shift register unit 105 to output gate drive signals in a time-division manner. This controls the multiple clock signal lines CKL to transmit clock signals corresponding to the first operating mode, enabling the first driving circuit 104 to operate in the first operating mode. Consequently, the scanning drive mode of each row pixel circuit 103 in the first area 101 is controlled to be progressive scanning. Accordingly, in the first operating mode, the scanning drive mode of the N rows of pixel circuits 103 electrically connected to the shift register unit 105 is progressive scanning.

[0040] In the second operating mode, the display panel has two clock terminals CK in the shift register unit 105 that receive the same clock signal from two clock signal lines CKL. This causes the N shift output terminals Gout of the shift register unit 105 to simultaneously output gate drive signals, i.e., control multiple clock signal lines CKL to transmit clock signals corresponding to the second operating mode. This allows the first drive circuit 104 to operate in the second operating mode, and correspondingly controls the scanning drive mode of the N rows of pixel circuits 103 electrically connected to the shift register unit 105 to be simultaneous scanning.

[0041] As described above, in the second operating mode, the scanning drive mode of the N rows of pixel circuits 103 electrically connected to the shift register unit 105 is simultaneous scanning. When the display panel switches resolution, for example, when switching from high resolution to low resolution, the display panel executes the second operating mode. If the total scanning drive time for displaying one frame in the second operating mode is consistent with the first operating mode, then the charging time of each row of pixel circuits 103 can be increased in the second operating mode, which is beneficial for improving the pixel charging rate. It can also reduce the number of scanning drives of the clock signal provided by the clock signal line, which is beneficial for reducing the power consumption of the display panel, thus increasing the pixel charging time at low resolution. Alternatively, if the charging time of each row of pixel circuits 103 in the second operating mode is consistent with the first operating mode, then the total scanning drive time for displaying one frame in the second operating mode is reduced, which is beneficial for improving the refresh rate of the display panel, enabling the display panel to be compatible with higher refresh rates at low resolution.

[0042] It is understandable that the second zone also includes a driver chip, which provides the necessary electrical signals to each signal line in the second zone to control the display panel for display. Figure 1 The driver chip is not shown.

[0043] In this invention, the N shift output terminals of the shift register unit are electrically connected to N adjacent rows of pixel circuits. In the first operating mode, multiple clock signal lines provide different clock signals, causing the N shift output terminals of the shift register unit to output gate drive signals in a time-division manner, thus scanning each row of pixel circuits in the first region sequentially. In the second operating mode, two clock terminals in the shift register unit receive the same clock signal provided by two clock signal lines, causing the N shift output terminals of the shift register unit to simultaneously output gate drive signals, thus scanning the corresponding N rows of pixel circuits electrically connected to the shift register unit simultaneously. Based on this, regardless of the resolution of the display panel, using the second operating mode can increase the charging time of each row of pixel circuits, which is beneficial for improving the pixel charging rate and reducing the power consumption of the display panel; or, using the second operating mode can help improve the refresh rate of the display panel, enabling the display panel to be compatible with higher refresh rates at lower resolutions.

[0044] Optionally, in the first operating mode, the effective pulse width of the gate drive signal is H, where H equals the scan duration of one row of pixel circuits in the display panel. Optionally, in the second operating mode, the effective pulse width of the gate drive signal is N*H, where H equals the scan duration of one row of pixel circuits in the display panel. For example, the first drive circuit is electrically connected to Na row pixel circuits, where Na is greater than N.

[0045] In this embodiment, in the first working mode, multiple clock signal lines provide different clock signals to multiple clock terminals in the shift register unit, so that the N shift output terminals of the shift register unit output gate drive signals in a time-division manner. Then, the pixel circuits in each row of the first area are scanned line by line, and the N row pixel circuits electrically connected to the first-level shift register unit are scanned line by line. So, the total scanning drive time for displaying one frame is Na*H, and the number of scan drives provided by the clock signal lines is Na.

[0046] In the second working mode, the shift register unit has two clock terminals that receive the same clock signal from two clock signal lines, causing the N shift output terminals of the shift register unit to simultaneously output gate drive signals. Then, the N rows of pixel circuits electrically connected to the first-stage shift register unit are scanned simultaneously. The total scan drive time for displaying one frame is (Na / N)*N*H=Na*H, and the number of scan drives provided by the clock signal lines is (Na / N).

[0047] As mentioned above, when the total scanning drive time for displaying one frame remains constant, the charging time of each row of pixel circuits can be increased in the second working mode, which is beneficial to improving the pixel charging rate. In addition, the number of scanning drives of the display panel can be reduced, which is beneficial to reducing the power consumption of the display panel.

[0048] In other embodiments, depending on the product requirements, the total scanning drive duration for displaying one frame in the first operating mode may be designed to be different from the total scanning drive duration for displaying one frame in the second operating mode; or, in the first operating mode, the effective pulse width of the gate drive signal may be greater than or equal to H; or, in the second operating mode, the effective pulse width of the gate drive signal may be less than or equal to N*H.

[0049] Figure 2 yes Figure 1 The diagram shows a timing representation of the display panel, such as... Figure 2 As shown, the optional second zone 102 includes Ya clock signal lines CKL, where Ya ≥ 4; among the Ya clock signal lines CKL, any two clock signal lines CKL provide clock signals with the same frequency.

[0050] In this embodiment, the second region 102 includes a first clock signal line CKL1, a second clock signal line CKL2, a third clock signal line CKL3, and a fourth clock signal line CKL4. The clock signals of the first clock signal line CKL1, the second clock signal line CKL2, the third clock signal line CKL3, and the fourth clock signal line CKL4 all have the same frequency.

[0051] In the first operating mode, the phases of the clock signals of the first clock signal line CKL1, the second clock signal line CKL2, the third clock signal line CKL3, and the fourth clock signal line CKL4 are different.

[0052] In the second operating mode, at least two clock signal lines CKL1, CKL2, CKL3, and CKL4 have clock signals with the same phase. For example, the clock signal of the first clock signal line CKL1 has the same phase as the clock signal of the second clock signal line CKL2, and the clock signal of the third clock signal line CKL3 has the same phase as the clock signal of the fourth clock signal line CKL4.

[0053] Understandable. Figure 2 The timing of the four clock signal lines CKL shown is only an example. The frequency and phase of the clock signals provided by each clock signal line CKL can be adjusted reasonably according to the product requirements.

[0054] like Figure 2As shown, the optional second zone 102 includes clock signal lines 1 to ya, where ya ≥ 4; in the first working mode, the phase of the clock signal provided by the j-th clock signal line is earlier than the phase of the clock signal provided by the (j+1)-th clock signal line, and the phase difference between the two is a*H, 1≤j≤Ya; in the second working mode, the clock signal provided by the (2j-1)-th clock signal line is the same as the clock signal provided by the (2j)-th clock signal line, and the phase difference between the clock signal provided by the (2j-2)-th clock signal line and the clock signal provided by the (2j)-th clock signal line is b*H, 1≤2j≤Ya; a and b are both positive integers, and H is equal to the scanning duration of a row of pixel circuits in the display panel.

[0055] In this embodiment, the optional second region 102 may include the first clock signal line CKL1 to the fourth clock signal line CKL4.

[0056] In the first operating mode, the phase of the clock signal provided by the first clock signal line CKL1 is earlier than the phase of the clock signal provided by the second clock signal line CKL2, with a phase difference of a*H; the phase of the clock signal provided by the second clock signal line CKL2 is earlier than the phase of the clock signal provided by the third clock signal line CKL3, with a phase difference of a*H; the phase of the clock signal provided by the third clock signal line CKL3 is earlier than the phase of the clock signal provided by the fourth clock signal line CKL4, with a phase difference of a*H; the phase of the clock signal provided by the fourth clock signal line CKL4 is the same as the phase of the clock signal provided by the first clock signal line CKL1, with a phase difference of a*H. 'a' can be set to 1, and the value of 'a' can be adjusted appropriately according to product requirements, and is not limited to this.

[0057] In the second operating mode, the clock signal provided by the first clock signal line CKL1 is the same as the clock signal provided by the second clock signal line CKL2, and the clock signal provided by the third clock signal line CKL3 is the same as the clock signal provided by the fourth clock signal line CKL4. The phase difference between the clock signals provided by the second clock signal line CKL2 and the fourth clock signal line CKL4 is b*H. b can be set to N, and the value of b can be adjusted appropriately according to product requirements; it is not limited to this.

[0058] Figure 3 This is a schematic diagram of a shift register unit provided in an embodiment of the present invention, as shown below. Figure 3As shown, the optional shift register unit 105 includes: a node control module 151, electrically connected to the input terminal IN, the first input clock terminal CKA, the second input clock terminal CKB, the first node Q1, and the second node Q2, used to control the signals of the first node Q1 and the second node Q2; and N shift output modules 152, the i-th shift output module 152 being electrically connected to the first node Q1, the second node Q2, the i-th control clock terminal CKO, the first level signal terminal VG1, and the i-th shift output terminal Gout, used to control the signal of the i-th shift output terminal Gout, where 1≤i≤N. Figure 3 If N=2, then the shift register unit 105 includes two shift output modules 152, namely the first shift output module 152(1) and the second shift output module 152(2). Correspondingly, the shift register unit 105 includes two control clock terminals CKO, namely the control clock terminal CKO(1) electrically connected to the first shift output module 152(1) and the control clock terminal CKO(2) electrically connected to the second shift output module 152(2). The shift register unit 105 also includes two shift output terminals Gout, namely the shift output terminal Gout1 electrically connected to the first shift output module 152(1) and the shift output terminal Gout2 electrically connected to the second shift output module 152(2).

[0059] In this embodiment, the shift register unit 105 includes a node control module 151. The node control module 151 is electrically connected to the input terminal IN, the first input clock terminal CKA, and the second input clock terminal CKB. The input terminal IN provides an input signal, wherein the input signal of the input terminal IN of the first-stage shift register unit VSR(1) in the first driving circuit 104 is the start control signal provided by the first start control line STV. The first input clock terminal CKA is one clock terminal CK of the shift register unit 105, used to receive the clock signal provided by one clock signal line CDL. The second input clock terminal CKB is the other clock terminal CK of the shift register unit 105, used to receive the clock signal provided by one clock signal line CDL.

[0060] The node control module 151 is also electrically connected to the first node Q1 and the second node Q2. Responding to the signals provided by the input terminal IN, the clock signals provided by the first input clock terminal CKA, and the clock signals provided by the second input clock terminal CKB, the node control module 151 controls the signal of the first node Q1 to transition to a corresponding high or low level, and also controls the signal of the second node Q2 to transition to a corresponding high or low level.

[0061] The shift register unit 105 includes N shift output modules 152. Each shift output module 152 is electrically connected to a first node Q1, a second node Q2, a control clock terminal CKO, and a first-level signal terminal VG1. The control clock terminal CKO in the shift output module 152 is a clock terminal CK of the shift register unit 105, used to receive a clock signal provided by a clock signal line CCL. The first-level signal terminal VG1 provides a first-level signal, which can be designed as a fixed high level or a fixed low level depending on the scanning drive method of the display panel. Alternatively, depending on product requirements, the first-level signal can also be designed as an electrical signal with high-low level transitions.

[0062] The shift output module 152 is also electrically connected to the shift output terminal Gout. In response to the signals provided by the first node Q1, the second node Q2, the clock signal provided by the control clock terminal CKO, and the first level signal provided by the first level signal terminal VG1, the shift output module 152 controls the signal of the shift output terminal Gout to transition to a corresponding high or low level.

[0063] Specifically, the shift register unit 105, in response to the clock signals provided by multiple clock signal lines CKL and signals provided by other terminals, drives the scanning of the N-row pixel circuit 103. In the first operating mode, the multiple clock signal lines CKL provide different clock signals, causing the N shift output terminals Gout of the shift register unit 105 to output gate drive signals in a time-division manner, thereby achieving row-by-row scanning of the N-row pixel circuit 103. In the second operating mode, at least two clock signal lines CKL provide the same clock signal, causing two clock terminals CK in the shift register unit 105 to receive the same clock signal. Therefore, the N shift output terminals Gout of the shift register unit 105 simultaneously output gate drive signals, achieving simultaneous scanning of the N-row pixel circuit 103.

[0064] As mentioned above, the second working mode of the display panel can increase the charging time of each row of pixel circuits, which is beneficial to improving the pixel charging rate and reducing the power consumption of the display panel; it is also beneficial to improve the refresh rate of the display panel, so that the display panel can be compatible with higher refresh rates.

[0065] Figure 4 yes Figure 3 A timing diagram of a shift register unit is shown below, as follows: Figure 4As shown, in the second operating mode, in the shift register unit 105, the first input clock terminal CKA and the second input clock terminal CKB receive the same input clock signal, and the N control clock terminals CKO receive the same control clock signal; the input clock signal and the control clock signal are different. Alternatively, in the first operating mode, in the shift register unit 105, the first input clock terminal CKA, the second input clock terminal CKB, and the N control clock terminals CKO receive different clock signals.

[0066] In this embodiment, in the first working mode, the clock signals received by the first input clock terminal CKA, the second input clock terminal CKB, the control clock terminal CKO(1), and the control clock terminal CKO(2) in the shift register unit 105 are different. Thus, the shift register unit 105 responds to the control of multiple clock signals, and its shift output terminal Gout1 and shift output terminal Gout2 output gate drive signals in a time-division manner.

[0067] In the second operating mode, the clock signal received by the first input clock terminal CKA and the clock signal received by the second input clock terminal CKB in the shift register unit 105 are the same, and the clock signal received by the control clock terminal CKO(1) and the control clock terminal CKO(2) are the same. However, the input clock signal received by the first input clock terminal CKA is different from the control clock signal received by the control clock terminal CKO. Thus, in response to the control of multiple clock signals, the shift register unit 105 simultaneously outputs gate drive signals at its shift output terminals Gout1 and Gout2.

[0068] As described above, the effective level width of the shift output terminal Gout in the second working mode can be greater than the effective level width of the shift output terminal Gout in the first working mode, thus increasing the charging time of a row of pixel circuit 103 in the second working mode.

[0069] In other embodiments, if the effective level width of the shift output terminal Gout in the second working mode is equal to the effective level width of the shift output terminal Gout in the first working mode, then the total scanning drive time of one frame in the second working mode is reduced, which can improve the refresh rate of the display panel.

[0070] Figure 5 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention, as shown below. Figure 5As shown, the optional node control module 151 includes: a first node submodule 153, electrically connected to the second node Q2, the first input clock terminal CKA, and the first node Q1, for controlling the signal of the first node Q1; a second node submodule 154, electrically connected to the second input clock terminal CKB, the input terminal IN, and the second node Q2, for controlling the signal of the second node Q2; and a third node submodule 155, electrically connected to the first input clock terminal CKA, the second level signal terminal VG2, and the first node Q1, for controlling the signal of the first node Q1.

[0071] In this embodiment, the node control module 151 includes a first node submodule 153, a second node submodule 154, and a third node submodule 155.

[0072] The first node submodule 153 is electrically connected to the second node Q2, the first input clock terminal CKA, and the first node Q1. Optionally, the control terminal of the first node submodule 153 is electrically connected to the second node Q2, the input terminal of the first node submodule 153 is electrically connected to the first input clock terminal CKA, and the output terminal of the first node submodule 153 is electrically connected to the first node Q1. The first node submodule 153 is turned on or off in response to the signal control of the second node Q2, thereby controlling the signal of the first node Q1 according to the clock signal provided by the first input clock terminal CKA. Specifically, if the signal of the second node Q2 is at the on level (i.e., active level) that turns on the first node submodule 153, then the first node submodule 153 is turned on, the clock signal provided by the first input clock terminal CKA is written into the first node Q1, and the signal of the first node Q1 changes with the high and low level transitions of the clock signal provided by the first input clock terminal CKA; if the signal of the second node Q2 is at the off level (i.e., inactive level) that turns off the first node submodule 153, then the first node submodule 153 is turned off.

[0073] The second node submodule 154 is electrically connected to the second input clock terminal CKB, the input terminal IN, and the second node Q2. Optionally, the control terminal of the second node submodule 154 is electrically connected to the second input clock terminal CKB, the input terminal of the second node submodule 154 is electrically connected to the input terminal IN, and the output terminal of the second node submodule 154 is electrically connected to the second node Q2. The second node submodule 154 is turned on or off in response to the clock signal of the second input clock terminal CKB, thereby controlling the signal of the second node Q2 according to the input signal provided by the input terminal IN. Specifically, if the clock signal of the second input clock terminal CKB is at the on level that turns on the second node submodule 154, then the second node submodule 154 is turned on, and the input signal provided by the input terminal IN is written to the second node Q2; if the clock signal of the second input clock terminal CKB is at the off level that turns off the second node submodule 154, then the second node submodule 154 is turned off.

[0074] The third node submodule 155 is electrically connected to the first input clock terminal CKA, the second level signal terminal VG2, and the first node Q1. Optionally, the control terminal of the third node submodule 155 is electrically connected to the first input clock terminal CKA, the input terminal of the third node submodule 155 is electrically connected to the second level signal terminal VG2, and the output terminal of the third node submodule 155 is electrically connected to the first node Q1. The third node submodule 155 is turned on or off in response to the clock signal of the first input clock terminal CKA, thereby controlling the signal of the first node Q1 according to the second level signal provided by the second level signal terminal VG2. Specifically, if the clock signal of the first input clock terminal CKA is the on-level that turns on the third node submodule 155, then the third node submodule 155 is turned on, and the second level signal provided by the second level signal terminal VG2 is written to the first node Q1; if the clock signal of the first input clock terminal CKA is the off-level that turns off the third node submodule 155, then the third node submodule 155 is turned off. The second level signal terminal VG2 provides a second level signal. This second level signal can be reasonably designed as a fixed high level or a fixed low level according to the scanning drive method of the display panel. Of course, if required by the product, the second level signal can also be reasonably designed as an electrical signal with high and low level transitions.

[0075] In this embodiment, the optional first node submodule 153 includes transistor M11, the gate of which is electrically connected to the second node Q2. The second node submodule 154 includes transistor M12, the gate of which is electrically connected to the second input clock terminal CKB. The third node submodule 155 includes transistor M13, the gate of which is electrically connected to the first input clock terminal CKA. Optionally, transistors M11, M12, and M13 can all be NMOS.

[0076] like Figure 5 As shown, the optional shift output module 152 includes: a first output submodule 156, electrically connected to the first node Q1, the first level signal terminal VG1 and the shift output terminal Gout, used to control the signal of the shift output terminal Gout; and a second output submodule 157, electrically connected to the second node Q2, the control clock terminal CKO and the shift output terminal Gout, used to control the signal of the shift output terminal Gout.

[0077] In this embodiment, the shift output module 152 includes a first output submodule 156 and a second output submodule 157.

[0078] The first output submodule 156 is electrically connected to the first node Q1, the first level signal terminal VG1, and the shift output terminal Gout. Optionally, the control terminal of the first output submodule 156 is electrically connected to the first node Q1, the input terminal of the first output submodule 156 is electrically connected to the first level signal terminal VG1, and the output terminal of the first output submodule 156 is electrically connected to the shift output terminal Gout. The first output submodule 156 is turned on or off in response to the signal from the first node Q1, thereby controlling the signal of the shift output terminal Gout according to the first level signal provided by the first level signal terminal VG1. Specifically, if the signal from the first node Q1 is the on-level that turns on the first output submodule 156, then the first output submodule 156 is turned on, and the first level signal provided by the first level signal terminal VG1 is written to the shift output terminal Gout; if the signal from the first node Q1 is the off-level that turns off the first output submodule 156, then the first output submodule 156 is turned off.

[0079] The second output submodule 157 is electrically connected to the second node Q2, the control clock terminal CKO, and the shift output terminal Gout. Optionally, the control terminal of the second output submodule 157 is electrically connected to the second node Q2, the input terminal of the second output submodule 157 is electrically connected to the control clock terminal CKO, and the output terminal of the second output submodule 157 is electrically connected to the shift output terminal Gout. The second output submodule 157 is turned on or off in response to the signal from the second node Q2, thereby controlling the signal of the shift output terminal Gout according to the clock signal provided by the control clock terminal CKO. Specifically, if the signal from the second node Q2 is at the on-level that turns on the second output submodule 157, then the second output submodule 157 is turned on, and the clock signal provided by the control clock terminal CKO is written to the shift output terminal Gout. The signal of the shift output terminal Gout changes with the high and low level transitions of the clock signal provided by the control clock terminal CKO. If the signal from the second node Q2 is at the off-level that turns off the second output submodule 157, then the second output submodule 157 is turned off.

[0080] like Figure 5 As shown, the optional shift output module 152 includes: a potential holding submodule 158, and a second output submodule 157 electrically connected to the second node Q2 through the potential holding submodule 158; the potential holding submodule 158 is also electrically connected to the second level signal terminal VG2, which is used to control the signal transmission of the second node Q2 to the second output submodule 157.

[0081] In this embodiment, the control terminal of the optional potential holding submodule 158 is electrically connected to the second level signal terminal VG2, the input terminal of the potential holding submodule 158 is electrically connected to the second node Q2, and the output terminal of the potential holding submodule 158 is electrically connected to the control terminal of the second output submodule 157. The potential holding submodule 158 is turned on or off in response to the control of the second level signal of the second level signal terminal VG2, thereby controlling the turn on or off of the second output submodule 157 according to the signal provided by the second node Q2. Specifically, if the second level signal of the second level signal terminal VG2 is the on level that turns on the potential holding submodule 158, then the potential holding submodule 158 is turned on, and the signal provided by the second node Q2 is written to the control terminal of the second output submodule 157. The second output submodule 157 turns on or off in response to the signal control of the second node Q2. If the second level signal of the second level signal terminal VG2 is the off level that turns off the potential holding submodule 158, then the potential holding submodule 158 is turned off, and the second output submodule 157 maintains the on state or maintains the off state in response to the signal control of the output terminal Q21 of the potential holding submodule 158.

[0082] As described above, the second level signal of the optional second level signal terminal VG2 can be a fixed level signal. This second level signal is the conduction level that makes the potential holding submodule 158 conduct. During the operation of the first drive circuit 104, the potential holding submodule 158 remains in the conducting state, and the second output submodule 157 is turned on or off in response to the signal control of the second node Q2.

[0083] In this embodiment, in the optional shift output module 152(1), the first output submodule 156 includes transistor M14, the gate of transistor M14 is electrically connected to the first node Q1, the second output submodule 157 includes transistor M15, the gate of transistor M15 is electrically connected to node Q21, and the potential holding submodule 158 includes transistor M16, the gate of transistor M16 is electrically connected to the second level signal terminal VG2. In the optional shift output module 152(2), the first output submodule 156 includes transistor M17, the gate of transistor M17 is electrically connected to the first node Q1, the second output submodule 157 includes transistor M18, the gate of transistor M18 is electrically connected to node Q21, and the potential holding submodule 158 includes transistor M19, the gate of transistor M19 is electrically connected to the second level signal terminal VG2. Optional transistors M14, M15, M16, M17, M18, and M19 can all be NMOS.

[0084] like Figure 5As shown, the optional shift register unit 105 further includes: a first coupling submodule 159, electrically connected between the first node Q1 and the first level signal terminal VG1; the shift output module 152 includes: a second coupling submodule 160, electrically connected between the output terminal Q21 of the potential holding submodule 158 and the shift output terminal Gout.

[0085] In this embodiment, the optional first coupling submodule 159 includes a capacitor C11, the second coupling submodule 160 in the shift output module 152(1) includes a capacitor C12, and the second coupling submodule 160 in the shift output module 152(2) includes a capacitor C13.

[0086] like Figure 5 As shown, the optional node control module 151 includes at least one of a forward scan control submodule 161 and a reverse scan control submodule 162; the forward scan control submodule 161 is electrically connected to a first forward scan signal terminal SZA, a second forward scan signal terminal SZB, and an input terminal IN, and is used to control the signal at the input terminal IN; the reverse scan control submodule 162 is electrically connected to a first reverse scan signal terminal SFA, a second reverse scan signal terminal SFB, and an input terminal IN, and is used to control the signal at the input terminal IN; the forward scan control submodule 161 and the reverse scan control submodule 162 are activated in a time-division multiplexing manner.

[0087] In this embodiment, the optional node control module 151 includes a forward scan control submodule 161 and a reverse scan control submodule 162, so the first driving circuit 104 can perform forward and reverse scans. When the first driving circuit 104 performs a forward scan, the forward scan control submodule 161 remains on, and the reverse scan control submodule 162 remains off. When the first driving circuit 104 performs a reverse scan, the forward scan control submodule 161 remains off, and the reverse scan control submodule 162 remains on.

[0088] The input terminal of the optional forward scan control submodule 161 is electrically connected to the first forward scan signal terminal SZA, the control terminal of the forward scan control submodule 161 is electrically connected to the second forward scan signal terminal SZB, and the output terminal of the forward scan control submodule 161 is electrically connected to the input terminal IN. When the first drive circuit 104 performs forward scan, the forward scan control submodule 161 remains on, and the signal received by the first forward scan signal terminal SZA is transmitted to the input terminal IN.

[0089] The input terminal of the optional reverse scan control submodule 162 is electrically connected to the first reverse scan signal terminal SFA, the control terminal of the reverse scan control submodule 162 is electrically connected to the second reverse scan signal terminal SFB, and the output terminal of the reverse scan control submodule 162 is electrically connected to the input terminal IN. When the first drive circuit 104 performs reverse scan, the reverse scan control submodule 162 remains on, and the signal received by the first reverse scan signal terminal SFA is transmitted to the input terminal IN.

[0090] In other embodiments, the node control module may optionally include a forward scan control submodule, or the node control module may include a reverse scan control submodule, or the node control module may not include a forward scan control submodule and may not include a reverse scan control submodule.

[0091] like Figure 5 As shown, the optional forward scan control submodule 161 includes transistor M20, the gate of which is electrically connected to the second forward scan signal terminal SZB. The optional reverse scan control submodule 162 includes transistor M21, the gate of which is electrically connected to the second reverse scan signal terminal SFB. Both transistors M21 and M22 can be NMOS.

[0092] One of the first-level signal terminal and the second-level signal terminal can be selected to have the same signal as the second forward scan signal terminal; the other of the first-level signal terminal and the second-level signal terminal can be selected to have the same signal as the second reverse scan signal terminal. For example... Figure 5 As shown, when the display panel's scanning sequence is forward scanning, the signals of the first level signal terminal VG1 and the second reverse scan signal terminal SFB are the same, both being low; the signals of the second level signal terminal VG2 and the second forward scan signal terminal SZB are the same, both being high, so that the forward scan control submodule 161 is turned on. Of course, when the display panel's scanning sequence changes, such as switching to reverse scanning, the signals of the second level signal terminal VG2 and the second reverse scan signal terminal SFB are the same, both being high, so that the reverse scan control submodule 162 is turned on; the signals of the first level signal terminal VG1 and the second forward scan signal terminal SZB are the same, both being low.

[0093] It is understood that, depending on the product requirements, the type of transistors in the shift register unit can be reasonably designed, and is not limited to NMOS; for example, the multiple transistors in the shift register unit may include at least one NMOS transistor and at least one PMOS transistor, or the multiple transistors in the shift register unit may all be PMOS transistors, or the multiple transistors in the shift register unit may all be NMOS transistors.

[0094] Figure 6 This is a schematic diagram of another display panel provided in an embodiment of the present invention, which is optional. Figure 6 The structure of the intermediate shift register 105 is as follows Figure 5 As shown. Optionally, the first forward scan signal terminal SZA of the Mth stage shift register unit 105 can be electrically connected to the first shift output terminal Gout of the (M-1)th stage shift register unit 105; the first reverse scan signal terminal SFA of the Mth stage shift register unit 105 can be electrically connected to the Nth shift output terminal Gout of the (M+1)th stage shift register unit 105. N can be set to 2.

[0095] For the first-stage shift register unit VSR1, the first forward scan signal terminal SZA of the first-stage shift register unit VSR1 is electrically connected to the first start control line STV, and the first reverse scan signal terminal SFA of the first-stage shift register unit VSR1 is electrically connected to the second shift output terminal Gout2 of the second-stage shift register unit VSR2 to receive the gate drive signal Gout (4).

[0096] For the second-stage shift register unit VSR2, the first forward scan signal terminal SZA of the second-stage shift register unit VSR2 is electrically connected to the first shift output terminal Gout1 of the first-stage shift register unit VSR1 to receive the gate drive signal Gout(1), and the first reverse scan signal terminal SFA of the second-stage shift register unit VSR2 is electrically connected to the second shift output terminal Gout2 of the third-stage shift register unit VSR3 to receive the gate drive signal Gout(6).

[0097] For the third-stage shift register unit VSR3, the first forward scan signal terminal SZA of the third-stage shift register unit VSR3 is electrically connected to the first shift output terminal Gout1 of the second-stage shift register unit VSR2 to receive the gate drive signal Gout(3), and the first reverse scan signal terminal SFA of the third-stage shift register unit VSR3 is electrically connected to the second shift output terminal Gout2 of the fourth-stage shift register unit VSR4 to receive the gate drive signal Gout(8). And so on.

[0098] like Figure 6 As shown, N=2 can be selected; the second region 102 includes the first clock signal line CKL1 to the fourth clock signal line CKL4; the first driving circuit 104 includes a multi-stage shift register circuit 106, the shift register circuit 106 includes two-stage shift register units 105, and the shift register circuit 106 satisfies the following conditions: the first input clock terminal CKA of the first-stage shift register unit (e.g., VSR1) is electrically connected to the second clock signal line CKL2, the second input clock terminal CKB is electrically connected to the first clock signal line CKL1, and the control clock terminal CKO(1) of the first shift output module 152(1) is electrically connected to the third Clock signal line CKL3, control clock terminal CKO(2) of the second shift output module 152(2) is electrically connected to the fourth clock signal line CKL4; first input clock terminal CKA of the second-stage shift register unit (e.g., VSR2) is electrically connected to the fourth clock signal line CKL4, second input clock terminal CKB is electrically connected to the third clock signal line CKL3, control clock terminal CKO(1) of the first shift output module 152(1) is electrically connected to the first clock signal line CKL1, and control clock terminal CKO(2) of the second shift output module 152(2) is electrically connected to the second clock signal line CKL2.

[0099] Figure 7 yes Figure 6The diagram shown illustrates the timing of the display panel in its first operating mode. Here, the first driving circuit can be selected as forward scanning. Taking the shift register circuit 106, composed of the third-level shift register unit VSR3 and the fourth-level shift register unit VSR4, as an example, the forward scanning operation process is described as follows:

[0100] In stage t11, the gate drive signal Gout(3) output by the first shift output terminal Gout1 of the second-stage shift register unit VSR2 is at a high level, and the clock signal provided by the first clock signal line CKL1 is at a high level; then in the third-stage shift register unit VSR3, transistor M13 is turned off, transistor M12 is turned on, the second node Q2 is at a high level to turn on transistors M11, M15 and M18, the first node Q1 is at a low level to turn off transistors M14 and M17, the gate drive signal Gout(5) output by the shift output terminal Gout1 is at a low level and the gate drive signal Gout(6) output by the shift output terminal Gout2 is at a low level.

[0101] During stage t12, the clock signal provided by the second clock signal line CKL2 is at a high level; then in the third-stage shift register unit VSR3, transistor M13 is turned on, transistor M12 is turned off, the second node Q2 is maintained at a high level to turn on transistors M11, M15 and M18, the first node Q1 is at a high level to turn on transistors M14 and M17, the gate drive signal Gout(5) output by the shift output terminal Gout1 is at a low level and the gate drive signal Gout(6) output by the shift output terminal Gout2 is at a low level.

[0102] In stage t13, the clock signal provided by the third clock signal line CKL3 is at a high level; then in the third-stage shift register unit VSR3, transistors M13 and M12 are turned off, the second node Q2 is kept at a high level to turn on transistors M11, M15 and M18, the first node Q1 is at a low level to turn off transistors M14 and M17, the gate drive signal Gout(5) output by the shift output terminal Gout1 is at a high level and the gate drive signal Gout(6) output by the shift output terminal Gout2 is at a low level.

[0103] During stage t14, the clock signal provided by the fourth clock signal line CKL4 is at a high level; then in the third-stage shift register unit VSR3, transistors M13 and M12 are turned off, the second node Q2 is kept at a high level to turn on transistors M11, M15 and M18, the first node Q1 is kept at a low level to turn off transistors M14 and M17, the gate drive signal Gout(5) output by the shift output terminal Gout1 is at a low level and the gate drive signal Gout(6) output by the shift output terminal Gout2 is at a high level.

[0104] After stage t14, in the third-stage shift register unit VSR3, the gate drive signal Gout(5) output by the shift output terminal Gout1 is low and the gate drive signal Gout(6) output by the shift output terminal Gout2 is low.

[0105] Similarly, for the fourth-stage shift register unit VSR4, in stage t13, transistor M12 is turned on, the second node Q2 is high, the gate drive signal Gout(7) output by shift output Gout1 is low, and the gate drive signal Gout(8) output by shift output Gout2 is low; in stage t15, the gate drive signal Gout(7) output by shift output Gout1 is high, and the gate drive signal Gout(8) output by shift output Gout2 is low; in stage t16, the gate drive signal Gout(7) output by shift output Gout1 is low, and the gate drive signal Gout(8) output by shift output Gout2 is high. After stage t16, in the fourth-stage shift register unit VSR4, the gate drive signal Gout(7) output by shift output Gout1 is low, and the gate drive signal Gout(8) output by shift output Gout2 is low.

[0106] Figure 8 yes Figure 6 The diagram shown illustrates the timing of the display panel in the second operating mode. Here, the first driving circuit can be selected as forward scanning. Taking the shift register circuit 106, composed of the third-level shift register unit VSR3 and the fourth-level shift register unit VSR4, as an example, the forward scanning operation process is described as follows:

[0107] During the t21 to t22 stage, the gate drive signal Gout(3) output by the first shift output terminal Gout1 of the second-stage shift register unit VSR2 is at a high level, the clock signal provided by the first clock signal line CKL1 is at a high level, and the clock signal provided by the second clock signal line CKL2 is at a high level; then in the third-stage shift register unit VSR3, transistors M13 and M12 are turned on, the second node Q2 is at a high level to turn on transistors M11, M15 and M18, the first node Q1 is at a high level to turn on transistors M14 and M17, the gate drive signal Gout(5) output by the shift output terminal Gout1 is at a low level and the gate drive signal Gout(6) output by the shift output terminal Gout2 is at a low level.

[0108] During the t23 to t24 stage, the clock signal provided by the third clock signal line CKL3 is at a high level, and the clock signal provided by the fourth clock signal line CKL4 is at a high level; then in the third-stage shift register unit VSR3, transistors M13 and M12 are turned off, the second node Q2 is kept at a high level to turn on transistors M11, M15 and M18, the first node Q1 is at a low level to turn off transistors M14 and M17, the gate drive signal Gout(5) output by the shift output terminal Gout1 is at a high level and the gate drive signal Gout(6) output by the shift output terminal Gout2 is at a high level.

[0109] After stage t24, in the third-stage shift register unit VSR3, the gate drive signal Gout(5) output by the shift output terminal Gout1 is low and the gate drive signal Gout(6) output by the shift output terminal Gout2 is low.

[0110] Similarly, for the fourth-stage shift register unit VSR4, during stages t23 to t24, the first node Q1 is at a high level, the second node Q2 is at a high level, the gate drive signal Gout(7) output by the shift output terminal Gout1 is at a low level, and the gate drive signal Gout(8) output by the shift output terminal Gout2 is at a low level; during stages t25 to t26, the gate drive signal Gout(7) output by the shift output terminal Gout1 is at a high level, and the gate drive signal Gout(8) output by the shift output terminal Gout2 is at a high level. After stage t26, in the fourth-stage shift register unit VSR4, the gate drive signal Gout(7) output by the shift output terminal Gout1 is at a low level, and the gate drive signal Gout(8) output by the shift output terminal Gout2 is at a low level.

[0111] In this embodiment, in the first operating mode, multiple clock signal lines provide different clock signals, causing the N shift output terminals of the shift register unit to output gate drive signals in a time-division manner, thus scanning each row of pixel circuits in the first area sequentially. In the second operating mode, two clock terminals in the shift register unit receive the same clock signal from two clock signal lines, causing the N shift output terminals of the shift register unit to output gate drive signals simultaneously, thus scanning the N rows of pixel circuits electrically connected to the shift register unit simultaneously. Based on this, the display panel adopts the second operating mode, which can increase the charging time of each row of pixel circuits, thus improving the pixel charging rate and reducing the power consumption of the display panel; or, adopting the second operating mode can improve the refresh rate of the display panel, enabling the display panel to be compatible with higher refresh rates.

[0112] Figure 9 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention, and... Figure 5 There are differences. The following only describes them. Figure 9 Different from Figure 5 Part of Figure 9 Zhongyu Figure 5 The same structure will not be described again here.

[0113] like Figure 9 As shown, the optional node control module 151 includes: a first node submodule 201, electrically connected to the second node Q2, the first level signal terminal VG1, and the first node Q1, used to control the signal of the first node Q1; a second node submodule 202, electrically connected to the first node Q1, the first level signal terminal VG1, and the second node Q2, used to control the signal of the second node Q2; a third node submodule 203, electrically connected to the first input clock terminal CKA, the second input clock terminal CKB, the second level signal terminal VG2, and the first node Q1, used to control the signal of the first node Q1; and the input terminal IN is the second node Q2.

[0114] In this embodiment, the control terminal of the first node submodule 201 is electrically connected to the second node Q2. In response to the signal from the second node Q2, the first node submodule 201 connects or disconnects the transmission path between the first level signal terminal VG1 and the first node Q1. The control terminal of the second node submodule 202 is electrically connected to the first node Q1. In response to the signal from the first node Q1, the second node submodule 202 connects or disconnects the transmission path between the first level signal terminal VG1 and the second node Q2.

[0115] The optional third node submodule 203 includes: a first control subunit 204, electrically connected to the first control signal terminal VC1, the first input clock terminal CKA, and the third node Q3, for controlling the signal of the third node Q3; a second control subunit 205, electrically connected to the second control signal terminal VC2, the second input clock terminal CKB, and the third node Q3, for controlling the signal of the third node Q3; and a third control subunit 206, electrically connected to the third node Q3, the second level signal terminal VG2, and the first node Q1, for controlling the signal of the first node Q1.

[0116] In this embodiment, the control terminal of the first control subunit 204 is electrically connected to the first control signal terminal VC1. The first control subunit 204 responds to the control of the signal of the first control signal terminal VC1 to make the transmission path between the first input clock terminal CKA and the third node Q3 open or close.

[0117] The control terminal of the second control subunit 205 is electrically connected to the second control signal terminal VC2. The second control subunit 205 responds to the signal of the second control signal terminal VC2 to make the transmission path between the second input clock terminal CKB and the third node Q3 open or close.

[0118] The control terminal of the third control subunit 206 is electrically connected to the third node Q3. The third control subunit 206 responds to the signal control of the third node Q3 to make the transmission path between the second level signal terminal VG2 and the first node Q1 open or closed.

[0119] In this embodiment, the optional first node submodule 201 includes transistor M31, the gate of which is electrically connected to the second node Q2. The second node submodule 202 includes transistor M32, the gate of which is electrically connected to the first node Q1. The first control subunit 204 includes transistor M33, the gate of which is electrically connected to the first control signal terminal VC1. The second control subunit 205 includes transistor M34, the gate of which is electrically connected to the second control signal terminal VC2. The third control subunit 206 includes transistor M35, the gate of which is electrically connected to the third node Q3.

[0120] Figure 9 The structure of the intermediate shift output module 152 and Figure 5 The same applies, so it will not be repeated here, and the same structure will be used. Figure 5 The attached figures are labeled with reference to the figures.

[0121] One of the first-level signal terminal and the second-level signal terminal can be selected, and its signal is the same as that of the first control signal terminal; the other of the first-level signal terminal and the second-level signal terminal can be selected, and its signal is the same as that of the second control signal terminal. For example... Figure 9As shown, the signals of the optional second level signal terminal VG2 and the first control signal terminal VC1 are the same, both being high level; the signals of the first level signal terminal VG1 and the second control signal terminal VC1 are the same, both being low level.

[0122] like Figure 9 As shown, the optional node control module 151 includes at least one of a forward scan control submodule 207 and a reverse scan control submodule 208; the forward scan control submodule 207 is electrically connected to a first forward scan signal terminal SZA, a second forward scan signal terminal SZB, and an input terminal IN, and is used to control the signal at the input terminal IN; the reverse scan control submodule 208 is electrically connected to a first reverse scan signal terminal SFA, a second reverse scan signal terminal SFB, and an input terminal IN, and is used to control the signal at the input terminal IN; the forward scan control submodule 207 and the reverse scan control submodule are activated in a time-division multiplexing manner.

[0123] Figure 9 Neutral scanning control submodule 207 and Figure 5 The difference is that, Figure 9 The control terminal of the forward scan control submodule 207 is electrically connected to the first forward scan signal terminal SZA, the input terminal of the forward scan control submodule 207 is electrically connected to the second forward scan signal terminal SZB, and the output terminal of the forward scan control submodule 207 is electrically connected to the input terminal IN. When the first drive circuit 104 performs a forward scan, the forward scan control submodule 207 is activated accordingly, and the signal from the second forward scan signal terminal SZB is transmitted to the input terminal IN.

[0124] Figure 9 The reverse scanning control submodule 208 and Figure 5 The difference is that, Figure 9 The control terminal of the reverse scan control submodule 208 is electrically connected to the first reverse scan signal terminal SFA, the input terminal of the reverse scan control submodule 208 is electrically connected to the second reverse scan signal terminal SFB, and the output terminal of the reverse scan control submodule 208 is electrically connected to the input terminal IN. When the first drive circuit 104 performs reverse scan, the reverse scan control submodule 208 is activated accordingly, and the signal from the second reverse scan signal terminal SFB is transmitted to the input terminal IN.

[0125] like Figure 9 As shown, the optional forward scan control submodule 207 includes transistor M36, the gate of which is electrically connected to the first forward scan signal terminal SZA. The optional reverse scan control submodule 208 includes transistor M37, the gate of which is electrically connected to the first reverse scan signal terminal SFA. Both transistors M36 and M37 can be NMOS.

[0126] like Figure 9As shown, when the display panel's scanning sequence is forward scanning, the selected first-level signal terminal VG1 and the second-backscan signal terminal SFB have the same signal, both being low; the second-level signal terminal VG2 and the second-forward scan signal terminal SZB have the same signal, both being high. Of course, if the display panel's scanning sequence changes, such as switching to reverse scanning, the selected second-level signal terminal VG2 and the second-backscan signal terminal SFB have the same signal, both being high; the first-level signal terminal VG1 and the second-forward scan signal terminal SZB have the same signal, both being low.

[0127] Figure 10 This is a schematic diagram of another display panel provided in an embodiment of the present invention, which is optional. Figure 10 The structure of the intermediate shift register 105 is as follows Figure 9 As shown. Optionally, the first forward scan signal terminal SZA of the Mth stage shift register unit 105 can be electrically connected to the first shift output terminal Gout of the (M-1)th stage shift register unit 105; the first reverse scan signal terminal SFA of the Mth stage shift register unit 105 can be electrically connected to the Nth shift output terminal Gout of the (M+1)th stage shift register unit 105. N can be set to 2.

[0128] like Figure 10 As shown, N=2 can be selected; the second region 102 includes the first clock signal line CKL1 to the sixth clock signal line CKL6; the first driving circuit 104 includes a multi-stage shift register circuit 210, the shift register circuit 210 includes three-stage shift register units 105, and the shift register circuit 210 satisfies the following conditions:

[0129] The first input clock terminal CKA of the first-level shift register unit (e.g., VSR1) is electrically connected to the fourth clock signal line CKL4, the second input clock terminal CKB is electrically connected to the fifth clock signal line CKL5, the control clock terminal CKO(1) of the first shift output module 152(1) is electrically connected to the first clock signal line CKL1, and the control clock terminal CKO(2) of the second shift output module 152(2) is electrically connected to the second clock signal line CKL2.

[0130] The first input clock terminal CKA of the second-level shift register unit (e.g., VSR2) is electrically connected to the sixth clock signal line CKL6, the second input clock terminal CKB is electrically connected to the first clock signal line CKL1, the control clock terminal CKO(1) of the first shift output module 152(1) is electrically connected to the third clock signal line CKL3, and the control clock terminal CKO(2) of the second shift output module 152(2) is electrically connected to the fourth clock signal line CKL4.

[0131] The first input clock terminal CKA of the third-level shift register unit (e.g., VSR3) is electrically connected to the second clock signal line CKL2, the second input clock terminal CKB is electrically connected to the third clock signal line CKL3, the control clock terminal CKO(1) of the first shift output module 152(1) is electrically connected to the fifth clock signal line CKL5, and the control clock terminal CKO(2) of the second shift output module 152(2) is electrically connected to the sixth clock signal line CKL6.

[0132] Figure 11 yes Figure 10 The diagram shown illustrates the timing of the display panel in its first operating mode. Here, the first driving circuit can be selected as forward scanning. Taking the shift register circuit 210, composed of the first-stage shift register unit VSR1, the second-stage shift register unit VSR2, and the third-stage shift register unit VSR3, as an example, its forward scanning operation is described as follows:

[0133] 1) For the first-stage shift register unit VSR1:

[0134] In stage t31, the start control signal provided by the first start control line STV is high, and the clock signal provided by the first clock signal line CKL1 is high; then transistor M36 is turned on, the second node Q2 is high to turn on transistors M31, M15 and M18, the first node Q1 is low to turn off transistors M32, M14 and M17, transistor M33 is turned on and transistor M34 is turned off, the third node Q3 is low to turn off transistor M35, the gate drive signal Gout(1) output by the shift output terminal Gout1 is high and the gate drive signal Gout(2) output by the shift output terminal Gout2 is low;

[0135] In stage t32, the clock signal provided by the second clock signal line CKL2 is at a high level; then transistor M36 is turned off, the second node Q2 is kept at a high level to turn on transistors M31, M15 and M18, the first node Q1 is at a low level to turn off transistors M32, M14 and M17, transistor M33 is turned on and transistor M34 is turned off, the third node Q3 is at a low level to turn off transistor M35, the gate drive signal Gout(1) output by the shift output terminal Gout1 is at a low level and the gate drive signal Gout(2) output by the shift output terminal Gout2 is at a high level;

[0136] After stage t32, in the first-stage shift register unit VSR1, the gate drive signal Gout(1) output by the shift output terminal Gout1 is low and the gate drive signal Gout(2) output by the shift output terminal Gout2 is low.

[0137] 2) For the second-stage shift register unit VSR2:

[0138] In stage t31, the gate drive signal Gout(1) is high, and the clock signal provided by the first clock signal line CKL1 is high; then transistor M36 is turned on, the second node Q2 is high to turn on transistors M31, M15 and M18, the first node Q1 is low to turn off transistors M32, M14 and M17, transistor M33 is turned on and transistor M34 is turned off, the third node Q3 is low to turn off transistor M35, the gate drive signal Gout(3) output by the shift output terminal Gout1 is low and the gate drive signal Gout(4) output by the shift output terminal Gout2 is low;

[0139] During stage t32, the clock signal provided by the second clock signal line CKL2 is at a high level; then transistor M36 is turned off, the second node Q2 is kept at a high level to turn on transistors M31, M15 and M18, the first node Q1 is at a low level to turn off transistors M32, M14 and M17, transistor M33 is turned on and transistor M34 is turned off, the third node Q3 is at a low level to turn off transistor M35, the gate drive signal Gout(3) output by the shift output terminal Gout1 is at a low level and the gate drive signal Gout(4) output by the shift output terminal Gout2 is at a low level;

[0140] In stage t33, the clock signal provided by the third clock signal line CKL3 is at a high level; then transistor M36 is turned off, the second node Q2 is kept at a high level to turn on transistors M31, M15 and M18, the first node Q1 is at a low level to turn off transistors M32, M14 and M17, transistor M33 is turned on and transistor M34 is turned off, the third node Q3 is at a low level to turn off transistor M35, the gate drive signal Gout(3) output by the shift output terminal Gout1 is at a high level and the gate drive signal Gout(4) output by the shift output terminal Gout2 is at a low level;

[0141] During stage t34, the clock signal provided by the fourth clock signal line CKL4 is at a high level; then transistor M36 is turned off, the second node Q2 is kept at a high level to turn on transistors M31, M15 and M18, the first node Q1 is at a low level to turn off transistors M32, M14 and M17, transistor M33 is turned on and transistor M34 is turned off, the third node Q3 is at a low level to turn off transistor M35, the gate drive signal Gout(3) output by the shift output terminal Gout1 is at a low level and the gate drive signal Gout(4) output by the shift output terminal Gout2 is at a high level;

[0142] After stage t34, in the second-stage shift register unit VSR2, the gate drive signal Gout(3) output by the shift output terminal Gout1 is low and the gate drive signal Gout(4) output by the shift output terminal Gout2 is low.

[0143] 3) For the third-level shift register unit VSR3:

[0144] In stage t33, the gate drive signal Gout(3) is high, and the clock signal provided by the third clock signal line CKL3 is high; then transistor M36 is turned on, the second node Q2 is high to turn on transistors M31, M15 and M18, the first node Q1 is low to turn off transistors M32, M14 and M17, transistor M33 is turned on and transistor M34 is turned off, the third node Q3 is low to turn off transistor M35, the gate drive signal Gout(5) output by the shift output terminal Gout1 is low and the gate drive signal Gout(6) output by the shift output terminal Gout2 is low;

[0145] During stage t34, the clock signal provided by the fourth clock signal line CKL4 is at a high level; then transistor M36 is turned off, the second node Q2 is kept at a high level to turn on transistors M31, M15 and M18, the first node Q1 is at a low level to turn off transistors M32, M14 and M17, transistor M33 is turned on and transistor M34 is turned off, the third node Q3 is at a low level to turn off transistor M35, the gate drive signal Gout(5) output by the shift output terminal Gout1 is at a low level and the gate drive signal Gout(6) output by the shift output terminal Gout2 is at a low level;

[0146] During stage t35, the clock signal provided by the 5th clock signal line CKL5 is at a high level; then transistor M36 is turned off, the second node Q2 is kept at a high level to turn on transistors M31, M15 and M18, the first node Q1 is at a low level to turn off transistors M32, M14 and M17, transistor M33 is turned on and transistor M34 is turned off, the third node Q3 is at a low level to turn off transistor M35, the gate drive signal Gout(5) output by the shift output terminal Gout1 is at a high level and the gate drive signal Gout(6) output by the shift output terminal Gout2 is at a low level;

[0147] During stage t36, the clock signal provided by the 6th clock signal line CKL6 is at a high level; then transistor M36 is turned off, the second node Q2 is kept at a high level to turn on transistors M31, M15 and M18, the first node Q1 is at a low level to turn off transistors M32, M14 and M17, transistor M33 is turned on and transistor M34 is turned off, the third node Q3 is at a low level to turn off transistor M35, the gate drive signal Gout(5) output by the shift output terminal Gout1 is at a low level and the gate drive signal Gout(6) output by the shift output terminal Gout2 is at a high level;

[0148] After stage t36, in the third-stage shift register unit VSR3, the gate drive signal Gout(5) output by the shift output terminal Gout1 is low and the gate drive signal Gout(6) output by the shift output terminal Gout2 is low.

[0149] Figure 12 yes Figure 10 The diagram shown illustrates the timing of the display panel in the second operating mode. Here, the first driving circuit can be selected as forward scanning. Taking the shift register circuit 210, composed of the first-stage shift register unit VSR1, the second-stage shift register unit VSR2, and the third-stage shift register unit VSR3, as an example, the forward scanning operation process is described as follows:

[0150] 1) For the first-stage shift register unit VSR1:

[0151] During the t41 to t42 stage, the start control signal provided by the first start control line STV is at a high level, the clock signal provided by the first clock signal line CKL1 is at a high level, and the clock signal provided by the second clock signal line CKL2 is at a high level; then transistor M36 is turned on, the second node Q2 is at a high level to turn on transistors M31, M15 and M18, the first node Q1 is at a low level to turn off transistors M32, M14 and M17, transistor M33 is turned on and transistor M34 is turned off, the third node Q3 is at a low level to turn off transistor M35, the gate drive signal Gout(1) output by the shift output terminal Gout1 is at a high level and the gate drive signal Gout(2) output by the shift output terminal Gout2 is at a high level;

[0152] During the t43 to t44 stage, the clock signal provided by the third clock signal line CKL3 is at a high level, and the clock signal provided by the fourth clock signal line CKL4 is at a high level; then transistor M36 is turned off, transistor M33 is turned on and transistor M34 is turned off, the third node Q3 is at a high level to turn on transistor M35, the first node Q1 is at a high level to turn on transistors M32, M14 and M17, the second node Q2 is at a low level to turn off transistors M31, M15 and M18, the gate drive signal Gout(1) output by the shift output terminal Gout1 is at a low level and the gate drive signal Gout(2) output by the shift output terminal Gout2 is at a low level;

[0153] After stage t44, in the first-stage shift register unit VSR1, the gate drive signal Gout(1) output by the shift output terminal Gout1 is low and the gate drive signal Gout(2) output by the shift output terminal Gout2 is low.

[0154] 2) For the second-stage shift register unit VSR2:

[0155] During the t41 to t42 stage, the gate drive signal Gout(1) is high, the clock signal provided by the first clock signal line CKL1 is high, and the clock signal provided by the second clock signal line CKL2 is high; then transistor M36 is turned on, the second node Q2 is high to turn on transistors M31, M15 and M18, the first node Q1 is low to turn off transistors M32, M14 and M17, transistor M33 is turned on and transistor M34 is turned off, the third node Q3 is low to turn off transistor M35, the gate drive signal Gout(3) output by the shift output terminal Gout1 is low and the gate drive signal Gout(4) output by the shift output terminal Gout2 is low;

[0156] During the t43 to t44 stage, the clock signal provided by the third clock signal line CKL3 is at a high level, and the clock signal provided by the fourth clock signal line CKL4 is at a high level; then transistor M36 is turned off, the second node Q2 is kept at a high level to turn on transistors M31, M15 and M18, the first node Q1 is at a low level to turn off transistors M32, M14 and M17, transistor M33 is turned on and transistor M34 is turned off, the third node Q3 is at a low level to turn off transistor M35, the gate drive signal Gout(3) output by the shift output terminal Gout1 is at a high level and the gate drive signal Gout(4) output by the shift output terminal Gout2 is at a high level;

[0157] After stage t44, in the second-stage shift register unit VSR2, the gate drive signal Gout(3) output by the shift output terminal Gout1 is low and the gate drive signal Gout(4) output by the shift output terminal Gout2 is low.

[0158] 3) For the third-level shift register unit VSR3:

[0159] During the t43 to t44 stage, the gate drive signal Gout(3) is high, the clock signal provided by the third clock signal line CKL3 is high, and the clock signal provided by the fourth clock signal line CKL4 is high; then transistor M36 is turned on, the second node Q2 is high to turn on transistors M31, M15 and M18, the first node Q1 is low to turn off transistors M32, M14 and M17, transistor M33 is turned on and transistor M34 is turned off, the third node Q3 is low to turn off transistor M35, the gate drive signal Gout(5) output by the shift output terminal Gout1 is low and the gate drive signal Gout(6) output by the shift output terminal Gout2 is low;

[0160] During the t45 to t46 stage, the clock signal provided by the 5th clock signal line CKL5 is at a high level, and the clock signal provided by the 6th clock signal line CKL6 is at a high level; then transistor M36 is turned off, the second node Q2 is kept at a high level to turn on transistors M31, M15 and M18, the first node Q1 is at a low level to turn off transistors M32, M14 and M17, transistor M33 is turned on and transistor M34 is turned off, the third node Q3 is at a low level to turn off transistor M35, the gate drive signal Gout(5) output by the shift output terminal Gout1 is at a high level and the gate drive signal Gout(6) output by the shift output terminal Gout2 is at a high level;

[0161] After stage t46, in the third-stage shift register unit VSR3, the gate drive signal Gout(5) output by the shift output terminal Gout1 is low and the gate drive signal Gout(6) output by the shift output terminal Gout2 is low.

[0162] In this embodiment, in the first operating mode, multiple clock signal lines provide different clock signals, causing the N shift output terminals of the shift register unit to output gate drive signals in a time-division manner, thus scanning each row of pixel circuits in the first area sequentially. In the second operating mode, two clock terminals in the shift register unit receive the same clock signal from two clock signal lines, causing the N shift output terminals of the shift register unit to output gate drive signals simultaneously, thus scanning the N rows of pixel circuits electrically connected to the shift register unit simultaneously. Based on this, the display panel adopts the second operating mode, which can increase the charging time of each row of pixel circuits, thus improving the pixel charging rate and reducing the power consumption of the display panel; or, adopting the second operating mode can improve the refresh rate of the display panel, enabling the display panel to be compatible with higher refresh rates.

[0163] It is understood that the structure of the shift register unit and the timing of the display panel provided in the above embodiments are only some examples of the present invention. Those skilled in the art can reasonably design the structure of the shift register unit and the timing of the display panel while ensuring the normal operation of the display panel, and are not limited thereto.

[0164] Based on the same inventive concept, embodiments of the present invention also provide a display device, which includes a display panel as described in any of the above embodiments. Figure 13 This is a schematic diagram of a display device provided in an embodiment of the present invention, such as... Figure 13 As shown, the display device 300 provided in this embodiment of the invention possesses the corresponding functional modules and beneficial effects of the display panel described in any of the above embodiments. The display device 300 can be a smartphone, in-vehicle display, tablet computer, laptop computer, super mobile personal computer, netbook, smart wearable device, augmented reality (AR) / virtual reality (VR) device, or other terminal device. The display panel can be any type of display panel, such as a micro light-emitting diode display panel or an organic light-emitting diode display panel, and is not limited thereto.

[0165] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0166] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: Zone 1 and Zone 2; The first area includes multiple rows of pixel circuits; The second region includes a first start control line, a first drive circuit, and multiple clock signal lines. The first start control line is electrically connected to the first drive circuit, which includes a multi-stage shift register unit. Each shift register unit includes multiple clock terminals and N shift output terminals. The multiple clock terminals are electrically connected to the multiple clock signal lines, and the N shift output terminals are electrically connected to N adjacent rows of pixel circuits, where N ≥ 2. The display panel includes a first working mode and a second working mode; In the first working mode, the multiple clock terminals in the shift register unit receive different clock signals provided by multiple clock signal lines, so that the N shift output terminals of the shift register unit output gate drive signals in a time-division manner. In the second working mode, the shift register unit has two clock terminals that receive the same clock signal provided by the two clock signal lines, so that the N shift output terminals of the shift register unit simultaneously output gate drive signals. The shift register unit includes: a node control module electrically connected to an input terminal, a first input clock terminal, a second input clock terminal, a first node, and a second node, used to control the signals of the first node and the second node; There are N shift output modules. The i-th shift output module is electrically connected to the first node, the second node, the i-th control clock terminal, the first level signal terminal, and the i-th shift output terminal, and is used to control the signal of the i-th shift output terminal, where 1≤i≤N.

2. The display panel according to claim 1, characterized in that, In the first operating mode, the effective pulse width of the gate drive signal is H, where H is equal to the scan duration of a row of pixel circuits in the display panel.

3. The display panel according to claim 1, characterized in that, In the second operating mode, the effective pulse width of the gate drive signal is N*H, where H is equal to the scan duration of a row of pixel circuits in the display panel.

4. The display panel according to claim 1, characterized in that, In the second working mode, in the shift register unit, the first input clock terminal and the second input clock terminal receive the same input clock signal, and the N control clock terminals receive the same control clock signal; The input clock signal is different from the control clock signal.

5. The display panel according to claim 1, characterized in that, In the first operating mode, in the shift register unit, the first input clock terminal, the second input clock terminal, and the N control clock terminals receive different clock signals.

6. The display panel according to claim 1, characterized in that, The second region includes Ya clock signal lines, where Ya ≥ 4; Of the Ya clock signal lines, any two randomly selected clock signal lines provide clock signals with the same frequency.

7. The display panel according to claim 1, characterized in that, The second region includes clock signal lines 1 to ya, where ya ≥ 4; In the first working mode, the phase of the clock signal provided by the j-th clock signal line is earlier than the phase of the clock signal provided by the (j+1)-th clock signal line, and the phase difference between the two is a*H, 1≤j≤Ya; In the second working mode, the clock signal provided by the (2j-1) clock signal line is the same as the clock signal provided by the (2j) clock signal line, and the phase difference between the clock signal provided by the (2j-2) clock signal line and the clock signal provided by the (2j) clock signal line is b*H, 1≤2j≤Ya; a and b are both positive integers, and H is equal to the scanning time of a row of pixel circuits in the display panel.

8. The display panel according to claim 1, characterized in that, N=2； The second region includes clock signal lines 1 through 4; The first driving circuit includes a multi-stage shift register circuit, the shift register circuit includes two stages of the shift register unit, and the shift register circuit satisfies the following conditions: The first input clock terminal of the shift register unit of the first stage is electrically connected to the second clock signal line, the second input clock terminal is electrically connected to the first clock signal line, the control clock terminal of the first shift output module is electrically connected to the third clock signal line, and the control clock terminal of the second shift output module is electrically connected to the fourth clock signal line. The first input clock terminal of the shift register unit of the second level is electrically connected to the fourth clock signal line, the second input clock terminal is electrically connected to the third clock signal line, the control clock terminal of the first shift output module is electrically connected to the first clock signal line, and the control clock terminal of the second shift output module is electrically connected to the second clock signal line.

9. The display panel according to claim 1, characterized in that, N=2； The second region includes clock signal lines 1 through 6; The first driving circuit includes a multi-stage shift register circuit, which includes three stages of the shift register unit. The shift register circuit satisfies the following conditions: The first input clock terminal of the shift register unit of the first stage is electrically connected to the fourth clock signal line, the second input clock terminal is electrically connected to the fifth clock signal line, the control clock terminal of the first shift output module is electrically connected to the first clock signal line, and the control clock terminal of the second shift output module is electrically connected to the second clock signal line. The first input clock terminal of the shift register unit of the second level is electrically connected to the sixth clock signal line, the second input clock terminal is electrically connected to the first clock signal line, the control clock terminal of the first shift output module is electrically connected to the third clock signal line, and the control clock terminal of the second shift output module is electrically connected to the fourth clock signal line. The first input clock terminal of the shift register unit of the third level is electrically connected to the second clock signal line, the second input clock terminal is electrically connected to the third clock signal line, the control clock terminal of the first shift output module is electrically connected to the fifth clock signal line, and the control clock terminal of the second shift output module is electrically connected to the sixth clock signal line.

10. The display panel according to claim 1, characterized in that, The node control module includes: The first node submodule is electrically connected to the second node, the first input clock terminal and the first node, and is used to control the signal of the first node; The second node submodule is electrically connected to the second input clock terminal, the input terminal and the second node, and is used to control the signal of the second node; The third node submodule is electrically connected to the first input clock terminal, the second level signal terminal, and the first node, and is used to control the signal of the first node.

11. The display panel according to claim 1, characterized in that, The node control module includes: The first node submodule is electrically connected to the second node, the first level signal terminal and the first node, and is used to control the signal of the first node; The second node submodule is electrically connected to the first node, the first level signal terminal and the second node, and is used to control the signal of the second node; The third node submodule is electrically connected to the first input clock terminal, the second input clock terminal, the second level signal terminal and the first node, and is used to control the signal of the first node; The input terminal is the second node.

12. The display panel according to claim 11, characterized in that, The third node submodule includes: The first control subunit is electrically connected to the first control signal terminal, the first input clock terminal and the third node, and is used to control the signal of the third node; The second control subunit is electrically connected to the second control signal terminal, the second input clock terminal and the third node, and is used to control the signal of the third node; The third control subunit is electrically connected to the third node, the second level signal terminal, and the first node, and is used to control the signal of the first node.

13. The display panel according to claim 12, characterized in that, One of the first level signal terminal and the second level signal terminal has the same signal as the first control signal terminal; The other of the first level signal terminal and the second level signal terminal has the same signal as the second control signal terminal.

14. The display panel according to claim 10 or 11, characterized in that, The node control module includes at least one of a forward scan control submodule and a reverse scan control submodule; The forward scan control submodule is electrically connected to the first forward scan signal terminal, the second forward scan signal terminal, and the input terminal, and is used to control the signal at the input terminal. The backscan control submodule is electrically connected to the first backscan signal terminal, the second backscan signal terminal and the input terminal, and is used to control the signal at the input terminal. The forward scan control submodule and the reverse scan control submodule are activated in a time-sharing manner.

15. The display panel according to claim 14, characterized in that, The first positive scan signal terminal of the shift register unit of the Mth stage is electrically connected to the first shift output terminal of the shift register unit of the (M-1)th stage; The first backscan signal terminal of the shift register unit of the Mth stage is electrically connected to the Nth shift output terminal of the shift register unit of the (M+1)th stage.

16. The display panel according to claim 14, characterized in that, One of the first level signal terminal and the second level signal terminal is the same as the signal of the second forward scan signal terminal; The other of the first level signal terminal and the second level signal terminal has the same signal as the second reverse scan signal terminal.

17. The display panel according to claim 1, characterized in that, The shift output module includes: The first output submodule is electrically connected to the first node, the first level signal terminal, and the shift output terminal, and is used to control the signal of the shift output terminal; The second output submodule is electrically connected to the second node, the control clock terminal, and the shift output terminal, and is used to control the signal of the shift output terminal.

18. The display panel according to claim 17, characterized in that, The shift output module includes: A potential-holding submodule is provided, and the second output submodule is electrically connected to the second node through the potential-holding submodule. The potential holding submodule is also electrically connected to a second level signal terminal, used to control the signal transmission of the second node to the second output submodule.

19. The display panel according to claim 18, characterized in that, The shift register unit further includes: a first coupling submodule, electrically connected between the first node and the first level signal terminal; The shift output module includes a second coupling submodule electrically connected between the output terminal of the potential holding submodule and the shift output terminal.

20. A display device, characterized in that, include: The display panel as described in any one of claims 1-19.

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