Gain-adjustable amplifying circuit and amplifier

Abstract

The invention discloses a gain-adjustable amplifying circuit and an amplifier, and is applied to the technical field of electronics. Wherein the gain adjusting unit is connected with an MOS (Metal Oxide Semiconductor) tube at a non-output end side in the second-stage signal amplification circuit and a numerical control signal device, and is used for acquiring a first numerical control signal sent by the numerical control signal device and realizing gain adjustment of the amplification circuit according to the first numerical control signal; and the current balance unit is connected with the first-stage signal amplification circuit, the second-stage signal amplification circuit and the numerical control signal device, and is used for acquiring a second numerical control signal sent by the numerical control signal device, and realizing stable current output of the amplification circuit according to the second numerical control signal and the current increased by gain adjustment of the amplification circuit. Therefore, the output port standing waves are kept consistent when the gain of the circuit is adjusted through the gain adjusting unit, and the additional phase shift generated by the signal is reduced. Through the current balance unit, the input / output radio frequency tube current of the amplification circuit during gain adjustment can be effectively stabilized.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a gain adjustable amplification circuit and an amplifier. Background Art

[0002] Traditional low-noise amplifiers often do not have gain adjustment functions, and it is difficult to meet the current technical requirements of multi-channel large-scale communication system arrays for adjustable link gain distribution.

[0003] In order to make the low noise amplifier have a certain gain adjustable capability, the general design method is to add a current rudder at the output end of the low noise amplifier to extract / inject the current of the RF core tube, thereby changing the gain of the low noise amplifier. However, in different gain modes, the working state of the RF core tube is different, which causes the low noise amplifier to present different port standing waves and cause the signal to produce additional phase shift. The different port standing waves affect the RF performance of adjacent modules in the link, and the additional phase dependence generated by the signal will affect the accuracy of the output signal.

[0004] In view of the above technology, seeking a gain adjustable amplifier circuit is an urgent problem to be solved by those skilled in the art. Summary of the invention

[0005] The purpose of the present application is to provide a gain adjustable amplifier circuit and amplifier, which can solve the problem in the prior art that different port standing waves and additional phase shift of the signal are presented at the output end of the amplifier by adding a current rudder at the output end of the amplifier to extract / inject the current of the RF core tube, thereby changing the gain of the low noise amplifier.

[0006] In order to solve the above technical problems, the present application provides a gain adjustable amplifier circuit, comprising: a gain adjustment unit, a current balancing unit, a first-stage signal amplifier circuit and a second-stage signal amplifier circuit, wherein the second-stage signal amplifier circuit comprises a plurality of MOS tubes;

[0007] The first end of the gain adjustment unit is connected to the gate of the MOS tube on the non-output end side in the second-stage signal amplification circuit, the second end of the gain adjustment unit is connected to the drain of the MOS tube on the non-output end side, and the third end of the gain adjustment unit is connected to the digital control signal device, and is used to obtain the first digital control signal sent by the digital control signal device, and implement the gain adjustment of the amplifier circuit according to the first digital control signal;

[0008] The first end of the current balancing unit is connected to the output end of the first-stage signal amplifying circuit and the input end of the second-stage signal amplifying circuit, the second end of the current balancing unit is connected to the adjustment end of the second-stage signal amplifying circuit, and the third end of the current balancing unit is connected to the digital control signal device, and is used to obtain the second digital control signal sent by the digital control signal device, and to increase the current by gain adjustment according to the second digital control signal and the amplifying circuit to achieve stable current output of the amplifying circuit.

[0009] Preferably, the gain adjustment unit includes X gain adjustment circuits with the same structure; X is an integer greater than zero;

[0010] The first ends of the gain adjustment circuits are connected to each other and are commonly connected to the gate of the MOS tube on the non-output end side as the first end of the gain adjustment unit;

[0011] The second ends of the gain adjustment circuits are connected to each other and are commonly connected to the drain of the MOS tube on the non-output end side as the second end of the gain adjustment unit;

[0012] The third ends of the gain adjustment circuits are connected to each other and are commonly connected to the digital control signal device as the third end of the gain adjustment unit.

[0013] Preferably, the gain adjustment circuit includes a first MOS tube and a first transmission gate;

[0014] The gate of the first MOS tube is connected to the gate of the MOS tube on the non-output side as the first end of the gain adjustment circuit, the drain of the first MOS tube is connected to the drain of the MOS tube on the non-output side as the second end of the gain adjustment circuit, and the source of the first MOS tube is connected to the first end of the first transmission gate;

[0015] The second end of the first transmission gate is grounded, and the third end of the first transmission gate is connected to the digital control signal device as the third end of the gain adjustment circuit.

[0016] Preferably, the current balancing unit includes M current balancing circuits with the same structure, where M is an integer greater than zero;

[0017] The first ends of the current balancing circuits are connected to each other and are commonly connected as the first end of the current balancing unit to the output end of the first-stage signal amplifying circuit and the input end of the second-stage signal amplifying circuit;

[0018] The second ends of the current balancing circuits are connected to each other and are commonly connected to the regulating end of the second-stage signal amplifying circuit as the second end of the current balancing unit;

[0019] The third terminals of the current balancing circuits are connected to each other and are commonly connected to the digital control signal device as the third terminal of the current balancing unit.

[0020] Preferably, the current balancing circuit comprises: a second MOS tube, a second transmission gate and a radio frequency choke resistor;

[0021] Wherein, the first end of the radio frequency choke resistor is connected to the output end of the first stage signal amplification circuit and the input end of the second stage signal amplification circuit as the first end of the current balancing circuit; the second end of the radio frequency choke resistor is connected to the first end of the second transmission gate;

[0022] The second end of the second transmission gate is connected to the gate of the second MOS tube, and the third end of the second transmission gate is connected to the digital control signal device as the third end of the current balancing circuit;

[0023] The source of the second MOS tube is grounded, and the drain of the second MOS tube is connected to the regulating end of the second-stage signal amplifying circuit as the second end of the current balancing circuit.

[0024] Preferably, the first-stage signal amplification circuit comprises: a first amplifier, a second amplifier and a first transformer;

[0025] The input end of the first amplifier is connected to the converter as the input end of the first stage signal amplification circuit, the first pin end of the first amplifier is grounded, and the output end of the first amplifier is connected to the first end of the first transformer;

[0026] The second end of the first transformer is connected to the first pin end of the second amplifier, the third end of the first transformer is connected to the first voltage end, and the fourth end of the first transformer is connected to the input end of the second amplifier;

[0027] The second pin end of the second amplifier is connected to the second voltage end, and the output end of the second amplifier is connected to the input end of the second stage signal amplification circuit as the output end of the first stage signal amplification circuit.

[0028] Preferably, the first-stage signal amplification circuit further includes: a first decoupling capacitor and a second decoupling capacitor;

[0029] Wherein, the first end of the first decoupling capacitor is connected to the third end of the first transformer and the first voltage end;

[0030] The second terminal of the first decoupling capacitor is grounded;

[0031] A first end of the second decoupling capacitor is connected to the second end of the first transformer and the first pin end of the second amplifier;

[0032] The second terminal of the second decoupling capacitor is grounded.

[0033] Preferably, the second-stage signal amplification circuit comprises: a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a first asymmetric five-port transformer and a second transformer;

[0034] The gate of the third MOS tube is connected to the output end of the first-stage signal amplification circuit and the first end of the gain adjustment unit as the input end of the second-stage signal amplification circuit, the source of the third MOS tube is grounded, and the drain of the third MOS tube is connected to the first end of the first asymmetric five-port transformer and the second end of the gain adjustment unit;

[0035] The second end of the first asymmetric five-port transformer is connected to the third voltage end; the third end of the first asymmetric five-port transformer is connected to the source of the fourth MOS tube, and together they are connected to the second end of the current balancing unit as the regulating end of the second-stage signal amplification circuit; the fourth end of the first asymmetric five-port transformer is connected to the gate of the fourth MOS tube;

[0036] The drain of the fourth MOS tube is connected to the source of the fifth MOS tube;

[0037] The gate of the fifth MOS tube is connected to the fourth voltage terminal, and the drain of the fifth MOS tube is connected to the first terminal of the second transformer;

[0038] The third terminal of the second transformer is connected to the second voltage terminal;

[0039] The second end of the second transformer and the fourth end of the second transformer serve together as the output end of the second-stage signal amplifying circuit.

[0040] Preferably, the second-stage signal amplification circuit further includes: a third decoupling capacitor, a fourth decoupling capacitor, a fifth decoupling capacitor, a sixth decoupling capacitor, and a first matching capacitor;

[0041] Wherein, a first end of the third decoupling capacitor is connected to the fifth end of the first asymmetric five-port transformer, and a second end of the third decoupling capacitor is grounded;

[0042] A first end of the fourth decoupling capacitor is connected to the second end and the third voltage end of the first asymmetric five-port transformer, and a second end of the fourth decoupling capacitor is grounded;

[0043] A first end of the fifth decoupling capacitor is connected to the gate of the fifth MOS tube and the fourth voltage end, and a second end of the fifth decoupling capacitor is grounded;

[0044] A first end of the sixth decoupling capacitor is connected to the third end and the second voltage end of the second transformer, and a second end of the sixth decoupling capacitor is grounded;

[0045] The first end of the first matching capacitor is connected to the second end of the second transformer, and the second end of the first matching capacitor is connected to the fourth end of the second transformer.

[0046] On the other hand, the present application also provides an amplifier, comprising the above-mentioned gain adjustable amplifier circuit.

[0047] A gain-adjustable amplifier circuit provided in the present application includes: a gain adjustment unit, a current balancing unit, a first-stage signal amplifier circuit and a second-stage signal amplifier circuit, wherein the second-stage signal amplifier circuit includes a plurality of MOS tubes; a first end of the gain adjustment unit is connected to a gate of the MOS tube on a non-output end side of the second-stage signal amplifier circuit, a second end of the gain adjustment unit is connected to a drain of the MOS tube on the non-output end side, and a third end of the gain adjustment unit is connected to a digital control signal device, for obtaining a first digital control signal sent by the digital control signal device, and implementing gain adjustment of the amplifier circuit according to the first digital control signal; a first end of the current balancing unit is connected to an output end of the first-stage signal amplifier circuit and an input end of the second-stage signal amplifier circuit, a second end of the current balancing unit is connected to an adjustment end of the second-stage signal amplifier circuit, and a third end of the current balancing unit is connected to the digital control signal device, for obtaining a second digital control signal sent by the digital control signal device, and implementing a stable current output of the amplifier circuit by increasing the current through gain adjustment according to the second digital control signal and the amplifier circuit. It can be seen that, based on the traditional current steering, the present application connects a gain adjustment unit in parallel in the MOS tube at the non-output end, which ensures that when the circuit gain is adjusted, the port standing wave output at the final output end remains consistent, and reduces the additional phase shift generated by the RF signal during gain adjustment. At the same time, the present application also adds a current balancing unit, which can effectively stabilize the input / output RF tube current of the amplifier circuit during gain adjustment to ensure that its working state is not affected. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0049] FIG1 is a structural diagram of a gain adjustable amplifier circuit provided by the present application;

[0050] FIG2 is a complete circuit diagram of a gain adjustable amplifier circuit provided in the present application. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0052] The core of this application is to provide a gain adjustable amplification circuit and an amplifier.

[0053] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0054] FIG1 is a structural diagram of a gain adjustable amplifier circuit provided by the present application, as shown in FIG1 , comprising: a gain adjustment unit 1, a current balancing unit 2, a first-stage signal amplifier circuit 3 and a second-stage signal amplifier circuit 4, wherein the second-stage signal amplifier circuit comprises a plurality of MOS tubes. In addition, FIG1 also comprises a converter 5 and a digital control signal device 6. The connection relationship of the circuit is as follows: the first end of the gain adjustment unit 1 is connected to the gate of the MOS tube on the non-output side of the second-stage signal amplifier circuit 4, the second end of the gain adjustment unit 1 is connected to the drain of the MOS tube on the non-output side, and the third end of the gain adjustment unit 1 is connected to the digital control signal device 6, which is used to obtain the first digital control signal sent by the digital control signal device 6, and to achieve gain adjustment of the amplifier circuit according to the first digital control signal; the first end of the current balancing unit 2 is connected to the output end of the first-stage signal amplifier circuit 3 and the input end of the second-stage signal amplifier circuit 4, the second end of the current balancing unit 2 is connected to the adjustment end of the second-stage signal amplifier circuit 4, and the third end of the current balancing unit 2 is connected to the digital control signal device 6, which is used to obtain the second digital control signal sent by the digital control signal device 6, and to achieve stable current output of the amplifier circuit according to the second digital control signal and the current increased by gain adjustment of the amplifier circuit. In the circuit relationship, the input end of the first-stage signal amplifier circuit 3 is connected to the converter 5 as the input end of the gain adjustable amplifier circuit, and the output end of the second-stage signal amplifier circuit 4 is the output end of the gain adjustable amplifier circuit.

[0055] In a specific embodiment, if the gain adjustment part is set in the first-stage signal amplifier circuit 3 (which can be understood as the signal input circuit), the noise of the signal will be increased while adjusting the gain; if the gain adjustment part is set on the output end side of the second-stage signal amplifier circuit 4 (which can be understood as the output circuit of the signal), different port standing waves will be output while adjusting the gain, and the signal will produce additional phase shift. Therefore, the present application will realize the gain adjustment. The gain adjustment unit 1 is connected in parallel to the drain of the MOS tube on the non-output end side of the second-stage signal amplifier circuit 4, and it mainly increases or decreases the equivalent transistor size of the MOS tube on the non-output end side through the first digital control signal sent by the digital control signal device 6, thereby realizing the gain adjustment of the amplifier circuit. Since the current process of realizing gain adjustment is mainly realized by increasing or decreasing the equivalent transistor size of the MOS tube on the non-output end side of the second signal amplifier circuit 4, and the size of the equivalent transistor size of the MOS tube on the non-output end side will affect the input / output radio frequency tube current in the circuit, it is also necessary to add a current balancing unit 2 that can ensure the stability of the radio frequency tube current in the circuit in the circuit design. The two ends of the current balancing unit 2 are respectively connected to the output end of the first signal amplifying circuit 3 and the regulating end of the second signal amplifying circuit 4, and the current is reduced or increased mainly by the second digital control signal sent by the digital control signal device 6. That is to say, when the gain adjustment unit 1 implements gain adjustment, the increased or decreased current is offset by the reduced or increased current in the current balancing unit 2, thereby stabilizing the input / output radio frequency tube current in the circuit.

[0056] It should be noted that the present application does not limit the specific structures of the gain adjustment unit 1, the current balancing unit 2, the first-stage signal amplifying circuit 3 and the second-stage signal amplifying circuit 4, which can be set according to the needs of the user.

[0057] On the basis of the above embodiment, as a preferred embodiment, the gain adjustment unit 1 includes X gain adjustment circuits with the same structure, where X is an integer greater than 0. The connection relationship of the circuits is as follows: the first ends of the gain adjustment circuits are connected to each other and are commonly connected to the gate of the MOS tube on the non-output side as the first end of the gain adjustment unit 1; the second ends of the gain adjustment circuits are connected to each other and are commonly connected to the drain of the MOS tube on the non-output side as the second end of the gain adjustment unit 1; the third ends of the gain adjustment circuits are connected to each other and are commonly connected to the digital control signal device 6 as the third end of the gain adjustment unit 1. As shown in FIG2 , each gain adjustment circuit includes a first MOS tube M1 (M1_1-M1_X) and a first transmission gate Q1 (Q1_1-Q1_X). The connection relationship of the gain adjustment circuit under this structure is as follows: the gate of the first MOS tube M1 is connected to the gate of the MOS tube M3 (the MOS tube on the non-output side in FIG2 is M3) on the non-output side as the first end of the gain adjustment circuit, the drain of the first MOS tube M1 is connected to the drain of the MOS tube M3 on the non-output side as the second end of the gain adjustment circuit, and the source of the first MOS tube M1 is connected to the first end of the first transmission gate Q1; the second end of the first transmission gate Q1 is grounded, and the third end of the first transmission gate Q1 is connected to the digital control signal device 6 as the third end of the gain adjustment circuit. At the same time, it should be noted that the dotted box in the gain adjustment unit 1 in FIG2 represents the parallel gain adjustment circuit.

[0058] In a specific embodiment, the gain adjustment unit 1 is specifically composed of X gain adjustment circuits with the same structure, wherein the first MOS tube M1 in each gain adjustment circuit is connected in parallel to the drain of the MOS tube M3 on the non-output end side, the source of the first MOS tube M1 is connected in series to the ground through the corresponding transmission gate Q1, and the gate of the first MOS tube M1 is short-circuited with the gate of the MOS tube M3 on the non-output end side, and shares the same bias. The gain adjustment unit 1 realizes the on and off of the first MOS tube M1 (M1_1-M1_X) in each gain adjustment circuit through the first digital control signal (N-bits). For example: taking the opening of the 1-bit (X=1) gain adjustment circuit as an example, N-bits=1-bit=Enable. When the first MOS tube M1_1 in the first gain adjustment circuit is turned on and connected in parallel with the MOS tube M3 on the non-output end side, the equivalent M3 transistor size increases and the gain increases.

[0059] It should be noted that the X gain adjustment circuits in the present application are mainly used to expand the adjustment gain range of the circuit, and the specific values ​​can be set according to the needs of the user.

[0060] It should also be noted that the embodiment provided in this application is only one possible implementation method, but is not limited to only this implementation method and can be set according to the needs of the user.

[0061] The present application provides a specific structure of a gain adjustment unit, under which the gain adjustment can be achieved by adjusting the equivalent transistor size of the MOS tube on the non-output end side, and ensures that when the circuit gain is adjusted, the port standing wave output at the final output end remains consistent, and reduces the additional phase shift generated by the RF signal during gain adjustment.

[0062] On the basis of the above embodiment, as a preferred embodiment, the current balancing unit 2 includes M current balancing circuits with the same structure, where M is an integer greater than 0. The circuit connection relationship of the current balancing unit 2 is as follows: the first ends of the current balancing circuits are connected to each other and are commonly connected to the output end of the first-stage signal amplifying circuit 3 and the input end of the second-stage signal amplifying circuit 4 as the first end of the current balancing unit 2; the second ends of the current balancing circuits are connected to each other and are commonly connected to the adjustment end of the second-stage signal amplifying circuit 4 as the second end of the current balancing unit 2; the third ends of the current balancing circuits are connected to each other and are commonly connected to the digital control signal device 6 as the third end of the current balancing unit 2. As a preferred embodiment, as shown in FIG2 , each current balancing circuit includes: a second MOS tube M2 (M2_1-M2_M), a second transmission gate Q2 (Q2_1-Q2_M) and a radio frequency choke resistor Rchock (Rchock_1-Rchock_M), and the specific connection relationship of the current balancing circuit is: the first end of the radio frequency choke resistor Rchock is connected to the output end of the first-stage signal amplification circuit 3 and the input end of the second-stage signal amplification circuit 4 as the first end of the current balancing circuit; the second end of the radio frequency choke resistor Rchock is connected to the first end of the second transmission gate Q2; the second end of the second transmission gate Q2 is connected to the gate of the second MOS tube M2, and the third end of the second transmission gate Q2 is connected to the digital control signal device 6 as the third end of the current balancing circuit; the source of the second MOS tube M2 is grounded, and the drain of the second MOS tube M2 is connected to the adjustment end of the second-stage signal amplification circuit 4 as the second end of the current balancing circuit. At the same time, it should be noted that the dotted box in the current balancing unit 2 in FIG2 represents the parallel current balancing circuit.

[0063] In a specific embodiment, the current balancing unit 2 is specifically composed of M current balancing circuits with the same structure, and the gate of the second MOS transistor M2 in each current balancing circuit is connected to the gate of the MOS transistor M3 on the non-output side through the corresponding second transmission gate Q2 and the RF choke resistor Rchock (the MOS transistor M3 on the non-output side in the circuit shown in FIG. 2 is also used as the MOS transistor on the input side of the second signal amplifying circuit), so that when the second MOS transistor M2 is turned on, it shares the same bias with the MOS transistor M3 on the non-output side. The current balancing unit 2 is controlled by the second digital control signal ( ) to realize the on and off of the second MOS tube M2 (M2_1-M2_M) in each current balancing circuit. For example: taking the opening of a 1-bit (X=1) gain adjustment circuit as an example, N-bits=1-bit=Enable. The first MOS tube M1_1 in the first gain adjustment circuit is turned on and connected in parallel with the MOS tube M3 on the non-output side, then the equivalent M5 transistor size increases and the gain increases. The conduction of M1_1 will directly lead to an increase in current. The current balancing unit 2 provided in the present application will be due to the second digital control signal ( ) = Disable and turn off the second MOS tube M2_1 in the first current balancing circuit. Since M2_1 and M1_1 have the same size and bias, the current flowing through their drains is the same. Therefore, the increased current of M1_1 and the reduced current of M2_1 offset each other, thereby stabilizing the working state of the circuit and ensuring the consistency of the port standing wave and signal phase consistency while adjusting the amplifier gain. The meaning of the first digital control signal (N-bits) is the same as that of the second digital control signal ( ) have opposite meanings.

[0064] The specific value of M may be the same as or different from that of N. It should be noted that the M current balancing circuits in the present application are mainly used to expand the current adjustment range of the circuit, and the specific value may be set according to the needs of the user.

[0065] It should also be noted that the embodiment provided in this application is only one possible implementation method, but is not limited to only this implementation method and can be set according to the needs of the user.

[0066] The present application provides a specific structure of a current balancing unit, under which the input / output radio frequency tube current of the amplifier circuit can be effectively stabilized when the gain is adjusted, ensuring that its working state is not affected.

[0067] Based on the above embodiments, as a preferred embodiment, as shown in FIG2 , the first-stage signal amplifying circuit 3 includes: a first amplifier U1 , a second amplifier U2 , a first transformer T1 , a first decoupling capacitor Decap1 and a second decoupling capacitor Decap2 . The connection relationship of the circuit is as follows: the input end of the first amplifier U1 is connected to the converter 5 as the input end of the first-stage signal amplification circuit 3, the first pin end of the first amplifier U1 is grounded, and the output end of the first amplifier U1 is connected to the first end of the first transformer T1; the second end of the first transformer T1 is connected to the first pin end of the second amplifier U2, the third end of the first transformer T1 is connected to the first voltage end VB1, and the fourth end of the first transformer T1 is connected to the input end of the second amplifier U2; the second pin end of the second amplifier U2 is connected to the second voltage end VB2, and the output end of the second amplifier U2 is connected to the input end of the second-stage signal amplification circuit 4 as the output end of the first-stage signal amplification circuit 3; the first end of the first decoupling capacitor Decap1 is connected to the third end of the first transformer T1 and the first voltage end VB1; the second end of the first decoupling capacitor Decap1 is grounded; the first end of the second decoupling capacitor Decap2 is connected to the second end of the first transformer T1 and the first pin end of the second amplifier U2; the second end of the second decoupling capacitor Decap2 is grounded.

[0068] And based on Figure 2, it can be seen that the second-stage signal amplification circuit 4 includes: a third MOS tube M3 (the MOS tube on the non-output end side in the previous text), a fourth MOS tube M4, a fifth MOS tube M5, a first asymmetric five-port transformer T2, a second transformer T3, a third decoupling capacitor Decap3, a fourth decoupling capacitor Decap4, a fifth decoupling capacitor Decap5, a sixth decoupling capacitor Decap6, and a first matching capacitor C1. The connection relationship of the circuit is as follows: the gate of the third MOS tube M3 is connected to the output end of the first stage signal amplification circuit 3 and the first end of the gain adjustment unit 1 as the input end of the second stage signal amplification circuit 4, the source of the third MOS tube M3 is grounded, the drain of the third MOS tube M6 is connected to the first end of the first asymmetric five-port transformer T2 and the second end of the gain adjustment unit 1; the second end of the first asymmetric five-port transformer T2 is connected to the third voltage end VB3; the third end of the first asymmetric five-port transformer T2 is connected to the source of the fourth MOS tube M4, and they are connected to the second end of the current balance unit 2 as the adjustment end of the second stage signal amplification circuit 4; the fourth end of the first asymmetric five-port transformer T2 is connected to the gate of the fourth MOS tube M4; the drain of the fourth MOS tube M4 is connected to the source of the fifth MOS tube M5; the gate of the fifth MOS tube M5 is connected to the fourth voltage end VB4, and the drain of the fifth MOS tube M5 is connected to the first end of the second transformer T3; the third end of the second transformer T3 is connected to the second voltage end VB2; the second end of the second transformer T3 and the fourth end of the second transformer T3 are jointly used as the output end (RFOUTP and RFOUTN) of the second-stage signal amplifying circuit 4; the first end of the third decoupling capacitor Decap3 is connected to the fifth end of the first asymmetric five-port transformer T2, and the second end of the third decoupling capacitor Decap3 is grounded; the first end of the fourth decoupling capacitor Decap4 is connected to the second end of the first asymmetric five-port transformer T2 and the third voltage end VB3, and the second end of the fourth decoupling capacitor Decap4 is grounded; the first end of the fifth decoupling capacitor Decap5 is connected to the gate of the fifth MOS tube M5 and the fourth voltage end VB4, and the second end of the fifth decoupling capacitor Decap5 is grounded; the first end of the sixth decoupling capacitor Decap6 is connected to the third end of the second transformer T3 and the second voltage end VB2, and the second end of the sixth decoupling capacitor Decap6 is grounded; the first end of the first matching capacitor C1 is connected to the second end of the second transformer T3, and the second end of the first matching capacitor C1 is grounded.

[0069] In a specific embodiment, as shown in FIG2 , the first-stage signal amplification circuit 3 is composed of a first amplifier U1, a second amplifier U2, a first transformer T1, and peripheral passive matching components to form a current multiplexing structure. The signal output by the first amplifier U1 is coupled to the input of the second amplifier U2 through the first transformer T1, and the current multiplexing of the first amplifier U1 and the second amplifier U2 is realized through the main coil of the first transformer T1. This circuit can effectively reduce power consumption and increase gain, and has a better suppression effect on the noise of the subsequent circuit.

[0070] In the second signal amplification circuit 4, the second-stage signal amplification circuit 4 is composed of a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5 and peripheral passive matching elements to form a current multiplexing structure. At the same time, in the second-stage signal amplification circuit 4, the fourth MOS tube M4 and the fifth MOS tube M5 also form a Cascode stacking structure, which increases the linearity and isolation of the overall circuit. In the second signal amplification circuit 4, the first asymmetric five-port transformer T1 can mainly achieve impedance matching of the third MOS tube M3 and the fourth MOS tube M4 by adjusting parameters; the second transformer T3 is used to convert the single-ended signal into a differential signal while completing impedance matching. The first matching capacitor C1 in the second signal amplification circuit 4 is used to adjust the resonance point of the second transformer T4.

[0071] Among them, since the first-stage signal amplification circuit 3 and the second signal amplification circuit 4 are both current multiplexing structures, and the circuits of the current multiplexing structure often have an instability tendency, the cascade of multiple current multiplexing structures will increase this instability. Therefore, the second signal amplification circuit 4 provided in the present application adopts an asymmetric five-port transformer technology, and the stability problem of the current multiplexing structure is effectively solved by implicitly introducing a negative feedback inductor at the current multiplexing node (the source of the fourth MOS tube M4 in Figure 2). Specifically, the traditional transformer coil is divided into two sections by using a decoupling capacitor, the inductance close to the multiplexing node is very small, and the coupling coefficient provided for the transformer is also very small, which does not affect the operation of the transformer main coil, and saves the area of ​​a stability inductor, and the circuit structure is compact. The introduction of this inductor can effectively increase the real part of the input end of the current multiplexing structure (the gate of the fourth MOS tube M4), reducing the risk of circuit oscillation. Using this technology, the present application realizes the continuous multi-stage application of the current multiplexing structure, effectively improves the circuit gain and reduces the number of cascaded stages of the amplifier circuit, which is conducive to controlling the circuit power consumption and compressing the chip size.

[0072] It can be seen that, based on the traditional current steering, the present application connects a gain adjustment unit in parallel in the MOS tube at the non-output end, which ensures that when the circuit gain is adjusted, the port standing wave output at the final output end remains consistent, and reduces the additional phase shift generated by the RF signal during gain adjustment. At the same time, the present application also adds a current balancing unit, which can effectively stabilize the input / output RF tube current of the amplifier circuit during gain adjustment to ensure that its working state is not affected. And the present application realizes the continuous multi-stage application of the current multiplexing structure, effectively improves the circuit gain and reduces the number of cascade stages of the amplifier circuit, which is beneficial to control circuit power consumption and compress chip size.

[0073] On the other hand, the present application also provides an amplifier, including the above-mentioned gain adjustable amplifier circuit, and having the same beneficial effects. Since the embodiment of the amplifier provided in the present application is the same as the embodiment of the above-mentioned gain adjustable amplifier circuit, the present application will not elaborate on it here.

[0074] The above is a detailed introduction to a gain adjustable amplifier circuit and amplifier provided by the present application. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can refer to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

[0075] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. A gain adjustable amplifier circuit, characterized in that: include: A gain adjustment unit, a current balancing unit, a first-stage signal amplification circuit and a second-stage signal amplification circuit, wherein the second-stage signal amplification circuit includes a plurality of MOS tubes; The first end of the gain adjustment unit is connected to the gate of the MOS tube on the non-output end side in the second-stage signal amplifying circuit, the second end of the gain adjustment unit is connected to the drain of the MOS tube on the non-output end side, and the third end of the gain adjustment unit is connected to the digital control signal device, and is used to obtain the first digital control signal sent by the digital control signal device, and implement the gain adjustment of the amplifying circuit according to the first digital control signal; The first end of the current balancing unit is connected to the output end of the first-stage signal amplifying circuit and the input end of the second-stage signal amplifying circuit, the second end of the current balancing unit is connected to the adjustment end of the second-stage signal amplifying circuit, and the third end of the current balancing unit is connected to the digital control signal device, for obtaining the second digital control signal sent by the digital control signal device, and realizing stable current output of the amplifying circuit by increasing the current through gain adjustment according to the second digital control signal and the amplifying circuit.

2. The gain adjustable amplifier circuit according to claim 1, characterized in that: The gain adjustment unit includes X gain adjustment circuits with the same structure, where X is an integer greater than zero; The first ends of the gain adjustment circuits are connected to each other and are commonly connected to the gate of the MOS tube on the non-output end side as the first end of the gain adjustment unit; The second ends of the gain adjustment circuits are connected to each other and serve as the second end of the gain adjustment unit and are connected to the drain of the MOS tube on the non-output end side; The third ends of the gain adjustment circuits are connected to each other and are commonly connected to the digital control signal device as the third end of the gain adjustment unit.

3. The gain adjustable amplifier circuit according to claim 2, characterized in that: The gain adjustment circuit includes a first MOS tube and a first transmission gate; The gate of the first MOS transistor is connected to the gate of the MOS transistor on the non-output end side as the first end of the gain adjustment circuit, the drain of the first MOS transistor is connected to the drain of the MOS transistor on the non-output end side as the second end of the gain adjustment circuit, and the source of the first MOS transistor is connected to the first end of the first transmission gate; The second end of the first transmission gate is grounded, and the third end of the first transmission gate is connected to the digital control signal device as the third end of the gain adjustment circuit.

4. The gain adjustable amplifier circuit according to claim 1, characterized in that: The current balancing unit includes M current balancing circuits with the same structure, where M is an integer greater than zero; The first ends of the current balancing circuits are connected to each other and serve as the first end of the current balancing unit, connected to the output end of the first-stage signal amplifying circuit and the input end of the second-stage signal amplifying circuit; The second ends of the current balancing circuits are connected to each other and are commonly connected to the regulating end of the second-stage signal amplifying circuit as the second end of the current balancing unit; The third ends of the current balancing circuits are connected to each other and serve as the third end of the current balancing unit connected to the digital control signal device.

5. The gain adjustable amplifier circuit according to claim 4, characterized in that: The current balancing circuit comprises: a second MOS tube, a second transmission gate and a radio frequency choke resistor; Wherein, the first end of the RF choke resistor is connected to the output end of the first-stage signal amplification circuit and the input end of the second-stage signal amplification circuit as the first end of the current balancing circuit; the second end of the RF choke resistor is connected to the first end of the second transmission gate; The second end of the second transmission gate is connected to the gate of the second MOS tube, and the third end of the second transmission gate is connected to the digital control signal device as the third end of the current balancing circuit; The source of the second MOS tube is grounded, and the drain of the second MOS tube is connected to the regulating end of the second-stage signal amplifying circuit as the second end of the current balancing circuit.

6. The gain adjustable amplifier circuit according to claim 1, characterized in that: The first-stage signal amplification circuit includes: a first amplifier, a second amplifier and a first transformer; The input end of the first amplifier is connected to the converter as the input end of the first stage signal amplification circuit, the first pin end of the first amplifier is grounded, and the output end of the first amplifier is connected to the first end of the first transformer; The second end of the first transformer is connected to the first pin end of the second amplifier, the third end of the first transformer is connected to the first voltage end, and the fourth end of the first transformer is connected to the input end of the second amplifier; The second pin end of the second amplifier is connected to the second voltage end, and the output end of the second amplifier is connected to the input end of the second stage signal amplification circuit as the output end of the first stage signal amplification circuit.

7. The gain adjustable amplifier circuit according to claim 6, characterized in that: The first-stage signal amplifying circuit further includes: a first decoupling capacitor and a second decoupling capacitor; Wherein, the first end of the first decoupling capacitor is connected to the third end of the first transformer and the first voltage end; The second end of the first decoupling capacitor is grounded; A first end of the second decoupling capacitor is connected to a second end of the first transformer and a first pin end of the second amplifier; A second terminal of the second decoupling capacitor is grounded.

8. The gain adjustable amplifier circuit according to any one of claims 1 to 7, characterized in that: The second-stage signal amplification circuit includes: a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a first asymmetric five-port transformer and a second transformer; The gate of the third MOS transistor is connected to the output end of the first-stage signal amplifying circuit and the first end of the gain adjusting unit as the input end of the second-stage signal amplifying circuit, the source of the third MOS transistor is grounded, and the drain of the third MOS transistor is connected to the first end of the first asymmetric five-port transformer and the second end of the gain adjusting unit; The second end of the first asymmetric five-port transformer is connected to the third voltage end; the third end of the first asymmetric five-port transformer is connected to the source of the fourth MOS tube, and both are connected to the second end of the current balancing unit as the regulating end of the second-stage signal amplification circuit; the fourth end of the first asymmetric five-port transformer is connected to the gate of the fourth MOS tube; The drain of the fourth MOS tube is connected to the source of the fifth MOS tube; The gate of the fifth MOS transistor is connected to the fourth voltage terminal, and the drain of the fifth MOS transistor is connected to the first terminal of the second transformer; The third terminal of the second transformer is connected to the second voltage terminal; The second end of the second transformer and the fourth end of the second transformer serve together as an output end of the second-stage signal amplifying circuit.

9. The gain adjustable amplifier circuit according to claim 8, characterized in that: The second-stage signal amplifying circuit further includes: a third decoupling capacitor, a fourth decoupling capacitor, a fifth decoupling capacitor, a sixth decoupling capacitor, and a first matching capacitor; Wherein, the first end of the third decoupling capacitor is connected to the fifth end of the first asymmetric five-port transformer, and the second end of the third decoupling capacitor is grounded; The first end of the fourth decoupling capacitor is connected to the second end of the first asymmetric five-port transformer and the third voltage end, and the second end of the fourth decoupling capacitor is grounded; The first end of the fifth decoupling capacitor is connected to the gate of the fifth MOS tube and the fourth voltage end, and the second end of the fifth decoupling capacitor is grounded; A first end of the sixth decoupling capacitor is connected to the third end of the second transformer and the second voltage end, and a second end of the sixth decoupling capacitor is grounded; The first end of the first matching capacitor is connected to the second end of the second transformer, and the second end of the first matching capacitor is connected to the fourth end of the second transformer.

10. An amplifier, characterized in that: The invention comprises the gain adjustable amplifier circuit as described in any one of claims 1 to 9.

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