Method and apparatus for controlling second harmonics of power amplifier over wide frequency range

Abstract

The disclosure relates to a method and apparatus for controlling second harmonics of a power amplifier over a wide frequency range. A power amplifier is provided. The power amplifier includes a first circuit including a first transistor and a second transistor coupled to a third transistor and a fourth transistor, respectively. The power amplifier also includes a second circuit including a transformer having a first winding and a second winding. The first winding includes a first terminal coupled to the third transistor and a second terminal coupled to the fourth transistor to receive a differential voltage signal with gain from the first circuit. The second winding includes a first terminal that is grounded and a second terminal that serves as an output terminal. The power amplifier circuit further includes a third circuit including a programmable capacitor from a midpoint of the first winding to a common node coupled to ground. The programmable capacitor is tunable to reduce second harmonics seen at the output terminal.

Description

Technical Field

[0001] The present technology relates to electronic circuits and operating methods. Background Art

[0002] A broadband power amplifier is a general electronic device that amplifies signals across a wide frequency range. It has applications in a variety of fields because it can deliver high power and maintain consistent amplification across a wide frequency spectrum. Broadband power amplifiers are used in telecommunication systems such as cellular networks, where they are used to amplify signals in the RF (radio frequency) range, ensuring efficient transmission and reception of signals across multiple frequency bands, and enabling reliable communication in a wide coverage area. In wireless communication systems such as Wi-Fi networks, Bluetooth devices, or satellite communication systems, broadband power amplifiers are used to amplify signals in the required frequency range to achieve long-distance communication, improve signal quality, and ensure reliable data transmission across various wireless protocols.

[0003] In many applications using broadband power amplifiers (such as RF power amplifiers, driver amplifiers, and low noise amplifiers), harmonic control may be required to minimize the presence of second harmonics to maintain signal integrity, improve linearity, and prevent distortion over the entire operating frequency range. The present application provides a simple but effective method and apparatus for controlling the second harmonic of a power amplifier over a wide frequency range. Summary of the invention

[0004] In one aspect, the present disclosure provides an apparatus comprising: a first circuit comprising a first transistor and a second transistor coupled to a third transistor and a fourth transistor, respectively, the first transistor comprising a first gate configured to receive a first voltage input, the second transistor comprising a second gate configured to receive a second voltage input, the third transistor comprising a source coupled to a drain of the first transistor, and the fourth transistor comprising a source coupled to the drain of the second transistor; a second circuit comprising a transformer having a first winding and a second winding, the first winding comprising a first terminal coupled to the drain of the third transistor and a second terminal coupled to the drain of the fourth transistor, the first winding being configured to draw a current associated with a differential voltage signal based on the first voltage input and the second voltage input, the second winding comprising a third terminal grounded via a sixth resistor and a fourth terminal serving as an output terminal; and a third circuit comprising a first resistor, a second common node, a second resistor, a programmable capacitor, a third resistor, a first common node, and a fourth resistor coupled in series to a ground terminal in sequence from a midpoint of the first winding.

[0005] On the other hand, the present disclosure provides an apparatus comprising: a first pair of transistors configured to receive a first voltage input and a second voltage input at their gate terminals, respectively; a second pair of transistors comprising respective sources coupled to respective drains of the first pair of transistors, the second pair of transistors configured to provide a differential voltage signal based on the first voltage input and the second voltage input; a transformer comprising a primary winding and a secondary winding, the primary winding coupled to the respective drains of the second pair of transistors to receive a current signal associated with the differential voltage signal, the primary winding comprising a midpoint that divides the primary winding into two sections with equal resistance, the secondary winding coupled between a ground terminal and an output terminal; and at least one programmable capacitor coupled between the midpoint of the primary winding and a first common node coupled to the first pair of transistors.

[0006] On the other hand, the present disclosure provides a method for suppressing second harmonics in a broadband power amplifier, the method comprising: configuring a first pair of transistors so that the corresponding two gates receive a first voltage input and a second voltage input, respectively; configuring a second pair of transistors to provide a differential voltage signal based on the first voltage input and the second voltage input; providing a transformer including a first winding and a second winding, the first winding including a midpoint that divides the first winding into two sections with equal resistance; coupling the first winding between the corresponding drains of the second pair of transistors to receive a current signal associated with the differential voltage signal; coupling the second winding between a ground terminal and an output terminal; coupling at least one programmable capacitor between the midpoint of the first winding and a first common node coupled to the corresponding sources of the first pair of transistors, the programmable capacitor being configured to allow capacitance adjustment from 0.1 pF to 10 μF; coupling a power supply to a second common node of a center tap line, the second common node being connected to the midpoint of the first winding via a first resistor and to the programmable capacitor via a second resistor; and coupling the first common node to the programmable capacitor via a third resistor and to ground via a fourth resistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] A further understanding of the nature and advantages of particular embodiments may be achieved by reference to the remainder of the specification and drawings, wherein the same reference numerals are used to refer to similar components. In some instances, a sub-label is associated with a reference numeral to represent one of multiple similar components. When a reference numeral is cited without specifying an existing sub-label, it is intended to refer to all such multiple similar components.

[0008] Figure 1 is a circuit diagram of a power amplifier according to an embodiment of the present technology.

[0009] Figure 2is a graph of second harmonic signal power level versus decoupling capacitor capacitance based on an output signal power of 20 dBm in accordance with an embodiment of the present technology.

[0010] Figure 3 is a flow chart illustrating a method for controlling second harmonics in a broadband power amplifier according to an embodiment of the present technology. DETAILED DESCRIPTION

[0011] The present invention relates to electronic circuits and methods of operation. Specifically, it presents a power amplifier circuit having a programmable decoupling capacitor to tune the center tap impedance and influence the power amplifier common mode behavior and efficiency. The optimized center tap impedance results in control of the second harmonic signal for each operating frequency of the power amplifier over a wide range. Other embodiments exist.

[0012] In the following description, for purposes of explanation, numerous details are set forth to provide a thorough understanding of the described embodiments. However, it will be apparent to those skilled in the art that other embodiments may be practiced without some of these details. Several embodiments are described herein, and although various features are attributed to different embodiments, it should be understood that features described with respect to one embodiment may also be combined with other embodiments. However, by the same token, a single feature or multiple features of any described embodiment should not be considered essential to every embodiment of the present invention, as other embodiments of the present invention may omit such features.

[0013] In the following detailed description, a number of specific details are set forth in order to provide a more thorough understanding of the present technology. However, it will be appreciated by those skilled in the art that the present technology may be practiced without being limited to these specific details. In other examples, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the present technology.

[0014] The reader should pay attention to all papers and documents that are filed at the same time as this specification and are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. Unless otherwise expressly stated, all features disclosed in this specification (including any attached claims, abstracts and drawings) can be replaced by alternative features for the same, equivalent or similar purposes. Therefore, unless otherwise expressly stated, each feature disclosed is only an example of a general series of equivalent or similar features.

[0015] Furthermore, any element in the claims that does not explicitly recite a “means” for performing a specified function or a “step” for performing a specific function should not be construed as a “means” or “step” clause as specified in 35 U.S.C. § 112, paragraph 6. Specifically, the use of “the step of” or “the action of” in the claims herein is not intended to invoke the provisions of 35 U.S.C. § 112, paragraph 6.

[0016] When an element is referred to herein as being "connected" or "coupled" to another element, it is understood that the element may be directly connected to the other element or have an intervening element present between the elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, it is understood that there are no intervening elements in the "direct" connection between the elements. However, the presence of a direct connection does not exclude other connections in which intervening elements may be present.

[0017] When an element is referred to herein as being "disposed" in some manner relative to another element (e.g., disposed on, disposed between, disposed below, disposed adjacent to, or disposed in some other relative manner), it is understood that the element may be disposed directly relative to the other element (e.g., disposed directly on the other element) or have intervening elements present between the elements. Conversely, when an element is referred to as being "directly disposed" relative to another element, it is understood that in the "direct" instance there are no intervening elements. However, the presence of a direct disposition does not exclude other instances in which intervening elements may be present.

[0018] Similarly, when an element is referred to herein as being "joined" to another element, it is understood that the element may be joined directly to the other element (without any intervening elements) or with an intervening element present between the joined elements. Conversely, when an element is referred to as being "directly joined" to another element, it is understood that there are no intervening elements in the "direct" joining between the elements. However, the presence of direct joining does not exclude other forms of joining in which intervening elements may be present.

[0019] Likewise, when an element is referred to herein as an "electronic circuit" or simply a "circuit," it is generally recognized as the building block of modern electronics. Circuits are made up of various electronic components, such as resistors, capacitors, inductors, diodes, transistors, and integrated circuits. These components are carefully selected and interconnected to create circuits that can perform specific tasks or perform specific functions. Circuits can be as simple as a basic switch that turns a light on and off, or they can be very complex, such as those found in advanced computer systems, communication devices, or medical equipment. They can be classified into different types based on their use, including amplifiers, oscillators, filters, power supplies, and logic gates, among others.

[0020] In addition, the terms left, right, front, back, top, bottom, forward, backward, clockwise and counterclockwise are used only for explanation purposes and are not limited to any fixed direction or orientation. Instead, they are only used to indicate the relative position and / or direction between the various parts of an object and / or component.

[0021] In addition, for ease of description, the methods and processes described herein may be described in a particular order. However, it should be understood that unless the context otherwise indicates, the intermediary processes may occur before and / or after any portion of the described processes, and that various other processes may be reordered, added, and / or omitted according to various embodiments.

[0022] Unless otherwise indicated, all numbers used herein to indicate quantities, dimensions, and the like are to be understood as being modified by the term "about" in all instances. In this application, unless otherwise specifically indicated, the use of the singular includes the plural, and the use of the terms "and" and "or" means "and / or" unless otherwise indicated. In addition, the use of the terms "comprising" and "having", as well as other forms such as "includes," "included," "has," "have," and "had," are to be considered non-exclusive. In addition, terms such as "element" or "component" encompass both elements and components comprising one unit and elements and components comprising more than one unit, unless otherwise specifically indicated.

[0023] As used herein, the phrase "at least one" preceding a series of items separated by the terms "and" or "or" modifies the entire list, rather than each member of the list (i.e., each item). The phrase "at least one" does not require selection of at least one of each item listed; rather, the phrase allows for a meaning that includes at least one of any one item and / or at least one of any combination of items. For example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; and / or any combination of A, B, and C. In examples where selection of "at least one of each of A, B, and C," or alternatively, "at least one of A, at least one of B, and at least one of C," is intended, it is explicitly described as such.

[0024] A general aspect includes an apparatus configured as a broadband power amplifier. The apparatus includes: a first circuit including a first transistor and a second transistor coupled to a third transistor and a fourth transistor, respectively, the first transistor including a first gate configured to receive a first voltage input, the second transistor including a second gate configured to receive a second voltage input, the third transistor including a source coupled to the drain of the first transistor, and the fourth transistor including a source coupled to the drain of the second transistor. The apparatus also includes: a second circuit including a transformer having a first winding and a second winding, the first winding including a first terminal coupled to the drain of the third transistor and a second terminal coupled to the drain of the fourth transistor, the first winding being configured to draw a current associated with a differential voltage signal based on the first voltage input and the second voltage input, the second winding including a third terminal connected to ground via a sixth resistor and a fourth terminal used as an output terminal for outputting a single-ended voltage signal. The apparatus also includes: a third circuit including a first resistor, a second common node, a second resistor, a programmable capacitor, a third resistor, a first common node, and a fourth resistor coupled in series to a ground terminal in sequence from a midpoint of the first winding.

[0025] Implementations may include one or more of the following features. The apparatus may include a fourth circuit including a fifth resistor having a first terminal coupled to a DC voltage VDD and a second terminal coupled to the second common node, the second common node being connected to both the first resistor and the second resistor. The programmable capacitor may include a switched capacitor array. The programmable capacitor may include a digitally controlled capacitor. The programmable capacitor may include a MEMS-based capacitor. The programmable capacitor may include a capacitance that can be adjusted by a controller in a range from 0.1 pF to 10 μF based on the frequency of the differential voltage signal in a range from 1 MHz to 19 GHz to reduce the second harmonic signal at the output terminal by at least 10 dBm. The first voltage input may include a first voltage signal at a frequency selected from 1 MHz to 19 GHz, and the second voltage input may include a second voltage signal having the same value but opposite polarity as the first voltage signal at the same frequency. The third transistor and the fourth transistor may include a common gate terminal connected to ground. The first transistor may include a source coupled to a seventh resistor, the seventh resistor coupled to the first common node. The second transistor may include a source coupled to an eighth resistor, the eighth resistor coupled to the first common node.

[0026] Another general aspect includes an apparatus for suppressing second harmonics in a broadband power amplifier. The apparatus also includes: a first pair of transistors configured to receive a first voltage input and a second voltage input at their gate terminals, respectively. The apparatus may include: a second pair of transistors including respective sources coupled to respective drains of the first pair of transistors, the second pair of transistors configured to provide a differential voltage signal based on the first voltage input and the second voltage input. The apparatus also includes: a transformer including a primary winding and a secondary winding, the primary winding coupled to the respective drains of the second pair of transistors to receive a current signal associated with the differential voltage signal, the primary winding including a midpoint that divides the primary winding into two sections of equal resistance, the secondary winding coupled between a ground terminal and an output terminal. The apparatus also includes: at least one programmable capacitor coupled between the midpoint of the primary winding and a first common node coupled to the first pair of transistors.

[0027] Implementations may include one or more of the following features. The apparatus may include: a first resistor coupled between the midpoint of the primary winding to a second common node; a second resistor coupled between the second common node and the programmable capacitor; a third resistor coupled between the programmable capacitor and the first common node; a fourth resistor coupled between the first common node and ground. The apparatus further includes a fifth resistor coupled between a DC voltage VDD and the second common node. The apparatus also includes: a sixth resistor coupled between the secondary winding and ground; a seventh resistor coupled between the drain of the first of the first pair of transistors and the first common node; and an eighth resistor coupled between the drain of the second of the first pair of transistors and the first common node. The differential voltage signal may include a frequency in the range from 1 MHz to 19 GHz. The programmable capacitor includes a switched capacitor array. The programmable capacitor includes a MEMS-based capacitor. The differential voltage signal includes a frequency range from 1 MHz to 19 GHz. The programmable capacitor includes a capacitance that is adjustable in a range from 0.1 pF to 10 μF to reduce a second harmonic signal at the output terminal by at least 10 dBm.

[0028] Another general aspect includes a method for reducing second harmonic interference to the output of a broadband power amplifier. The method includes configuring a first pair of transistors so that the respective two gates receive a first voltage input and a second voltage input, respectively. The method also includes configuring a second pair of transistors to provide a differential voltage signal based on the first voltage input and the second voltage input. The method includes providing a transformer including a first winding and a second winding, the first winding including a midpoint that divides the first winding into two sections with equal resistance. The method further includes coupling the first winding between the respective drains of the second pair of transistors to receive a current signal associated with the differential voltage signal. The method further includes coupling the second winding between a ground terminal and an output terminal. The method includes coupling at least one programmable capacitor between the midpoint of the first winding and a first common node coupled to the respective sources of the first pair of transistors, the programmable capacitor being configured to allow capacitance adjustment from 0.1 pF to 10 μF. In addition, the method includes coupling a power supply to a second common node of a center tap line, the second common node being connected to the midpoint of the first winding via a first resistor and to the programmable capacitor via a second resistor. In addition, the method includes coupling the first common node to the programmable capacitor via a third resistor and to ground via a fourth resistor. The method also includes using a controller to adjust the capacitance of the programmable capacitor to reduce a second harmonic signal at the output terminal for each frequency of the differential voltage signal.

[0029] Figure 1 is a circuit diagram of a power amplifier according to an embodiment of the present technology. This diagram is only an example, which should not overly limit the scope of the claims. A person skilled in the art will recognize many variations, alternatives and modifications. In an embodiment, the power amplifier circuit includes a first circuit, which includes at least a first transistor 111 and a second transistor 112 for receiving a first voltage input In+ and a second voltage input In- at its gate terminal, respectively. The source terminal of the first transistor 111 is coupled to a first common node 131 via a resistor 127. The source terminal of the second transistor 112 is coupled to the first common node 131 via another resistor 128. Optionally, the first voltage input In+ is a voltage signal having a voltage value V at a frequency in a wide range from 1MHz to 19GHz. Optionally, the second voltage input In- is a voltage signal having the same value as the first voltage input but with an opposite polarity (i.e., -V) at the same frequency. In another embodiment, the differential voltage signal (In+-In-) is received by the gate terminals of the first and second transistors. The first common node 131 is grounded via a resistor 124.

[0030] refer to Figure 1, the first circuit further includes a third transistor 113 and a fourth transistor 114 configured to provide a gain of the differential voltage signal (In+-In-). The third transistor 113 and the fourth transistor 114 have a common gate terminal connected to ground. The third transistor 113 has its source terminal coupled to the drain terminal of the first transistor 111. The fourth transistor 114 also has its source terminal coupled to the drain terminal of the second transistor 112, forming a pair of push-pull structures in a complementary manner to amplify the differential voltage signal. The transistor 113 amplifies the positive half of the input signal, while the transistor 114 amplifies the negative half. In an embodiment, the first circuit is a gain circuit configured to provide a differential voltage signal with a gain.

[0031] In addition, the power amplifier circuit includes a second circuit, which includes at least one transformer having a first winding 141 and a second winding 142. The first winding 141 has its two terminals coupled to the drain terminals of the third transistor 113 and the fourth transistor 114, respectively, to draw a current signal associated with the gain of the differential voltage signal across the two terminals of the first winding 141. The first winding is a primary winding of the transformer. The second winding 142 has one terminal grounded via a resistor 126 and the other terminal used as an output terminal 150. The second winding is a secondary winding of the transformer. In an embodiment, the second circuit is an output circuit, which is configured to receive a differential voltage signal with a gain at the two terminals of the first winding and output a single-ended voltage signal at the output terminal of the second winding.

[0032] Reference again Figure 1, the power amplifier circuit includes a third circuit, the third circuit including at least one programmable capacitor 101 coupled to a number of resistors in a series connection. In an embodiment, the series connection of the third circuit begins with a first resistor 121, which has one terminal coupled to the midpoint 140 of the first winding 141 and another terminal coupled to the second common node 132. The series connection is followed by a second resistor 122, which has one terminal coupled to the second common node 132 and another terminal coupled to the programmable capacitor 101. In addition, the programmable capacitor 101 is coupled to a third resistor 123, which is then connected to the first common node 131. The center tap is connected to the midpoint 140 of the first winding 141, and the two amplified signals are combined at the midpoint 140. In addition, a fourth circuit is included by coupling the second common node 132 to the power supply VDD via a resistor 125. The third resistor 123 is used as a reference point for the output signal, ensuring that the positive and negative halves of the amplified waveform are balanced and properly aligned. It helps to eliminate even harmonics and reduce distortion in the output signal. By coupling the power supply VDD to the center tap, the second circuit can effectively utilize the entire power supply voltage, allowing improved efficiency and power handling capabilities. In addition, especially for broadband power amplifiers, it helps to achieve a balanced output signal with reduced distortion caused by the common mode signal and the second harmonic seen at the output terminal 150. The second harmonic signal is essentially a frequency component of twice the frequency of the amplified fundamental signal. It is usually a byproduct of the nonlinearity of the amplifier, caused by components such as transistors, diodes, or even by passive intermodulation in connectors and transmission lines. The second harmonic signal can distort the desired output and reduce the fidelity of the amplifier. In communications, this can mean an increase in bit error rate or a decrease in data throughput. In frequency-sensitive applications such as RF communications, the second harmonic can occupy additional bandwidth, potentially causing interference to other channels or services, causing power waste, and reducing the overall efficiency of the amplifier. Therefore, reducing or suppressing the second harmonic signal at the output of a broadband power amplifier is one of the solutions provided by the present technology in the present disclosure.

[0033] The midpoint of the primary winding on the transformer can usually be found during the construction of the transformer. It will involve winding half of the total number of turns of the coil, then marking or connecting to that point, and then winding the remaining number of turns. This is called a center-tapped transformer. The midpoint simply divides the primary winding into two sections with equal resistance. If the transformer has been made, then in order to find the midpoint of the primary winding, at least one technique involved may include applying a known voltage across the entire primary winding, then measuring the voltage at various points along the winding until a point is found where the voltage is half of the total voltage. Optionally, for a transformer without a center tap, an alternative way to achieve a similar result is to use two identical transformers and connect them in series, taking the midpoint between the two transformers. In the context of broadband power amplifiers, the term "center tap impedance" generally refers to the impedance seen at the center tap of a transformer or inductor (i.e., the impedance at the midpoint of the primary winding), which is typically used in the output stage of such amplifiers. The center tap configuration is typically used for purposes such as phase separation or providing a DC return path.

[0034] The operating frequency range of a broadband power amplifier may vary depending on its design, specifications, and intended applications, which may cause changes in the center tap impedance. Or from another perspective, changing the center impedance will affect the performance of the broadband power amplifier in many ways. Typical broadband power amplifiers are designed to cover a wide frequency range, typically spanning from a few megahertz (MHz) to several gigahertz (GHz). In many cases, broadband power amplifiers are used in applications such as wireless communications, radar systems, test and measurement equipment, and broadband signal amplification. These applications require amplifying signals across a wide spectrum. For example, broadband power amplifiers used in wireless communications can operate in the range of 100MHz to 3GHz, covering popular frequency bands for cellular networks, Wi-Fi, Bluetooth, and other wireless communication standards. In other cases, broadband power amplifiers designed for microwave applications (such as radar systems or satellite communications) can operate in the frequency range of 1GHz to 19GHz or even higher. In an embodiment, controlling the center tap impedance can effectively affect the common mode behavior of the power amplifier over a wide frequency range. The center tap impedance should be properly matched to the source or load impedance to ensure efficient power transfer and minimize signal reflections. For the power amplifier circuit in the present disclosure, the center tap impedance can be controlled and adjusted by tuning the capacitance of the programmable capacitor. The optimized center tap impedance can reduce or minimize the second harmonic at any operating frequency of the power amplifier. The center tap impedance can also affect the common mode impedance seen by the common mode signal, potentially reducing the common mode rejection performance.

[0035] In some embodiments, the programmable capacitor 101 is provided as a capacitor or a capacitor array, wherein its capacitance can be adjusted externally. For example, the programmable capacitor 101 is provided as a switched capacitor array. The switched capacitor array generally includes a capacitor array that is coupled in parallel and is controlled by a switch array using a clock signal or control logic provided from a controller to connect or disconnect the capacitor to tune the capacitance. The capacitance range of the switched capacitor array is determined by the number and value of the individual capacitors in the array. Depending on the design and configuration of the array, the capacitance range can vary from a few picofarads to hundreds or thousands of picofarads. In another example, the programmable capacitor 101 is provided as a digitally controlled capacitor. The digitally controlled capacitor generally provides discrete steps of capacitance adjustment. The range of achievable capacitance values ​​depends on the number and value of the individual capacitors in the structure. Depending on the specific design and implementation, the capacitance range can vary from a few picofarads to microfarads or higher. In another example, the programmable capacitor 101 can be provided as a MEMS-based capacitor. A MEMS-based capacitor includes an electrode plate that is actuated using an electrostatic, thermal or piezoelectric mechanism to adjust its gap for changing the capacitance. MEMS-based capacitors are available in a wide range of capacitance values, typically from pico-farads to tens or even hundreds of micro-farads. The capacitance range depends on the specific design and structure of the MEMS-based capacitor, including the size of the plates and the actuation mechanism. Given their microscopic size and precision engineering, MEMS capacitors typically exhibit high Q values, making them desirable for RF and microwave applications. In general, each type of programmable capacitor can be controlled by an external controller (i.e., not part of the amplifier circuit), so that the center-tap impedance can be adjusted in situ based on real-time performance and individual system settings.

[0036] Figure 2 is a graph of the second harmonic signal power level relative to the decoupling capacitor capacitance based on an output signal power of 20 dBm according to an embodiment of the present technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. Figure 2 Two examples of second harmonic signal power density (HD2) in a power amplifier and capacitance of a programmable capacitor at two different operating frequencies are shown. The second harmonic signal power density is measured at the output terminal 150, where the output power density is set to 20 dBm as a reference for the two examples. Curve 201 corresponds to a power amplifier with an operating frequency of 7 GHz and a second harmonic signal of 14 GHz. For 7 GHz operation, the variation of HD2 shows a minimum value when the capacitance is set to 1.25 pF. Curve 202 corresponds to a power amplifier with an operating frequency of 5 GHz and a second harmonic signal of 10 GHz. The graph shows that if the capacitance of the programmable capacitor is selected to be 2.75 pF, HD2 can be reduced to a minimum level.

[0037] Figure 3 1 is a flow chart illustrating a method for controlling second harmonics in a broadband power amplifier according to an embodiment of the present technology. This figure is merely an example and should not unduly limit the scope of the claims. A person of ordinary skill in the art will recognize many variations, alternatives, and modifications. In an embodiment, based on Figure 1 The power amplifier circuit introduced in the invention provides a method 300 for controlling the second harmonic in a broadband power amplifier and enhancing the amplifier efficiency while reducing common mode distortion. As an example only, the method 300 includes a step 301 of configuring a first pair of transistors to have their gates receive a first voltage input and a second voltage input, respectively. In an embodiment, the first pair of transistors are provided as a first transistor 111 and a second transistor 112 and are configured according to Figure 1 . The circuit system wiring shown in . The gate terminal of the first transistor receives a first voltage input. The gate terminal of the second transistor receives a second voltage input. Optionally, the first voltage input represents a positive voltage signal and the second voltage input represents a negative voltage signal. Each of the two signals may have the same value and the same frequency. For this broadband power amplifier, the frequency may be one of a wide range from 1 MHz to 10s GHz. The first voltage input and the second voltage input may be considered as differential voltage signals for the broadband power amplifier. Optionally, the source terminals of the first pair of transistors are respectively coupled to a first common node (with two coupling resistors).

[0038] refer to Figure 3 , the method 300 further includes a step 303 of configuring a second pair of transistors to provide a differential voltage signal based on the first voltage input and the second voltage input. In an embodiment, the second pair of transistors is provided as Figure 1 1 and 12. The third transistor 113 and the fourth transistor 114 are shown in the figure. Specifically, the third transistor 113 has its source terminal coupled to the drain terminal of the first transistor 111. The fourth transistor 114 has its source terminal coupled to the drain terminal of the second transistor 112. The third transistor and the fourth transistor share a common gate terminal that is grounded. The third transistor 113 forms a push-pull functional structure that amplifies the first voltage input (i.e., the positive half) in combination with the first transistor 111. The fourth transistor 114 also forms a push-pull functional structure that amplifies the second voltage input (i.e., the negative half) in combination with the second transistor 112.

[0039] In addition, the method 300 includes providing a transformer (eg, a transformer having a first winding and a second winding) at an output stage of the broadband power amplifier circuit. Figure 1The method 300 includes a step 305 for coupling the first winding between the respective drains of the second pair of transistors to receive a current signal associated with the differential voltage signal. The current signal can be converted into an amplified voltage signal across the two terminals of the first winding. The first winding is a primary winding of the transformer. In addition, the method 300 also includes a step 309 for coupling the second winding between the ground terminal and the output terminal. Figure 1 , one terminal of the second winding 142 is first coupled to the resistor 126 and then to ground. The other terminal of the second winding 142 is the output terminal 150. The second winding is the secondary winding of the transformer. In an embodiment of the method, the transformer is a center-tapped transformer, the midpoint of its primary winding is predetermined.

[0040] Furthermore, method 300 includes step 311 for coupling at least one programmable capacitor between a midpoint of the first winding and a first common node coupled to respective sources of the first pair of transistors. Figure 1 , the third circuit includes a first resistor 121, a second resistor 122, a programmable capacitor 101, and a third resistor 123 connected in series, wherein the first resistor 121 is coupled to the midpoint of the first winding of the transformer, and the third resistor is further coupled to the first common node 131. The center tap line associated with the programmable capacitor allows the transformer at the output stage of the power amplifier to adjust the coupling between the amplifier and the load, and adds a control mechanism for reducing noise (such as second harmonic signals). In an embodiment, the programmable capacitor can be externally controlled to allow capacitance adjustment for each operating frequency over a wide range during operation of the broadband power amplifier. The programmable capacitor provides a way to effectively adjust the impedance in the center tap line, which in turn reduces or eliminates the second harmonic signal from the output signal.

[0041] Furthermore, method 300 includes step 313 for coupling a power source to a second common node of a center tap line coupled to the midpoint and to a second resistor coupled to the programmable capacitor. Figure 1 In the example of FIG. 1 , the power supply VDD is added to the second common node 132, which is commonly joined by the first resistor 121 and the second resistor 122 in the center tap line. The power supply is a voltage source coupled to the second common node 132 via the resistor 125. By coupling the power supply to the center tap line, the output stage of the broadband power amplifier can effectively utilize the entire power supply voltage, allowing for improved efficiency and power handling capability.

[0042] Furthermore, the method 300 includes a step 315 for grounding the first common node. Figure 1In the example of , the first common node is further coupled to a fourth resistor 124, which is connected to ground. These steps provide a broadband power amplifier that can operate over a wide frequency range, such as used as an RF power amplifier, driver amplifier, or low noise amplifier in many applications.

[0043] In addition, a method for controlling a second harmonic signal of a broadband power amplifier is to use a controller to adjust the capacitance of a programmable capacitor to reduce a second harmonic signal at an output terminal, which is twice the frequency of an input signal, for each operating frequency of a differential voltage signal. Figure 1 As shown in FIG. 1 , the programmable capacitor 101 will be the main contributor to the center tap impedance at the operating frequency. By tuning the capacitor, the center tap impedance can be easily adjusted. Figure 2 In the example shown in , when the capacitance of the programmable capacitor is tuned to a specific value of 1.25 pF, the second harmonic power density can be minimized in the case of a second harmonic at 14 GHz (which is twice the operating frequency of the power amplifier, 7 GHz).

[0044] In general, programmable capacitors are provided as capacitors that can be electronically controlled by an external controller using control signals. The specific control mechanism depends on the type of programmable capacitor used. For example, a programmable capacitor is a digitally controlled capacitor that has digital control inputs that accept binary or digital signals to select or adjust the capacitance value. These control inputs can be connected to a microcontroller, a digital potentiometer, or other digital control circuitry. The control signal determines the desired capacitance setting, and the programmable capacitor adjusts its internal configuration accordingly.

[0045] In another example, a programmable capacitor can be controlled by an analog control voltage to determine a desired capacitance value, and the capacitor adjusts its internal configuration to achieve that value. This control voltage can be generated using a digital-to-analog converter (DAC), voltage divider, or other analog control circuitry.

[0046] In another example, a programmable capacitor may have a mechanical control mechanism. This may involve using a mechanical actuator or switch to physically modify the structure of the capacitor and change its effective capacitance. Optionally, the switch may be electrically controlled.

[0047] In an embodiment, the method proposed above can be applied to various applications where harmonic control is required. For example, in telecommunications where broadband power amplifiers are used to amplify signals in the RF (radio frequency) range, or in wireless communications where signals in a desired frequency range are amplified, or in radar systems where broadband power amplifiers typically operate over a wide frequency range to achieve accurate detection of targets and accurate estimation of their characteristics (including distance, speed, and direction that require low-noise amplification). It can also be applied to test and measurement applications. The power amplifier device size is relatively large and has a good distribution of parasitic inductance and capacitance. Common-mode impedance is also affected by packaging and board-level chip parasitics, making accurate modeling difficult and time-consuming. Therefore, the method of using programmable capacitors to tune the center tap impedance in test measurements also helps to adjust the common-mode impedance seen by the common-mode signal at the output terminal. Therefore, the development cycle of the power amplifier can be reduced.

[0048] While the above is a complete description of specific embodiments, various modifications, alternative constructions, and equivalents may be used. Therefore, the above descriptions and illustrations should not be taken as limiting the scope of the present technology, which is defined by the appended claims.

Claims

1. A device comprising: a first circuit comprising a first transistor and a second transistor coupled to a third transistor and a fourth transistor, respectively, the first transistor comprising a first gate configured to receive a first voltage input, the second transistor comprising a second gate configured to receive a second voltage input, the third transistor comprising a source coupled to a drain of the first transistor, and the fourth transistor comprising a source coupled to a drain of the second transistor; a second circuit comprising a transformer having a first winding including a first terminal coupled to a drain of the third transistor and a second terminal coupled to a drain of the fourth transistor, the first winding being configured to sink a current associated with a differential voltage signal based on the first voltage input and the second voltage input, and a second winding including a third terminal connected to ground via a sixth resistor and a fourth terminal serving as an output terminal; and A third circuit includes a first resistor, a second common node, a second resistor, a programmable capacitor, a third resistor, a first common node, and a fourth resistor coupled in series from a midpoint of the first winding to a ground terminal in sequence.

2. The apparatus of claim 1 , further comprising a fourth circuit comprising a fifth resistor having a first terminal coupled to a DC voltage VDD and a second terminal coupled to the second common node, the second common node being connected to both the first resistor and the second resistor.

3. The apparatus of claim 1, wherein the programmable capacitor comprises a switched capacitor array.

4. The apparatus of claim 1, wherein the programmable capacitor comprises a digitally controlled capacitor.

5. The apparatus of claim 1, wherein the programmable capacitor comprises a MEMS-based capacitor.

6. The apparatus of claim 1 , wherein the programmable capacitor comprises a capacitance that can be adjusted by a controller in a range from 0.1 pF to 10 μF based on a frequency of the differential voltage signal in a range from 1 MHz to 19 GHz to reduce a second harmonic signal at the output terminal by at least 10 dBm.

7. The apparatus of claim 1, wherein the first voltage input comprises a first voltage signal at a frequency selected from 1 MHz to 19 GHz, and the second voltage input comprises a second voltage signal having the same value as the first voltage signal but an opposite polarity at the same frequency.

8. The apparatus of claim 1, wherein the third transistor and the fourth transistor comprise a common gate that is grounded.

9. The apparatus of claim 1, wherein the first transistor comprises a source coupled to a seventh resistor, the seventh resistor coupled to the first common node.

10. The apparatus of claim 1, wherein the second transistor comprises a source coupled to an eighth resistor, the eighth resistor coupled to the first common node.

11. A device comprising: a first pair of transistors configured to receive a first voltage input and a second voltage input at their gate terminals, respectively; a second pair of transistors including respective sources coupled to respective drains of the first pair of transistors, the second pair of transistors configured to provide a differential voltage signal based on the first voltage input and the second voltage input; a transformer including a primary winding and a secondary winding, the primary winding coupled to respective drains of the second pair of transistors to receive a current signal associated with the differential voltage signal, the primary winding including a midpoint dividing the primary winding into two sections having equal resistances, the secondary winding coupled between a ground terminal and an output terminal; and At least one programmable capacitor is coupled between the midpoint of the primary winding and a first common node coupled to the first pair of transistors.

12. The apparatus of claim 11, further comprising: a first resistor coupled between the midpoint of the primary winding and a second common node; a second resistor coupled between the second common node and the programmable capacitor; a third resistor coupled between the programmable capacitor and the first common node; and a fourth resistor coupled between the first common node and ground. 13 . The apparatus of claim 12 , further comprising a fifth resistor coupled between a DC voltage VDD and the second common node.

14. The apparatus of claim 13, further comprising: a sixth resistor coupled between the secondary winding and ground; a seventh resistor coupled between a drain of a first one of the first pair of transistors and the first common node; and an eighth resistor coupled between the drain of the second one of the first pair of transistors and the first common node.

15. The apparatus of claim 11, wherein the programmable capacitor comprises a switched capacitor array.

16. The apparatus of claim 11, wherein the programmable capacitor comprises a MEMS-based capacitor.

17. The apparatus of claim 11, wherein the differential voltage signal comprises a frequency range from 1 MHz to 19 GHz.

18. The apparatus of claim 17, wherein the programmable capacitor comprises a capacitance adjustable in a range from 0.1 pF to 10 μF to reduce a second harmonic signal at the output terminal by at least 10 dBm.

19. A method for suppressing second harmonics in a broadband power amplifier, the method comprising: configuring the first pair of transistors so that the corresponding two gates receive the first voltage input and the second voltage input respectively; configuring a second pair of transistors to provide a differential voltage signal based on the first voltage input and the second voltage input; providing a transformer including a first winding and a second winding, the first winding including a midpoint dividing the first winding into two sections having equal resistance; coupling the first winding between respective drains of the second pair of transistors to receive a current signal associated with the differential voltage signal; coupling the second winding between a ground terminal and an output terminal; coupling at least one programmable capacitor between the midpoint of the first winding and a first common node coupled to respective sources of the first pair of transistors, the programmable capacitor configured to allow capacitance adjustment from 0.1 pF to 10 μF; coupling a power source to a second common node of the center tap line, the second common node being connected to the midpoint of the first winding via a first resistor and to the programmable capacitor via a second resistor; and The first common node is coupled to the programmable capacitor via a third resistor and to ground via a fourth resistor.

20. The method of claim 19, further comprising using a controller to adjust a capacitance of the programmable capacitor to reduce a second harmonic signal at the output terminal for each frequency of the differential voltage signal.

Images