Distributed matrix type switching system, message forwarding method and chip

Abstract

The invention relates to a distributed matrix type switching system, a message forwarding method and a chip, the system comprises a plurality of input ports and a plurality of output ports, each input port is connected with a switching module, the number of the input ports is consistent with that of the output ports, and the number of the output ports is equal to that of the input ports. Each output port is connected with one buffer module, each switching module is respectively connected with all the buffer modules, and each switching module is used for carrying out message scheduling forwarding on original messages received by the corresponding input port. Therefore, the message after the message scheduling and forwarding processing is output from any one output port in all the output ports. When the system is used for forwarding the message, the'header blocking problem 'is avoided, the message forwarding delay is reduced, and the forwarding efficiency of the whole chip is improved.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a distributed matrix switching system, a message forwarding method and a chip. Background Art

[0002] Network communication has become an indispensable communication technology in our daily life and production. In the process of network communication, switches are usually used to realize the exchange of network messages. The switch chip is the core chip in the switch. The quality of the switch chip architecture design directly affects the performance of the switch. Therefore, the switch chip architecture design is the key link in the switch chip design.

[0003] The main function of the switch chip is to realize the data forwarding function between multiple ports, usually through table lookup forwarding to achieve layer 2, layer 3, layer 4 switching. Figure 1 shown.

[0004] based on Figure 1 The process of message exchange processing in the single bus switching architecture shown is as follows:

[0005] (1) The port processing module Port receives the original message from the physical interface and puts it into the input buffer (Port_0 to Port_N);

[0006] (2) The inbound port scheduling module In_mux schedules the message from a port input buffer to the next stage according to the relevant algorithm;

[0007] (3) The message parsing module Pkt_parser extracts keywords from the original message, usually dmac+vlan_id+port_id or quintuple+port_id, etc.; searches switch_tbl by keywords, writes the original message to the cache Data_Ram, and gives the control information to the subsequent module through cfifo;

[0008] (4) The message editing module Pkt_edit obtains the table lookup return result (including message editing information and information forwarded from a certain port); takes the message from Data_Ram through the control information in cfifo, and edits the message accordingly according to the table lookup return result, and sends the processed message to the subsequent distribution module for forwarding;

[0009] (5) The outbound port distribution module Out_dmux receives the control information and messages from the Pkt_edit module, and sends the messages to the buffer of the corresponding output port according to the forwarding port (FW_port) returned by the table lookup;

[0010] (6) The port processing module Port reads data from the output buffer and sends it out from the physical interface.

[0011] For the existing single-table bus forwarding process, there is a first technical problem (header blocking problem), which is analyzed as follows: As an example, see Figure 2 , the message from port 0 is forwarded to port 3, the message from port 1 is forwarded to port 4, the message from port 2 is forwarded to port 5, RR scheduling is adopted between the ports, and each port has messages to be forwarded at the same time. The forwarding diagram is as follows Figure 2 As shown. Port 0 forwards to port 3, port 1 forwards to port 4, and port 2 forwards to port 5. Logically, they are independent and have no relationship with each other. However, when a single bus architecture is used, the message forwarded from port 1 to port 4 can only be executed after port 0 completes forwarding a message, and the message forwarded from port 2 to port 5 can only be executed after port 1 completes forwarding a message. These unrelated message forwardings (such as port 0 forwarding to port 3 should not affect the processing of port 1 forwarding to port 4) have a head blocking problem due to the use of a single bus architecture, and the more ports there are, the more serious the "head blocking" problem is.

[0012] There is a second technical problem with the existing single-table bus forwarding process, see Figure 3 As shown in the figure, the processing on the switching bus is based on a complete message, and the processing rate of the switching bus is much higher than the port rate. When the In_mux module uses non-full packet scheduling between multiple input ports (that is, some data in the input buffer of a port is not a complete message and is scheduled for processing), the "waiting waste" problem will occur. Especially when the rates between the ports are inconsistent, this "waiting waste" is more obvious.

[0013] In summary, the above-mentioned single-sheet bus-based exchange method has the following problems:

[0014] (1) Multi-port message exchange has the problem of "head of line blocking";

[0015] (2) When multi-port non-full-packet scheduling occurs, a "waiting waste" problem will occur on the bus. Summary of the invention

[0016] The technical problem to be solved by the present invention is to provide a distributed matrix switching system, a message forwarding method and a chip, aiming to solve at least one of the above technical problems.

[0017] In the first aspect, the technical solution of the present invention to solve the above-mentioned technical problem is as follows: a distributed matrix switching system, comprising multiple input ports and multiple output ports, each of the input ports is connected to a switching module, the number of the multiple input ports is consistent with the number of the multiple output ports, each of the output ports is connected to a buffer module, each of the switching modules is respectively connected to all the buffer modules, and each of the switching modules is used to schedule and forward the original message received by the corresponding input port, so that the message after the message scheduling and forwarding processing is output from any output port of all the output ports.

[0018] The beneficial effect of the present invention is as follows: in this solution, a switching module is set for each input port, so that each input port can be processed in parallel, and the original message received from any input port of the multiple input ports can be output from any output port of all the output ports, so that in the process of message forwarding based on the system, there is no longer a "header blocking problem", the message forwarding delay is reduced, and the forwarding efficiency of the entire chip is improved.

[0019] Based on the above technical solution, the present invention can also be improved as follows.

[0020] Furthermore, each of the switching modules is connected to all buffer modules in a full cross connection manner.

[0021] Furthermore, for each of the buffer modules, the buffer module includes an original cache space and a newly added cache space. The original cache space is used to store messages after message scheduling and forwarding processing, and the newly added cache space is used to store a whole packet identifier, and the whole packet identifier is used to indicate whether the message after message scheduling and forwarding processing has been completely stored.

[0022] In a second aspect, in order to solve the above technical problem, the present invention further provides a message forwarding method, which is applied to a distributed matrix switching system described in the first aspect, and the method comprises:

[0023] Receiving the original message through any one of the multiple input ports and performing parsing and editing processing;

[0024] The parsed and edited message is forwarded to the buffer module of the corresponding output port by using the whole packet scheduling processing method;

[0025] The message after parsing and editing is output from the corresponding output port through the buffer module.

[0026] The beneficial effect of the present invention is that in the process of forwarding messages based on a distributed matrix switching system, the whole packet scheduling processing method is used to forward the parsed and edited messages to the buffer module of the corresponding output port, which can avoid the problem of "waiting waste" on the internal bus of the chip and improve the bus utilization rate inside the chip.

[0027] Further, the whole packet scheduling method is adopted to forward the parsed and edited message to the buffer module of the corresponding output port, including:

[0028] When the buffer module receives the message after parsing and editing, the message after parsing and editing is written into the original cache space in the buffer module, and the whole packet identifier is stored in the newly added cache space in the buffer module. The whole packet identifier is used to indicate whether the message after parsing and editing has been completely stored. The whole packet identifier is written into the newly added cache space after the message after parsing and editing is completely written into the original cache space.

[0029] Further, the whole packet identifier is read from the buffer module after the message processed by the parsing and editing, and the message processed by the parsing and editing is output from the corresponding output port through the buffer module, including:

[0030] In the process of reading the message processed by parsing and editing from the original cache space of the buffer module, when the whole packet identifier is read, the message processed by parsing and editing is output from the corresponding output port.

[0031] Furthermore, the width of the newly added cache space is 1, and the depth is determined based on the bit width and depth of the original cache space.

[0032] In a third aspect, in order to solve the above technical problem, the present invention further provides a chip, including the distributed matrix switching system described in the first aspect.

[0033] In a fourth aspect, in order to solve the above-mentioned technical problem, the present invention also provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the message forwarding method of the present application is implemented.

[0034] In a fifth aspect, in order to solve the above-mentioned technical problem, the present invention further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the message forwarding method of the present application is implemented.

[0035] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for describing the embodiments of the present invention are briefly introduced below.

[0037] Figure 1 A schematic diagram of a single bus switching architecture provided for one embodiment of the present invention;

[0038] Figure 2 A schematic diagram of a single bus switching process provided by an embodiment of the present invention;

[0039] Figure 3 A schematic diagram of a single bus exchange rate provided for one embodiment of the present invention;

[0040] Figure 4 A schematic diagram of the structure of a distributed switching matrix system provided by an embodiment of the present invention;

[0041] Figure 5 A schematic diagram of a flow chart of a message forwarding method provided by an embodiment of the present invention;

[0042] Figure 6 A schematic diagram of a message processing flow provided for an embodiment of the present invention;

[0043] Figure 7 A schematic diagram of a message forwarding process based on a distributed switching matrix system provided by an embodiment of the present invention;

[0044] Figure 8 A schematic diagram of a whole-packet FIFO structure provided by an embodiment of the present invention;

[0045] Fig. 9 A schematic diagram of a whole packet scheduling bus provided by an embodiment of the present invention;

[0046] Fig.10 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0047] The principles and features of the present invention are described below. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0048] The technical solution of the present invention and how the technical solution of the present invention solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present invention will be described below in conjunction with the accompanying drawings.

[0049] The solution provided by the embodiment of the present invention can be applied to any application scenario requiring message forwarding.

[0050] The embodiment of the present invention provides a possible implementation method, such as Figure 4 As shown, a distributed matrix switching system is provided, including multiple input ports and multiple output ports, each of the input ports is connected to a switching module, the number of the multiple input ports is consistent with the number of the multiple output ports, each of the output ports is connected to a buffer module, each of the switching modules is connected to all the buffer modules respectively, and each of the switching modules is used to schedule and forward the original message received by the corresponding input port, so that the message after the message scheduling and forwarding processing is output from any output port of all the output ports. In this way, the original message received by any input port can be output from any output port of all the output ports. The input and output of each port are independent of each other, that is, each input port and each output port are independent of each other and do not affect each other.

[0051] Among them, see Figure 4 , multiple input ports are specifically Figure 4 Port 0 to port N shown on the left, the switch modules corresponding to the multiple input ports are specifically Figure 4 As shown in Switch_0 to Switch_N, each of the output ports is specifically Figure 4 Port 0 to port N shown on the right, the buffer modules corresponding to the output ports are specifically Figure 4 MUX_0 to MUX_N shown in .

[0052] For each of the switching modules, the internal structure of the switching module can be found in Figure 4 In the structural diagram on the left, a switching module includes modules such as pkt_parser, switch_tbl, pkt_edit (Pkt_edit), data_ram (Data_Ram) and dmux (Out_dmux). The functions of each module are the same as those of each module in the prior art, and will not be repeated here.

[0053] Among them, based on the distributed matrix switching system, distributed forwarding of multiple messages can be performed, that is, multiple messages enter from multiple input ports and are output from multiple output ports. Among them, the meaning of message scheduling and forwarding refers to the original message received from the input port, which is processed by various modules inside the distributed matrix switching system. Its specific working principle and processing process will be described in detail in the message forwarding method below, and will not be repeated here.

[0054] Optionally, each of the switching modules is connected to all buffer modules respectively in a full cross connection manner.

[0055] Optionally, for each of the buffer modules, the buffer module includes an original cache space and a newly added cache space, the original cache space is used to store messages after message scheduling and forwarding processing, and the newly added cache space is used to store a whole packet identifier, and the whole packet identifier is used to indicate whether the message after message scheduling and forwarding processing has been completely stored.

[0056] On the basis of the original cache space, a new cache space is added. The whole packet identifier stored in the new cache space is used to determine whether the message after message scheduling and forwarding processing has been completely stored in the buffer module, thereby realizing whole packet storage and whole packet scheduling.

[0057] Based on the above distributed matrix switching system, the present application also provides a message forwarding method, see Figure 5 The method may include the following steps:

[0058] S10, receiving the original message through any one of the multiple input ports and performing parsing and editing processing;

[0059] The specific implementation process of an input port parsing and editing the original message can be found in Figure 6 Input processing flow on the left:

[0060] (1) The input port receives the original message and puts it into the input buffer;

[0061] (2) The inbound port scheduling module In_mux reads the original message from the input buffer and parses the message according to the relevant algorithm, extracts the keyword from the original message through the message parsing module Pkt_parser, and stores the original message in the data cache;

[0062] (3) Use the keyword to look up the table through switch_tbl and obtain the table lookup return result;

[0063] (4) Edit the original message according to the result returned by the table lookup through the message editing module Pkt_edit;

[0064] (5) According to the table lookup result, the output port distribution module Out_dmux forwards the edited message to the buffer module Data_Ram of the corresponding output port.

[0065] Among them, the transmission structure of the original message defined in the code is as follows:

[0066]

[0067] S20, forwarding the parsed and edited message to the buffer module of the corresponding output port by using the whole packet scheduling processing method;

[0068] Specifically, one implementation of the above S20 is:

[0069] When the buffer module receives the message after parsing and editing, the message after parsing and editing is written into the original cache space in the buffer module, and the whole packet identifier is stored in the newly added cache space in the buffer module. The whole packet identifier is used to indicate whether the message after parsing and editing has been completely stored. The whole packet identifier is written into the newly added cache space after the message after parsing and editing is completely written into the original cache space.

[0070] In the present application, the buffer module Data_Ram can also be expressed as New_Data_fifo, and New_Data_fifo includes the original buffer space Data_fifo and the newly added buffer space Eop_fifo. That is, on the basis of the original buffer space Data_fifo, a newly added buffer space Eop_fifo is added. For details, see Figure 8 In the present application, a whole packet identifier (also referred to as eop information) is added to the cache space Eop_fifo to indicate whether a complete message frame has been stored in Data_fifo.

[0071] Specifically, the parsed and edited message is written into the original cache space, and when eop is valid, the eop information is written into the newly added cache space Eop_fifo. In this way, when the newly added cache space Eop_fifo is not empty, it means that there is already a complete frame of message in the original cache space Data_fifo. In other words, when eop information is stored in the newly added cache space Eop_fifo, it means that there is already a complete frame of message in the original cache space Data_fifo.

[0072] Among them, eop is effective means that the newly added cache space Eop_fifo is free and does not store other information.

[0073] Optionally, the width of the newly added cache space Eop_fifo is 1, and the depth is a value determined based on the bit width and depth of the original cache space Data_fifo.

[0074] Specifically, the message and the whole packet identifier after parsing and editing can be written through the write interface of the buffer module New_data_fifo.

[0075] As an example, the write interface signal is implemented as follows:

[0076] New_data_fifo.full=Data_fifo.full|Eop_fifo.full

[0077] Data_fifo.wr=New_data_fifo.wr

[0078] Eop_fifo.wr=New_data_fifo.wr&New_data_fifo.eop

[0079] S30, outputting the parsed and edited message from the corresponding output port through the buffer module.

[0080] Optionally, the whole packet identifier is read from the buffer module after the message after parsing and editing. In the above S30, the message after parsing and editing is output from the corresponding output port through the buffer module, including:

[0081] In the process of reading the message processed by parsing and editing from the original cache space of the buffer module, when the whole packet identifier is read, the message processed by parsing and editing is output from the corresponding output port.

[0082] When the whole packet identifier is read, it indicates that the message after parsing and editing has been completely read out from the buffer module.

[0083] Specifically, the message after parsing and editing can be read through the read interface of the buffer module New_data_fifo. For the read interface of the buffer module New_data_fifo, only when Data_fifo and Eop_fifo are not empty at the same time, it means that New_data_fifo is not empty, and data (message after parsing and editing) can be read. During the reading process of New_data_fifo, data is directly read from Data_fifo first. When the last beat of data of a frame of message is read, one beat of eop information is read from Eop_fifo, indicating that a complete message has been read.

[0084] As an example, the read interface signal is implemented as follows:

[0085] New_data_fifo.empty=Data_fifo.empty|Eop_fifo.empty

[0086] Data_fifo.rd=New_data_fifo.rd

[0087] Eop_fifo.rd=New_data_fifo.rd&Data_fifo.eop

[0088] Through the above processing, the whole package scheduling can be realized. Figure 3 In the same environment, the scheduling situation on the bus becomes Fig. 9 As shown in the figure, a complete message is processed continuously at this time, and there will be no idle waiting on the bus, so the bus utilization rate is greatly improved.

[0089] In the process of reading the parsed and edited message through the read interface, you can also refer to Figure 6 The output processing flow shown on the right side, for the N channels of the output port, first select a channel from the N channels to read the data. After the channel is selected, based on the selected channel, read the parsed and edited message from the cache module. In the process of reading a frame of parsed and edited message, determine whether it is the end of a frame of message. If so, reselect the channel to read the next frame of message. If not, continue to read the parsed and edited message until the end of the parsed and edited message of the frame is read.

[0090] Based on the scheme of this application, see Figure 7 As shown, for Figure 2 Under the same forwarding conditions, ports 0, 1 and 2 can be processed in parallel, and there is no "header block problem", which reduces the message forwarding delay and improves the forwarding efficiency of the entire chip. Figure 7 The message table lookup forwarding shown in the figure refers to the processing process of each switching module. Figure 2 The message scheduling and forwarding process shown in Figure 2 The messages received by each input port are processed one by one. Figure 7 The messages received by each input interface are processed in parallel.

[0091] Based on the above-mentioned system and method, the system and method involved in the scheme of the present application can be implemented in hardware, for example, in a chip, which can be a network card chip or a switching chip, and the above-mentioned network card chip or switching chip can be an FPGA (Field Programmable Gate Array) chip.

[0092] Based on the same principle as a message forwarding method provided in the scheme of the present application, a message forwarding device can also be provided. The message forwarding device of the embodiment of the present invention can execute the message forwarding method provided in the embodiment of the present invention. The implementation principle is similar. The actions performed by each module and unit in the message forwarding device in each embodiment of the present invention correspond to the steps in the message forwarding method in each embodiment of the present invention. For the detailed functional description of each module of the message forwarding device, please refer to the description in the corresponding message forwarding method shown in the previous text, which will not be repeated here.

[0093] Among them, the above-mentioned message forwarding device can be a computer program (including program code) running in a computer device, for example, the message forwarding device is an application software; the device can be used to execute the corresponding steps in the method provided in the embodiment of the present invention.

[0094] In some embodiments, the message forwarding device provided by the embodiment of the present invention can be implemented in a combination of software and hardware. As an example, the message forwarding device provided by the embodiment of the present invention can be a processor in the form of a hardware decoding processor, which is programmed to execute the message forwarding method provided by the embodiment of the present invention. For example, the processor in the form of a hardware decoding processor can adopt one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs) or other electronic components.

[0095] The modules involved in the embodiments of the present invention may be implemented by software or hardware, wherein the name of a module does not limit the module itself in some cases.

[0096] Based on the same principle as the method shown in the embodiments of the present invention, an electronic device is also provided in the embodiments of the present invention, which may include but is not limited to: a processor and a memory; the memory is used to store a computer program; the processor is used to execute the method shown in any embodiment of the present invention by calling the computer program.

[0097] In an alternative embodiment, an electronic device is provided, such as Fig.10 As shown, Fig.10 The electronic device 4000 shown includes: a processor 4001 and a memory 4003. The processor 4001 and the memory 4003 are connected, such as through a bus 4002. Optionally, the electronic device 4000 may also include a transceiver 4004, which may be used for data interaction between the electronic device and other electronic devices, such as data transmission and / or data reception. It should be noted that in actual applications, the transceiver 4004 is not limited to one, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present invention.

[0098] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. It may implement or execute various exemplary logic blocks, modules and circuits described in conjunction with the disclosure of the present invention. Processor 4001 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0099] The bus 4002 may include a path to transmit information between the above components. The bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The bus 4002 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.10 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0100] The memory 4003 can be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory) or other optical disk storage, optical disk storage (including compressed optical disk, laser disk, optical disk, digital versatile disk, Blu-ray disk, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to this.

[0101] The memory 4003 is used to store the application code (computer program) for executing the solution of the present invention, and the execution is controlled by the processor 4001. The processor 4001 is used to execute the application code stored in the memory 4003 to implement the content shown in the above method embodiment.

[0102] The electronic device may also be a terminal device. Fig.10 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present invention.

[0103] An embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer-readable storage medium is run on a computer, the computer can execute the corresponding contents of the aforementioned method embodiment.

[0104] According to another aspect of the present invention, a computer program product or a computer program is also provided, the computer program product or the computer program comprising computer instructions, the computer instructions being stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the methods provided in the implementation modes of the above-mentioned various embodiments.

[0105] Computer program code for performing the operations of the present invention may be written in one or more programming languages, or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0106] It should be understood that the flow charts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the method and computer program product according to various embodiments of the present invention. In this regard, each box in the flow chart or block diagram can represent a module, a program segment, or a part of a code, and the module, the program segment, or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0107] The computer-readable storage medium provided by the embodiment of the present invention may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present invention, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, device, or device.

[0108] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by the electronic device, the electronic device executes the method shown in the above embodiment.

[0109] The above description is only a preferred embodiment of the present invention and an explanation of the technical principles used. Those skilled in the art should understand that the disclosure scope involved in the present invention is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present invention (but not limited to) by each other.

Claims

1. A distributed matrix switching system, characterized in that: It includes multiple input ports and multiple output ports, each of the input ports is connected to a switching module, the number of the multiple input ports is consistent with the number of the multiple output ports, each of the output ports is connected to a buffer module, each of the switching modules is connected to all the buffer modules respectively, and each of the switching modules is used to schedule and forward the original message received by the corresponding input port, so that the message after the message scheduling and forwarding processing is output from any output port among all the output ports.

2. The system according to claim 1, characterized in that Each of the switching modules is connected to all buffer modules in a full cross connection manner.

3. The system according to claim 1, characterized in that For each of the buffer modules, the buffer module includes an original cache space and a newly added cache space. The original cache space is used to store messages processed by message scheduling and forwarding, and the newly added cache space is used to store a whole packet identifier, and the whole packet identifier is used to indicate whether the message processed by message scheduling and forwarding has been completely stored.

4. A message forwarding method, characterized in that: Using the distributed matrix switching system of claim 1, the method comprises: Receiving the original message through any one of the multiple input ports and performing parsing and editing processing; The parsed and edited message is forwarded to the buffer module of the corresponding output port by using the whole packet scheduling processing method; The message after parsing and editing is output from the corresponding output port through the buffer module.

5. The method according to claim 4, characterized in that The whole packet scheduling method is adopted to forward the parsed and edited message to the buffer module of the corresponding output port, including: When the buffer module receives the message after parsing and editing, the message after parsing and editing is written into the original cache space in the buffer module, and the whole packet identifier is stored in the newly added cache space in the buffer module. The whole packet identifier is used to indicate whether the message after parsing and editing has been completely stored. The whole packet identifier is written into the newly added cache space after the message after parsing and editing is completely written into the original cache space.

6. The method according to claim 5, characterized in that The whole packet identifier is read from the buffer module after the message processed by the parsing and editing, and the message processed by the parsing and editing is output from the corresponding output port through the buffer module, including: In the process of reading the message processed by parsing and editing from the original cache space of the buffer module, when the whole packet identifier is read, the message processed by parsing and editing is output from the corresponding output port.

7. The method according to claim 6, characterized in that The width of the newly added cache space is 1, and the depth is determined based on the bit width and depth of the original cache space.

8. A chip, characterized in that: It comprises a distributed matrix switching system as described in claim 1.

9. An electronic device, characterized in that: The method comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 4 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 4 to 7 is implemented.

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