Circuit board and method of manufacturing the same

Abstract

The present disclosure provides a circuit board including a buried capacitor, a substrate and an insulating layer. The buried capacitor includes a dielectric layer and a pair of first and second electrodes, wherein the dielectric layer has a first side, a second side adjacent to the first side, a third side opposite to the first side, and a fourth side opposite to the second side, and the first and second electrodes cover the first and third sides, respectively. The substrate surrounds the buried capacitor, wherein the substrate is physically connected to the second and fourth sides of the dielectric layer, and the first electrode is located between the first side and a sidewall of the substrate. The insulating layer covers the buried capacitor and the substrate, wherein the insulating layer extends from an upper surface of the substrate to a lower surface of the substrate along the first electrode and the sidewall of the substrate. The buried capacitor has the dielectric layer physically connected to the substrate to improve the position accuracy, and the present disclosure reduces the size of the buried capacitor by process combination to improve the element integration of the circuit board.

Description

Technical Field

[0001] This disclosure relates to circuit boards and their manufacturing methods, and in particular to circuit boards including embedded capacitors. Background Technology

[0002] Circuit board manufacturing typically uses embedded bonding to integrate embedded capacitors into the circuit board. However, when the embedded capacitors are very small, they are susceptible to displacement due to the impact of flowing material during bonding, leading to malfunctions or failures of the circuit board. Furthermore, small embedded capacitors often have small pads, increasing the difficulty of electrically connecting the circuit layers within the circuit board to the embedded capacitors. Summary of the Invention

[0003] To address the aforementioned issues, this disclosure provides a circuit board including embedded capacitors and a method for manufacturing the same, enabling the production of precisely positioned embedded capacitors through a simplified process, thereby improving the reliability and component integration of the circuit board.

[0004] According to one embodiment of this disclosure, a circuit board includes a first embedded capacitor, a substrate, and an insulating layer. The first embedded capacitor includes a dielectric layer and a pair of first and second electrodes, wherein the dielectric layer has a first side surface, a second side surface adjacent to the first side surface, a third side surface opposite to the first side surface, and a fourth side surface opposite to the second side surface, and the first and second electrodes respectively cover the first and third side surfaces. The substrate surrounds the first embedded capacitor, wherein the substrate is physically connected to the second and fourth side surfaces of the dielectric layer, and the first electrode is located between the first side surface and a sidewall of the substrate. The insulating layer covers the first embedded capacitor and the substrate, wherein the insulating layer extends from the upper surface of the substrate to the lower surface of the substrate along the first electrode and the sidewall.

[0005] In some implementations, the substrate and the dielectric layer are integrally formed.

[0006] In some embodiments, the dielectric layer has an upper surface connecting the first side and the second side, and the upper surface of the substrate and the upper surface of the dielectric layer are coplanar.

[0007] In some embodiments, the first electrode includes a first pad on the dielectric layer, a second pad under the dielectric layer, and an electrode plate that physically connects the first pad and the second pad.

[0008] In some embodiments, the first electrode includes a first pad located on the dielectric layer, and the second electrode includes a second pad located on the dielectric layer, the second pad and the first pad being separate from each other.

[0009] In some embodiments, the circuit board further includes a second embedded capacitor, wherein the second embedded capacitor includes a dielectric layer and a pair of third and fourth electrodes, and the length of the dielectric layer of the second embedded capacitor between the third and fourth electrodes is different from the length of the dielectric layer of the first embedded capacitor between the first and second electrodes.

[0010] According to one embodiment of this disclosure, a method of manufacturing a circuit board includes the following steps: Providing an initial substrate. Performing a first aperture process on the initial substrate to form a pair of apertures, a dielectric layer located between the pair of apertures, and a substrate physically connected to the dielectric layer, wherein the dielectric layer has a pair of side surfaces facing the pair of apertures and opposite to each other. Forming a conductive layer on the substrate, on the dielectric layer, and in the pair of apertures. Forming a mask on the conductive layer, wherein the mask at least covers the pair of apertures. Etching the conductive layer using the mask to expose the dielectric layer and the substrate, retaining the conductive layer located in the pair of apertures. After etching the conductive layer using the mask, removing the mask. After removing the mask, retaining the conductive layer located on the pair of side surfaces of the dielectric layer, and removing other conductive layers in the pair of apertures located outside the pair of side surfaces.

[0011] In some embodiments, the step of forming a mask on the conductive layer includes shielding the conductive portion of the conductive layer located on the dielectric layer with the mask, and also includes retaining the conductive portion located on the dielectric layer after removing the mask.

[0012] In some implementations, the step of removing other conductive layers located outside the pair of sides of the pair of openings includes performing a second opening process along the pair of openings to expand the pair of openings in a direction away from the pair of sides, wherein the first opening process and the second opening process use the same process steps.

[0013] In some embodiments, the step of forming a mask on the conductive layer includes masking a conductive portion of the conductive layer, wherein the conductive portion is located on a substrate portion of the substrate, and the step of performing a second aperture process includes removing the conductive portion and the substrate portion.

[0014] According to the above embodiments, the disclosed circuit board includes an embedded capacitor and a substrate formed using an aperture process and a mask etching process. The substrate is physically connected to the dielectric layer of the embedded capacitor, thereby improving the positional accuracy of the embedded capacitor and the reliability of the circuit board. Forming the dielectric layer of the embedded capacitor using the aperture process reduces the size of the embedded capacitor, thereby improving the component integration of the circuit board, and allows for the simultaneous fabrication of embedded capacitors of various sizes and arrangements. The electrodes of the embedded capacitor are formed using the mask etching process, thus allowing for the independent fabrication of electrode pads and reducing misalignment between the electrode pads and other components. Attached Figure Description

[0015] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0016] Figure 1 A cross-sectional view of a circuit board is shown according to one embodiment of the present disclosure.

[0017] Figure 2A and Figure 2B Draw Figure 1 Top view and cross-sectional view of the embedded capacitor and substrate.

[0018] Figures 3A to 3T Multiple views of the circuit board at various intermediate stages of the manufacturing process are illustrated according to some embodiments of this disclosure.

[0019] Figure 4 A top view of a circuit board is shown according to some embodiments disclosed herein. Detailed Implementation

[0020] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly.

[0022] It should be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part without departing from the teachings of this document.

[0023] This disclosure provides a circuit board including embedded capacitors and a method for manufacturing the same, wherein the dielectric layer of the embedded capacitors is physically connected to the substrate, thereby improving the positional accuracy of the embedded capacitors and the reliability of the circuit board. The dielectric layer of the embedded capacitors is formed by an aperture process, and the electrodes of the embedded capacitors are formed by a mask etching process. Therefore, the size (e.g., volume) of the embedded capacitors can be reduced to improve the component integration of the circuit board, and the electrode pads can be independently manufactured according to design requirements to reduce the misalignment between components.

[0024] According to one embodiment of this disclosure, Figure 1 A cross-sectional view of circuit board 10 is shown. To clearly depict the components included in circuit board 10, Figure 1 Only some of the components of the circuit board 10 are shown in this disclosure, but circuit boards that include additional components (such as seed layers under the conductive layers, system boards electrically connected to the circuit board, etc.) are also within the scope of this disclosure.

[0025] refer to Figure 1 The circuit board 10 includes an embedded capacitor 100, a substrate 200, an insulating layer 300, and contacts 400. The embedded capacitor 100 and the substrate 200 are both located within the insulating layer 300, thus the embedded capacitor 100 and the substrate 200 can be considered as components of the same level. For example, the embedded capacitor 100 and the substrate 200 can both be located on the same plane. Furthermore, the substrate 200 is physically connected to the embedded capacitor 100, allowing the embedded capacitor 100 to be precisely fixed at a designated position within the insulating layer 300. Therefore, when the contacts 400 extend into the insulating layer 300 and are electrically connected to the embedded capacitor 100, the risk of the contacts 400 and the embedded capacitor 100 forming an offset conductive path can be reduced, thereby improving the reliability of the circuit board 10.

[0026] To more clearly describe the relationship between the embedded capacitor 100 and the substrate 200 Figure 2A Draw Figure 1 A top view of the embedded capacitor 100 and the substrate 200. Figure 2B Draw along Figure 2A Cross-sectional view of centerline AA′. (Reference) Figures 1 to 2BThe embedded capacitor 100 includes a dielectric layer 110 and a pair of first electrodes 120 and second electrodes 130. The dielectric layer 110 has a first side surface 110a, a second side surface 110b adjacent to the first side surface 110a, a third side surface 110c relative to the first side surface 110a, a fourth side surface 110d relative to the second side surface 110b, an upper surface 110t connecting the first side surface 110a to the fourth side surface 110d, and a lower surface 110u connecting the first side surface 110a to the fourth side surface 110d.

[0027] although Figures 1 to 2B The dielectric layer 110 is depicted as a cuboid shape with straight edges, but in other embodiments, the dielectric layer 110 may have curved edges, a cubic shape, a trapezoidal shape, or other shapes. When the dielectric layer 110 has a trapezoidal shape, both the first side surface 110a and the third side surface 110c are beveled surfaces.

[0028] The first electrode 120 covers the first side surface 110a, and the second electrode 130 covers the third side surface 110c. Therefore, after applying a voltage to the first electrode 120 and the second electrode 130, the dielectric layer 110 between the first electrode 120 and the second electrode 130 can store electrical energy. More specifically, the first electrode 120 includes an electrode plate 122 on the first side surface 110a, a first pad 124 on the upper surface 110t, and a second pad 126 on the lower surface 110u. The electrode plate 122 physically connects the first pad 124 on the dielectric layer 110 and the second pad 126 under the dielectric layer 110, such that the first electrode 120 extends continuously from the upper surface 110t along the first side surface 110a to the lower surface 110u.

[0029] Similarly, the second electrode 130 includes an electrode plate 132 on the third side 110c, a first pad 134 on the upper surface 110t, and a second pad 136 on the lower surface 110u. The first pad 124 is separate from the first pad 134, and the second pad 126 is separate from the second pad 136. In some embodiments, the separation distance D1 between the first pad 124 and the first pad 134 in the x-direction may be the same as the separation distance D2 between the second pad 126 and the second pad 136 in the x-direction.

[0030] The first pad 124 of the first electrode 120 can extend along the x-direction toward the second electrode 130 on the upper surface 110t, so the first pad 124 is Figure 2AThe first electrode 120 has a length W1 in the x-direction. Similarly, the first pad 134 of the second electrode 130 may extend toward the first electrode 120 and have a length W1 in the x-direction. In some embodiments, the embedded capacitor 100 may consist of a dielectric layer 110, a first electrode 120, and a second electrode 130, such that the total length of the embedded capacitor 100 in the x-direction is twice the sum of the length W1 and the spacing D1.

[0031] The first electrode 120 can completely cover the first side surface 110a, such that the width of the first electrode 120 is approximately the width of the dielectric layer 110. For example... Figure 2A As shown, the opposite edges of the first electrode 120 can be aligned with the second side surface 110b and the fourth side surface 110d of the dielectric layer 110, respectively. Therefore, both the first electrode 120 and the dielectric layer 110 have a width W2 in the y-direction. In some embodiments, the electrode plate 122, the first pad 124, and the second pad 126 may have the same width W2, so that the first electrode 120 has a uniform width overall. In such embodiments, as... Figure 2A As shown, the area of ​​the first pad 124 on the upper surface 110t can be length W1 × width W2, but this disclosure is not limited to this.

[0032] The substrate 200 surrounds and is physically connected to the embedded capacitor 100, thereby fixing the embedded capacitor 100 at a position on the same layer as the substrate 200. Specifically, the substrate 200 is physically connected to the second side 110b and the fourth side 110d of the dielectric layer 110, thus fixing the dielectric layer 110 in the y-direction by the substrate 200. Since the substrate 200 directly connects to the opposite sides of the dielectric layer 110, the dielectric layer 110 can form a stable structure with the substrate 200, that is, the dielectric layer 110 can be firmly fixed in the substrate 200, thereby reducing or suppressing relative movement between the dielectric layer 110 and the substrate 200, and thus preventing the embedded capacitor 100 from shifting position.

[0033] It is worth noting that while the dielectric layer 110 is connected to the substrate 200 via its second side 110b and fourth side 110d, there is actually no interface or seam between the dielectric layer 110 and the substrate 200. Specifically, the dielectric layer 110 and the substrate 200 are continuous dielectric material layers. The dielectric material layer between the first electrode 120 and the second electrode 130 serves as the dielectric layer 110 of the embedded capacitor 100, while the dielectric material layer surrounding the embedded capacitor 100 serves as the substrate 200. In other words, the substrate 200 and the dielectric layer 110 can be integrally formed into one piece, so that the directly connected substrate 200 and the dielectric layer 110 have the same material composition.

[0034] In some embodiments, the upper surface 200t and lower surface 200u of the substrate 200 may be coplanar with the upper surface 110t and lower surface 110u of the dielectric layer 110, respectively, so that the substrate 200 is physically connected to the integral second side surface 110b and fourth side surface 110d, thereby providing a stable connection between the substrate 200 and the dielectric layer 110. For example... Figure 2B As shown, the dielectric layer 110 and the substrate 200 can be continuous and uniformly thick dielectric material layers, wherein the dielectric layer 110 has a thickness T1 in the z-direction that is the same as the substrate 200 has a thickness T2 in the z-direction. For example, the thickness T1 of the dielectric layer 110 and the thickness T2 of the substrate 200 can be as small as 40 micrometers while still having a solid connection.

[0035] The substrate 200 can be separated from the first side 110a and the third side 110c of the dielectric layer 110, such that at least two accommodating spaces can be formed between the substrate 200 and the dielectric layer 110. For example, as Figure 2A and Figure 2B As shown, the substrate 200 and the dielectric layer 110 may have a pair of openings 210a and 210b, and the first electrode 120 and the second electrode 130 may be located in the openings 210a and 210b respectively, so that the first electrode 120 and the second electrode 130 can be located between the substrate 200 and the dielectric layer 110.

[0036] An opening 210a extends from the upper surface 200t of the substrate 200 to the lower surface 200u of the substrate 200, such that the first side surface 110a of the dielectric layer 110 and the sidewall 200a of the substrate 200 are located on opposite sides of the opening 210a. Similarly, an opening 210b extends the substrate 200, separating the third side surface 110c of the dielectric layer 110 from the sidewall 200c of the substrate 200 on opposite sides of the opening 210b.

[0037] The first electrode 120 extends along the opening 210a and covers the first side surface 110a of the dielectric layer 110. Therefore, the electrode plate 122 is located between the first side surface 110a and the sidewall 200a, and the electrode plate 122 and the sidewall 200a are separated from each other in the x-direction. Similarly, the electrode plate 132 of the second electrode 130 is located between the third side surface 110c and the sidewall 200c, and the electrode plate 132 and the sidewall 200c are separated from each other. In some embodiments, the separation distance between the electrode plate 132 and the sidewall 200c in the x-direction can be the same as the separation distance D3 between the electrode plate 122 and the sidewall 200a. Although Figures 2A to 2B The openings 210a and 210b are shown as rectangular shapes with straight sidewalls, but in other embodiments, the openings 210a and 210b may have arc-shaped sidewalls, conical sidewalls, cubic shapes, cylindrical shapes or other shapes.

[0038] Reference Figure 1 An insulating layer 300 covers the embedded capacitor 100 and the substrate 200, such that the embedded capacitor 100 and the substrate 200 are both located within the insulating layer 300. Specifically, the insulating layer 300 covers the upper surface 110t and lower surface 110u of the dielectric layer 110, the first electrode 120, the second electrode 130, and the upper surface 200t and lower surface 200u of the substrate 200. Further, the insulating layer 300 extends from the upper surface 200t to the lower surface 200u of the substrate 200 along the electrode plate 122 of the first electrode 120 and the sidewall 200a of the substrate 200, and the insulating layer 300 extends from the upper surface 200t to the lower surface 200u of the substrate 200 along the electrode plate 132 of the second electrode 130 and the sidewall 200c of the substrate 200. In other words, the insulating layer 300 fills... Figure 2B The diagram shows an opening 210a between the first electrode 120 and the sidewall 200a, and an opening 210b between the second electrode 130 and the sidewall 200c.

[0039] Contact 400 is located in insulating layer 300, extending toward embedded capacitor 100 and electrically connected to first electrode 120 and second electrode 130. For example, multiple contacts 400 may extend from the outer surface of insulating layer 300 to contact first pad 124, second pad 126, first pad 134, and second pad 136. In some embodiments, contacts 400 may directly contact first pad 124, second pad 126, first pad 134, and second pad 136, wherein contacts 400 are aligned with the individual pads, thereby forming a conductive path where contacts 400 are aligned with first electrode 120 or second electrode 130.

[0040] According to some embodiments disclosed herein Figures 3A to 3T This diagram shows multiple views of the circuit board at various intermediate stages of the manufacturing process. Specifically, Figure 3A , Figure 3C , Figure 3E , Figure 3H , Figure 3K , Figure 3N and Figure 3Q Draw a top view of the circuit board at various intermediate stages of the manufacturing process. Figure 3B , Figure 3D , Figure 3F , Figure 3I , Figure 3L , Figure 3O , Figure 3R and Figure 3T Draw a cross-sectional view of the circuit board along line AA′ in the top view of the manufacturing process. Figure 3G , Figure 3J , Figure 3M , Figure 3P and Figure 3S Then draw a cross-sectional view of the circuit board along line BB′ in the top view of the manufacturing process. Figures 3A to 3T The illustrated manufacturing method can be used to form, for example... Figures 1 to 2B The circuit board 10 described herein, however, should be understood by those skilled in the art, that the circuit board manufacturing method disclosed herein can also be used to form other circuit boards including embedded capacitors within the scope of this disclosure.

[0041] It is worth noting that, unless otherwise specified, when Figures 3A to 3T When illustrating or describing a series of steps as an embodiment, the order in which these steps are described should not be limited. For example, some steps may be performed in a different order than described in the embodiment, some steps may occur simultaneously, some steps may be unnecessary, and / or some steps may be repeated. Furthermore, additional steps may be performed before, during, or after the illustrated steps to complete the circuit board formation.

[0042] refer to Figures 3A to 3B An initial substrate 20 is provided. Specifically, the initial substrate 20 includes at least one dielectric material layer, wherein the dielectric material layer is used in subsequent steps to form a dielectric layer for an embedded capacitor and a substrate connected to the embedded capacitor. For example, the dielectric material layer may include silicon, ceramic, glass, epoxy glass, graphene oxide, or other dielectric materials suitable as capacitors, wherein the ceramic may include BaTiO3, CaTiO3, SrTiO3, or CaZrO3.

[0043] In some embodiments, the initial substrate 20 may further include a conductive film (not specifically shown) on a dielectric material layer. When the conductive layer (e.g.) Figures 3E to 3G When the conductive layer 500 shown is subsequently formed on the conductive film, the conductive film can improve the integrity and stability of the conductive layer. The conductive film can be a metal thin film, and the type of metal contained in the conductive film can be the same as or similar to the type of metal contained in the subsequent conductive layer. For example, when the subsequent conductive layer includes copper, titanium / copper can be used as the material of the conductive film. In some examples, the conductive film can also be used as a seed layer for electroplating.

[0044] refer to Figures 3C to 3DA first aperture process is performed on the initial substrate 20 to form a pair of apertures 210a and 210b, a dielectric layer 110 located between the apertures 210a and 210b, and a substrate 200 physically connected to the dielectric layer 110. Specifically, the first aperture process forms apertures 210a and 210b extending from the upper surface to the lower surface of the initial substrate 20, wherein the apertures 210a and 210b are aligned with each other in the x-direction, so that the initial substrate 20 can be divided along the edges of the apertures 210a and 210b into the dielectric layer 110 between the apertures 210a and 210b and the substrate 200 surrounding the dielectric layer 110.

[0045] After forming openings 210a and 210b, the dielectric layer 110 has a first side surface 110a and a third side surface 110c facing each other, wherein the first side surface 110a faces the opening 210a and the sidewall 200a of the substrate 200, and the third side surface 110c faces the opening 210b and the sidewall 200c of the substrate 200. The dielectric layer 110 also has a second side surface 110b and a fourth side surface 110d facing each other, wherein the second side surface 110b and the fourth side surface 110d are physically connected to the substrate 200. Since the dielectric layer 110 and the substrate 200 are two elements separated by the openings 210a and 210b, the connection between the dielectric layer 110 and the substrate 200 substantially does not have an interface or seam.

[0046] Holes 210a and 210b divide the area between them into the dielectric layer 110 of the embedded capacitor. The distance between holes 210a and 210b in the x-direction defines the length of the dielectric layer 110 in the x-direction, and the distance between holes 210a and 210b in the y-direction defines the width of the dielectric layer 110 in the y-direction. In other words, holes 210a and 210b define the dimensions (e.g., volume) of the dielectric layer 110 of the embedded capacitor. Therefore, if a high-precision hole-making process is used to form small-sized holes 210a and 210b (e.g., width in the x or y direction), the dielectric layer 110 and the subsequently formed embedded capacitor can have a correspondingly small volume. For example, the first hole-making process can be laser drilling, routing, punching, or other suitable hole-making processes.

[0047] refer to Figures 3E to 3G A conductive layer 500 is formed on the substrate 200, on the dielectric layer 110, in the opening 210a, and in the opening 210b. Specifically, the conductive layer 500 is formed on... Figures 3C to 3DIn the structure shown, the upper surface 200t of the substrate 200, the lower surface 200u of the substrate 200, the upper surface 110t of the dielectric layer 110, and the lower surface 110u of the dielectric layer 110 are thus covered. The conductive layer 500 is also formed in the openings 210a and 210b to cover the exposed surfaces in the openings, such as the sidewalls 200a, 200b, and 200d of the substrate 200 in the opening 210a, and the first sidewall 110a of the dielectric layer 110 in the opening 210a. Similarly, the conductive layer 500 also covers the exposed surfaces in the opening 210b, including the sidewalls 200c and the third sidewall 110c.

[0048] In some embodiments, the conductive layer 500 may be formed conformally, such that the horizontal portions (e.g., the conductive layer 500 on the upper surface 110t) and vertical portions (e.g., the conductive layer 500 on the first side surface 110a) of the conductive layer 500 have similar thicknesses. For example, the conductive layer 500 may be formed by vapor deposition, sputtering, electroplating, electroless plating, or other suitable deposition techniques to form a conductive material including, for example, copper. In some examples, the conductive layer 500 in the openings 210a and 210b may be formed using plating through-hole (PTH) technology in circuit board manufacturing processes.

[0049] In some embodiments, the conductive layer 500 is formed after the openings 210a and 210b, and the conductive layer 500 does not completely fill the openings 210a and 210b, thereby leaving gaps in each of the openings 210a and 210b. For example, such as Figure 3F As shown, the thickness of the conductive layer 500 can be less than the width of the openings 210a and 210b in the x direction. Therefore, the remaining opening 210a separates the conductive layer 500 covering the first side 110a and the conductive layer 500 covering the sidewall 200a.

[0050] refer to Figures 3H to 3J A mask 600 is formed on the conductive layer 500 to shield the conductive layer 500 in the openings 210a and 210b. Specifically, the mask 600 is formed on the conductive layers 500 on the upper surface 110t and upper surface 200t, and also on the conductive layers 500 on the lower surface 110u and lower surface 200u, such that both ends of the openings 210a and 210b are shielded by the mask 600. For example, forming the mask 600 may include forming a photoresist material (e.g., dry film) on the conductive layer 500, and patterning the photoresist material through steps such as exposure and development, thereby forming a mask 600 that completely shields the openings 210a and 210b.

[0051] Since the mask 600 covers the openings 210a and 210b, the portion of the conductive layer 500 located in the openings 210a and 210b can remain unetched in the subsequent etching process. In embodiments where the conductive layer 500 does not completely fill the openings 210a and 210b, the surface of the mask 600 that contacts the conductive layer 500 can be parallel to the upper surface 110t of the dielectric layer 110, so that the mask 600 does not fill the openings 210a and 210b, thus preserving the gaps in the openings 210a and 210b.

[0052] In addition to shielding openings 210a and 210b, mask 600 can also shield portions of the conductive layers 500 located on the upper surface 110t and lower surface 110u of the dielectric layer 110. In subsequent processes, these shielded portions of the conductive layers 500 on the dielectric layer 110 will form the electrode portions of an embedded capacitor; details will be described below. Furthermore, mask 600 can also shield portions of the conductive layers 500 located on the upper surface 200t and lower surface 200u of the substrate 200. In some embodiments, these shielded portions of the conductive layers 500 on the substrate 200 will be subsequently removed, such as... Figures 3Q to 3S As shown, however, in some other embodiments, the portion of the conductive layer 500 that is shielded on these substrates 200 can be used as the electrode portion of other embedded capacitors.

[0053] refer to Figures 3K to 3M An etching process is performed on the conductive layer 500 using a mask 600 to remove a portion of the conductive layer 500, exposing the dielectric layer 110 and the substrate 200. Specifically, an etching process, such as wet etching, can be performed on the conductive layer 500, and the etching process can be stopped at the surface of the dielectric layer 110 and the substrate 200, thereby retaining the portion of the conductive layer 500 that is masked by the mask 600. In some other embodiments, the etching process can be a selective etching process for metal materials, thus allowing etching of the conductive layer 500 that is not masked by the mask 600.

[0054] Because the mask 600 shields openings 210a and 210b, portions of the conductive layer 500 located in openings 210a and 210b can be retained after the etching process. In embodiments where the mask 600 shields the conductive layer 500 on the dielectric layer 110, a portion of the conductive layer 500 on the dielectric layer 110 is also retained after the etching process. Figure 3LAs shown, the conductive layer 500 retained in the opening 210a and located on the first side 110a will serve as the electrode 122 of the first electrode 120, the conductive layer 500 retained on the upper surface 110t will serve as the first pad 124 of the first electrode 120, and the conductive layer 500 retained on the lower surface 110u will serve as the second pad 126 of the first electrode 120. Similarly, the conductive layers 500 retained in the opening 210b, on the upper surface 110t, and on the lower surface 110u will serve as the electrode 132, the first pad 134, and the second pad 136 of the second electrode 130. In other words, etching the conductive layer 500 using the mask 600 can define the pattern and dimensions (e.g., length and width) of the first electrode 120 and the second electrode 130 of the embedded capacitor.

[0055] In an embodiment where the mask 600 shields the conductive layer 500 located on the substrate 200, a portion of the conductive layer 500 on the substrate 200 can be retained after the etching process. For example, such as Figure 3L As shown, the conductive layer 500 on the sidewall 200a of the substrate 200 in the opening 210a can be retained as a conductive portion 510, the conductive layer 500 on the upper surface 200t can be retained as a conductive portion 512, and the conductive layer 500 on the lower surface 200u can be retained as a conductive portion 514. In subsequent... Figures 3Q to 3S In the illustrated embodiment, conductive portions 510, 512, and 514 are removed; however, in some other embodiments, these conductive portions may serve as electrode portions of other embedded capacitors. The conductive layers 500 located on the sidewalls 200b and 200d of the substrate 200 in the opening 210a may also be retained as conductive portions 516 and 518, which will be removed in subsequent processes.

[0056] refer to Figures 3N to 3P After etching the conductive layer 500 using mask 600, mask 600 is removed. After removing mask 600, openings 210a and 210b are re-exposed, and dielectric layer 110, substrate 200, and conductive patterns on both are retained. In embodiments where mask 600 includes photoresist material, a photoresist stripper, for example, can be used to strip the photoresist.

[0057] refer to Figures 3Q to 3SThe conductive patterns on the first side 110a and third side 110c of the dielectric layer 110 are retained, while other conductive patterns in the openings 210a and 210b located outside the first side 110a and third side 110c are removed. Specifically, a second opening process can be performed along the openings 210a and 210b, wherein the opening location avoids the conductive patterns on the first side 110a, thereby retaining the electrode plate 122 of the first electrode 120. In embodiments including a first pad 124 and a second pad 126 on the dielectric layer 110, the second opening process further retains the first pad 124 and the second pad 126 to form a first electrode 120 including the electrode plate 122, the first pad 124, and the second pad 126. Similarly, the second opening process also retains the electrode plate 132, the first pad 134, and the second pad 136 of the second electrode 130. Therefore, after the second aperture process, an embedded capacitor 100 including a dielectric layer 110, a first electrode 120, and a second electrode 130 is formed.

[0058] The second aperture process removes a portion of the conductive pattern in apertures 210a and 210b, making the first electrode 120 and the second electrode 130 independent of other conductive patterns, thus allowing them to serve as paired electrodes for the embedded capacitor 100. For example, such as Figure 3S As shown, the second aperture process can remove the conductive patterns located on sidewalls 200b and 200d in aperture 210a (i.e., Figure 3P The conductive portions 516 and 518 in the first electrode 120 and the second electrode 130 are made into independent conductive patterns. In such an example, the second opening process and the first opening process may use the same process steps (e.g., drilling or profile cutting), but the opening size or opening position of the second opening process is different from that of the first opening process.

[0059] In some embodiments where the conductive pattern remains on the substrate 200, the second aperture process can further expand the aperture 210a in a direction away from the first side 110a and expand the aperture 210b in a direction away from the third side 110c, thereby removing the conductive pattern on the substrate 200. For example, the second aperture process can remove... Figure 3O The conductive portions 510, 512, and 514, and the portion of substrate 200 located between conductive portions 512 and 514, cause the opening 210a to expand toward substrate 200 along the x-direction. In such an example, the sidewall 200a recedes toward substrate 200, causing... Figure 3R The width of the opening 210a in the middle is greater than Figure 3O The width of the opening 210a in the middle.

[0060] It is worth noting that, Figures 3Q to 3SThe illustrated embodiment forms a single embedded capacitor 100 surrounded by a substrate 200, thus retaining only the electrode 122 in opening 210a and the electrode 132 in opening 210b. However, in other embodiments where the substrate 200 surrounds the embedded capacitor 100 and additional embedded capacitors adjacent to the embedded capacitor 100, additional embedded capacitors may be retained. Figure 3O The conductive portions 510, 512 and 514 in the present disclosure serve as electrodes for an additional embedded capacitor, but this disclosure is not limited thereto.

[0061] refer to Figure 3T An insulating layer 300 is formed on the dielectric layer 110 and the substrate 200, so that the insulating layer 300 covers the embedded capacitor 100 and the substrate 200. Specifically, the insulating layer 300 can be directly formed on... Figures 3Q to 3S In the structure shown, the insulating layer 300 physically contacts the upper surface 110t and lower surface 110u of the dielectric layer 110, the upper surface 200t and lower surface 200u of the substrate 200, the first electrode 120, and the second electrode 130. The insulating layer 300 further extends into the openings 210a and 210b, thereby physically contacting the electrode plate 122 on the first side 110a and the electrode plate 132 on the third side 110c. Since the insulating layer 300 extends from the upper surface 110t and upper surface 200t to the lower surface 110u and lower surface 200u along the openings 210a and openings 210b, the embedded capacitor 100 and the substrate 200 can form a stably connected element in the same layer.

[0062] Manufacturing circuit boards including embedded capacitors according to the method disclosed herein offers several advantages. The method uses an aperture process combined with the formation and etching of a conductive layer to manufacture embedded capacitors connected to the substrate, thus simplifying the manufacturing process and eliminating the need for embedded lamination, thereby improving the positional accuracy of the embedded capacitors and the reliability of the circuit board. Because the dielectric layers of both the substrate and the embedded capacitors are formed using the same material layer, a high-strength connection is achieved between the substrate and the embedded capacitors, allowing for a reduction in the thickness of the embedded capacitors while maintaining the structural stability of the circuit board.

[0063] The method disclosed herein defines the length and width of the dielectric layer of the embedded capacitor using an aperture process and directly forms electrodes on the dielectric layer using a mask etching process. Therefore, this method can manufacture small-sized and precisely positioned embedded capacitors, thereby improving the component integration density of the circuit board. The mask etching process also helps to reduce the spacing between pairs of pads in the embedded capacitor, thereby reducing the size of the embedded capacitor. For example, the spacing between pairs of pads (e.g., ...) Figure 2BThe spacing D1 shown can be as small as 20 micrometers while still precisely forming the embedded capacitor at the designated location on the circuit board. In the example above, the volume of the embedded capacitor can be as small as 270 × 120 × 40 cubic micrometers.

[0064] Since the length and width of embedded capacitors primarily depend on the size and spacing of the paired apertures formed by the aperture-opening process, embedded capacitors of various sizes can be manufactured simultaneously on the same substrate, or non-standard sized embedded capacitors can be manufactured according to capacitance value requirements. Furthermore, various arrangements of embedded capacitors can be provided based on design needs. In addition, the position of the embedded capacitors also depends on the paired apertures formed by the aperture-opening process, resulting in high positioning accuracy and reducing the likelihood of short circuits between different embedded capacitors. Therefore, the spacing between multiple embedded capacitors can be shortened to improve the component integration of the circuit board.

[0065] To illustrate the above advantages, Figure 4 A top view of a circuit board 30 is illustrated according to some embodiments of this disclosure. The circuit board 30 includes a plurality of embedded capacitors 100a to 100d, wherein each of the embedded capacitors 100a to 100d has a similar... Figure 3T The structure of the embedded capacitor 100 is shown. In other words, each of the embedded capacitors 100a to 100d includes a pair of first electrodes 120 and second electrodes 130 and a dielectric layer 110 between the first electrodes 120 and the second electrodes 130.

[0066] like Figure 4 As shown, since the aperture process can simultaneously form pairs of apertures with different sizes and spacings, the length W3 of the dielectric layer 110 of the embedded capacitor 100a in the y-direction can be different from the length W4 of the dielectric layer 110 of the embedded capacitor 100b in the y-direction. Furthermore, the pad dimensions of the embedded capacitors 100a and 100b correspond to their respective apertures; therefore, the pad area of ​​the first electrode 120 of the embedded capacitor 100a on the dielectric layer 110 can be different from the pad area of ​​the first electrode 120 of the embedded capacitor 100b on the dielectric layer 110.

[0067] Figure 4Embedded capacitors 100c and 100d are adjacent capacitors, with a spacing D4 between them. Because the via process can precisely form paired vias for embedded capacitors 100c and 100d, a large spacing D4 is not required, thus preventing short circuits between them. For example, the spacing D4 between embedded capacitors 100c and 100d can be as small as 20 micrometers without causing them to fail. In some embodiments, the first electrode 120 of embedded capacitor 100c and the second electrode 130 of embedded capacitor 100d can share the same via; that is, the spacing D4 between embedded capacitors 100c and 100d is the width of one via.

[0068] In addition to defining the dimensions of the embedded capacitor, the method disclosed herein uses a mask etching process to define the pad dimensions of the embedded capacitor. This allows for the independent fabrication of electrode pads corresponding to the contacts, reducing misalignment between the contacts and pads. For example, in an embodiment where contact openings are formed using a laser drilling process, the area of ​​the electrode pads formed by the opening process and the mask etching process (e.g., Figure 2A The length (W1) × width (W2) shown can be as small as 120 × 120 square micrometers while still aligning and matching the subsequently formed contacts.

[0069] Furthermore, the mask etching process can form traces at the same layer as the electrode pads while simultaneously creating the pads for embedded capacitors. For example, such as Figure 4 As shown, the circuit board 30 may include traces 700 located on a substrate, wherein traces 700 and the first electrode 120 / second electrode 130 undergo the same conductive layer formation and etching steps, and therefore traces 700 and the first electrode 120 / second electrode 130 are located in the same layer. In embodiments where traces 700 and the first electrode 120 / second electrode 130 are formed from a uniform conductive layer, the pads of traces 700 and the first electrode 120 / second electrode 130 may have the same thickness, but in other embodiments, traces 700 may be reprocessed to have a thickness different from that of the first electrode 120 / second electrode 130.

[0070] According to the embodiments disclosed above, a circuit board including embedded capacitors is manufactured using an aperture process and a mask etching process. Therefore, a simplified process can be used to manufacture small-sized and precisely positioned embedded capacitors, thereby improving the reliability of the circuit board and the component integration. The dielectric layer of the embedded capacitor is physically connected to the substrate of the same layer in the circuit board, and the electrode pads of the embedded capacitor can be designed independently of the dielectric layer, thus reducing the risk of the embedded capacitor shifting from other components in the circuit board.

[0071] The foregoing outlines features of some embodiments to enable those skilled in the art to better understand the ideas disclosed herein. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0072] [Symbol Explanation]

[0073] 10,30: Circuit board

[0074] 20: Initial substrate

[0075] 100, 100a, 100b, 100c, 100d: Embedded capacitors

[0076] 110: Dielectric layer

[0077] 110a: First side view

[0078] 110b: Second side

[0079] 110c: Third side

[0080] 110d: Fourth side view

[0081] 110t: Upper surface

[0082] 110u: Lower surface

[0083] 120: First electrode

[0084] 122: Plate

[0085] 124: First Pad

[0086] 126: Second pad

[0087] 130: Second electrode

[0088] 132: Plate

[0089] 134: First Pad

[0090] 136: Second pad

[0091] 200:Substrate

[0092] 200a, 200b, 200c, 200d: Sidewalls

[0093] 200t: Upper surface

[0094] 200u: Lower surface

[0095] 210a, 210b: Openings

[0096] 300: Insulation layer

[0097] 400: Contact element

[0098] 500: Conductive layer

[0099] 510, 512, 514, 516, 518: Conductive parts

[0100] 600: Mask

[0101] 700: Wiring

[0102] AA′,BB′: lines

[0103] D1, D2, D3, D4: Spacing

[0104] T1, T2: Thickness

[0105] W1, W3, W4: Length

[0106] W2: Width

[0107] x, y, z: Direction.

Claims

1. A method for manufacturing a circuit board, characterized in that, include: Provide initial substrate; A first aperture process is performed on the initial substrate to form a pair of apertures, a dielectric layer located between the pair of apertures, and a substrate physically connected to the dielectric layer, wherein the dielectric layer has a pair of sides facing the pair of apertures and opposite to each other. A conductive layer is formed on the substrate, on the dielectric layer, and in the pair of openings; A mask is formed on the conductive layer, wherein the mask at least covers the pair of openings and the conductive portion of the conductive layer located on the dielectric layer is also covered by the mask. The conductive layer is etched using the mask to expose the dielectric layer and the substrate, while retaining the conductive layer located in the pair of openings; After etching the conductive layer using the mask, remove the mask; After removing the mask, the conductive layers on the pair of sides of the dielectric layer and the conductive portions on the dielectric layer are retained, and the other conductive layers in the pair of openings located outside the pair of sides are removed to form an embedded capacitor. as well as An insulating layer is formed on the dielectric layer and the substrate, such that the insulating layer covers the embedded capacitor and the substrate.

2. The method according to claim 1, characterized in that, The step of removing the other conductive layer located outside the pair of sides of the pair of openings includes performing a second opening process along the pair of openings to expand the pair of openings in a direction away from the pair of sides, wherein the first opening process and the second opening process use the same process steps.

3. The method according to claim 2, characterized in that, The step of forming the mask on the conductive layer includes shielding a conductive portion of the conductive layer with the mask, the conductive portion being located on a substrate portion of the substrate; as well as The steps of performing the second aperture process include removing the conductive portion and the substrate portion.

4. A circuit board manufactured using the method of claim 1, characterized in that, include: A first embedded capacitor includes a dielectric layer and a pair of first electrodes and second electrodes, wherein the dielectric layer has a first side, a second side adjacent to the first side, a third side relative to the first side, and a fourth side relative to the second side, and the first electrode and the second electrode respectively cover the first side and the third side. A substrate surrounding the first embedded capacitor, wherein the substrate is physically connected to the second side and the fourth side of the dielectric layer, and the first electrode is located between the first side and the sidewall of the substrate, wherein the substrate and the dielectric layer are integrally formed. as well as An insulating layer covers the first embedded capacitor and the substrate, wherein the insulating layer extends from the upper surface of the substrate to the lower surface of the substrate along the first electrode and the sidewall, and physically contacts the upper and lower surfaces of the dielectric layer.

5. The circuit board according to claim 4, characterized in that, The dielectric layer has an upper surface connecting the first side and the second side, and the upper surface of the substrate and the upper surface of the dielectric layer are coplanar.

6. The circuit board according to claim 4, characterized in that, The first electrode includes a first pad located on the dielectric layer, a second pad located under the dielectric layer, and an electrode plate physically connecting the first pad and the second pad.

7. The circuit board according to claim 4, characterized in that, The first electrode includes a first pad located on the dielectric layer, and the second electrode includes a second pad located on the dielectric layer, wherein the second pad and the first pad are separated from each other.

8. The circuit board according to claim 4, characterized in that, The device further includes a second embedded capacitor, wherein the second embedded capacitor includes a dielectric layer and a pair of third and fourth electrodes, and the length of the dielectric layer of the second embedded capacitor located between the third and fourth electrodes is different from the length of the dielectric layer of the first embedded capacitor located between the first and second electrodes.

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