A Group III nitride device with single-event irradiation resistance

Abstract

The present invention discloses a Group III nitride device with single-event irradiation resistance. The present invention introduces a hole storage layer between the buffer layer and the channel layer of the epitaxial layer structure. The hole storage layer forms a hole potential well in the energy band structure to effectively collect the irradiation-induced excess holes in the channel layer. At the same time, an extraction electrode and a second source electrode are provided to collect the irradiation-induced excess holes in the region near the gate and between the gate and the source respectively. Among them, the extraction electrode is arranged between the gates arranged at intervals in sequence, and the extraction electrode and the second source electrode are connected to the first source electrode through a metal interconnection layer. The present invention can effectively improve the single-event irradiation resistance of the device, and the manufacturing process is compatible with the existing process without introducing additional complex process steps.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, relates to gallium nitride power devices, and particularly relates to a group III nitride device with anti-irradiation ability. Background Art

[0002] Due to the advantages of low on-resistance, fast switching speed, high switching frequency, etc., GaN HEMT devices are beneficial to the realization of lightweight, miniaturized, high-efficiency, and high-power-density power systems, and have broad application prospects in the fields of new-generation mobile communications, data centers, intelligent vehicles, aerospace, etc. In particular, it has great application potential in fields such as aerospace that are sensitive to the volume and weight of power systems. In aerospace applications, electronic devices are exposed to the irradiation of high-energy particles, which may cause single-event effects and result in the degradation or even failure of the devices. In conventional-structured GaN HEMT devices, due to the lack of an effective irradiation-induced carrier regulation structure, the non-equilibrium holes introduced by heavy-ion irradiation may accumulate in the region near the gate, causing the "back barrier effect", resulting in a negative drift of the threshold voltage, leading to source-drain punch-through of the device in the blocking state, and further causing an increase in leakage current or even device burnout. At present, the single-event burnout voltage of GaN HEMT devices is still relatively low, which limits the application of GaN power devices in aerospace scenarios.

[0003] Therefore, in order to improve the anti-single-event irradiation ability of GaN HEMT devices and promote the application of GaN HEMT devices in aerospace scenarios, corresponding designs need to be proposed from the energy band structure and device structure to effectively collect, store, and extract irradiation-induced holes. Summary of the Invention

[0004] Aiming at the deficiencies of the prior art, the present invention provides a group III nitride device with anti-single-event irradiation ability. The present invention introduces a hole storage layer between the buffer layer and the channel layer of the epitaxial layer structure. The hole storage layer forms a hole potential well in the energy band structure to collect the irradiation-induced excess holes in the channel layer; by setting an extraction electrode and a second source electrode to collect the irradiation-induced excess holes in the region near the gate and between the gate and the source respectively. The extraction electrode and the second source electrode are connected to the first source electrode through a metal interconnection layer. The manufacturing process of the present invention is compatible with the existing process, and there is no need to introduce additional complex process steps, providing a solution for improving the anti-single-event irradiation ability of the device.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions:

[0006] The present invention provides a group-III nitride device with anti-single-particle irradiation ability. The group-III nitride device includes a substrate, a buffer layer, a hole storage layer, a channel layer, a barrier layer, and a first passivation layer from bottom to top. A first source electrode and a drain electrode are respectively disposed on both sides of the channel layer. A p-GaN layer is disposed near the first source electrode between the first source electrode and the drain electrode. Gates arranged at intervals in the y direction are disposed on the p-GaN layer. Etching holes are disposed between the gates arranged at intervals. The etching holes are etched to the channel layer, the hole storage layer, or the buffer layer, and extraction electrodes are disposed in the etching holes. The extraction electrodes are in contact with the sidewalls and the bottom along the etching holes; a second source electrode is further disposed near the first source electrode. The second source electrode is connected to the first source electrode and the extraction electrodes through a metal interconnection layer; except for the top surfaces of the extraction electrodes, the first source electrode, the second source electrode, and the drain electrode, the remaining regions of the surface are filled with a second passivation layer.

[0007] As a preferred embodiment of the present invention, the depth of the extraction electrode and the depth of the second source electrode are independent of each other.

[0008] As a preferred embodiment of the present invention, the etching holes are etched to the upper surface or the inside of the buffer layer; or the etching holes are etched to the upper surface or the inside of the hole storage layer; or the etching holes are etched to the upper surface or the inside of the channel layer.

[0009] As a preferred embodiment of the present invention, the depths of adjacent etching holes are the same or different.

[0010] In the present invention, the bottom of each etching hole may be located on the upper surface or inside of the buffer layer, on the upper surface or inside of the hole storage layer, or on the upper surface or inside of the channel layer, or one or more of them.

[0011] As a preferred embodiment of the present invention, the extraction electrodes form Schottky contacts or Ohmic contacts with the semiconductor layers on the sidewalls and the bottom.

[0012] As a preferred embodiment of the present invention, the second source electrode penetrates through the barrier layer, the channel layer, and the hole storage layer and extends into the inside of the buffer layer; or the second source electrode penetrates through the barrier layer and the channel layer and extends into the inside of the hole storage layer; or the second source electrode penetrates through the barrier layer and extends into the inside of the channel layer; or the second source electrode penetrates through the barrier layer, the channel layer, and the hole storage layer and contacts the upper surface of the buffer layer; or the second source electrode penetrates through the barrier layer and the channel layer and contacts the upper surface of the hole storage layer; or the second source electrode penetrates through the barrier layer and contacts the upper surface of the channel layer.

[0013] As a preferred embodiment of the present invention, the etching holes forming the extraction electrodes have a circular, elliptical, polygonal or other irregularly shaped cross-section in the xy plane. The shapes and sizes of the adjacent etching holes in the xy plane are the same or different. The ratio of the projection length of the etching holes in the y direction to the length of the p-GaN layer in the y direction is 5%-90%.

[0014] As a preferred embodiment of the present invention, the gate is one or a combination of a Schottky p-GaN gate, an ohmic p-GaN gate, a recessed gate structure, a MIS gate, or a complex gate structure having the above gate structure characteristics.

[0015] As a preferred embodiment of the present invention, the bottom of the extraction electrode is located on the upper surface of the hole storage layer, and the bottom of the second source electrode is located on the upper surface of the hole storage layer.

[0016] As a preferred embodiment of the present invention, the extraction electrodes with the bottom located on the upper surface of the hole storage layer and the extraction electrodes with the bottom located inside the channel layer are arranged at intervals in sequence, and the bottom of the second source electrode is located on the upper surface of the hole storage layer.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1) The present invention introduces a hole storage layer between the buffer layer and the channel layer to form a hole potential well, which can effectively collect the irradiation-induced excess holes in the channel layer, prevent them from accumulating between the gate and the source and in the vicinity of the gate, realize the regulation of the irradiation-induced excess holes, suppress the back barrier effect, and improve the single-event irradiation resistance of the device.

[0019] 2) The present invention provides extraction electrodes between the gates arranged at intervals, a second source electrode is provided near the first source electrode, and the extraction electrodes, the second source electrode and the first source electrode are connected by a metal interconnection layer, which can efficiently extract the irradiation-induced holes caused by single-particle incidence between the gate and the source and in the vicinity of the gate, further suppress the back barrier effect, and thus improve the single-event irradiation resistance of the device.

[0020] 3) The manufacturing process of the device structure in the present invention is completely compatible with the traditional process, and no additional complex process steps need to be introduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0022] Figure 1(a) is a schematic diagram of Embodiment 1 of the present invention.

[0023] Figure 1(b) is a cross-sectional view of AA' in Figure 1(a), which shows the functions of the hole storage layer, extraction electrode, and second source electrode for collecting and extracting irradiation-induced holes.

[0024] Figure 1(c) is a cross-sectional view of BB' in Figure 1(a).

[0025] Figure 1(d) is a schematic diagram of the energy band structure from the p-GaN layer to the buffer layer in Embodiment 1 of the present invention.

[0026] Figure 2 is a schematic diagram of Step 1 of the present invention.

[0027] Figure 3 is a schematic diagram of Step 2 of the present invention.

[0028] Figure 4 is a schematic diagram of Step 3 of the present invention.

[0029] Figure 5 is a schematic diagram of Step 4 of the present invention.

[0030] Figure 6 is a schematic diagram of Step 5 of the present invention.

[0031] Figure 7 is a schematic diagram of Step 6 of the present invention.

[0032] Figure 8 is a schematic diagram of Step 7 of the present invention.

[0033] Figure 9 is a schematic diagram of Step 8 of the present invention.

[0034] Figure 10 is a schematic diagram of Step 9 of the present invention.

[0035] Figure 11 is a schematic diagram of Step 10 of the present invention.

[0036] Figure 12 is a schematic diagram of Step 11 of the present invention.

[0037] Figure 13 is a schematic diagram of Step 12 of the present invention.

[0038] Figure 14 is a schematic diagram of Step 13 of the present invention.

[0039] Figure 15 is a schematic diagram of Step 14 of the present invention.

[0040] Figure 16 is a schematic diagram of Step 15 of the present invention.

[0041] Figure 17 It is a schematic diagram of step 16 of the present invention.

[0042] Figure 18(a) is a schematic diagram of Embodiment 2 of the present invention.

[0043] Figure 18(b) is a cross-sectional view of AA' in Figure 18(a).

[0044] Figure 18(c) is a cross-sectional view of BB' in Figure 18(a).

[0045] Figure 18(d) is a cross-sectional view of CC' in Figure 18(a).

[0046] Figure 19(a) is a schematic diagram of Embodiment 3 of the present invention.

[0047] Figure 19(b) is a cross-sectional view of AA' in Figure 19(a).

[0048] Figure 19(c) is a cross-sectional view of BB' in Figure 19(a).

[0049] In the figure: 1. Substrate; 2. Buffer layer; 3. Hole storage layer; 4. Channel layer; 5. Barrier layer; 6. First passivation layer; 7. First source electrode; 8. Drain electrode; 9. p-GaN layer; 10. Gate electrode; 11. Extraction electrode; 12. Second source electrode; 13. Metal interconnection layer; 14. Second passivation layer. Detailed implementation manners

[0050] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0051] The preparation processes of the present invention are all existing processes. The preparation method of the present invention includes the following steps:

[0052] 1) Select a substrate layer. The materials of the substrate layer include, but are not limited to, one of materials such as silicon, silicon carbide, sapphire, gallium nitride, gallium oxide, and diamond, or several of these materials, or other complex materials with the above material components, or composite material substrates such as QST substrates. The size of the substrate layer includes, but is not limited to, two inches, four inches, and six inches.

[0053] 2) The growth methods of the buffer layer include, but are not limited to, one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth process of the buffer layer includes, but is not limited to, growing one of the ternary nitrides such as AlN, AlGaN, GaN, InN, InGaN, InAlN or two-dimensional materials, or several of them, or other complex materials with the above material components at a temperature of 0 - 1500 °C and a pressure of 0 - 300 Torr as the device buffer layer. The buffer layer structure consists of at least one layer of material, and includes, but is not limited to, one of various complex structure designs such as an AlGaN stress relaxation layer with a gradually changing Al composition, a superlattice structure, a low-temperature grown AlN structure, etc., or a combination of several of these complex structures, or other complex structures with the above structural characteristics.

[0054] 3) The growth methods of the hole storage layer include, but are not limited to, one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth process of the hole storage layer includes, but is not limited to, growing one of the ternary nitrides such as AlN, AlGaN, GaN, InN, InGaN, InAlN or two-dimensional materials, or several of them, or other complex materials with the above material components at a temperature of 0 - 1500 °C and a pressure of 0 - 300 Torr as the device hole storage layer. The hole storage layer consists of at least one layer of semiconductor material and includes, but is not limited to, various complex structure designs.

[0055] 4) The growth methods of the channel layer include, but are not limited to, one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth process of the channel layer includes, but is not limited to, growing one of the ternary nitrides such as AlN, AlGaN, GaN, InN, InGaN, InAlN or two-dimensional materials, or several of them, or other complex materials with the above material components at a temperature of 0 - 1500 °C and a pressure of 0 - 300 Torr as the device channel layer. The channel layer consists of at least one layer of semiconductor material and includes, but is not limited to, various complex structure designs.

[0056] 5) The growth method of the barrier layer includes, but is not limited to, one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth process of the barrier layer includes, but is not limited to, growing one of the group III nitrides such as AlN, AlGaN, GaN, InN, InGaN, InAlN or two-dimensional materials, or several of them, or other complex materials with the above material components as the device barrier layer under the conditions of a temperature of 0 to 1500 °C and a pressure of 0 to 300 Torr. The barrier layer is composed of at least one layer of semiconductor material and includes, but is not limited to, various complex structure designs.

[0057] 6) The growth method of the p-GaN layer includes, but is not limited to, one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth process of the p-GaN layer includes, but is not limited to, growing the p-GaN layer under the conditions of a temperature of 0 to 1500 °C and a pressure of 0 to 300 Torr. The p-GaN layer is composed of at least one layer of semiconductor material and includes, but is not limited to, various complex structure designs.

[0058] 7) The etching method of the p-GaN layer includes, but is not limited to, one of the etching methods such as RIE, ICP, hydrogen fluoride release etching, wet etching, etc., or a combination of several etching methods, or other complex process flows involving multiple etching methods. The etching process of the p-GaN layer includes, but is not limited to, etching the p-GaN layer under the conditions of an RF power of 0 to 600 W and a pressure of 0 to 100 mTorr.

[0059] 8) The growth method of the first source and drain includes, but is not limited to, one or a combination of coating methods such as E-beam evaporation deposition, Sputter, LPCVD, PLD, ALD, PEALD, etc., or other complex process flows involving multiple coating methods. The growth process of the first source and drain includes, but is not limited to, growing one of the materials such as Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, etc., or several of them, or other complex materials with the above material components as the device first source and drain under the conditions of a temperature of 0 to 1200 °C and a pressure of 0 to 300 Torr. The annealing method includes, but is not limited to, annealing at 95 to 1500 °C.

[0060] 9) The deposition methods of the first passivation layer and the second passivation layer include, but are not limited to, one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The deposition process of the first passivation layer and the second passivation layer includes, but is not limited to, depositing at a temperature of 0 - 1500 °C and a pressure of 0 - 300 Torr, including, but not limited to, (Al x Ga 1-x )2O3, Al2O3, AlN, SiN x , SiO2, HfO2, ZrO2, SOG, PI, SiON, HfZrO, etc. as one of the materials, or several of these materials, or a composite material composed of other various materials with the above material components as the first passivation layer and the second passivation layer of the device. The structure of the first passivation layer and the second passivation layer consists of at least one layer and includes, but is not limited to, various complex structure designs.

[0061] 10) The etching methods of the first passivation layer and the second passivation layer include, but are not limited to, one of the etching methods such as RIE, ICP, hydrogen fluoride release etching, wet etching, etc., or a combination of several etching methods, or other complex process flows involving multiple etching methods. The etching process of the first passivation layer and the second passivation layer includes, but is not limited to, etching the first passivation layer and the second passivation layer under the conditions of RF power of 0 - 600 W and pressure of 0 - 100 mTorr.

[0062] 11) The growth methods of the gate include, but are not limited to, one or a combination of coating methods such as E-beam evaporation deposition, Sputter, LPCVD, PLD, ALD, PEALD, etc., or other complex process flows involving multiple coating methods. The growth process of the gate includes, but is not limited to, growing at a temperature of 0 - 1200 °C and a pressure of 0 - 300 Torr, including, but not limited to, one of the materials such as Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, etc., or several of these materials, or other complex materials with the above material components as the gate of the device. The annealing method includes, but is not limited to, annealing at 95 - 1500 °C.

[0063] 12) The etching methods of the buffer layer, the hole storage layer, the channel layer, and the barrier layer include, but are not limited to, one of the etching methods such as RIE, ICP, hydrogen fluoride release etching, wet etching, etc., or a combination of several etching methods, or other complex process flows involving multiple etching methods. The etching process of the buffer layer, the hole storage layer, the channel layer, and the barrier layer includes, but is not limited to, etching under the conditions of RF power of 0 - 600 W and pressure of 0 - 100 mTorr.

[0064] 13) The growth methods of the extraction electrode, the second source electrode, and the metal interconnection layer include, but are not limited to, one or a combination of coating methods such as E-beam evaporation deposition, Sputter, LPCVD, PLD, ALD, PEALD, etc., or other complex process flows involving multiple coating methods. The growth process of the extraction electrode, the second source electrode, and the metal interconnection layer includes, but is not limited to, growing one, several, or other complex materials with the above material components as the device extraction electrode, the second source electrode, and the metal interconnection layer under the conditions of a temperature of 0 to 1200 °C and a pressure of 0 to 300 Torr. The annealing method includes, but is not limited to, annealing at 95 to 1500 °C.

[0065] Example 1

[0066] See Figure 1(a) - Figure 1(c) The present invention provides a group-III nitride device. The group-III nitride device includes, from bottom to top, a substrate 1, a buffer layer 2, a hole storage layer 3, a channel layer 4, a barrier layer 5, and a first passivation layer 6. A first source electrode 7 and a drain electrode 8 are respectively arranged on both sides of the channel layer 4. A p-GaN layer 9 is arranged near the first source electrode 7 between the first source electrode 7 and the drain electrode 8. Gates 10 arranged at intervals in the y direction are arranged on the p-GaN layer 9. Etching holes are arranged between the gates 10 arranged at intervals, and extraction electrodes 11 are arranged in the etching holes. The extraction electrodes 11 are in contact with the side walls and the bottom along the etching holes. A second source electrode 12 is further arranged near the first source electrode 7. The second source electrode 12 is connected to the first source electrode 7 and the extraction electrodes 11 through a metal interconnection layer 13. Except for the top surfaces of the extraction electrodes 11, the first source electrode 7, the second source electrode 12, and the drain electrode 8, the remaining areas of the surface are filled with a second passivation layer 14.

[0067] FIG. 1(d) is a schematic diagram of the energy band structure from the p-GaN layer to the buffer layer of Example 1 of the present invention. It can be seen from the figure that the hole storage layer forms a hole potential well in the energy band structure and can effectively collect the radiation-induced excess holes in the channel layer.

[0068] In this embodiment, the p-GaN layer has a size of 3 μm in the x direction and 60 μm in the y direction. The number of gates arranged at intervals on the p-GaN layer is 4, and the number of extraction electrodes arranged at intervals is 4. The opening shape of each gate on the first passivation layer is rectangular, with a size of 2 μm in the x direction and 5 μm in the y direction. The gate metal completely covers the opening of each gate on the first passivation layer, and except for the side close to the drain, the edge of the gate metal extends 0.2 μm from the sidewall of the corresponding first passivation layer gate opening in the corresponding direction, and the gate metal extends 0.5 μm from the side of the p-GaN layer close to the drain.

[0069] The bottom of the etching hole of the extraction electrode is located on the upper surface of the hole storage layer. The opening shapes of the etching holes on the first and second passivation layers are both rectangular, with a size of 2 μm in the x direction and 6 μm in the y direction, and the opening shapes and sizes of each extraction electrode on the first passivation layer and the second passivation layer are the same. The shapes of the etching holes for forming the extraction electrodes on the buffer layer, hole storage layer, channel layer, and barrier layer are all rectangular, with a size of 1.2 μm in the x direction and 5 μm in the y direction. The distance between the gate adjacent to the etching hole and the sidewall of the etching hole is 2.5 μm.

[0070] The distance between the gate and the first source is 3 μm, and the distance between the gate and the drain is 15 μm; the size of the first source and the drain in the x direction is 3 μm; the distance between the second source and the first source is 1 μm, the size of the second source in the x direction is 3 μm, and the bottom of the second source is located on the upper surface of the storage layer.

[0071] The distance between the metal interconnection layer that connects the extraction electrode, the second source, and the first source and the drain on the side close to the drain is 12 μm.

[0072] The substrate material of the device of the present invention includes, but is not limited to, one of silicon, silicon carbide, sapphire, gallium nitride, gallium oxide, diamond, etc., or several of these materials, or other complex materials with the above material components, or composite material substrates such as QST substrates. In this embodiment, silicon is selected as the substrate.

[0073] The buffer layer of the device of the present invention includes, but is not limited to, one of materials such as group III nitrides like AlN, AlGaN, GaN, InN, InGaN, InAlN, or two-dimensional materials, or several of these materials, or other complex materials having the above material components. The buffer layer structure of the device of the present invention consists of at least one layer of material, and also includes, but is not limited to, one of various complex structure designs such as an AlGaN stress relaxation layer with a gradually changing Al composition, a superlattice structure, a low-temperature grown AlN structure, or a combination of several of these complex structures, or other complex structures having the above structural characteristics. In this embodiment, an AlN layer with a thickness of 50 nm and a GaN layer with a thickness of 3000 nm are selected as the buffer layer from bottom to top.

[0074] The hole storage layer of the device of the present invention includes, but is not limited to, one of materials such as group III nitrides like AlN, AlGaN, GaN, InN, InGaN, InAlN, or two-dimensional materials, or several of these materials, or other complex materials having the above material components. The hole storage layer is composed of at least one layer of semiconductor material, and also includes, but is not limited to, various complex structure designs. In this embodiment, AlGaN with an Al composition of 0.2 and a thickness of 10 nm is selected as the hole storage layer.

[0075] The channel layer of the device of the present invention includes, but is not limited to, one of materials such as group III nitrides like AlN, AlGaN, GaN, InN, InGaN, InAlN, or two-dimensional materials, or several of these materials, or other complex materials having the above material components. The channel layer is composed of at least one layer of semiconductor material, and also includes, but is not limited to, various complex structure designs. In this embodiment, GaN with a thickness of 300 nm is selected as the channel layer.

[0076] The barrier layer of the device of the present invention includes, but is not limited to, one of materials such as group III nitrides like AlN, AlGaN, GaN, InN, InGaN, InAlN, or two-dimensional materials, or several of these materials, or other complex materials having the above material components. The barrier layer is composed of at least one layer of semiconductor material, and also includes, but is not limited to, various complex structure designs. In this embodiment, an AlGaN layer with an Al composition of 0.2 and a thickness of 15 nm is selected as the barrier layer.

[0077] The Mg doping concentration of the p-GaN layer of the device of the present invention can be 1×10 17 ~1×10 21 cm -3 、 and the thickness can be 0 - 500 nm. In this embodiment, a p-GaN layer with a doping concentration of 1×10 19 cm -3 and a thickness of 100 nm is selected.

[0078] The gate material of the device of the present invention includes, but is not limited to, one of the materials such as Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, or several of these materials, or other complex materials having the above material components. The gate structure of the device of the present invention includes, but is not limited to, one or a combination of several of the Schottky-type p-GaN gate, ohmic p-GaN gate, recessed gate, MIS gate, or other complex gate structures having the above gate characteristics. In this embodiment, 20 nm of Ni and 80 nm of Au are selected as the gate metal of the device to form a Schottky contact with the p-GaN layer.

[0079] The first source and drain materials of the device of the present invention include, but are not limited to, one of the materials such as Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, or several of these materials, or other complex materials having the above material components. The drain structure of the device of the present invention includes, but is not limited to, one or a combination of two of the Schottky drain, ohmic drain, or other complex drain structures having the characteristics of the Schottky drain and ohmic drain. The first source structure of the device of the present invention includes, but is not limited to, one or a combination of two of the Schottky source, ohmic source, or other complex source structures having the characteristics of the Schottky source and ohmic source. In this embodiment, 20 nm of Ti, 150 nm of Al, 50 nm of Ni, and 80 nm of Au are selected as the first source and drain metals of the device to form an ohmic contact with the channel layer.

[0080] The second source material of the device of the present invention includes, but is not limited to, one of the materials such as Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, or several of these materials, or other complex materials having the above material components. The source structure of the device of the present invention includes, but is not limited to, one or a combination of two of the Schottky source, ohmic source, or other complex source structures having the characteristics of the Schottky source and ohmic source. In this embodiment, 20 nm of Ni and 200 nm of Au are selected as the second source material of the device to form a Schottky contact with the semiconductor layer on the sidewall and bottom of the etched hole.

[0081] The extraction electrode material of the device of the present invention includes, but is not limited to, one of the materials such as Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, or several of these materials, or other complex materials having the above material components. In this embodiment, 20 nm of Ni and 200 nm of Au are selected as the extraction electrode material of the device to form a Schottky contact with the semiconductor layer on the sidewall and bottom of the etched hole.

[0082] The metal interconnect layer material of the device of the present invention includes, but is not limited to, one of the materials such as Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, or several of these materials, or other complex materials having the above material components. In this embodiment, 20 nm of Ni and 200 nm of Au are selected as the metal interconnect layer material of the device.

[0083] See Figure 2 - Figure 16 , this embodiment provides a preparation process for a group III nitride device with anti-single particle irradiation ability, and a group III nitride device as shown in Figure 1(a) - Figure 1(c) is prepared, and the specific steps are as follows:

[0084] 1) Select a substrate. In this embodiment, a two-inch Si(111) is used as the substrate. First, it is put into a mixed solution of three parts of sulfuric acid, one part of hydrogen peroxide, and one part of water for pickling, then put into a 5% hydrofluoric acid solution to remove the surface oxide, and finally the surface of the substrate is cleaned successively with acetone, isopropyl alcohol, and absolute ethanol, and finally placed in water, taken out and dried, as shown in Figure 2 .

[0085] 2) Grow a buffer layer. In this embodiment, trimethylaluminum (TMAl) and NH3 are introduced into the MOCVD reaction chamber, and an AlN layer with a thickness of 50 nm is grown on the substrate at a temperature of 1120 °C and a pressure of 70 Torr. Stop introducing TMAl, keep introducing NH3, and raise the temperature to 1200 °C for high-temperature treatment. After growing the AlN layer, trimethylgallium (TMGa) and NH3 are introduced into the MOCVD reaction chamber, and a GaN layer with a thickness of 3000 nm is grown at a temperature of 900 °C and a pressure of 70 Torr, as shown in Figure 3 .

[0086] 3) Grow a hole storage layer. In this embodiment, after growing the buffer layer, TMAl is gradually introduced into the MOCVD reaction chamber and TMGa is reduced, and AlGaN with an Al composition of 0.20 and a thickness of 10 nm is grown as the hole storage layer at a temperature of 960 °C and a pressure of 70 Torr, as shown in Figure 4 .

[0087] 4) Grow a channel layer. In this embodiment, after growing the hole storage layer, TMGa and NH3 are introduced into the MOCVD reaction chamber, and GaN with a thickness of 300 nm is grown as the channel layer at a temperature of 900 °C and a pressure of 70 Torr, as shown in Figure 5 .

[0088] 5) Growth of the barrier layer. In this embodiment, after growing the channel layer, TMAl is gradually introduced into the MOCVD reaction chamber and TMGa is reduced. AlGaN with an Al composition of 0.20 and a thickness of 15 nm is grown as the barrier layer at a temperature of 960 °C and a pressure of 70 Torr, as shown in Figure 6 .

[0089] 6) Growth of the p-GaN layer. In this embodiment, after growing the barrier layer, the p-GaN layer is epitaxially grown. TMGa, bis(cyclopentadienyl)magnesium (Cp2Mg), NH3, and H2 are introduced into the MOCVD reaction chamber. The p-GaN layer with a doping concentration of 1×10 19 cm -3 and a thickness of 100 nm is grown at a temperature of 940 °C and a pressure of 70 Torr, and annealed at a temperature of 700 °C, as shown in Figure 7 .

[0090] 7) Etching of the p-GaN layer. In this embodiment, after growing the p-GaN layer, ICP etching is performed to partially remove the p-GaN. The ICP power is set to 100 W, the pressure is 5 mTorr, and Cl2, O2, and Ar are introduced, as shown in Figure 8 .

[0091] 8) Etching and deposition of the drain and the first source. ICP etching is used to remove the barrier layer in the regions under the first source and the drain. The ICP power is set to 100 W, the pressure is 5 mTorr, and Cl2, O2, and Ar are introduced. E-beam evaporation deposition is used to sequentially deposit 20 nm of Ti, 150 nm of Al, 50 nm of Ni, and 80 nm of Au. The metal in the regions other than the first source and the drain is selectively removed by lift-off and annealed at 830 °C, as shown in Figure 9 .

[0092] 9) Growth of the first passivation layer. PECVD is used to deposit 80 nm of SiO2 as the first passivation layer by introducing N2O and 5% SiH4 / N2 at a temperature of 300 °C and a pressure of 850 mTorr, as shown in Figure 10 .

[0093] 10) Etching of the first passivation layer. RIE etching is used to remove the first passivation layer in the gate region, extraction electrode region, first source region, drain region, and second source region. The RIE power is set to 200 W, the pressure is 3 - 10 mTorr, and CHF3 and Ar are introduced, as shown in Figure 11 .

[0094] 11) Deposition of the gate. E-beam evaporation deposition is used to sequentially deposit 20 nm of Ni and 80 nm of Au. The metal in the regions other than the gate is selectively removed by lift-off and annealed at 300 °C, as shown in Figure 12 .

[0095] 12) Grow the second passivation layer. Use PECVD to deposit 500 nm of SiO2 as the second passivation layer by introducing N2O and 5% SiH4 / N2 at a temperature of 300 °C and a pressure of 850 mTorr, as Figure 13 .

[0096] 13) Etch the second passivation layer. Use RIE etching to remove the second passivation layer in the extraction electrode region, the first source region, the drain region, and the second source region. Set the RIE power to 200 W, the pressure to 3 - 10 mTorr, and introduce CHF3 and Ar, as Figure 14 .

[0097] 14) Etch the barrier layer and the channel layer in the second source region. Use ICP etching to remove the barrier layer and the channel layer in the second source region. In this embodiment, etch to the upper surface of the hole storage layer. Set the ICP power to 100 W, the pressure to 5 mTorr, and introduce Cl2, O2, and Ar, as Figure 15 .

[0098] 15) Etch the barrier layer and the channel layer in the extraction electrode region. Use ICP etching to remove the barrier layer and the channel layer in the extraction electrode region. In this embodiment, etch to the upper surface of the hole storage layer. Set the ICP power to 100 W, the pressure to 5 mTorr, and introduce Cl2, O2, and Ar, as Figure 16 .

[0099] 16) Deposit the extraction electrode, the second source, and the metal interconnection layer. Use E-beam evaporation to deposit 20 nm of Ni and 200 nm of Au in sequence. Selectively remove the metal in the regions other than above the extraction electrode, the second source, the metal interconnection layer, the first source, and the drain by lift-off, as Figure 17 .

[0100] Example 2

[0101] As Figure 18(a) - Figure 18(d) , in this embodiment, the extraction electrodes 11 with the bottom located on the upper surface of the hole storage layer 3 and the extraction electrodes 11 with the bottom located inside the channel layer 4 are arranged alternately in sequence. The bottom of the second source 12 is located on the upper surface of the hole storage layer 3. The manufacturing process is the same as that of Example 1.

[0102] Example 3

[0103] As Figure 19(a) - Figure 19(c) , in this embodiment, the bottom of the extraction electrode 11 is located inside the buffer layer 2, and the bottom of the second source 12 is located inside the channel layer 4. The manufacturing process is the same as that of Example 1.

[0104] The above embodiments are only some possible structures of the present invention. In practical applications, parameters such as the material selection, thickness, and doping concentration design of each layer, as well as the specific HEMT structure design (such as whether there are other semiconductor layers between the buffer layer, hole storage layer, channel layer, and barrier layer, whether there are other semiconductor layers between the substrate and the buffer layer, other gate types, SOI structure devices, graded semiconductor layer components, drain-like designs), the size ratio of the extraction electrode relative to the p-GaN layer in the y direction, the depth of the etching hole specifically forming the extraction electrode, the shape and size of the etching hole specifically forming the extraction electrode, the shape and size of the specific gate, the shape and size of the specific gate electrode, the spacing between the specific extraction electrode and the gate electrode, the depth of the specific second source electrode, the shape and size of the specific second source electrode, the shape and size of other key structures, the type of metal-semiconductor contact, and the position, depth, and shape of the metal-semiconductor contact formation can be appropriately changed according to different application conditions. In addition, the buffer layer, hole storage layer, channel layer, and barrier layer mean that there should be at least one layer structure in this layer, rather than only one layer structure. Without departing from the principle of the present invention, these changes should also be regarded as the protection scope of the present invention.

[0105] As mentioned above, the above are only the preferred embodiments of the present invention, and there is no limitation in any form and essence to the present invention. It should be pointed out that for those of ordinary skill in the art in this technical field, without departing from the method of the present invention, several improvements and supplements can still be made, and these improvements and supplements should also be regarded as the protection scope of the present invention. Any equivalent changes such as slight modifications, decorations, and evolutions made by those skilled in the art who are familiar with this specialty without departing from the spirit and scope of the present invention by using the technical content disclosed above are all equivalent embodiments of the present invention; at the same time, any equivalent changes, modifications, and evolutions made to the above embodiments based on the substantial technology of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A III-nitride device having single particle irradiation resistance, characterized in that: The III-group nitride device comprises, from bottom to top, a substrate, a buffer layer, a hole storage layer, a channel layer, a barrier layer, a p-GaN layer and a first passivation layer. A first source and a drain are provided on both sides of the channel layer, respectively. The p-GaN layer is located between the first source and the drain and close to the first source. The p-GaN layer is provided with gates arranged at intervals along the y direction. Etching holes are provided between the gates arranged at intervals. The etching holes are etched to the channel layer, the hole storage layer or the buffer layer. Extraction electrodes are provided in the etching holes. The extraction electrodes are in contact with the side walls and the bottom of the etching holes along the etching holes. A second source is also provided near the first source. The second source is connected to the first source and the extraction electrode through a metal interconnection layer. Except for the top surfaces of the extraction electrode, the first source, the second source and the drain, the remaining surface areas are filled with a second passivation layer.

2. A III-nitride device with single particle irradiation resistance according to claim 1, characterized in that: The bottom of the etching hole is located on the upper surface or inside of the buffer layer; or the bottom of the etching hole is located on the upper surface or inside of the hole storage layer; or the bottom of the etching hole is located on the upper surface or inside of the channel layer.

3. A III-nitride device with single particle irradiation resistance according to claim 1, characterized in that: Adjacent etched holes have the same depth.

4. A III-nitride device with single particle irradiation resistance according to claim 1, characterized in that: Adjacent etched holes have different depths.

5. The III-nitride device with single particle irradiation resistance according to claim 1, characterized in that: The extraction electrode forms a Schottky contact or an Ohmic contact with the semiconductor layer at the sidewall and bottom of the etched hole.

6. A III-nitride device with single particle irradiation resistance according to claim 1, characterized in that: The second source electrode extends into the buffer layer through the barrier layer, the channel layer and the hole storage layer; or the second source electrode extends into the hole storage layer through the barrier layer and the channel layer; or the second source electrode extends into the channel layer through the barrier layer; or the second source electrode passes through the barrier layer, the channel layer and the hole storage layer to contact the upper surface of the buffer layer; or the second source electrode passes through the barrier layer and the channel layer to contact the upper surface of the hole storage layer; or the second source electrode passes through the barrier layer to contact the upper surface of the channel layer.

7. A III-nitride device with single particle irradiation resistance according to claim 1, characterized in that: The shape of the etched cross section of the etched hole in the xy plane is circular, elliptical, polygonal or other irregular edge shapes, and the shapes and sizes of the etched cross sections of adjacent etched holes in the xy plane are the same or different.

8. The III-nitride device with single particle irradiation resistance according to claim 1, characterized in that: The gate is one of a Schottky-type p-GaN gate, an ohmic-type p-GaN gate, a recessed gate structure, and a MIS gate, or a combination of the two.

9. A III-nitride device having single particle irradiation resistance according to any one of claims 1 to 8, characterized in that: The bottom of the extraction electrode is located on the upper surface of the hole storage layer, and the bottom of the second source electrode is located on the upper surface of the hole storage layer.

10. A III-nitride device having single particle irradiation resistance according to any one of claims 1 to 8, characterized in that: The extraction electrode with its bottom located on the upper surface of the hole storage layer and the extraction electrode with its bottom located inside the channel layer are arranged in sequence and spaced apart, and the bottom of the second source electrode is located on the upper surface of the hole storage layer.

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