A semiconductor terminal structure with embedded FLR buried JTE, its manufacturing method and semiconductor device

Abstract

The present invention provides a semiconductor terminal structure with an embedded FLR buried JTE, a method for manufacturing the same, and a semiconductor device, belonging to the field of semiconductor device technology. The semiconductor terminal structure comprises a substrate, an epitaxial layer, and an interlayer dielectric layer stacked in sequence; a buried layer and a well region located above the buried layer are provided in the epitaxial layer; the buried layer is divided into multiple buried suspended JTE partitions by a separation region; and a plurality of field limiting rings are provided in at least the epitaxial layer closest to the main junction region of the semiconductor device. The substrate, epitaxial layer, and separation region are all doped with the first type; the buried layer, well region, and field limiting rings are all doped with the second type. This structural design enables better distribution of the electric field of the semiconductor device, reduces the degree of electric field concentration, and improves the device's voltage resistance.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and particularly relates to a semiconductor terminal structure with an embedded FLR buried JTE, a manufacturing method thereof, and a semiconductor device including the semiconductor terminal structure. Background Art

[0002] The curvature effect of the pn junction in wide-bandgap semiconductor devices causes electric field concentration at the junction edge, severely degrading the device's reverse blocking capability. This in turn causes premature device breakdown, significantly reducing the device's withstand voltage. To address this issue, terminal structures are typically designed into semiconductor devices to adjust the electric field distribution and increase the device's breakdown voltage.

[0003] Currently, the most common termination structures used in commercial wide-bandgap semiconductor devices (such as silicon carbide devices) are field-limiting rings (FLRs) and / or junction termination extensions (JTEs). While a termination design with only a field-limiting ring (FLR) is simple to implement and offers relatively stable device performance, it requires more chip area and reduces chip utilization. A termination design with only a JTE, while offering higher efficiency, is more sensitive to cross-sectional charge and requires a more complex fabrication process, resulting in higher manufacturing costs. Therefore, a combined FLR and JTE termination structure can better mitigate electric field concentration.

[0004] However, with the diversification of epitaxial structures in wide-bandgap semiconductor devices, especially in trench MOSFETs (metal-oxide-semiconductor field-effect transistors), the design of doped regions to protect the trench gate corners has made it impossible to use conventional FLR or JTE structures in the device's terminal region. This is because the epitaxial structure protecting the trench gate corners will shield all FLR and JTE functions, causing the terminal structure to fail. Summary of the Invention

[0005] To address the aforementioned technical issues, the present invention provides a semiconductor terminal structure with an embedded FLR and buried JTE. This semiconductor terminal structure can be stably applied to semiconductor devices with gate corner protection zones, optimizes the device's electric field distribution, and increases its breakdown voltage. It also reduces the device's sensitivity to interface charge, improving its overall performance.

[0006] Specifically, in order to achieve the above-mentioned purpose, the present invention adopts the following technical solutions:

[0007] A wide bandgap semiconductor terminal structure with an embedded FLR buried JTE comprises a substrate, an epitaxial layer and an interlayer dielectric layer stacked in sequence; a buried layer and a well region located above the buried layer are provided in the epitaxial layer; the buried layer is divided into a plurality of buried suspended JTE partitions by a separation region; a plurality of field limiting rings are provided in at least the epitaxial layer closest to the main junction region of the semiconductor device; the substrate, the epitaxial layer and the separation region are all doped with a first type; the buried layer, the well region and the field limiting rings are all doped with a second type.

[0008] In a preferred solution, the separation region is a first doping region, and the doping concentration of the first doping region is greater than the doping concentration of the epitaxial layer.

[0009] In a further preferred embodiment, the first doped region is a multi-layer structure, and the size of each layer along the direction from the substrate to the interlayer dielectric layer is different.

[0010] In a preferred solution, an electric field blocking layer is provided in the epitaxial layer between the buried layer and the well region.

[0011] In a preferred solution, a first trench is provided in the field limiting ring; and the first trench is filled with the interlayer dielectric layer.

[0012] In a further preferred embodiment, the first groove is a multi-level groove.

[0013] The present invention also provides a method for preparing the wide bandgap semiconductor terminal structure with embedded FLR and buried JTE, comprising the following steps:

[0014] S1. Growing an epitaxial layer on a substrate and forming a buried layer in the epitaxial layer; the buried layer divides the epitaxial layer into a first epitaxial layer located below the buried layer and a second epitaxial layer located above the buried layer; forming a separation region in the buried layer to obtain a buried suspended JTE partition;

[0015] S2. forming a well region in an upper layer of the second epitaxial layer;

[0016] S3, forming an embedded FLR partition consisting of a plurality of field limiting rings in the epitaxial layer closest to the main junction region of the semiconductor device;

[0017] S4. Depositing an interlayer dielectric layer on the upper surface of the second epitaxial layer.

[0018] The present invention also provides a wide bandgap semiconductor terminal structure semiconductor device comprising the embedded FLR buried JTE.

[0019] In a preferred solution, the semiconductor device includes a second doping region in the epitaxial layer of the main junction region, and the doping type of the second doping region is the second type.

[0020] In a further preferred solution, a second trench is provided in the second doping region, and the second trench is filled with the interlayer dielectric layer.

[0021] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0022] (1) In the present invention, a composite terminal structure of embedded FLR buried JTE is designed, and the size of each buried suspended JTE partition along the direction from the main junction region to the terminal region is adjusted, as well as the number of FLRs in each embedded FLR partition, the doping width of each FLR and the spacing between two adjacent FLRs are adjusted, so that the electric field of the device is better distributed, the degree of electric field concentration is reduced, and the voltage resistance of the device is improved.

[0023] (2) The separation area in the buried layer that is farthest from the main junction area (or closest to the scribe area) serves as the electric field cutoff area, which can prevent charges from entering the scribe area and avoid leakage of the device; at the same time, it can also quickly cut off the electric field, thereby achieving the purpose of alleviating the electric field strength and adjusting the electric field distribution.

[0024] (3) The well region can reduce the sensitivity of the terminal structure to the interface charge and prevent the electric field from gathering from the separation region to the device surface. At the same time, the well region can also serve as a JTE structure to further optimize the electric field distribution inside the device and improve the device's voltage resistance.

[0025] (4) The electric field blocking layer can further block the electric field passing through the separation region and optimize the electric field distribution inside the device, thereby further improving the breakdown characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1 to 4 A diagram showing the process of preparing a semiconductor terminal structure in Example 3 of the present invention;

[0027] Figure 5 A schematic structural diagram of a semiconductor device including a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE provided by the present invention;

[0028] Figure 6 A schematic structural diagram of another semiconductor device provided by the present invention including a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE;

[0029] Figure 7 A schematic structural diagram of another semiconductor device provided by the present invention including a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE;

[0030] Figure 8A schematic structural diagram of another semiconductor device provided by the present invention including a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE;

[0031] Figure 9 A schematic structural diagram of another semiconductor device provided by the present invention including a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE;

[0032] Figure 10 A schematic structural diagram of another semiconductor device provided by the present invention including a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE;

[0033] Figure 11 A schematic structural diagram of another semiconductor device provided by the present invention including a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE;

[0034] Figure 12 A schematic structural diagram of another semiconductor device provided by the present invention including a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE;

[0035] Figure 13 A schematic structural diagram of another semiconductor device provided by the present invention including a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE;

[0036] Figure 14 A schematic structural diagram of another semiconductor device provided by the present invention including a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE;

[0037] Figure 15 A schematic structural diagram of another semiconductor device provided by the present invention including a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE;

[0038] Figure 16 Schematic diagram of the preparation process of forming a buried layer in the epitaxial layer in step S1 of embodiment 3 of the present invention.

[0039] In the figure: 1. Substrate; 2. Epitaxial layer; 201. First epitaxial layer; 202. Second epitaxial layer; 3. Interlayer dielectric layer; 4. Buried layer; 401. Buried suspended JTE partition; 5. Well region; 6. Separation region; 601. First doped region; 7. Embedded FLR partition; 701. Field limiting ring; 8. Electric field blocking layer; 9. Anode; 10. Cathode; 11. Second doped region. DETAILED DESCRIPTION

[0040] The following content clearly and completely describes the technical solution of the present application in conjunction with the embodiments so that those skilled in the art can fully understand the present application. Obviously, the embodiments described are only some preferred embodiments of the present application, rather than all embodiments. Any equivalent transformation or substitution made by those of ordinary skill in the art to the following embodiments without creative work falls within the scope of protection of the present application.

[0041] Directional terms used in this application, such as "upper," "lower," "inner," "outer," "bottom," and "upper surface," indicate positions or locations based on the figures in the specification or the positions or locations in which the product of this application is typically placed when in use. These terms are intended solely to facilitate description and understanding of the product structure of this application. Therefore, these directional terms should not be construed as limiting this application. In this application, unless otherwise expressly defined, expressions such as "upper," "above," "above," and "upper surface" of a first feature relative to a second feature indicate that the first and second features may be in direct contact or indirect contact through an intermediary; that the first feature may be directly above or obliquely above the second feature, or simply indicate that the first feature is at a higher level than the second feature. Expressions such as "lower," "below," "below," and "lower surface" of a first feature relative to a second feature indicate that the first and second features may be in direct contact or indirect contact through an intermediary; that the first feature may be directly below or obliquely below the second feature, or simply indicate that the first feature is at a lower level than the second feature. The ordinal numbers used in this application, such as "first" and "second," are used solely for descriptive purposes to distinguish similar objects and are not to be construed as indicating or implying relative importance or implicitly indicating the quantity of the technical features indicated. Methods not described in detail in the following examples are conventional methods well known to those skilled in the art.

[0042] Example 1

[0043] Reference Figure 5 A wide bandgap semiconductor termination structure with embedded FLRs (field limiting rings) and buried JTEs (junction termination extensions) comprises a substrate 1, an epitaxial layer 2 located on the upper surface of substrate 1, and an interlayer dielectric layer 3 located on the upper surface of epitaxial layer 2. A buried layer 4 and a well region 5 located above the buried layer 4 are provided in epitaxial layer 2. The buried layer 4 is divided into several buried floating JTE regions 401 by separation regions 6. The semiconductor device is divided into a main junction region A, a termination region B, and a scribe region C. An embedded FLR region 7 is provided in at least the epitaxial layer 2 closest to the main junction region A of the semiconductor device. Several field limiting rings 701 are provided in each embedded FLR region 7. The substrate 1, epitaxial layer 2, and separation regions 6 are doped with a first type of doping. The buried layer 4, well region 5, and field limiting rings 701 are doped with a second type of doping.

[0044] In the above scheme, the buried layer 4 is divided into multiple buried floating JTE zones 401, with an embedded FLR zone provided in at least the epitaxial layer closest to the main junction region A. This composite FLR-buried JTE termination structure design, combined with adjustments to the dimensions of each buried floating JTE zone 401 along the direction from the main junction region A to the terminal region B, as well as the number of FLRs within each embedded FLR zone, the doping width of each FLR (the FLR's dimension in the direction from the main junction region A to the terminal region B), and the spacing between adjacent FLRs, improves the device's electric field distribution, reduces field concentration, and enhances the device's withstand voltage. The partition region 6 in the buried layer 4, farthest from the main junction region A, serves as an electric field cutoff region, preventing charge from entering the scribe region C and thus preventing device leakage. It also allows for rapid electric field cutoff, mitigating field intensity and regulating field distribution. The well region 5 can reduce the sensitivity of the terminal structure to interface charges and prevent the electric field from gathering from the separation region 6 to the device surface; at the same time, the well region can also serve as a JTE structure to further optimize the electric field distribution inside the device and improve the device's voltage resistance.

[0045] In a further preferred embodiment, Figure 6 As shown, an electric field blocking layer 8 is provided in the epitaxial layer 2 between the buried layer 4 and the well region 5. The doping type of the electric field blocking layer 8 is the second type. The electric field blocking layer 8 can further block the electric field passing through the separation region, optimize the electric field distribution within the device, and thus further improve the breakdown characteristics of the device.

[0046] As an example, the material of the substrate 1 is at least one of SiC, GaN, Ga2O3, diamond, and AlN.

[0047] As an example, the well region 5 is continuously distributed in the epitaxial layer 2 (eg Figure 7 、 10 , 12). Or the well regions 5 are spaced apart in the epitaxial layer 2 (as shown in FIG. Figure 5 、 6 , 8, 9, 11, 13-15).

[0048] As an example, in some embodiments, the epitaxial layer 2 serves as the separation region 6 (e.g. Figure 8 In some other embodiments, the separation region 6 is a first doped region 601 (as shown in FIG. Figures 5-7 , 9~15).

[0049] As an example, in some embodiments, Figures 5-7As shown, the first doping region 601 is a single-layer structure. The width of each first doping region 601 (the dimension along the direction from the main junction region A to the terminal region B) can be the same or different. The distance between two adjacent first doping regions 601 can be the same or different. In other embodiments, the first doping region 601 is a multi-layer structure, and the width of each layer (the dimension along the direction from the main junction region A to the terminal region B) is different. Figure 9 As shown, the first doped region 601 has a two-layer structure, with the width of the upper layer being greater than that of the lower layer. It is understood that the first doped region 601 may also have a multi-layer structure with other numbers of layers, where the width of each layer gradually decreases or increases along the direction from the interlayer dielectric layer 3 to the substrate 1, or the width of different layers first decreases and then increases, or the width of different layers first increases and then decreases.

[0050] As an example, in some embodiments, Figure 10 、 Figure 11 As shown, the embedded FLR partition 7 is provided only in the epitaxial layer 2 closest to the main junction region A. In other embodiments, as Figures 5 to 9 、 Figures 12-15 As shown, a plurality of embedded FLR partitions 7 are provided in the epitaxial layer 2. Compared with the buried suspended JTE partition 401, a plurality of embedded FLR partitions 7 can be sequentially arranged in the epitaxial layer 2 (eg, Figures 5 to 9 As shown), they can also be distributed in the epitaxial layer 2 at intervals (as shown Figure 12 As shown in FIG. 1 ). The number of field limiting rings 701 in each embedded FLR partition 7 can be the same or different. The width of each field limiting ring 701 (the dimension along the direction from the main junction region A to the terminal region B) can be the same or different. The distance between two adjacent field limiting rings 701 can be the same or different.

[0051] As an example, in some embodiments, Figure 13 As shown, along the direction of the interlayer dielectric layer 3 pointing to the substrate 1, the doping depth of the field limiting ring 701 penetrates into the epitaxial layer 2 below the buried layer 4 (burying the suspended JTE partition 401). In other embodiments, as Figure 14 As shown, along the direction of the interlayer dielectric layer 3 pointing to the substrate 1, the doping depth of the field limiting ring 701 makes the field limiting ring 701 not contact the buried layer 4. At this time, the buried floating JTE partitions 401 are all floating JTEs. In other embodiments, such as Figures 5 to 12 As shown, along the direction from the interlayer dielectric layer 3 to the substrate 1 , the doping depth of the field limiting ring 701 penetrates into the buried layer 4 (ie, penetrates into the buried suspended JTE partition 401 ), but does not penetrate through the buried layer 4 .

[0052] As an example, in some embodiments, Figure 15As shown, a first trench is provided in the field limiting ring 701 and is filled with an interlayer dielectric layer 3. The number of stages of the first trench M is ≥ 1, i.e., the first trench can be a single-stage trench or a multi-stage trench. The first trench is used to assist ion implantation to form the field limiting ring 701.

[0053] For example, if Figure 5 As shown, the buried layer 4 located in the terminal area B is divided into four separation areas 6 (i.e. Figure 5 The first doped region 601 on the upper surface is divided into four buried floating JTE partitions 401. The partition region 6 closest to the scribe region C serves as an electric field cutoff region. The width of each partition region 6 can be the same or different; the distance between two adjacent partition regions 6 can be the same or different. In the epitaxial layer 2 where three of the four buried floating JTE partitions 401 are located, there are corresponding embedded FLR partitions 7. Each embedded FLR partition 7 is composed of multiple field limiting rings 701. The number of field limiting rings 701 in each embedded FLR partition 7 can be the same or different; the width of each field limiting ring 701 can be the same or different; the distance between two adjacent field limiting rings 701 can be the same or different. By adjusting any one of the parameters or a combination thereof, such as the size and / or number of each separation region 6 along the direction from the main junction region A to the terminal region B, the distance between two adjacent separation regions 6, the doping width and / or number of the field limiting rings 701, and the distance between two adjacent field limiting rings 701, the distribution of the electric field in the device can be adjusted to improve the breakdown characteristics of the device.

[0054] Example 2

[0055] Continue to refer to Figure 5 A semiconductor device includes the semiconductor terminal structure of embodiment 1. The semiconductor device also includes an anode 9, a cathode 10, and a second doping region 11. The second doping region 11 is disposed in the epitaxial layer 2 located in the main junction region A. The doping type of the second doping region 11 is the second type. The second doping region 11 forms a main junction with the epitaxial layer 2. The anode 9 is deposited on the upper surface of the second doping region 11. The cathode 10 is deposited on the surface of the substrate 1 facing away from the epitaxial layer 2.

[0056] As an example, Figure 13 As shown, along the direction from the interlayer dielectric layer 3 to the substrate 1, the doping depth of the second doping region 11 penetrates into the epitaxial layer 2 below the buried layer 4 (burying the suspended JTE partition 401). In other embodiments, as Figure 14 As shown, along the direction of the interlayer dielectric layer 3 pointing to the substrate 1, the doping depth of the second doping region 11 is such that the second doping region 11 does not contact the buried layer 4. In other embodiments, as Figures 5 to 12As shown, along the direction from the interlayer dielectric layer 3 to the substrate 1 , the doping depth of the second doping region 11 penetrates into the buried layer 4 (ie, penetrates into the buried suspended JTE partition 401 ), but does not penetrate through the buried layer 4 .

[0057] As an example, Figure 15 As shown, a second trench is provided in the second doping region 11. The second trench is filled with an interlayer dielectric layer 3. An anode 9 covers the upper surface of the second doping region 11 and the upper surface of the interlayer dielectric layer 3 located in the second trench.

[0058] Example 3

[0059] Reference Figures 1 to 4 and Figure 16 A method for preparing a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE comprises the following steps:

[0060] S1. Growing an epitaxial layer on a substrate and forming a buried layer in the epitaxial layer; the buried layer divides the epitaxial layer into a first epitaxial layer located below the buried layer and a second epitaxial layer located above the buried layer; forming a separation region in the buried layer to obtain a buried suspended JTE partition;

[0061] S2, forming a well region in the upper layer of the second epitaxial layer;

[0062] S3, forming an embedded FLR partition consisting of multiple field limiting rings in the epitaxial layer closest to the main junction region of the semiconductor device;

[0063] S4. Depositing an interlayer dielectric layer on the upper surface of the second epitaxial layer.

[0064] As an example, the method of forming the buried layer in the epitaxial layer in step S1 is ion implantation. When the buried layers are spaced apart in the epitaxial layer, each buried layer is a buried suspended JTE partition; the epitaxial layer between two adjacent buried layers acts as a partition (e.g. Figure 16 When the buried layer is continuously distributed as a whole in the epitaxial layer, first doped regions are formed in the buried layer by ion implantation, and the first doped regions serve as separation regions (such as Figure 2 shown).

[0065] As an example, in step S1, a first epitaxial layer is first grown on a substrate, a buried layer is then grown on the upper surface of the first epitaxial layer, and a second epitaxial layer is then grown on the upper surface of the buried layer. The first epitaxial layer and the second epitaxial layer are collectively referred to as the epitaxial layer. Ion implantation is then used to form first doped regions spaced apart within the buried layer. The first doped regions serve as separation regions.

[0066] As an example, the method of forming the well region in step S2 is ion implantation.

[0067] As an example, the method of forming the field limiting ring in step S3 is ion implantation.

[0068] Example 4

[0069] Reference Figures 1 to 5 A method for preparing a semiconductor device includes the method for preparing a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE in Example 3, further comprising the following steps:

[0070] In step S3, a second doped region is formed in the epitaxial layer of the main junction region by ion implantation;

[0071] After the interlayer dielectric layer is deposited in step S4, the interlayer dielectric layer on the upper surface of the epitaxial layer in the main junction area is etched away, and an anode metal is deposited on the upper surface of the epitaxial layer in the main junction area to form an anode; then a drain metal is deposited on the lower surface of the substrate to form a drain electrode.

[0072] The embodiments described above are merely preferred embodiments of the present application and are not intended to limit the scope of protection of the present application. For any person skilled in the art, the present application may have various modifications and variations. Any simple equivalent changes and modifications made based on the scope of protection of the present application and the contents of the specification should be included in the scope of protection of the present application.

Claims

1. A wide bandgap semiconductor terminal structure with embedded FLR buried JTE, characterized in that: It comprises a substrate, an epitaxial layer and an interlayer dielectric layer stacked in sequence; a buried layer and a well region located above the buried layer are provided in the epitaxial layer; the buried layer is divided into a plurality of buried suspended JTE partitions by a separation region; the separation region is a first doped region, and the doping concentration of the first doped region is greater than the doping concentration of the epitaxial layer; the first doped region is a multi-layer structure, and the dimensions of each layer along the direction from the substrate to the interlayer dielectric layer are different; a plurality of field limiting rings are provided in at least the epitaxial layer closest to the main junction region of the semiconductor device; the doping type of the substrate, the epitaxial layer and the separation region are all of the first type; the doping type of the buried layer, the well region and the field limiting ring are all of the second type.

2. The semiconductor terminal structure according to claim 1, wherein: An electric field blocking layer is provided in the epitaxial layer between the buried layer and the well region.

3. The semiconductor terminal structure according to claim 1, wherein: A first trench is provided in the field limiting ring; the first trench is filled with the interlayer dielectric layer.

4. The semiconductor terminal structure according to claim 3, wherein: The first groove is a multi-level groove.

5. The method for preparing a semiconductor terminal structure according to any one of claims 1 to 4, characterized in that: The following steps are involved: S1. Growing an epitaxial layer on a substrate and forming a buried layer in the epitaxial layer; the buried layer divides the epitaxial layer into a first epitaxial layer located below the buried layer and a second epitaxial layer located above the buried layer; forming a separation region in the buried layer to obtain a buried suspended JTE partition; S2. forming a well region in an upper layer of the second epitaxial layer; S3, forming an embedded FLR partition consisting of a plurality of field limiting rings in the epitaxial layer closest to the main junction region of the semiconductor device; S4. Depositing an interlayer dielectric layer on the upper surface of the second epitaxial layer.

6. A semiconductor device, characterized in that: A semiconductor terminal structure comprising the semiconductor terminal structure according to any one of claims 1 to 4.

7. The semiconductor device according to claim 6, wherein: It includes a second doping region in the epitaxial layer located in the main junction region, and the doping type of the second doping region is the second type.

8. The semiconductor device according to claim 7, wherein: A second trench is provided in the second doping region, and the second trench is filled with the interlayer dielectric layer.

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