Back contact battery and manufacturing method thereof

Abstract

The invention discloses a back contact cell and a manufacturing method thereof, relates to the technical field of photovoltaics, and aims to enable an N-type doped polycrystalline silicon layer and a P-type doped polycrystalline silicon layer to have a good passivation effect and improve the conversion efficiency of the back contact cell. The back contact battery comprises a semiconductor substrate, and an N-type doped polycrystalline silicon layer and a P-type doped polycrystalline silicon layer which are positioned on the same surface of the semiconductor substrate. And at least partial region of the N-type doped polycrystalline silicon layer and at least partial region of the P-type doped polycrystalline silicon layer are arranged at intervals. Wherein the Raman peak normalization intensity value corresponding to the N-type doped polycrystalline silicon layer is greater than the Raman peak normalization intensity value corresponding to the P-type doped polycrystalline silicon layer, and / or the Raman peak area value corresponding to the N-type doped polycrystalline silicon layer is greater than the Raman peak area value corresponding to the P-type doped polycrystalline silicon layer, and / or the Raman peak normalization intensity value corresponding to the N-type doped polycrystalline silicon layer is greater than the Raman peak area value corresponding to the P-type doped polycrystalline silicon layer. And the half-peak width value of the Raman peak corresponding to the N-type doped polycrystalline silicon layer is greater than the half-peak width value of the Raman peak corresponding to the P-type doped polycrystalline silicon layer.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a back-contact cell and a method for manufacturing the same. Background Art

[0002] A solar cell is a device that can convert sunlight into electrical energy. Specifically, when the solar cell is in operation, sunlight shines on the semiconductor pn junction of the solar cell, forming new hole-electron pairs. Under the action of the built-in electric field of the pn junction, photogenerated holes flow to the p region, and photogenerated electrons flow to the n region. When the circuit is connected, current can be generated. Among them, a solar cell in which both the positive electrode and the negative electrode are on the back of the cell is a back-contact cell. Compared with a double-sided contact solar cell, the front of the back-contact cell is not blocked by a metal electrode, so that the light-facing side of the back-contact cell has a higher light utilization rate. Therefore, the back-contact cell has a higher short-circuit current and photoelectric conversion efficiency, and is one of the current technical directions for achieving high-efficiency crystalline silicon cells.

[0003] However, the passivation effect of the N region in the existing back-contact battery is poor, which is not conducive to improving the conversion efficiency of the back-contact battery. Summary of the invention

[0004] The purpose of the present application is to provide a back-contact battery and a method for manufacturing the same, so as to improve the passivation effect of the N region of the battery corresponding to the N-type doped polysilicon layer, so that both the N-type doped polysilicon layer and the P-type doped polysilicon layer have good passivation effects, thereby making the parts of the semiconductor substrate corresponding to the N-type doped polysilicon layer and the P-type doped polysilicon layer respectively have a lower carrier recombination rate, thereby improving the conversion efficiency of the back-contact battery.

[0005] In order to achieve the above-mentioned purpose, in the first aspect, the present application provides a back-contact battery, which includes: a semiconductor substrate, and an N-type doped polysilicon layer and a P-type doped polysilicon layer located on the same surface of the semiconductor substrate. At least a portion of the N-type doped polysilicon layer and at least a portion of the P-type doped polysilicon layer are arranged at intervals from each other. Among them, the normalized intensity value of the Raman peak corresponding to the N-type doped polysilicon layer is greater than the normalized intensity value of the Raman peak corresponding to the P-type doped polysilicon layer, and / or, the Raman peak area value corresponding to the N-type doped polysilicon layer is greater than the Raman peak area value corresponding to the P-type doped polysilicon layer, and / or, the Raman peak half-peak width value corresponding to the N-type doped polysilicon layer is greater than the Raman peak half-peak width value corresponding to the P-type doped polysilicon layer.

[0006] One of the P-type doped polysilicon layer and the N-type doped polysilicon layer can form a high-low junction with the semiconductor substrate, and the other can form a PN junction with the semiconductor substrate. Based on this, when the solar cell is in working state, the semiconductor substrate can form new hole-electron pairs after absorbing photons. Under the action of the built-in electric field of the above-mentioned PN junction and the high-low junction, the photogenerated holes flow to the P-type doped polysilicon layer, and the photogenerated electrons flow to the N-type doped polysilicon layer, and current can be generated after the circuit is connected. Based on this, it can be understood that the passivation effect of the P-type doped polysilicon layer and the N-type doped polysilicon layer on the semiconductor substrate is related to factors such as their own doping concentration, degree of crystallization and thickness. The types of doping elements doped in the N-type doped polysilicon layer and the P-type doped polysilicon layer are different. In addition, because the size of the N-type dopant phosphorus atom is relatively large, its corresponding doping method is substitutional diffusion; the size of the P-type dopant boron atom is relatively small, so its corresponding doping method is interstitial diffusion. At the same time, because the substitutional diffusion method is that the impurity atoms replace the positions of semiconductor atoms for diffusion, it is easy to generate more defects in the film layer when the N-type doped polysilicon layer is formed (relative to the P-type doped polysilicon layer). By adjusting the crystallization degree of the N-type doped polysilicon layer and the P-type doped polysilicon layer, the N-type doped polysilicon layer has a higher degree of crystallization, the number of grain boundaries in the N-type doped polysilicon layer is reduced, and the distribution of different grains in the N-type doped polysilicon layer is made more orderly and regular, thereby reducing the number of defects in the N-type doped polysilicon layer.

[0007] In addition, the difference in the Raman peak area values ​​corresponding to the N-type doped polysilicon layer and the P-type doped polysilicon layer, the difference in the Raman peak normalized intensity values ​​corresponding to the two, and the difference in the Raman peak half-peak width values ​​corresponding to the two come from the doping concentration and crystallization degree of the doping elements in the two. Within a certain range, the Raman peak area values ​​of the N-type doped polysilicon layer and the P-type doped polysilicon layer, the Raman peak normalized intensity values ​​corresponding to the two, and the Raman peak half-peak width values ​​corresponding to the two are proportional to the doping element concentration and the crystallization degree, respectively. Based on this, by adjusting the size relationship of at least one of the Raman peak area value, the Raman peak normalized intensity value and the Raman peak half-peak width value of the above two film layers, the crystallization degree and the doping concentration of the N-type doped polysilicon layer and the P-type doped polysilicon layer are regulated, and at least one of the Raman peak area value, the Raman peak normalized intensity value and the Raman peak half-peak width value corresponding to the N-type doped polysilicon layer is set to be larger than the Raman peak area value, the Raman peak normalized intensity value and the Raman peak half-peak width value corresponding to the P-type doped polysilicon layer, respectively, so as to reduce the internal defects of the N-type doped polysilicon layer caused by substitutional doping in the manufacturing process, ensure that the N-type doped polysilicon layer in the back contact battery has a lower number of defects, and improve the field passivation effect of the N-type doped polysilicon layer, so that both the N-type doped polysilicon layer and the P-type doped polysilicon layer have good passivation effects, thereby making the parts of the semiconductor substrate corresponding to the N-type doped polysilicon layer and the P-type doped polysilicon layer respectively have a lower carrier recombination rate, thereby improving the conversion efficiency of the back contact battery.

[0008] As a possible implementation scheme, the ratio between the Raman peak area value corresponding to the N-type doped polysilicon layer and the Raman peak area value corresponding to the P-type doped polysilicon layer is greater than or equal to 1.1:1 and less than or equal to 2.1:1.

[0009] The ratio between the Raman peak area value corresponding to the N-type doped polysilicon layer and the Raman peak area value corresponding to the P-type doped polysilicon layer is within the above range, which is conducive to preventing the Raman peak area value corresponding to the N-type doped polysilicon layer from being too small due to the small ratio, resulting in a low degree of crystallization and a low doping concentration of the N-type doped polysilicon layer, ensuring that the N-type doped polysilicon layer has fewer defects and a stronger field passivation effect. In addition, it can also prevent the Raman peak area value corresponding to the N-type doped polysilicon layer from being too large and / or the Raman peak area value corresponding to the P-type doped polysilicon layer from being too small due to the large ratio, reducing the process difficulty of manufacturing the N-type doped polysilicon layer, and ensuring that the N-type doped polysilicon layer and the P-type doped polysilicon layer have good passivation effects on the semiconductor substrate, further reducing the carrier recombination rate of the parts of the semiconductor substrate corresponding to the N-type doped polysilicon layer and the P-type doped polysilicon layer, respectively.

[0010] As a possible implementation scheme, the difference between the normalized intensity value of the Raman peak corresponding to the N-type doped polysilicon layer and the normalized intensity value of the Raman peak corresponding to the P-type doped polysilicon layer is greater than or equal to 0.1 and less than or equal to 0.4. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the ratio between the Raman peak area value corresponding to the N-type doped polysilicon layer and the Raman peak area value corresponding to the P-type doped polysilicon layer being greater than or equal to 1.1:1 and less than or equal to 2.1:1 as described above, which will not be repeated here.

[0011] As a possible implementation scheme, the half-peak width of the Raman peak corresponding to the N-type doped polysilicon layer is greater than or equal to 3 cm -1 , and less than or equal to 15cm -1 .

[0012] The value of the half-peak width of the Raman peak corresponding to the N-type doped polysilicon layer can reflect the crystal quality of the N-type doped polysilicon layer to a certain extent. The half-peak width of the Raman peak corresponding to the N-type doped polysilicon layer is related to the degree of crystallization, doping concentration and number of defects of the N-type doped polysilicon layer. Based on this, when the half-peak width of the Raman peak corresponding to the N-type doped polysilicon layer is within the above range, it can prevent the degree of crystallization of the N-type doped polysilicon layer from being too low and the number of defects from being too large due to the half-peak width of the Raman peak corresponding to the N-type doped polysilicon layer being too small, and further make the N-type doped polysilicon layer and the P-type doped polysilicon layer have good passivation effects. In addition, it can also prevent the difficulty of manufacturing the N-type doped polysilicon layer due to the large half-peak width of the Raman peak corresponding to the N-type doped polysilicon layer, thereby improving the yield of the back contact battery.

[0013] As a possible implementation scheme, the Raman peak half-peak width corresponding to the P-type doped polysilicon layer is greater than or equal to 1 cm -1 , and less than or equal to 11cm -1 .

[0014] The half-peak width value of the Raman peak corresponding to the P-type doped polysilicon layer is within the above range, which is conducive to preventing the P-type doped polysilicon layer from having too low a degree of crystallization and too low a doping concentration due to the Raman peak half-peak width value corresponding to the P-type doped polysilicon layer being too small, thereby ensuring that the P-type doped polysilicon layer has lower film defects and stronger field passivation effect. In addition, it can also prevent the P-type doped polysilicon layer from having too high a degree of crystallization and too high a doping concentration due to the Raman peak half-peak width value corresponding to the P-type doped polysilicon layer being too large, thereby reducing the process difficulty of manufacturing the P-type doped polysilicon layer, and preventing the manufacturing temperature from being too high to manufacture the P-type doped polysilicon layer with a high degree of crystallization and a high doping concentration, thereby preventing more P-type doped polysilicon layers from expanding into the semiconductor substrate, thereby ensuring that a PN junction or a high-low junction with a high built-in electric field strength can be formed between the P-type doped polysilicon layer and the semiconductor substrate, thereby further improving the conversion efficiency of the back contact battery.

[0015] As a possible implementation scheme, the normalized intensity value of the Raman peak corresponding to the N-type doped polysilicon layer is greater than or equal to 0.75 and less than 1. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the ratio between the Raman peak area value corresponding to the N-type doped polysilicon layer and the Raman peak area value corresponding to the P-type doped polysilicon layer being greater than or equal to 1.1:1 and less than or equal to 2.1:1, which will not be repeated here.

[0016] As a possible implementation scheme, the normalized intensity value of the Raman peak corresponding to the P-type doped polysilicon layer is greater than or equal to 0.65 and less than or equal to 0.8. The application principle of the beneficial effect in this case can refer to the aforementioned Raman peak half-peak width value corresponding to the P-type doped polysilicon layer is greater than or equal to 1cm -1 , and less than or equal to 11cm -1 The application principle of the beneficial effect will not be repeated here.

[0017] As a possible implementation scheme, the back contact battery further includes a first tunneling layer and a second tunneling layer. The first tunneling layer is at least located between the N-type doped polysilicon layer and the semiconductor substrate. The second tunneling layer is located between the P-type doped polysilicon layer and the semiconductor substrate. Moreover, the thickness of the first tunneling layer is less than the thickness of the second tunneling layer.

[0018] Compared with the boron atoms doped in the P-type doped polysilicon layer, the size of the phosphorus atoms in the N-type doped polysilicon layer is relatively large, and it is less likely to diffuse into the semiconductor substrate. Therefore, the thickness of the first tunneling layer is set to be relatively small, so that the first tunneling layer has a lower transmission resistance, which is conducive to improving the carrier collection efficiency of the N-type doped polysilicon layer. The thickness of the second tunneling layer is set to be relatively large, so that the second tunneling layer has a higher diffusion barrier effect on the boron atoms doped in the P-type doped polysilicon layer, ensuring that a PN junction or a high-low junction with a higher built-in electric field strength can be formed between the P-type doped polysilicon layer and the semiconductor substrate. In addition, the first tunnel layer and the second tunnel layer of different thicknesses have different chemical passivation effects. The Raman peak area value and / or the Raman peak normalized intensity value corresponding to the N-type doped polysilicon layer are set to be greater than the Raman peak area value and / or the Raman peak normalized intensity value corresponding to the P-type doped polysilicon layer, respectively. This can compensate for the defect that the comprehensive passivation effect of the back contact battery in the N region is lower than that in the P region due to the smaller thickness of the first tunnel layer (the passivation effect of the first tunnel layer is lower than the passivation effect of the second tunnel layer), thereby ensuring that both the N region and the P region of the back contact battery have good comprehensive passivation effects.

[0019] As a possible implementation scheme, a thickness ratio of the second tunneling layer to the first tunneling layer is greater than or equal to 1.01 and less than or equal to 3.

[0020] It can prevent the thickness of the second tunnel layer from being too large due to the thickness ratio of the second tunnel layer to the first tunnel layer being too large, so that the second tunnel layer can reduce its own transmission resistance as much as possible under the premise of having sufficient diffusion barrier effect, ensuring that the P-type doped polysilicon layer has a high carrier collection efficiency. In addition, it can also prevent the thickness difference between the first tunnel layer and the second tunnel layer from being too large, making it difficult to compensate for the difference in the comprehensive passivation effect of the back contact battery in the N region and the P region by adjusting the Raman peak area value and / or the Raman peak normalized intensity value corresponding to the N-type doped polysilicon layer and the P-type doped polysilicon layer, ensuring that the back contact battery has a high conversion efficiency.

[0021] As a possible implementation scheme, the N-type doped polysilicon layer and / or the P-type doped polysilicon layer includes a plurality of doped polysilicon layers stacked along the thickness direction of the semiconductor substrate. Along the thickness direction away from the semiconductor substrate, in the N-type doped polysilicon layer or the P-type doped polysilicon layer, the normalized intensity values ​​of the Raman peaks corresponding to the different doped polysilicon layers gradually increase, and / or the area values ​​of the Raman peaks corresponding to the different doped polysilicon layers gradually increase, and / or the half-peak width values ​​of the Raman peaks corresponding to the different doped polysilicon layers gradually increase.

[0022] Taking an N-type doped polysilicon layer having multiple doped polysilicon layers as an example for explanation: in the N-type doped polysilicon layer, at least one of the Raman peak area value, the Raman peak normalized intensity value, and the Raman peak half-peak width value corresponding to the doped polysilicon layer close to the semiconductor substrate is adjusted to be smaller than at least one of the Raman peak area value, the Raman peak normalized intensity value, and the Raman peak half-peak width value corresponding to the doped polysilicon layer away from the semiconductor substrate, so that the doped polysilicon layer located outside (i.e., the doped polysilicon layer away from the semiconductor substrate) has a higher doping concentration and crystallization degree. The doped polysilicon layer located outside needs to be in electrical contact with the electrode responsible for extracting carriers. When the doped polysilicon layer located outside has a higher doping concentration and crystallization degree, the contact resistance between the N-type doped polysilicon layer and the electrode can be reduced, thereby reducing the transmission loss. The doped polysilicon layer located on the inner side (i.e., the doped polysilicon layer close to the semiconductor substrate) has a smaller doping concentration, which can also reduce the doping concentration difference between the part of the N-type doped polysilicon layer close to the semiconductor substrate and the semiconductor substrate, reduce the risk of diffusion of doping elements in the N-type doped polysilicon layer into the semiconductor substrate, reduce the diffusion depth and / or diffusion concentration of the inner expansion layer, and further improve the conversion efficiency of the back contact battery. Secondly, the application principle of the P-type doped polysilicon layer having the beneficial effects of multiple doped polysilicon layers can be referred to the previous text and will not be repeated here.

[0023] As a possible implementation scheme, in an N-type doped polysilicon layer or a P-type doped polysilicon layer, the multilayer doped polysilicon layer includes a first doped polysilicon layer and a second doped polysilicon layer. The second doped polysilicon layer is located on the side of the first doped polysilicon layer away from the semiconductor substrate. Moreover, in the N-type doped polysilicon layer or the P-type doped polysilicon layer, the ratio between the normalized intensity value of the Raman peak corresponding to the first doped polysilicon layer and the normalized intensity value of the Raman peak corresponding to the second doped polysilicon layer is greater than or equal to 0.6:1 and less than 1:1, and / or the ratio between the Raman peak area value corresponding to the first doped polysilicon layer and the Raman peak area value corresponding to the second doped polysilicon layer is greater than or equal to 0.5:1 and less than 1:1.

[0024] Taking the ratio of the Raman peak area values ​​corresponding to the first doped polysilicon layer and the second doped polysilicon layer of the N-type doped polysilicon layer satisfying the above relationship as an example, it is possible to prevent the doping concentration of the first doped polysilicon layer from being too high or the doping concentration and degree of crystallization of the second doped polysilicon layer from being too low due to the ratio between the Raman peak area value corresponding to the first doped polysilicon layer and the Raman peak area value corresponding to the second doped polysilicon layer being too small, ensuring that the portion of the semiconductor substrate corresponding to the N-type doped polysilicon layer has an internal expansion with a lower concentration and / or a smaller diffusion depth, and ensuring that the N-type doped polysilicon layer and the electrode have a lower transmission loss. It is also possible to prevent the doping concentration of the first doped polysilicon layer from being too low or the doping concentration and degree of crystallization of the second doped polysilicon layer from being too high due to the ratio being too large, ensuring that the N-type doped polysilicon layer has a higher carrier collection efficiency, and reducing the process difficulty of manufacturing the N-type doped polysilicon layer. Secondly, the application principle of the beneficial effect that the ratio of the normalized intensity values ​​of the Raman peaks corresponding to the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer of the N-type doped polycrystalline silicon layer satisfies the above relationship, and the ratio of the Raman peak areas and / or normalized intensity values ​​of the Raman peaks corresponding to the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer of the P-type doped polycrystalline silicon layer satisfies the above relationship can be referred to the previous text and will not be repeated here.

[0025] As a possible implementation scheme, in an N-type doped polysilicon layer or a P-type doped polysilicon layer, the multi-layer doped polysilicon layer includes a first doped polysilicon layer and a second doped polysilicon layer. The second doped polysilicon layer is located on a side of the first doped polysilicon layer away from the semiconductor substrate. Furthermore, in the N-type doped polysilicon layer or the P-type doped polysilicon layer, the ratio of the thickness of the first doped polysilicon layer to the thickness of the second doped polysilicon layer is greater than or equal to 1:2 and less than or equal to 1:5.

[0026] Taking the ratio of the thickness of the first doped polysilicon layer and the thickness of the second doped polysilicon layer of the N-type doped polysilicon layer satisfying the above relationship as an example, it can prevent the thickness of the first doped polysilicon layer from being too large or the thickness of the second doped polysilicon layer from being too small due to the small ratio, ensure that the thickness of the first doped polysilicon layer with a relatively low doping concentration in the N-type doped polysilicon layer is relatively small, and ensure that the thickness of the second doped polysilicon layer with a relatively high doping concentration and a relatively high degree of crystallization in the N-type doped polysilicon layer is relatively large, so that the carrier collection efficiency between itself and the electrode is high and the transmission loss is low. The application principle of the beneficial effect of the ratio of the thickness of the first doped polysilicon layer and the second doped polysilicon layer of the P-type doped polysilicon layer satisfying the above relationship can be referred to the previous text and will not be repeated here.

[0027] In a second aspect, the present application provides a back-contact battery and a method for manufacturing the same, the method for manufacturing the back-contact battery comprising: first, providing a semiconductor substrate. Next, forming an N-type doped polysilicon layer and a P-type doped polysilicon layer on the same surface of the semiconductor substrate. Along the thickness direction perpendicular to the semiconductor substrate, at least a portion of the N-type doped polysilicon layer and at least a portion of the P-type doped polysilicon layer are spaced apart from each other. Among them, the normalized intensity value of the Raman peak corresponding to the N-type doped polysilicon layer is greater than the normalized intensity value of the Raman peak corresponding to the P-type doped polysilicon layer, and / or, the Raman peak area value corresponding to the N-type doped polysilicon layer is greater than the Raman peak area value corresponding to the P-type doped polysilicon layer, and / or, the half-peak width value of the Raman peak corresponding to the N-type doped polysilicon layer is greater than the half-peak width value of the Raman peak corresponding to the P-type doped polysilicon layer.

[0028] As a possible implementation scheme, forming an N-type doped polysilicon layer and / or a P-type doped polysilicon layer on a semiconductor substrate includes: forming a plurality of doped polysilicon layers stacked in sequence on the semiconductor substrate along the thickness direction of the semiconductor substrate; and gradually increasing the deposition rates corresponding to different doped polysilicon layers in the N-type doped polysilicon layer or the P-type doped polysilicon layer in the direction away from the semiconductor substrate. Among them, along the thickness direction away from the semiconductor substrate, the normalized intensity values ​​of the Raman peaks corresponding to different doped polysilicon layers in the N-type doped polysilicon layer or the P-type doped polysilicon layer gradually increase, and / or the Raman peak area values ​​corresponding to different doped polysilicon layers gradually increase, and / or the Raman peak half-peak width values ​​corresponding to different doped polysilicon layers gradually increase.

[0029] As a possible implementation scheme, forming a stacked multilayer doped polysilicon layer in sequence on a semiconductor substrate includes: depositing a first doped polysilicon layer on the semiconductor substrate. Next, depositing a second doped polysilicon layer on the side of the first doped polysilicon layer away from the semiconductor substrate. The deposition rate corresponding to the second doped polysilicon layer is greater than the deposition rate corresponding to the first doped polysilicon layer. The multilayer doped polysilicon layer includes a first doped polysilicon layer and a second doped polysilicon layer. Moreover, the ratio between the deposition rate corresponding to the second doped polysilicon layer and the deposition rate corresponding to the first doped polysilicon layer is greater than or equal to 2:1 and less than or equal to 5:1.

[0030] By adjusting the deposition rates of the first doped polysilicon layer and the second doped polysilicon layer, the density of the film layer after the deposition of the first doped polysilicon layer and the second doped polysilicon layer is adjusted. It can be understood that, under the same conditions of other factors, the greater the deposition rate, the looser the film layer, and the slower the deposition rate, the denser the film layer. The denser the film layer, the less likely it is to increase the degree of crystallization during the crystallization modification treatment, and the denser the film layer, the higher the doping barrier effect. Therefore, when the ratio between the deposition rate corresponding to the second doped polysilicon layer and the deposition rate corresponding to the first doped polysilicon layer is greater than or equal to 2:1 and less than or equal to 5:1, the crystallization degree and doping concentration of the first doped polysilicon layer and the second doped polysilicon layer can be controlled within a corresponding reasonable range by adjusting the deposition rate. The beneficial effects of the reasonable setting of the degree of crystallization and doping concentration of the first doped polysilicon layer and the second doped polysilicon layer can be referred to the previous text, and will not be repeated here.

[0031] The beneficial effects of the second aspect and its various implementations in this application can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0033] Figure 1 A schematic longitudinal cross-sectional view of a first structure of a back-contact battery provided in an embodiment of the present application;

[0034] Figure 2 A graph showing the relationship between the normalized intensity value of the Raman peak and the wave number of the N-type doped polysilicon layer in the back contact cell provided in an embodiment of the present application;

[0035] Figure 3 A graph showing the relationship between the normalized intensity value of the Raman peak and the wave number of the P-type doped polysilicon layer in the back contact cell provided in an embodiment of the present application;

[0036] Figure 4 A schematic longitudinal cross-sectional view of a second structure of a back contact battery provided in an embodiment of the present application;

[0037] Figure 5 A schematic longitudinal cross-sectional view of a third structure of a back-contact battery provided in an embodiment of the present application;

[0038] Figure 6 A schematic longitudinal cross-sectional view of a fourth structure of a back-contact battery provided in an embodiment of the present application;

[0039] Figure 7A schematic longitudinal cross-sectional view of a fifth structure of a back-contact battery provided in an embodiment of the present application;

[0040] Figure 8 A longitudinal cross-sectional schematic diagram of a sixth structure of a back-contact battery provided in an embodiment of the present application;

[0041] Fig. 9 A longitudinal cross-sectional schematic diagram of a seventh structure of a back-contact battery provided in an embodiment of the present application;

[0042] Fig.10 A schematic longitudinal cross-sectional view of an eighth structure of a back-contact battery provided in an embodiment of the present application;

[0043] Fig.11 A longitudinal cross-sectional schematic diagram of a ninth structure of a back-contact battery provided in an embodiment of the present application;

[0044] Fig.12 A graph showing the relationship between the normalized intensity value of the Raman peak and the wave number when the N-type doped polysilicon layer includes a first doped polysilicon layer and a second doped polysilicon layer in the back contact cell provided in an embodiment of the present application;

[0045] Fig.13 A graph showing the relationship between the normalized intensity value of the corresponding Raman peak and the wave number when the P-type doped polysilicon layer in the back contact cell provided in an embodiment of the present application includes a first doped polysilicon layer and a second doped polysilicon layer.

[0046] Figure numerals: 11 is a semiconductor substrate, 12 is an N-type doped polysilicon layer, 13 is a P-type doped polysilicon layer, 14 is a first tunneling layer, 15 is a second tunneling layer, 16 is a first doped polysilicon layer, 17 is a second doped polysilicon layer, and 18 is a surface passivation layer. DETAILED DESCRIPTION

[0047] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present application. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present application.

[0048] Various structural schematic diagrams according to embodiments of the present application are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for clearer expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0049] In the context of the present application, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0050] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0051] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0052] A solar cell is a device that can convert sunlight into electrical energy. Specifically, when the solar cell is in operation, sunlight shines on the semiconductor pn junction of the solar cell, forming new hole-electron pairs. Under the action of the built-in electric field of the pn junction, photogenerated holes flow to the p region, and photogenerated electrons flow to the n region. When the circuit is connected, current can be generated. Among them, a solar cell in which both the positive electrode and the negative electrode are on the back of the cell is a back-contact cell. Compared with a double-sided contact solar cell, the front of the back-contact cell is not blocked by a metal electrode, so that the light-facing side of the back-contact cell has a higher light utilization rate. Therefore, the back-contact cell has a higher short-circuit current and photoelectric conversion efficiency, and is one of the current technical directions for achieving high-efficiency crystalline silicon cells.

[0053] However, the passivation effect of the N region in the existing back contact battery is poor, which is not conducive to improving the conversion efficiency of the back contact battery. Specifically, in the back contact battery, the N-type doped polysilicon layer is doped with N-type impurities such as phosphorus, and the P-type doped polysilicon layer is doped with P-type impurities such as boron. Because the size of phosphorus atoms is relatively large, they are usually doped into the intrinsic polysilicon layer used to manufacture the N-type doped polysilicon layer by substitutional diffusion. The size of boron atoms is relatively small, and they are usually doped into the intrinsic polysilicon layer used to manufacture the P-type doped polysilicon layer by interstitial diffusion. Since the substitutional diffusion method is that impurity atoms diffuse in place of semiconductor atoms, it is easy to cause the formed N-type doped polysilicon layer to have more defects (relative to the P-type doped polysilicon layer), and, under the limitation of factors such as doping solid concentration, the doping concentration of impurities in the P-type doped polysilicon layer is limited. Therefore, the doping concentration of impurities in the N-type doped polysilicon layer is usually greater than the doping concentration of impurities in the P-type doped polysilicon layer, which makes the N-type doped polysilicon layer have more defects, resulting in poor passivation effect of the N-type doped polysilicon layer, which is not conducive to the balance of electrons and holes, and further leads to a high carrier recombination rate and poor battery performance.

[0054] In order to solve the above technical problems, in the first aspect, the embodiments of the present application provide a back contact battery. Figures 1 to 3 As shown, the back contact cell provided by the embodiment of the present application includes: a semiconductor substrate 11, and an N-type doped polysilicon layer 12 and a P-type doped polysilicon layer 13 located on the same surface of the semiconductor substrate 11. At least a portion of the N-type doped polysilicon layer 12 and at least a portion of the P-type doped polysilicon layer 13 are arranged at intervals from each other. Among them, the normalized intensity value of the Raman peak corresponding to the N-type doped polysilicon layer 12 is greater than the normalized intensity value of the Raman peak corresponding to the P-type doped polysilicon layer 13, and / or, the Raman peak area value corresponding to the N-type doped polysilicon layer 12 is greater than the Raman peak area value corresponding to the P-type doped polysilicon layer 13, and / or, the half-peak width value of the Raman peak corresponding to the N-type doped polysilicon layer 12 is greater than the half-peak width value of the Raman peak corresponding to the P-type doped polysilicon layer 13.

[0055] In the actual manufacturing process, when performing Raman testing on the N-type doped polysilicon layer and the P-type doped polysilicon layer, it is necessary to separate the other film layers (such as the N-type doped polysilicon layer on the side away from the semiconductor substrate and the P-type doped polysilicon layer on the side away from the semiconductor substrate) from the semiconductor substrate. Figure 4The doped silicon glass layer and / or the surface passivation layer 18, etc. in the semiconductor substrate are removed; and it is also necessary to perform measurements under the same test conditions, especially different film layers that need to be compared need to be measured under the same test conditions to improve the accuracy of the measurement results and the accuracy of the comparison results. Among them, the test position can be the area close to the interconnection structure on the side of the N-type doped polysilicon layer away from the semiconductor substrate, and the area close to the interconnection structure on the side of the P-type doped polysilicon layer away from the semiconductor substrate. The above-mentioned interconnection structure is a conductive structure electrically connected to the interconnection within the string. As for the specific Raman test parameters, they can be: spectral repeatability ±0.02cm -1 , spectral resolution greater than or equal to 0.35cm -1 And less than or equal to 0.65cm -1 , spatial resolution 250nm.

[0056] Secondly, the Raman peak normalized intensity value is obtained by normalizing the intensities corresponding to different Raman peaks in the Raman spectrum obtained after Raman testing of the N-type doped polysilicon layer and the P-type doped polysilicon layer. The Raman peak area value is obtained by integrating the Raman peak intensity and the corresponding Raman wave number. The Raman peak half-peak width value is the peak width value at half the peak height of the Raman peak.

[0057] like Figures 1 to 3As shown, one of the P-type doped polysilicon layer 13 and the N-type doped polysilicon layer 12 can form a high-low junction with the semiconductor substrate 11, and the other can form a PN junction with the semiconductor substrate 11. Based on this, when the solar cell is in a working state, the semiconductor substrate 11 can form a new hole-electron pair after absorbing photons. Under the action of the built-in electric field of the above-mentioned PN junction and the high-low junction, the photogenerated holes flow to the P-type doped polysilicon layer 13, and the photogenerated electrons flow to the N-type doped polysilicon layer 12, and current can be generated after the circuit is connected. Based on this, it can be understood that the passivation effect of the P-type doped polysilicon layer 13 and the N-type doped polysilicon layer 12 on the semiconductor substrate 11 is related to factors such as their own doping concentration, degree of crystallization and thickness. The types of doping elements doped in the N-type doped polysilicon layer 12 and the P-type doped polysilicon layer 13 are different. Moreover, since the size of the N-type dopant phosphorus atom is relatively large, its corresponding doping method is substitutional diffusion; the size of the P-type dopant boron atom is relatively small, so its corresponding doping method is interstitial diffusion. At the same time, since the substitutional diffusion method is that the impurity atoms replace the position of the semiconductor atoms for diffusion, it is easy to generate more defects in the film layer of the N-type doped polysilicon layer 12 when forming it (relative to the P-type doped polysilicon layer 13). By adjusting the degree of crystallization of the N-type doped polysilicon layer 12 and the P-type doped polysilicon layer 13, the N-type doped polysilicon layer 12 has a higher degree of crystallization, the number of grain boundaries in the N-type doped polysilicon layer 12 is reduced, and the distribution of different grains in the N-type doped polysilicon layer 12 is made more orderly and regular, thereby reducing the number of defects in the N-type doped polysilicon layer 12. In addition, the difference in the Raman peak area values ​​corresponding to the N-type doped polysilicon layer 12 and the P-type doped polysilicon layer 13, the difference in the Raman peak normalized intensity values ​​corresponding to the two, and the difference in the Raman peak half-peak width values ​​corresponding to the two come from the doping concentration and crystallization degree of the doping elements in the two. Within a certain range, the Raman peak area values ​​of the N-type doped polysilicon layer 12 and the P-type doped polysilicon layer 13, the Raman peak normalized intensity values ​​corresponding to the two, and the Raman peak half-peak width values ​​corresponding to the two are respectively proportional to the doping element concentration and the crystallization degree.Based on this, by adjusting the size relationship of at least one of the Raman peak area value, the Raman peak normalized intensity value and the Raman peak half-peak width value of the above-mentioned two film layers, the crystallization degree and doping concentration of the N-type doped polysilicon layer 12 and the P-type doped polysilicon layer 13 are regulated, and at least one of the Raman peak area value, the Raman peak normalized intensity value and the Raman peak half-peak width value corresponding to the N-type doped polysilicon layer 12 is set to be larger than the Raman peak area value, the Raman peak normalized intensity value and the Raman peak half-peak width value corresponding to the P-type doped polysilicon layer 13, respectively, so as to reduce The internal defects caused by substitutional doping of the low N-type doped polysilicon layer 12 during the manufacturing process ensure that the N-type doped polysilicon layer 12 in the back contact battery has a lower number of defects, and improve the field passivation effect of the N-type doped polysilicon layer 12, so that the N-type doped polysilicon layer 12 and the P-type doped polysilicon layer 13 have good passivation effects on the semiconductor substrate 11, thereby making the parts of the semiconductor substrate 11 corresponding to the N-type doped polysilicon layer 12 and the P-type doped polysilicon layer 13 respectively have a lower carrier recombination rate, thereby improving the conversion efficiency of the back contact battery.

[0058] In actual application, the semiconductor substrate may be any semiconductor substrate such as a silicon substrate, a silicon germanium substrate, a germanium substrate or a gallium arsenide substrate.

[0059] For the N-type doped polysilicon layer and the P-type doped polysilicon layer, in terms of the formation range, such as Figure 1 As shown, at least a portion of the N-type doped polysilicon layer 12 and at least a portion of the P-type doped polysilicon layer 13 may be spaced apart in a direction parallel to the surface of the semiconductor substrate 11. Alternatively, as Figure 5 As shown, at least a portion of the N-type doped polysilicon layer 12 and at least a portion of the P-type doped polysilicon layer 13 may also be spaced apart and distributed along a thickness direction parallel to the semiconductor substrate 11 through an insulating layer (the material of the insulating layer may include any insulating material such as silicon oxide, silicon nitride or silicon oxynitride).

[0060] It is possible that each region in the N-type doped polysilicon layer is spaced apart from each region in the P-type doped polysilicon layer. In this case, the risk of leakage between the N-type doped polysilicon layer and the P-type doped polysilicon layer is low, which is beneficial to improving the conversion efficiency of the back contact battery. Alternatively, it is also possible that only some regions in the N-type doped polysilicon layer and only some regions in the P-type doped polysilicon layer are spaced apart. In this case, the electrically connected portions in the N-type doped polysilicon layer and the P-type doped polysilicon layer can form a diode structure with a lower reverse breakdown voltage to reduce the risk of hot spots in the back contact battery; in this case, the proportion of the electrically connected portions in the N-type doped polysilicon layer and the P-type doped polysilicon layer can be determined based on the requirements for the hot spot risk and conversion efficiency of the back contact battery in the actual application scenario, and is not specifically limited here.

[0061] In terms of the formation position, Figure 1 As shown, the P-type doped polysilicon layer 13 can be directly formed on the semiconductor substrate 11. Alternatively, as shown in FIG. Figure 6 As shown, the back contact battery may also include a first tunneling layer 14, which is located between the P-type doped polysilicon layer 13 and the semiconductor substrate 11. In this case, the first tunneling layer 14 and the P-type doped polysilicon layer 13 may constitute a tunneling passivation contact structure to chemically passivate the semiconductor substrate 11 and selectively collect holes, thereby reducing the carrier recombination rate on the side of the semiconductor substrate 11 where the first tunneling layer 14 is formed, which is beneficial to improving the photoelectric conversion efficiency of the back contact battery. Among them, the embodiment of the present application does not specifically limit the material and thickness of the first tunneling layer 14. Exemplarily, the material of the first tunneling layer may include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium nitride. The thickness of the first tunneling layer may be greater than or equal to 0.5 nm and less than or equal to 5 nm.

[0062] As for the N-type doped polysilicon layer, Figure 1 As shown, the N-type doped polysilicon layer 12 can be directly formed at least on the semiconductor substrate 11 (e.g., the N-type doped polysilicon layer 12 can be formed only on the semiconductor substrate 11, or the N-type doped polysilicon layer 12 can be formed on the semiconductor substrate 11 and extend to part of the P-type doped polysilicon layer 13). Or, Figure 6 and Figure 7 As shown, the back contact cell may also include a second tunneling layer 15, which is at least located between the N-type doped polysilicon layer 12 and the semiconductor substrate 11. In this case, the second tunneling layer 15 and the N-type doped polysilicon layer 12 may constitute a tunneling passivation contact structure to chemically passivate the semiconductor substrate 11 and selectively collect electrons, thereby reducing the carrier recombination rate on the side of the semiconductor substrate 11 where the second tunneling layer 15 is formed, and is conducive to improving the photoelectric conversion efficiency of the back contact cell. It can be understood that the formation range of the second tunneling layer 15 changes with the change of the formation range of the N-type doped polysilicon layer 12, the second tunneling layer 15 is arranged on the side of the N-type doped polysilicon layer 12 close to the semiconductor substrate 11, and the second tunneling passivation layer is arranged between the N-type doped polysilicon layer 12 and the structure in contact with itself. Secondly, the material and thickness of the second tunneling layer 15 may refer to the material and thickness of the first tunneling layer 14 mentioned above. The material of the second tunneling layer 15 and the material of the first tunneling layer 14 may be the same or different. The thickness of the second tunnel layer 15 may be the same as or different from the thickness of the first tunnel layer 14 .

[0063] Among them, Figure 8As shown, when the thickness of the second tunneling layer 15 is different from the thickness of the first tunneling layer 14, the thickness of the first tunneling layer 14 can be less than the thickness of the second tunneling layer 15. In this case, compared with the boron atoms doped in the P-type doped polysilicon layer 13, the size of the phosphorus atoms in the N-type doped polysilicon layer 12 is relatively large, and it is less likely to diffuse into the semiconductor substrate 11. Therefore, the thickness of the first tunneling layer 14 is relatively small, so that the first tunneling layer 14 has a lower transmission resistance, which is conducive to improving the carrier collection efficiency of the N-type doped polysilicon layer 12. The thickness of the second tunneling layer 15 is relatively large, so that the second tunneling layer 15 has a higher diffusion barrier effect on the boron atoms doped in the P-type doped polysilicon layer 13, ensuring that a PN junction or a high-low junction with a higher built-in electric field strength can be formed between the P-type doped polysilicon layer 13 and the semiconductor substrate 11. In addition, the first tunnel layer 14 and the second tunnel layer 15 with different thicknesses have different chemical passivation effects. The Raman peak area value and / or the Raman peak normalized intensity value corresponding to the N-type doped polysilicon layer 12 are set to be greater than the Raman peak area value and / or the Raman peak normalized intensity value corresponding to the P-type doped polysilicon layer 13, respectively. This can make up for the defect that the comprehensive passivation effect of the back contact battery in the N region is lower than the comprehensive passivation effect in the P region due to the small thickness of the first tunnel layer 14 (the passivation effect of the first tunnel layer 14 is lower than the passivation effect of the second tunnel layer 15), thereby ensuring that the N region and the P region of the back contact battery have good comprehensive passivation effects.

[0064] When the thickness of the first tunnel layer is less than that of the second tunnel layer, the thickness difference between the two can be determined according to the requirements for the passivation effect of the first tunnel layer and the second tunnel layer in the actual application scenario, and the requirements for the diffusion barrier effect of the two, and no specific limitation is made here.

[0065] Exemplarily, the thickness ratio of the second tunnel layer to the first tunnel layer may be greater than or equal to 1.01 and less than or equal to 3. For example, the thickness ratio of the first tunnel layer to the second tunnel layer may be 1.01, 1.1, 1.2, 1.4, 1.6, 1.8, 2, 2.2, 2.5, 2.8 or 3. In this case, it is possible to prevent the thickness of the second tunnel layer from being too large due to the excessive thickness ratio of the second tunnel layer to the first tunnel layer, so that the second tunnel layer can reduce its own transmission resistance as much as possible under the premise of having sufficient diffusion barrier effect, and ensure that the P-type doped polysilicon layer has a higher carrier collection efficiency. In addition, it is also possible to prevent the thickness difference between the first tunnel layer and the second tunnel layer from being too large, which makes it difficult to compensate for the difference in the comprehensive passivation effect of the back contact battery in the N region and the P region by adjusting the Raman peak area value and / or the Raman peak normalized intensity value corresponding to the N-type doped polysilicon layer and the P-type doped polysilicon layer, and ensure that the back contact battery has a higher conversion efficiency.

[0066] From the doping aspect, in the actual application process, as mentioned above, due to the limitations of doping solid concentration and doping difficulty, the doping concentration of the dopant in the N-type doped polysilicon layer is often greater than the doping concentration of the dopant in the P-type doped polysilicon layer. As for the specific size of the doping concentration of the dopant in the N-type doped polysilicon layer and the P-type doped polysilicon layer and the difference between the two, it can be determined according to the requirements for the conversion efficiency of the back contact battery in the actual application scenario and the actual manufacturing process, and no specific limitation is made here.

[0067] For example, the ratio between the doping concentration of the dopant in the N-type doped polysilicon layer and the doping concentration of the dopant in the P-type doped polysilicon layer may be greater than or equal to 10 and less than or equal to 10. 4 For example, the ratio between the doping concentration of the dopant in the N-type doped polysilicon layer and the doping concentration of the dopant in the P-type doped polysilicon layer may be 10, 50, 100, 500, 1000, 2000, 3000, 4000, 5000, 8000, or 10 4 wait.

[0068] In terms of film thickness, the thickness of the N-type doped polysilicon layer may be equal to the thickness of the P-type doped polysilicon layer, or may be greater than the thickness of the P-type doped polysilicon layer. When the thickness of the N-type doped polysilicon layer and the P-type doped polysilicon layer are different, the thickness difference between the two may be determined based on the requirements for the passivation effects of the N-type doped polysilicon layer and the P-type doped polysilicon layer in the actual application scenario, and is not specifically limited here.

[0069] Exemplarily, the ratio between the thickness of the N-type doped polysilicon layer and the thickness of the P-type doped polysilicon layer may be greater than or equal to 0.25 and less than or equal to 1.5. For example, the ratio between the thickness of the N-type doped polysilicon layer and the thickness of the P-type doped polysilicon layer may be 0.25, 0.3, 0.5, 0.6, 0.8, 1, 1.2, 1.3, 1.4 or 1.5, etc.

[0070] From the perspective of film structure, Figure 8 As shown, the N-type doped polysilicon layer 12 and / or the P-type doped polysilicon layer 13 may be a single-layer structure. Figures 9 to 13 As shown, the N-type doped polysilicon layer 12 and / or the P-type doped polysilicon layer 13 may include multiple doped polysilicon layers stacked along the thickness direction of the semiconductor substrate 11. Along the thickness direction away from the semiconductor substrate 11, in the N-type doped polysilicon layer 12 or the P-type doped polysilicon layer, the normalized intensity values ​​of the Raman peaks corresponding to different doped polysilicon layers gradually increase, and / or, the area values ​​of the Raman peaks corresponding to different doped polysilicon layers gradually increase, and / or, the half-peak width values ​​of the Raman peaks corresponding to different doped polysilicon layers gradually increase.

[0071] Taking an N-type doped polysilicon layer having multiple doped polysilicon layers as an example for explanation: in the N-type doped polysilicon layer, at least one of the Raman peak area value, the Raman peak normalized intensity value, and the Raman peak half-peak width value corresponding to the doped polysilicon layer close to the semiconductor substrate is adjusted to be smaller than at least one of the Raman peak area value, the Raman peak normalized intensity value, and the Raman peak half-peak width value corresponding to the doped polysilicon layer away from the semiconductor substrate, so that the doped polysilicon layer located outside (i.e., the doped polysilicon layer away from the semiconductor substrate) has a higher doping concentration and crystallization degree. The doped polysilicon layer located outside needs to be in electrical contact with the electrode responsible for extracting carriers. When the doped polysilicon layer located outside has a higher doping concentration and crystallization degree, the contact resistance between the N-type doped polysilicon layer and the electrode can be reduced, thereby reducing the transmission loss. The doped polysilicon layer located on the inner side (i.e., the doped polysilicon layer close to the semiconductor substrate) has a smaller doping concentration, which can also reduce the doping concentration difference between the part of the N-type doped polysilicon layer close to the semiconductor substrate and the semiconductor substrate, reduce the risk of diffusion of doping elements in the N-type doped polysilicon layer into the semiconductor substrate, reduce the diffusion depth and / or diffusion concentration of the inner expansion layer, and further improve the conversion efficiency of the back contact battery. Secondly, the application principle of the P-type doped polysilicon layer having the beneficial effects of multiple doped polysilicon layers can be referred to the previous text and will not be repeated here.

[0072] In actual application, in the N-type doped polysilicon layer or the P-type doped polysilicon layer, only one of the normalized intensity values ​​of the Raman peaks, the area values ​​of the Raman peaks and the half-peak width values ​​of the Raman peaks corresponding to different layers of doped polysilicon layers may gradually increase; or, two of the normalized intensity values ​​of the Raman peaks, the area values ​​of the Raman peaks and the half-peak width values ​​of the Raman peaks corresponding to different layers of doped polysilicon layers may gradually increase; or, it may also be possible that the normalized intensity values ​​of the Raman peaks, the area values ​​of the Raman peaks and the half-peak width values ​​of the Raman peaks corresponding to different layers of doped polysilicon layers all gradually increase.

[0073] Secondly, only the N-type doped polysilicon layer may include multiple doped polysilicon layers, only the P-type doped polysilicon layer may include multiple doped polysilicon layers, or both the N-type doped polysilicon layer and the P-type doped polysilicon layer may include multiple doped polysilicon layers.

[0074] As for the number of doped polysilicon layers included in the N-type doped polysilicon layer or the P-type doped polysilicon layer, the differences in the normalized intensity values ​​of the Raman peaks of different doped polysilicon layers, the Raman peak area values ​​and the half-peak width values ​​of the Raman peaks, and the thicknesses of different doped polysilicon layers, they can be determined based on the passivation effect of the N-type doped polysilicon layer or the P-type doped polysilicon layer in the actual application scenario, and the requirements for the contact performance between the doped polysilicon layer and the electrode, and are not specifically limited here.

[0075] For example: Figures 9 to 13 As shown, the N-type doped polysilicon layer 12 and / or the P-type doped polysilicon layer 13 may include a first doped polysilicon layer 16 and a second doped polysilicon layer 17 ; the second doped polysilicon layer 17 is located on a side of the first doped polysilicon layer 16 away from the semiconductor substrate 11 .

[0076] Exemplarily, in the case where the N-type doped polysilicon layer and / or the P-type doped polysilicon layer include a first doped polysilicon layer and a second doped polysilicon layer, in the N-type doped polysilicon layer or the P-type doped polysilicon layer, the ratio between the Raman peak area value corresponding to the first doped polysilicon layer and the Raman peak area value corresponding to the second doped polysilicon layer can be greater than or equal to 0.5:1 and less than 1:1, and / or the ratio between the normalized intensity value of the Raman peak corresponding to the first doped polysilicon layer and the normalized intensity value of the Raman peak corresponding to the second doped polysilicon layer can be greater than or equal to 0.6:1 and less than 1:1.

[0077] For example, in an N-type doped polysilicon layer or a P-type doped polysilicon layer, the ratio between the Raman peak area value corresponding to the first doped polysilicon layer and the Raman peak area value corresponding to the second doped polysilicon layer can be 0.5:1, 0.6:1, 0.7:1, 0.8:1, 0.9:1 or 0.95:1, etc.

[0078] For example, in an N-type doped polysilicon layer or a P-type doped polysilicon layer, the ratio between the normalized intensity value of the Raman peak corresponding to the first doped polysilicon layer and the normalized intensity value of the Raman peak corresponding to the second doped polysilicon layer can be 0.6:1, 0.65:1, 0.7:1, 0.8:1, 0.9:1 or 0.95:1, etc.

[0079] Taking the ratio of the Raman peak area values ​​corresponding to the first doped polysilicon layer and the second doped polysilicon layer of the N-type doped polysilicon layer satisfying the above relationship as an example, it is possible to prevent the doping concentration of the first doped polysilicon layer from being too high or the doping concentration and degree of crystallization of the second doped polysilicon layer from being too low due to the ratio between the Raman peak area value corresponding to the first doped polysilicon layer and the Raman peak area value corresponding to the second doped polysilicon layer being too small, ensuring that the portion of the semiconductor substrate corresponding to the N-type doped polysilicon layer has an internal expansion with a lower concentration and / or a smaller diffusion depth, and ensuring that the N-type doped polysilicon layer and the electrode have a lower transmission loss. It is also possible to prevent the doping concentration of the first doped polysilicon layer from being too low or the doping concentration and degree of crystallization of the second doped polysilicon layer from being too high due to the ratio being too large, ensuring that the N-type doped polysilicon layer has a higher carrier collection efficiency, and reducing the process difficulty of manufacturing the N-type doped polysilicon layer. Secondly, the application principle of the beneficial effect that the ratio of the normalized intensity values ​​of the Raman peaks corresponding to the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer of the N-type doped polycrystalline silicon layer satisfies the above relationship, and the ratio of the Raman peak areas and / or normalized intensity values ​​of the Raman peaks corresponding to the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer of the P-type doped polycrystalline silicon layer satisfies the above relationship can be referred to the previous text and will not be repeated here.

[0080] Exemplarily, in the N-type doped polysilicon layer or the P-type doped polysilicon layer, the ratio of the thickness of the first doped polysilicon layer to the thickness of the second doped polysilicon layer may be greater than or equal to 1:2 and less than or equal to 1:5. For example, in the N-type doped polysilicon layer or the P-type doped polysilicon layer, the ratio of the thickness of the first doped polysilicon layer to the thickness of the second doped polysilicon layer may be 1:2, 1:2.5, 1:3, 1:3.5, 1:4, 1:4.5 or 1:5, etc. In this case, the ratio of the thickness of the first doped polysilicon layer and the thickness of the second doped polysilicon layer of the N-type doped polysilicon layer satisfies the above relationship as an example for explanation: it can prevent the thickness of the first doped polysilicon layer from being too large or the thickness of the second doped polysilicon layer from being too small due to the small ratio, ensure that the thickness of the first doped polysilicon layer with a relatively low doping concentration in the N-type doped polysilicon layer is relatively small, and ensure that the thickness of the second doped polysilicon layer with a relatively high doping concentration and a relatively large degree of crystallization in the N-type doped polysilicon layer is relatively large, so that the carrier collection efficiency between itself and the electrode is high and the transmission loss is low. The application principle of the beneficial effect of the ratio of the thickness of the first doped polysilicon layer and the second doped polysilicon layer of the P-type doped polysilicon layer satisfying the above relationship can be referred to the previous text and will not be repeated here.

[0081] It should be noted that, in the case where both the N-type doped polysilicon layer and the P-type doped polysilicon layer include a first doped polysilicon layer and a second doped polysilicon layer, the differences in Raman peak area values, normalized intensity values ​​of Raman peaks and thicknesses between the first doped polysilicon layer included in the N-type doped polysilicon layer and the first doped polysilicon layer included in the P-type doped polysilicon layer, as well as the differences in Raman peak area values, normalized intensity values ​​of Raman peaks and thicknesses between the second doped polysilicon layer included in the N-type doped polysilicon layer and the second doped polysilicon layer included in the P-type doped polysilicon layer, can be set according to actual needs and are not specifically limited here.

[0082] From the aspect of Raman test parameters of the film layer, the embodiment of the present application does not specifically limit the size of the Raman peak area value, the Raman peak normalized intensity value and the Raman peak half-peak width value corresponding to the N-type doped polysilicon layer and the P-type doped polysilicon layer, as long as the Raman peak area value corresponding to the N-type doped polysilicon layer is greater than the Raman peak area value corresponding to the P-type doped polysilicon layer, and / or, the Raman peak normalized intensity value corresponding to the N-type doped polysilicon layer is greater than the Raman peak normalized intensity value corresponding to the P-type doped polysilicon layer, and / or, the Raman peak half-peak width value corresponding to the N-type doped polysilicon layer is greater than the Raman peak half-peak width value corresponding to the P-type doped polysilicon layer. As mentioned above, the difference in the Raman peak area value corresponding to the N-type doped polysilicon layer and the P-type doped polysilicon layer, the difference in the Raman peak normalized intensity value corresponding to the two, and the Raman peak half-peak width value corresponding to the two come from the doping concentration and crystallization degree of the doping elements in the two. Within a certain range, the Raman peak area values ​​of the N-type doped polysilicon layer and the P-type doped polysilicon layer, the Raman peak normalized intensity values ​​corresponding to the two, and the Raman peak half-peak width values ​​corresponding to the two are respectively proportional to the concentration of the doping element and the degree of crystallization. In addition, the passivation effect of the P-type doped polysilicon layer and the N-type doped polysilicon layer on the semiconductor substrate is related to factors such as their own doping concentration, degree of crystallization and thickness. By adjusting at least one of the Raman peak area value, the Raman peak normalized intensity value and the Raman peak half-peak width value corresponding to the N-type doped polysilicon layer and the P-type doped polysilicon layer, the passivation effect of the N-type doped polysilicon layer and the P-type doped polysilicon layer can be regulated. Based on this, the Raman peak area value, Raman peak normalized intensity value and Raman peak half-peak width value corresponding to the N-type doped polysilicon layer and the P-type doped polysilicon layer, as well as the difference between the two can be determined according to the requirements for the passivation effect of the P-type doped polysilicon layer and the N-type doped polysilicon layer in the actual application scenario, and no specific limitation is made here.

[0083] Exemplarily, the ratio between the Raman peak area value corresponding to the N-type doped polysilicon layer and the Raman peak area value corresponding to the P-type doped polysilicon layer may be greater than or equal to 1.1:1 and less than or equal to 2.1:1. For example, the ratio between the Raman peak area value corresponding to the N-type doped polysilicon layer and the Raman peak area value corresponding to the P-type doped polysilicon layer may be 1.1:1, 1.2:1, 1.4:1, 1.6:1, 1.8:1, 2:1 or 2.1:1, etc. In this case, the ratio between the Raman peak area value corresponding to the N-type doped polysilicon layer and the Raman peak area value corresponding to the P-type doped polysilicon layer is within the above range, which is conducive to preventing the N-type doped polysilicon layer from having a low crystallization degree and a low doping concentration due to the small ratio, thereby ensuring that the N-type doped polysilicon layer has fewer defects and a stronger field passivation effect. In addition, it is also possible to prevent the Raman peak area value corresponding to the N-type doped polysilicon layer from being too large and / or the Raman peak area value corresponding to the P-type doped polysilicon layer from being too small due to the large ratio, thereby reducing the process difficulty of manufacturing the N-type doped polysilicon layer, and ensuring that the N-type doped polysilicon layer and the P-type doped polysilicon layer have good passivation effects on the semiconductor substrate, respectively, further reducing the carrier recombination rates of the parts of the semiconductor substrate corresponding to the N-type doped polysilicon layer and the P-type doped polysilicon layer, respectively.

[0084] Exemplarily, the difference between the normalized intensity value of the Raman peak corresponding to the N-type doped polysilicon layer and the normalized intensity value of the Raman peak corresponding to the P-type doped polysilicon layer may be greater than or equal to 0.1 and less than or equal to 0.4. For example, the difference between the normalized intensity value of the Raman peak corresponding to the N-type doped polysilicon layer and the normalized intensity value of the Raman peak corresponding to the P-type doped polysilicon layer may be 0.1, 0.12, 0.14, 0.18, 0.2, 0.25, 0.3, 0.35 or 0.4, etc. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the ratio between the Raman peak area value corresponding to the N-type doped polysilicon layer and the Raman peak area value corresponding to the P-type doped polysilicon layer being greater than or equal to 1.1:1 and less than or equal to 2.1:1 as described above, which will not be repeated here.

[0085] For example, the half-peak width of the Raman peak corresponding to the N-type doped polysilicon layer may be greater than or equal to 3 cm -1 , and less than or equal to 15cm -1 For example, the half-peak width of the Raman peak corresponding to the N-type doped polysilicon layer can be 3cm -1 , 5cm -1 、7cm -1 、8cm -1 、10cm -1 、12cm -1 、13cm -1 、14cm-1 or 15cm -1 Etc. In this case, the half-peak width value of the Raman peak corresponding to the N-type doped polysilicon layer can reflect the crystal quality of the N-type doped polysilicon layer to a certain extent. The half-peak width value of the Raman peak corresponding to the N-type doped polysilicon layer is related to the degree of crystallization, doping concentration and number of defects of the N-type doped polysilicon layer. Based on this, when the half-peak width value of the Raman peak corresponding to the N-type doped polysilicon layer is within the above range, it can prevent the degree of crystallization of the N-type doped polysilicon layer from being too low and the number of defects from being too large due to the half-peak width value of the Raman peak corresponding to the N-type doped polysilicon layer, and further make the N-type doped polysilicon layer and the P-type doped polysilicon layer have good passivation effects. In addition, it can also prevent the difficulty of manufacturing the N-type doped polysilicon layer due to the large half-peak width value of the Raman peak corresponding to the N-type doped polysilicon layer, thereby improving the yield of the back contact battery.

[0086] When the N-type doped polysilicon layer includes a first doped polysilicon layer and a second doped polysilicon layer, the half-peak width of the Raman peak corresponding to the N-type doped polysilicon layer may be greater than or equal to 5 cm -1 , and less than or equal to 15cm -1 .

[0087] When the N-type doped polysilicon layer is a single-layer structure, the half-peak width of the Raman peak corresponding to the N-type doped polysilicon layer can be greater than or equal to 3cm -1 , and less than or equal to 13cm -1 .

[0088] For example, the half-peak width of the Raman peak corresponding to the P-type doped polysilicon layer may be greater than or equal to 1 cm -1 , and less than or equal to 11cm -1 For example, the half-peak width of the Raman peak corresponding to the P-type doped polysilicon layer can be 1cm -1 , 3cm -1 , 5cm -1 、6cm -1 、8cm -1 、9cm -1 , 10cm -1 or 11cm -1Etc. In this case, the half-peak width value of the Raman peak corresponding to the P-type doped polysilicon layer is within the above range, which is conducive to preventing the P-type doped polysilicon layer from having too low a degree of crystallization and too low a doping concentration due to the Raman peak half-peak width value corresponding to the P-type doped polysilicon layer being too small, and ensuring that the P-type doped polysilicon layer has lower film defects and stronger field passivation effect. In addition, it can also prevent the P-type doped polysilicon layer from having too high a degree of crystallization and too high a doping concentration due to the Raman peak half-peak width value corresponding to the P-type doped polysilicon layer being too large, while reducing the process difficulty of manufacturing the P-type doped polysilicon layer, and it can also prevent the manufacturing temperature from being too high to manufacture the P-type doped polysilicon layer with a high degree of crystallization and a high doping concentration, resulting in more P-type doped polysilicon layers in the P-type doped polysilicon layer expanding into the semiconductor substrate, ensuring that a PN junction or a high-low junction with a high built-in electric field strength can be formed between the P-type doped polysilicon layer and the semiconductor substrate, further improving the conversion efficiency of the back contact battery.

[0089] Exemplarily, the normalized intensity value of the Raman peak corresponding to the N-type doped polysilicon layer may be greater than or equal to 0.75 and less than 1. For example, the normalized intensity value of the Raman peak corresponding to the N-type doped polysilicon layer may be 0.75, 0.77, 0.8, 0.83, 0.85, 0.88, 0.9, 0.92, 0.95 or 0.99, etc. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the ratio between the Raman peak area value corresponding to the N-type doped polysilicon layer and the Raman peak area value corresponding to the P-type doped polysilicon layer being greater than or equal to 1.1:1 and less than or equal to 2.1:1 as described above, which will not be repeated here.

[0090] When the N-type doped polysilicon layer includes a first doped polysilicon layer and a second doped polysilicon layer, a normalized intensity value of a Raman peak corresponding to the N-type doped polysilicon layer may be greater than or equal to 0.85 and less than or equal to 1.

[0091] When the N-type doped polysilicon layer is a single-layer structure, the normalized intensity value of the Raman peak corresponding to the N-type doped polysilicon layer may be greater than or equal to 0.75 and less than or equal to 0.9.

[0092] Exemplarily, the normalized intensity value of the Raman peak corresponding to the P-type doped polysilicon layer may be greater than or equal to 0.65 and less than or equal to 0.8. For example, the normalized intensity value of the Raman peak corresponding to the P-type doped polysilicon layer may be 0.65, 0.68, 0.7, 0.72, 0.75, 0.76, 0.78 or 0.8, etc. The application principle of the beneficial effect in this case can refer to the aforementioned Raman peak half-peak width value corresponding to the P-type doped polysilicon layer being greater than or equal to 1 cm -1 , and less than or equal to 11cm -1 The application principle of the beneficial effect will not be repeated here.

[0093] In a second aspect, an embodiment of the present application provides a method for manufacturing a back-contact battery. The method for manufacturing the back-contact battery includes the following steps: First, a semiconductor substrate is provided. Next, an N-type doped polysilicon layer and a P-type doped polysilicon layer are formed on the same surface of the semiconductor substrate. Along the thickness direction perpendicular to the semiconductor substrate, at least a portion of the N-type doped polysilicon layer and at least a portion of the P-type doped polysilicon layer are spaced apart from each other. Among them, the normalized intensity value of the Raman peak corresponding to the N-type doped polysilicon layer is greater than the normalized intensity value of the Raman peak corresponding to the P-type doped polysilicon layer, and / or, the Raman peak area value corresponding to the N-type doped polysilicon layer is greater than the Raman peak area value corresponding to the P-type doped polysilicon layer, and / or, the Raman peak half-peak width value corresponding to the N-type doped polysilicon layer is greater than the Raman peak half-peak width value corresponding to the P-type doped polysilicon layer.

[0094] The beneficial effects of the second aspect and its various implementations in the embodiments of the present application can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0095] In the actual application process, the material of the semiconductor substrate, and the relevant information of the N-type doped polysilicon layer and the P-type doped polysilicon layer can be referred to the previous text, and will not be repeated here. In addition, a P-type doped polysilicon layer may be formed on the semiconductor substrate first, and then an N-type doped polysilicon layer may be formed; or, an N-type doped polysilicon layer may be formed on the semiconductor substrate first, and then a P-type doped polysilicon layer may be formed. The embodiment of the present application does not specifically limit the manufacturing order of the N-type doped polysilicon layer and the P-type doped polysilicon layer, which can be determined according to the formation range of the N-type doped polysilicon layer and the P-type doped polysilicon layer, and actual needs. As for the specific formation process of the P-type doped polysilicon layer and the N-type doped polysilicon layer, it can be determined according to the formation range and film structure of the N-type doped polysilicon layer and the P-type doped polysilicon layer, as well as actual needs.

[0096] Exemplarily, when the N-type doped polysilicon layer and / or the P-type doped polysilicon layer is a single-layer structure, forming a single-layer N-type doped polysilicon layer and / or a P-type doped polysilicon layer on a semiconductor substrate may include the steps of: forming an intrinsic polysilicon layer on a semiconductor substrate by using processes such as chemical vapor deposition. Then, doping the intrinsic polysilicon layer by using processes such as diffusion, so that the intrinsic polysilicon layer forms an N-type doped polysilicon layer or a P-type doped polysilicon layer. Wherein, in the case of using a diffusion process for doping, after the doping process, a doped silicon glass layer will also be formed on the side of the N-type doped polysilicon layer or the P-type doped polysilicon layer away from the semiconductor substrate. Based on this, the doped silicon glass layer can be patterned by laser heat treatment, or photolithography combined with etching process, so that the remaining doped silicon glass layer forms a mask layer that only covers part of the N-type doped polysilicon layer or the P-type doped polysilicon layer. Alternatively, in the case where the mask layer does not include a doped silicon glass layer (or includes not only a doped silicon glass layer), a process such as chemical vapor deposition can be used to form a mask layer on the side of the N-type doped polysilicon layer or the P-type doped polysilicon layer away from the semiconductor substrate, and the mask layer is patterned by etching methods such as laser etching or etching slurry. Then, a process such as wet etching is used to remove the portion of the N-type doped polysilicon layer or the P-type doped polysilicon layer exposed outside the mask layer. Secondly, after one of the N-type doped polysilicon layer and the P-type doped polysilicon layer is formed in the above manner, the other can be formed in the same manner.

[0097] Exemplarily, when the N-type doped polysilicon layer and / or the P-type doped polysilicon layer includes a first doped multilayer and a second doped silicon layer, forming the N-type doped polysilicon layer and / or the P-type doped polysilicon layer on the semiconductor substrate may include the steps of: forming a stacked multilayer doped polysilicon layer in sequence on the semiconductor substrate along the thickness direction of the semiconductor substrate; and gradually increasing the deposition rates corresponding to different doped polysilicon layers in the N-type doped polysilicon layer or the P-type doped polysilicon layer in the direction away from the semiconductor substrate. Wherein, in the N-type doped polysilicon layer or the P-type doped polysilicon layer, the normalized intensity values ​​of the Raman peaks corresponding to different doped polysilicon layers gradually increase, and / or the area values ​​of the Raman peaks corresponding to different doped polysilicon layers gradually increase along the thickness direction away from the semiconductor substrate.

[0098] In the actual manufacturing process, the density of the film layer after the deposition of the different doped polysilicon layers can be adjusted by adjusting the deposition rate when forming the different doped polysilicon layers. It can be understood that, when other factors are the same, the greater the deposition rate, the looser the film layer, and the slower the deposition rate, the denser the film layer. The denser the film layer, the less likely it is to increase the degree of crystallization during the crystallization modification treatment, and the denser the film layer, the higher its doping hindrance effect. Based on this, the difference between the deposition rates of the different doped polysilicon layers in the N-type doped polysilicon layer or the P-type doped polysilicon layer can be determined according to the requirements for the thickness, Raman peak area value and Raman peak normalized intensity value of the different doped polysilicon layers in the actual application scenario, and no specific limitation is made here.

[0099] Exemplarily, sequentially forming a stacked multilayer doped polysilicon layer on a semiconductor substrate may include the steps of: depositing a first doped polysilicon layer on the semiconductor substrate. Next, depositing a second doped polysilicon layer on a side of the first doped polysilicon layer away from the semiconductor substrate. Furthermore, the ratio between the deposition rate corresponding to the second doped polysilicon layer and the deposition rate corresponding to the first doped polysilicon layer is greater than or equal to 2:1 and less than or equal to 5:1.

[0100] In the N-type doped polysilicon layer or the P-type doped polysilicon layer, the thickness, Raman peak area value and Raman peak normalized intensity value of the first doped polysilicon layer and the second doped polysilicon layer can be based on the above reference and will not be repeated here.

[0101] For example, the ratio between the deposition rate corresponding to the second doped polysilicon layer and the deposition rate corresponding to the first doped polysilicon layer can be 2:1, 2.5:1, 3:1, 4:1, 4.5:1 or 5:1, etc. In this case, the crystallization degree and doping concentration of the first doped polysilicon layer and the second doped polysilicon layer can be controlled within a corresponding reasonable range by adjusting the deposition rate. The beneficial effects of the reasonable setting of the crystallization degree and doping concentration of the first doped polysilicon layer and the second doped polysilicon layer can be referred to the above, and will not be repeated here.

[0102] As for the specific manufacturing process of different doped polysilicon layers, reference can be made to the manufacturing process of forming a single-layer structure of an N-type doped polysilicon layer and / or a P-type doped polysilicon layer on a semiconductor substrate as described above, and no further description is given here. In addition, the currently formed doped polysilicon layer may be patterned after forming a single-layer doped polysilicon layer and before forming a subsequent doped polysilicon layer; or, after forming all doped polysilicon layers, patterning of all doped polysilicon layers may be simultaneously achieved under the protection of the same mask layer.

[0103] It should be noted that if the manufactured back contact cell further includes a first tunneling layer and / or a second tunneling layer, the first tunneling layer is first formed by a deposition process before forming the N-type doped polysilicon layer; and / or, the second tunneling layer is first formed by a deposition process before forming the P-type doped polysilicon layer. The materials and thicknesses of the first tunneling layer and the second tunneling layer can be referred to above and will not be described here.

[0104] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0105] The embodiments of the present application are described above. However, these embodiments are only for clearer explanation, and are not intended to limit the scope of the present application. The scope of the present application is limited by the attached claims and their equivalents. Without departing from the scope of the present application, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present application.

Claims

1. A back contact battery, characterized in that: include: A semiconductor substrate, and an N-type doped polysilicon layer and a P-type doped polysilicon layer located on the same surface of the semiconductor substrate; At least a portion of the N-type doped polysilicon layer and at least a portion of the P-type doped polysilicon layer are spaced apart from each other; wherein a normalized intensity value of the Raman peak corresponding to the N-type doped polysilicon layer is greater than a normalized intensity value of the Raman peak corresponding to the P-type doped polysilicon layer, and / or a Raman peak area value corresponding to the N-type doped polysilicon layer is greater than a Raman peak area value corresponding to the P-type doped polysilicon layer, and / or a Raman peak half-peak width value corresponding to the N-type doped polysilicon layer is greater than a Raman peak half-peak width value corresponding to the P-type doped polysilicon layer.

2. The back contact cell according to claim 1, characterized in that: The difference between the normalized intensity value of the Raman peak corresponding to the N-type doped polysilicon layer and the normalized intensity value of the Raman peak corresponding to the P-type doped polysilicon layer is greater than or equal to 0.1 and less than or equal to 0.4; And / or, a ratio between a Raman peak area value corresponding to the N-type doped polysilicon layer and a Raman peak area value corresponding to the P-type doped polysilicon layer is greater than or equal to 1.1:1 and less than or equal to 2.1:

1.

3. The back contact cell according to claim 1 or 2, characterized in that: The normalized intensity value of the Raman peak corresponding to the N-type doped polysilicon layer is greater than or equal to 0.75 and less than 1; And / or, a normalized intensity value of the Raman peak corresponding to the P-type doped polysilicon layer is greater than or equal to 0.65 and less than or equal to 0.

8.

4. The back contact cell according to claim 1 or 2, characterized in that: The half-peak width of the Raman peak corresponding to the N-type doped polysilicon layer is greater than or equal to 3 cm -1 , and less than or equal to 15cm -1 ; And / or, the Raman peak half-peak width corresponding to the P-type doped polysilicon layer is greater than or equal to 1 cm -1 , and less than or equal to 11cm -1 .

5. The back contact cell according to claim 1 or 2, characterized in that: The back contact cell further includes a first tunneling layer and a second tunneling layer; the first tunneling layer is at least located between the N-type doped polysilicon layer and the semiconductor substrate; the second tunneling layer is located between the P-type doped polysilicon layer and the semiconductor substrate; The thickness of the first tunneling layer is smaller than the thickness of the second tunneling layer.

6. The back contact cell according to claim 5, characterized in that: A thickness ratio of the second tunneling layer to the first tunneling layer is greater than or equal to 1.01 and less than or equal to 3.

7. The back contact cell according to claim 1 or 2, characterized in that: The N-type doped polysilicon layer and / or the P-type doped polysilicon layer include multiple doped polysilicon layers stacked along the thickness direction of the semiconductor substrate; In the N-type doped polysilicon layer or the P-type doped polysilicon layer, along the thickness direction away from the semiconductor substrate, the normalized intensity values ​​of the Raman peaks corresponding to different layers of the doped polysilicon layers gradually increase, and / or, the area values ​​of the Raman peaks corresponding to different layers of the doped polysilicon layers gradually increase, and / or, the half-peak width values ​​of the Raman peaks corresponding to different layers of the doped polysilicon layers gradually increase.

8. The back contact battery according to claim 7, characterized in that: In the N-type doped polysilicon layer or the P-type doped polysilicon layer, the multi-layer doped polysilicon layer includes a first doped polysilicon layer and a second doped polysilicon layer; the second doped polysilicon layer is located on a side of the first doped polysilicon layer away from the semiconductor substrate; In the N-type doped polysilicon layer or the P-type doped polysilicon layer, the ratio between the normalized intensity value of the Raman peak corresponding to the first doped polysilicon layer and the normalized intensity value of the Raman peak corresponding to the second doped polysilicon layer is greater than or equal to 0.6:1 and less than 1:1, and / or the ratio between the area value of the Raman peak corresponding to the first doped polysilicon layer and the area value of the Raman peak corresponding to the second doped polysilicon layer is greater than or equal to 0.5:1 and less than 1:

1.

9. The back contact cell according to claim 7, characterized in that: In the N-type doped polysilicon layer or the P-type doped polysilicon layer, the multi-layer doped polysilicon layer includes a first doped polysilicon layer and a second doped polysilicon layer; the second doped polysilicon layer is located on a side of the first doped polysilicon layer away from the semiconductor substrate; In the N-type doped polysilicon layer or the P-type doped polysilicon layer, a ratio of a thickness of the first doped polysilicon layer to a thickness of the second doped polysilicon layer is greater than or equal to 1:2 and less than or equal to 1:

5.

10. A method for manufacturing a back contact battery, characterized in that: include: Providing a semiconductor substrate; forming an N-type doped polysilicon layer and a P-type doped polysilicon layer on the same surface of the semiconductor substrate; Along a thickness direction perpendicular to the semiconductor substrate, at least a portion of the N-type doped polysilicon layer and at least a portion of the P-type doped polysilicon layer are spaced apart from each other; wherein a normalized intensity value of a Raman peak corresponding to the N-type doped polysilicon layer is greater than a normalized intensity value of a Raman peak corresponding to the P-type doped polysilicon layer, and / or a Raman peak area value corresponding to the N-type doped polysilicon layer is greater than a Raman peak area value corresponding to the P-type doped polysilicon layer, and / or a Raman peak half-peak width value corresponding to the N-type doped polysilicon layer is greater than a Raman peak half-peak width value corresponding to the P-type doped polysilicon layer.

11. The method for manufacturing a back contact battery according to claim 10, characterized in that: Forming the N-type doped polysilicon layer and / or the P-type doped polysilicon layer on the semiconductor substrate comprises: A plurality of doped polysilicon layers are sequentially formed on the semiconductor substrate along the thickness direction of the semiconductor substrate; along the direction away from the semiconductor substrate, the deposition rates of different layers of the doped polysilicon layers in the N-type doped polysilicon layer or the P-type doped polysilicon layer gradually increase; Among them, along the thickness direction away from the semiconductor substrate, in the N-type doped polysilicon layer or the P-type doped polysilicon layer, the normalized intensity values ​​of the Raman peaks corresponding to different layers of the doped polysilicon layer gradually increase, and / or, the area values ​​of the Raman peaks corresponding to different layers of the doped polysilicon layer gradually increase, and / or, the half-peak width values ​​of the Raman peaks corresponding to different layers of the doped polysilicon layer gradually increase.

12. The method for manufacturing a back contact battery according to claim 11, characterized in that: The multiple layers of doped polysilicon layers are sequentially formed on the semiconductor substrate and stacked, comprising: depositing a first doped polysilicon layer on the semiconductor substrate; A second doped polysilicon layer is deposited on a side of the first doped polysilicon layer away from the semiconductor substrate; the multi-layer doped polysilicon layer includes the first doped polysilicon layer and the second doped polysilicon layer; the ratio between the deposition rate corresponding to the second doped polysilicon layer and the deposition rate corresponding to the first doped polysilicon layer is greater than or equal to 2:1 and less than or equal to 5:1.

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