LED chip and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor devices and devices, in particular to an LED chip and a preparation method thereof, and the preparation method comprises the following steps: 1) photoetching: photoetching a required pattern on an epitaxial layer; the top of the N-GaN layer, the multi-quantum hydrazine layer and the P-GaN layer form an N region of the LED chip, and the bottom of the N-GaN layer and a part of the substrate are provided with cutting channels; 2) deep etching: performing deep etching by using an ICP technology so as to at least expose the N-GaN layer; 3) performing angle etching: performing angle etching by using IBE (Inter-Back Etching) to enable the side wall of the N region and / or the side wall of the top edge of the cutting channel to be in an inverted trapezoidal shape; and 4) manufacturing a transparent conductive layer, and depositing a protective layer, a P electrode and an N electrode to obtain the LED chip. According to the process, the light emitting efficiency of the LED chip is improved, so that the external quantum efficiency is improved; the process is stable, and the yield can be improved; therefore, the cutting process step can be omitted, the yield can be improved, the subsequent processing flow is shortened, and the cost is controlled.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices and apparatuses, and in particular to an LED chip and a preparation method thereof. Background Art

[0002] Optimizing the chip structure during chip processing can improve the external quantum efficiency of LEDs by increasing brightness and reducing voltage. Currently, the chip light extraction efficiency is the main factor limiting the external quantum efficiency of the device. The main reason is that the refractive index difference between the substrate material, epitaxial material and air is large, resulting in the light generated in the active area being totally reflected at the interface of materials with different refractive indices and cannot be emitted from the chip.

[0003] At present, the sidewall morphology of chip structures is mostly vertical or positive trapezoidal. By changing the geometric shape of the chip, reducing the propagation distance of light inside the chip and reducing the absorption loss of light, an inverted trapezoidal structure can be used. The inverted trapezoidal structure can be made by laser positive scratching and then high-solubility acid solution high-temperature etching of the sidewall. However, this structure has a complex process, a long process, and a rough etching edge. Therefore, it is necessary to develop an etching method for the sidewall inverted trapezoidal structure with smooth etching edges, simple process, and easy implementation. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for preparing an LED chip to solve the problems in the prior art.

[0005] To achieve the above object and other related objects, the present invention provides a method for preparing an LED chip, the method comprising the following steps:

[0006] 1) Photolithography: photolithography a desired pattern on the epitaxial layer; the epitaxial layer is connected to the substrate, and the epitaxial layer starts from the substrate surface and includes an N-GaN layer, a multi-quantum hydrazine layer, and a P-GaN layer in sequence. The top of the N-GaN layer, the multi-quantum hydrazine layer, and the P-GaN layer form the N region of the LED chip, and a cutting path is provided on the bottom of the N-GaN layer and part of the substrate; the desired pattern is the target pattern of the LED chip and / or the cutting path pattern;

[0007] 2) Deep etching: deep etching is performed using inductively coupled plasma etching technology to expose at least the N-GaN layer;

[0008] 3) Angle etching: using ion beam etching technology to continue etching and perform angle etching, so that the sidewall of the N region and / or the sidewall of the top edge of the cutting path is in an inverted trapezoidal shape;

[0009] 4) Making a transparent conductive layer, depositing a protective layer, a P electrode and an N electrode, and obtaining the LED chip.

[0010] The invention also provides an LED chip obtained by the preparation method.

[0011] The present invention also provides a light emitting diode, which comprises the LED chip.

[0012] As described above, the method for preparing the LED chip of the present invention has the following beneficial effects:

[0013] (1) Compared with conventional processes, the process of the present invention improves light extraction efficiency, thereby improving external quantum efficiency;

[0014] (2) Compared with the sidewall inverted trapezoidal structure made by wet etching, the process of the present invention is stable and is conducive to improving the yield;

[0015] (3) It can save the cutting process step, which is beneficial to improve the yield, shorten the post-processing process and control the cost;

[0016] (4) The external quantum efficiency is precisely controllable, and the brightness improvement can be controlled within the range of 2% to 10%;

[0017] (5) The IBE process itself is universal and compatible and can be applied to the processing of other similar related devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Shown is a schematic diagram of changing the ion beam emission angle in IBE (ion beam etching) of the present invention.

[0019] Figure 2-1 Shown is a schematic diagram of the photon emission light path inside the chip in the comparative example.

[0020] Figure 2-2 Shown is a schematic diagram of the photon emission light path inside the chip in Examples 1-3 of the present invention.

[0021] Figure 3 Shown is a top view of the chip structure of the present invention.

[0022] Figure 4 It shows a schematic diagram of the chip structure prepared in Example 1 of the present invention, wherein the N region angle α is 65°.

[0023] Figure 5 It is a schematic diagram of the chip structure prepared in Example 2 of the present invention, wherein the cutting path angle β is 45°.

[0024] Figure 6 It is a schematic diagram of the chip structure prepared in Example 3 of the present invention, wherein the N region angle α is 50° and the cutting path angle β is 70°.

[0025] Figure 7 Shown is a schematic diagram of the chip structure prepared in a comparative example of the present invention.

[0026] Figures 4 to 7 In the figure, 1 is a sapphire substrate, 2 is N-GaN, 3 is multi-quantum hydrazine, 4 is P-GaN, 5 is an inverted trapezoidal side wall, 6 is the location of the cutting path, P is a P electrode, N is an N electrode, and α and β are the angles between the inverted trapezoidal side wall of the N region and the side wall of the top edge of the cutting path, respectively. DETAILED DESCRIPTION

[0027] The present invention provides a method for preparing an LED chip, the method comprising the following steps:

[0028] 1) Photolithography: photolithography of the required pattern on the epitaxial layer; the epitaxial layer is connected to the substrate, and the epitaxial layer starts from the substrate surface and includes an N-GaN layer, a multi-quantum hydrazine layer, and a P-GaN layer in sequence. The top of the N-GaN layer, the multi-quantum hydrazine layer, and the P-GaN layer form the N region of the LED chip, and a cutting path is provided on the bottom of the N-GaN layer and part of the substrate;

[0029] 2) Deep etching: deep etching is performed using inductively coupled plasma etching (ICP) technology to expose at least the N-GaN layer;

[0030] 3) Angle etching: Angle etching is performed using ion beam etching (IBE) technology to make the sidewall of the N region and / or the sidewall of the top edge of the cutting path in an inverted trapezoidal shape;

[0031] 4) Making a transparent conductive layer, depositing a protective layer, a P electrode and an N electrode, and obtaining the LED chip.

[0032] In the present invention, the "bottom", "bottom part" or "bottom edge" of the LED chip refers to the position close to the substrate, and the "top", "top part" or "top edge" refers to the position far from the substrate.

[0033] In the present invention, the top edge of the cutting path is a portion of the cutting path provided on the N-GaN layer. Figure 5 The position of the reference numeral 61 in the figure is the top edge of the cutting path.

[0034] In step 1), both the substrate and the epitaxial layer can be obtained by existing technologies. For example, the epitaxial layer can be grown on the substrate by existing technologies such as metal organic chemical vapor deposition technology.

[0035] The substrate is selected from any suitable substrate such as a silicon substrate, a sapphire substrate or a silicon carbide substrate.

[0036] The desired pattern can be formed by photolithography technology in the prior art. For example, photolithography includes the following steps:

[0037] 11) Cleaning the epitaxial layer of the LED chip;

[0038] 12) Using photoresist as a mask, or using photoresist and SiO2 as a mask;

[0039] 13) Using a light source of a specific wavelength to selectively expose the photoresist to cause a photochemical reaction;

[0040] 14) Use a developer to process the exposed photoresist to form a desired pattern.

[0041] The desired pattern can be a target pattern or a cutting path pattern of an LED chip. The target pattern of the LED chip refers to a pattern formed by photolithography and etching steps that is critical to the performance and luminous characteristics of the LED chip. The target pattern includes but is not limited to an electrode pattern, a quantum well layer, etc., which affect the current distribution, luminous efficiency, and light extraction efficiency of the LED chip. The cutting path pattern is located at the top edge of the cutting path.

[0042] In some embodiments of the present invention, in step 2), inductively coupled plasma etching technology is used to perform deep etching until the N-GaN layer is exposed or the substrate is exposed.

[0043] In the present invention, Figure 4 In the illustrated embodiment, only the sidewall of the N region of the LED chip is in an inverted trapezoidal shape, and the sidewall of the top edge of the cutting path is perpendicular to the substrate.

[0044] When preparing an LED chip with an inverted trapezoidal structure on the sidewall of the N region, the required pattern in step 1) is the target pattern; step 2) is to perform deep etching using inductively coupled plasma etching technology, with an etching depth of 0.6μm to 1.8μm; step 3) is to continue etching using ion beam etching technology until the total etching depth is 0.8μm to 2.0μm, and perform angle etching on the sidewall of the N region.

[0045] In the present invention, Figure 5 In the illustrated embodiment, the side wall of the N region of the LED chip is perpendicular to the substrate, and the side wall of the top edge of the cutting path is an inverted trapezoidal structure.

[0046] In an embodiment of preparing an LED chip in which the sidewall of the N region is perpendicular to the substrate and the sidewall of the top edge of the cutting path is an inverted trapezoidal structure, the following steps are included:

[0047] a) before the photolithography in step 1), the method further comprises: performing deep etching by using an inductively coupled plasma etching technique to expose the N-GaN layer, wherein the etching depth is 0.8 μm to 2 μm;

[0048] b) The required pattern of step 1) is a cutting path pattern;

[0049] c) Step 2) Etching the N-GaN layer to the substrate using ICP (inductively coupled plasma etching) technology, with an etching depth of 15 μm to 50 μm;

[0050] d) Step 3) is to use IBE (ion beam etching) etching technology to etch the sidewall of the cutting path into an inverted trapezoidal structure.

[0051] In the present invention, Figure 6 In the illustrated embodiment, the N-region sidewalls and the top edge sidewalls of the cutting path of the LED chip are both inverted trapezoidal structures.

[0052] In the embodiment of preparing an LED chip in which both the N-region sidewall and the top edge sidewall of the cutting path are inverted trapezoidal structures, steps 1) to 3) are cycled twice. Specifically:

[0053] First cycle: Step 1) the desired pattern is the target pattern; Step 2) deep etching is performed using ICP (inductively coupled plasma etching) technology, with an etching depth of 0.6 μm to 1.8 μm; Step 3) IBE (ion beam etching) etching technology is used to expose the N-GaN layer, with a total etching depth of 0.8 μm to 2.0 μm, and the inverted trapezoidal structure of the N region sidewall is etched;

[0054] Second cycle: Step 1) The required pattern is a cutting path pattern; Step 2) ICP (inductively coupled plasma etching) technology is used to deeply etch the N-GaN layer to the substrate, with an etching depth of 15μm to 50μm; Step 3) IBE (ion beam etching) etching technology is used to etch the inverted trapezoidal structure of the cutting path sidewall.

[0055] The ICP or IBE etching technology can be used to perform etching using the experimental steps in the prior art.

[0056] ICP etching technology uses inductively coupled plasma to etch GaN materials with Cl2 / Ar gas, which can achieve an etching rate of 500nm~687nm / min. The ICP system has two independent 13.56MHz RF power sources, one of which generates plasma at the top of the reaction chamber, and the other is connected to the inductor coil outside the reaction chamber, providing a bias voltage to provide a certain amount of energy to the plasma, so as to achieve the purpose of vertically acting on the substrate.

[0057] IBE etching technology uses ion beams with a certain amount of energy to bombard the substrate surface for etching, which is called ion beam etching. Inert gases such as Ar are filled into the ion source discharge chamber and ionized to form plasma. The ions are then drawn out and accelerated by the grid in a beam form. Ion beams with a certain amount of energy enter the studio and are fired at the solid surface to impact the atoms on the solid surface, causing the atoms of the material to sputter, achieving the purpose of etching. This is a purely physical process. IBE etching has good directionality and strong anisotropy.

[0058] IBE etching controls the chip sidewall profile by changing the ion beam incident angle. It performs sidewall etching at different angles by changing the wafer substrate tilt angle. The wafer substrate rotates by itself to ensure that the sidewalls of the LED chip have the same inverted trapezoidal structure. The chamfer of the chip sidewall can be precisely controlled by controlling the wafer substrate tilt angle. Figure 1 shown.

[0059] In certain embodiments of the present invention, the tilt angle of the wafer substrate is controlled to be 30° to 70° during the angle etching in step 3).

[0060] In certain embodiments of the present invention, the chamfer angle (or included angle) of the inverted trapezoidal side wall in step 3) is 30° to 70°.

[0061] In step 4), the transparent conductive layer is manufactured, the protective layer is deposited, the P electrode and the N electrode (including the pad electrode and the extended strip area) are deposited using the existing technology in the art.

[0062] The preparation method adopts dry etching to prepare the side wall of the LED chip into an inverted trapezoidal structure, thereby reducing the total reflection of the emitted light on the side wall of the chip, improving the brightness of the chip, and further improving the external quantum efficiency of the chip.

[0063] The invention also provides an LED chip obtained by the preparation method.

[0064] The present invention also provides a light emitting diode, which comprises the LED chip.

[0065] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0066] Before further describing the specific embodiments of the present invention, it should be understood that the scope of protection of the present invention is not limited to the specific embodiments described below; it should also be understood that the terms used in the examples of the present invention are for describing the specific embodiments rather than for limiting the scope of protection of the present invention; in the present specification and claims, unless otherwise expressly stated herein, the singular forms "a", "an" and "the" include plural forms.

[0067] When the embodiments give numerical ranges, it should be understood that, unless otherwise specified in the present invention, both endpoints of each numerical range and any numerical value between the two endpoints can be selected. Unless otherwise defined, all technical and scientific terms used in the present invention have the same meaning as those generally understood by those skilled in the art. In addition to the specific methods, equipment, and materials used in the embodiments, according to the grasp of the prior art by those skilled in the art and the record of the present invention, any methods, equipment, and materials of the prior art similar or equivalent to the methods, equipment, and materials described in the embodiments of the present invention can also be used to realize the present invention.

[0068] The following uses the preparation of a 10*28mil chip as an example to illustrate the experimental process.

[0069] Example 1 Preparation of LED Chip with Inverted Trapezoid Sidewall in N Region

[0070] Step 1: GaN-based LED epitaxial wafer growth, using metal organic chemical vapor deposition technology to grow N-GaN, multi-quantum hydrazine, and P-GaN on a sapphire substrate;

[0071] Step 2: The grown LED epitaxial wafer is cleaned, and the photoresist is used as a mask to form the target pattern by photolithography. The epitaxial layer is first etched to a depth of 0.6μm to 1.8μm using ICP (inductively coupled plasma etching) technology, and then the N-GaN of the LED is exposed using IBE (ion beam etching) etching technology. The etching rate of GaN is 34 to 36nm / min, the total etching depth is 0.8μm to 2.0μm, and the side wall inverted trapezoidal structure is completed;

[0072] The general steps of ICP are as follows:

[0073] 1) Place the semiconductor wafer to be etched into the etching reaction chamber and ensure that it is positioned correctly.

[0074] 2) Vacuum the reaction chamber to reduce the pressure to 3*10 -6 Torr, forming a high vacuum environment.

[0075] 3) Gas injection: Inject reaction gas Cl2 15sccm~50sccm, Ar 5sccm~15sccm into the reaction chamber.

[0076] 4) Generate plasma: Generate a high-frequency electromagnetic field in the reaction chamber through an inductively coupled coil, excite gas molecules to form plasma, and apply radio frequency (RF) power to the wafer. The RF power is 13.56MHz, ensuring an etching rate of 500nm to 687nm / min. The ICP system has two independent RF power sources, one of which generates plasma at the top of the reaction chamber, and the other is connected to the inductive coil outside the reaction chamber, providing a bias voltage to provide a certain amount of energy to the plasma, so as to achieve the purpose of acting vertically on the substrate.

[0077] 6) Etching process: The ions in the plasma are accelerated under the action of the electric field and bombard the surface of the wafer, reacting physically or chemically with the material, and the material is removed.

[0078] 7) Temperature control: The temperature in the reaction chamber is controlled at 23°C to 30°C to ensure the stability and uniformity of the etching process.

[0079] 8) Etching endpoint detection: Use optical or electronic sensors to monitor the etching process and automatically stop etching when the predetermined etching depth is reached.

[0080] 9) Wafer removal: The etched wafer is removed from the reaction chamber.

[0081] 10) Cleaning: After etching is completed, a cleaning step is performed to remove residues on the wafer surface.

[0082] The etching steps of IBE are as follows:

[0083] 1) Preparation stage: Place the sample to be etched on the sample stage in the IBE system.

[0084] 2) Vacuum pumping: Vacuum the reaction chamber to reduce the pressure to 3.5*10 -6 Torr, forming a high vacuum environment to ensure that the ion beam is not disturbed by gas molecules.

[0085] 3) Ion source selection: Select the Ar ion source to fill the ion source discharge chamber to generate an ion beam.

[0086] 4) Ion beam generation: Generate an ion beam through an ion source, adjust the ion beam energy to 400eV, and the energy density to 1.4mA / cm 2 .

[0087] 5) Ion beam focusing and shaping: Use electromagnetics to focus the ion beam and adjust its shape and size.

[0088] 6) Ion beam etching: The ion beam hits the sample surface to form the desired etching pattern.

[0089] 7) Etching process: adjust the angle of the sample stage to 50° to 70° so that the angle of the inverted trapezoidal side wall is 50° to 70°.

[0090] 8) Real-time monitoring: The etching process is observed in real time through the monitoring equipment installed on the IBE system to ensure that the etching is carried out according to the predetermined pattern.

[0091] 9) Etching time control: Set the etching time to ensure the desired etching depth and pattern are achieved.

[0092] 10) Etching endpoint detection: Use electron microscopy to determine whether the etching has reached the predetermined depth or shape.

[0093] 11) Cleaning: After etching is completed, a cleaning step is performed to remove residues or damaged layers on the sample surface.

[0094] 12) Sample removal: Remove the etched sample from the IBE system.

[0095] Step 3: Make a transparent conductive layer and deposit ITO.

[0096] Step 4: deposit a protective layer of SiO2 and etch out the pad electrode and the extended strip area;

[0097] Step 5: Make P / N electrodes;

[0098] Step 6: The wafer is back-ground and thinned, then cut with an invisible saw and split with a chip splitter to obtain discrete LED chips.

[0099] The structural diagram is as follows Figure 4 As shown, 1 is a sapphire substrate, 2 is N-GaN, 3 is multi-quantum hydrazine, 4 is P-GaN, P is a P pole, and N is an N pole. The angle α of the inverted trapezoidal side wall ranges from 65°.

[0100] Example 2: Preparation of LED Chip with Inverted Trapezoid-Shaped Sidewalls on the Top Edge of Cutting Roads

[0101] Step 1: GaN-based LED epitaxial wafer growth, using metal organic chemical vapor deposition technology to grow N-GaN, multi-quantum hydrazine, and P-GaN on a sapphire substrate;

[0102] Step 2: The grown LED epitaxial wafer is cleaned and etched using ICP technology (same steps as in Example 1) to expose the N-GaN, with an etching depth of 0.8 μm to 2 μm;

[0103] Step 3: Use photoresist and SiO2 as masks to photolithograph the cutting path pattern, use ICP technology to etch N-GaN until the sapphire substrate, the etching depth is 15μm~50μm, and then use IBE etching technology to complete the inverted trapezoidal structure of the top edge side wall of the cutting path. The IBE step is the same as Example 1, except that the angle range of the sample stage during the etching process is 30°~70°, that is, the angle range of the inverted trapezoidal side wall is 30°~70°; the ICP technical steps are the same as Example 1.

[0104] Step 3: Make a transparent conductive layer and deposit ITO;

[0105] Step 4: deposit a protective layer of SiO2 and etch out the pad electrode and the extended strip area;

[0106] Step 5: Make P / N electrodes;

[0107] Step 6: The wafer is back-grinded and thinned, and then split by a chip splitter to obtain discrete LED chips. Figure 5 As shown, the chamfer angle β of the inverted trapezoidal side wall of the cutting path is 45°.

[0108] Example 3: Preparation of LED Chip with Inverted Trapezoid-Shaped N-Region and Sidewalls of Cutting Road Top Edge

[0109] Step 1: GaN-based LED epitaxial wafer growth, using metal organic chemical vapor deposition technology to grow N-GaN, multi-quantum hydrazine, and P-GaN on a sapphire substrate;

[0110] Step 2: The grown LED epitaxial wafer is cleaned, and a photoresist is used as a mask to form a target pattern by photolithography. The epitaxial layer is first etched to a depth of 0.6 μm to 1.8 μm by ICP (the steps are the same as those in Example 1), and then the N-GaN of the LED is exposed by IBE etching technology, with a total etching depth of 0.8 μm to 2.0 μm, and the inverted trapezoidal structure of the N region side wall is completed; the IBE step is the same as that in Example 1, except that the angle of the sample stage during the etching process is 68°, that is, the chamfer of the inverted trapezoidal side wall is 70°;

[0111] Step 3: using photoresist and SiO2 as masks, photolithography out the cutting path pattern, using ICP technology (the steps are the same as those in Example 2) to etch N-GaN until the sapphire substrate, the etching depth is 15μm to 50μm, and then using IBE (ion beam etching) etching technology to complete the inverted trapezoidal structure of the cutting path side wall; the IBE step is the same as that in Example 1, except that the angle of the sample stage during the etching process is 48°, that is, the chamfer of the inverted trapezoidal side wall is 50°;

[0112] Step 3: Make a transparent conductive layer and deposit ITO

[0113] Step 4: deposit a protective layer of SiO2 and etch out the pad electrode and the extended strip area;

[0114] Step 5: Make P / N electrodes;

[0115] Step 6: The wafer is back-grinded and thinned, and then split by a chip splitter to obtain discrete LED chips. Figure 6 As shown, the included angle α of the sidewall of the inverted trapezoidal N region is 50°, and the included angle β of the cutting path is 70°.

[0116] Comparative Example

[0117] Step 1: GaN-based LED epitaxial wafer growth, using metal organic chemical vapor deposition technology to grow N-GaN, multi-quantum hydrazine, and P-GaN on a sapphire substrate;

[0118] Step 2: The grown LED epitaxial wafer is cleaned, and the desired pattern is formed by photolithography using photoresist as a mask. The N-GaN of the LED is exposed by ICP (inductively coupled plasma etching) technology, and the total etching depth is 0.8μm to 2.0μm. The ICP etching is the same as in Example 1.

[0119] Step 3: Make a transparent conductive layer and deposit ITO.

[0120] Step 4: deposit a protective layer of SiO2 and etch out the pad electrode and the extended strip area;

[0121] Step 5: Make P / N electrodes;

[0122] Step 6: The wafer is back-ground and thinned, then cut with an invisible saw and split with a chip splitter to obtain discrete LED chips.

[0123] The structural diagram is as follows Figure 7 As shown, 1 is a sapphire substrate, 2 is N-GaN, 3 is multi-quantum hydrazine, 4 is P-GaN, P is a P pole, and N is an N pole. The N region angle α is 90°.

[0124] like Figure 2-1 The figure shows a schematic diagram of the internal photon emission optical path of the LED chip prepared in the comparative example. The optical path is shown by the arrow in the figure. Since the refractive index of GaN is 2.3 and the refractive index of air is 1, the light is emitted from GaN to the air, and the critical angle of total reflection is 25.8°. When the photon incident angle is greater than 25.8° and less than 64.2°, it will be continuously reflected by the walls, resulting in energy consumption in the chip, and ultimately no light can be emitted, resulting in low light emission efficiency.

[0125] like Figure 2-2The figure shows a schematic diagram of the internal photon emission light path of the LED chip in which the inverted trapezoidal sidewall is formed by dry etching in Examples 1 to 3. The light path is shown by the arrow in the figure. The angle of the inverted trapezoidal sidewall is between 30° and 70°, which can increase the critical angle of total reflection, thereby improving the light extraction efficiency. This structure reduces the total reflection of the emitted light on the sidewall of the chip, and adjusts the angle of the inverted trapezoid within the range of 30° to 70°, so that the brightness of the LED chip is increased by 2% to 10% relative to the comparative example. Among them, Example 1 can brighten by 3% to 8%, Example 2 can brighten by 2% to 3%, and Example 3 can brighten by 2% to 10%.

[0126] The above examples are for the purpose of illustrating the embodiments disclosed by the present invention and are not to be construed as limiting the present invention. In addition, the various modifications listed herein and the variations of the methods in the invention are obvious to those skilled in the art without departing from the scope and spirit of the present invention. Although the present invention has been specifically described in conjunction with various specific preferred embodiments of the present invention, it should be understood that the present invention should not be limited to these specific embodiments. In fact, various modifications as described above that are obvious to those skilled in the art to obtain the invention should be included within the scope of the present invention.

Claims

1. A method for preparing an LED chip, characterized in that: The preparation method comprises the following steps: 1) Photolithography: photolithography a desired pattern on the epitaxial layer; the epitaxial layer is connected to the substrate, and the epitaxial layer starts from the substrate surface and includes an N-GaN layer, a multi-quantum hydrazine layer, and a P-GaN layer in sequence. The top of the N-GaN layer, the multi-quantum hydrazine layer, and the P-GaN layer form the N region of the LED chip, and a cutting path is provided on the bottom of the N-GaN layer and part of the substrate; the desired pattern is the target pattern of the LED chip and / or the cutting path pattern; 2) Deep etching: deep etching is performed using inductively coupled plasma etching technology to expose at least the N-GaN layer; 3) Angle etching: using ion beam etching technology to continue etching and perform angle etching, so that the sidewall of the N region and / or the sidewall of the top edge of the cutting path is in an inverted trapezoidal shape; 4) Making a transparent conductive layer, depositing a protective layer, a P electrode and an N electrode, and obtaining the LED chip.

2. The preparation method according to claim 1, characterized in that: The substrate is selected from a silicon substrate, a sapphire substrate or a silicon carbide substrate, and / or, in step 2), an inductively coupled plasma etching technique is used to perform deep etching until the N-GaN layer is exposed or the substrate is exposed.

3. The preparation method according to claim 1, characterized in that: When only the N-region sidewall of the LED chip is in an inverted trapezoidal shape, the preparation method includes any one or more of the following features: A. The required pattern in step 1) is the target pattern; B. Step 2) is to perform deep etching using inductively coupled plasma etching technology, with an etching depth of 0.6 μm to 1.8 μm; C. Step 3) is to continue etching using ion beam etching technology until the total etching depth is 0.8 μm to 2.0 μm, and perform angle etching on the N region sidewall.

4. The preparation method according to claim 1, characterized in that: When the LED chip is cut only to a top edge sidewall with an inverted trapezoidal structure, the preparation method includes any one or more of the following features: a) before the photolithography in step 1), the method further comprises: performing deep etching by using an inductively coupled plasma etching technique to expose the N-GaN layer, wherein the etching depth is 0.8 μm to 2 μm; b) Step 1) The required graphics include the target pattern and the cutting path graphics; c) Step 2) Etching the N-GaN layer to the substrate using inductively coupled plasma etching technology, with an etching depth of 15 μm to 50 μm; d) Step 3) is to use ion beam etching technology to etch the sidewall of the cutting path into an inverted trapezoidal structure.

5. The preparation method according to claim 1, characterized in that: When the N-region sidewalls and the top edge sidewalls of the cutting path of the LED chip are both inverted trapezoidal structures, steps 1) to 3) are cycled twice, the first cycle is to etch the N-region sidewalls into an inverted trapezoidal structure, and the second cycle is to etch the top edge sidewalls of the cutting path into an inverted trapezoidal structure.

6. The preparation method according to claim 5, characterized in that: The first cycle also includes any one or more of the following features: 1a) Step 1) The required pattern is the target pattern; 1b) In step 2), deep etching is performed using inductively coupled plasma etching technology, and the etching depth is 0.6 μm to 1.8 μm; 1c) Step 3) Use ion beam etching technology to expose the N-GaN layer, with a total etching depth of 0.8 μm to 2.0 μm, and perform etching of the inverted trapezoidal structure of the N region sidewall.

7. The preparation method according to claim 5, characterized in that: The second cycle also includes any one or more of the following features: 2a) The required pattern of step 1) is a cutting path pattern; 2b) Step 2) using inductively coupled plasma etching technology to deeply etch the N-GaN layer to the substrate, the etching depth being 15 μm to 50 μm; 2c) Step 3) Use ion beam etching technology to etch the inverted trapezoidal structure of the sidewall of the top edge of the cutting path.

8. The preparation method according to claim 1, characterized in that: The included angle of the inverted trapezoidal side wall in step 3) is 30° to 70°.

9. The LED chip obtained by the preparation method according to any one of claims 1 to 8.

10. A light emitting diode, characterized in that: The light emitting diode comprises the LED chip according to claim 9.

Images