Display device, apparatus for manufacturing display device, and wearable electronic device

Abstract

The invention relates to a display device, an apparatus for manufacturing the display device, and a wearable electronic device. The display device includes: a first sub-pixel; and a second sub-pixel positioned adjacent to the first sub-pixel. Each of the first sub-pixel and the second sub-pixel may include: a first electrode; a pixel defining layer on the first electrode; a first emission element on the pixel defining layer and configured to emit light; a first intermediate layer on the first emission element; a second emission element on the first intermediate layer and configured to emit light; and a second electrode on the second emission element. The trench may be formed by recessing at least a portion of the pixel defining layer in a boundary region between the first sub-pixel and the second sub-pixel. The first intermediate layer may be interrupted over the trench. The second emissive component may completely cover the first intermediate layer over the trench.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0115611 filed in the Korean Intellectual Property Office on August 31, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of the present disclosure relate to a display device, an apparatus for manufacturing the display device, and a wearable electronic device. Background Art

[0004] Recently, as interest in information displays and / or display devices has increased, research and development of such display devices has been continuously conducted or devoted. Summary of the invention

[0005] Aspects of one or more embodiments of the present disclosure are directed to a display device having improved reliability, an apparatus for manufacturing the display device, and a wearable electronic device.

[0006] One or more embodiments of the present disclosure may provide a display device, comprising: a first sub-pixel; and a second sub-pixel, positioned adjacent to the first sub-pixel. Each of the first sub-pixel and the second sub-pixel may include: a first electrode; a pixel defining layer, located on the first electrode; a first emission component, located on the pixel defining layer and configured to emit light; a first intermediate layer, located on the first emission component; a second emission component, located on the first intermediate layer and configured to emit light; and a second electrode, located on the second emission component. The groove may be formed by recessing at least a portion of the pixel defining layer in a boundary region between the first sub-pixel and the second sub-pixel. The first intermediate layer may be interrupted above the groove. The second emission component may completely cover the first intermediate layer above the groove.

[0007] The first intermediate layer may include a material having a higher charge conductivity than each of the first emission component and the second emission component, and the first intermediate layer has a conductive property.

[0008] The first intermediate layer and the second electrode may be electrically insulated from each other.

[0009] The pixel defining layer may include a first surface and a second surface and a third surface connecting the first surface to the second surface, the first surface and the second surface facing each other, the groove being between the first surface and the second surface. The first surface may include a first sidewall of the groove, the second surface may include a second sidewall of the groove, and the third surface may include a bottom surface of the groove.

[0010] Ends of the second emission assembly on the first and second side walls may be closer to the bottom surface than ends of the first intermediate layer, and the second emission assembly may completely cover the first intermediate layer on the first and second side walls.

[0011] The first emission component may be interrupted in the trench.The second emission component of the first sub-pixel and the second emission component of the second sub-pixel may be connected to each other.

[0012] Each of the first subpixel and the second subpixel may further include: a third emission component positioned between the first electrode and the first emission component, and the third emission component is configured to emit light; and a second intermediate layer positioned between the third emission component and the first emission component. The second intermediate layer may be interrupted above the groove. The first emission component may completely cover the second intermediate layer above the groove.

[0013] The second intermediate layer may include a material having a higher charge conductivity than each of the first emission component, the second emission component, and the third emission component, and the second intermediate layer has a conductive property. The first intermediate layer, the second intermediate layer, and the second electrode may be electrically insulated from each other.

[0014] On the first side wall and the second side wall, the end of the second emission assembly may be closer to the bottom surface than the end of the first intermediate layer, and the end of the first emission assembly may be closer to the bottom surface than the end of the second intermediate layer. On the first side wall and the second side wall, the second emission assembly may completely cover the first intermediate layer, and the first emission assembly may completely cover the second intermediate layer.

[0015] The third emission component and the first emission component may be interrupted in the groove.The second emission component of the first sub-pixel and the second emission component of the second sub-pixel may be connected to each other.

[0016] The trench may include a void surrounded by the first firing assembly, the second firing assembly, and the third firing assembly.

[0017] A distance between the first intermediate layer and the second electrode may be greater than a distance between the first intermediate layer and the second intermediate layer.

[0018] The first emission component may include a first hole transport component, a first emission layer, and a first electron transport component. The second emission component may include a second hole transport component, a second emission layer, and a second electron transport component. The third emission component may include a third hole transport component, a third emission layer, and a third electron transport component.

[0019] Each of the first subpixel and the second subpixel may further include: a substrate located below the first electrode; a pixel circuit layer located between the substrate and the first electrode, and the pixel circuit layer includes at least one transistor electrically connected to the first electrode; a planarization layer located between the pixel circuit layer and the first electrode; and an encapsulation layer located on the second electrode. The groove may pass through at least a portion of the planarization layer.

[0020] One or more embodiments of the present disclosure may provide an apparatus for manufacturing a display device, the display device including a first sub-pixel and a second sub-pixel, each of the first sub-pixel and the second sub-pixel including a first electrode, a pixel defining layer sequentially positioned on the first electrode, a first emission component, a first intermediate layer, a second emission component, and a second electrode, and a groove formed by recessing at least a portion of the pixel defining layer in a boundary region between the first sub-pixel and the second sub-pixel. The apparatus may include: a first deposition chamber configured to form a first intermediate layer on the pixel defining layer; and a second deposition chamber configured to form each of the first emission component and the second emission component on the pixel defining layer.

[0021] The first deposition chamber may include a first nozzle assembly configured to eject deposition material of the first intermediate layer, and a first angle limiting assembly connected to the first nozzle assembly and configured to limit an incident angle of the deposition material. The second deposition chamber may include a second nozzle assembly configured to eject deposition material of each of the first and second ejection assemblies, and a second angle limiting assembly connected to the second nozzle assembly and configured to limit an incident angle of the deposition material of each of the first and second ejection assemblies.

[0022] The deposition material of the first intermediate layer and the deposition material of each of the first emission component and the second emission component may be incident on the pixel defining layer at different incident angles.

[0023] The first intermediate layer may include a material having a higher charge conductivity than each of the first emission component and the second emission component, and the first intermediate layer has a conductive property.

[0024] The first angle limiting component may be configured to allow the deposition material of the first intermediate layer to be incident on the pixel defining layer at a low incident angle. The second angle limiting component may be configured to allow the deposition material of each of the first emission component and the second emission component to be incident on the pixel defining layer at a high incident angle.

[0025] Each of the first subpixel and the second subpixel may further include a second intermediate layer positioned between the second emission component and the second electrode and having a conductive property, and a third emission component positioned between the second intermediate layer and the second electrode. The first deposition chamber may be configured to spray the deposition material of the second intermediate layer onto the second emission component, and the second deposition chamber may be configured to spray the deposition material of the third emission component onto the second intermediate layer.

[0026] The deposition material of the second intermediate layer and the deposition material of the third emission component may be incident at different incident angles.

[0027] One or more embodiments of the present disclosure may provide a wearable electronic device, comprising: a display panel; and a lens positioned on the display panel. The display panel may include a first sub-pixel and a second sub-pixel positioned adjacent to the first sub-pixel. Each of the first sub-pixel and the second sub-pixel may include: a first electrode; a pixel defining layer located on the first electrode; a first emission component located on the pixel defining layer and configured to emit light; a first intermediate layer located on the first emission component; a second emission component located on the first intermediate layer and configured to emit light; and a second electrode located on the second emission component.

[0028] The groove may be formed by recessing at least a portion of the pixel defining layer in a boundary region between the first sub-pixel and the second sub-pixel. The first intermediate layer may be interrupted above the groove. The second emission component may completely cover the first intermediate layer above the groove.

[0029] Each of the first subpixel and the second subpixel may further include: a third emission component positioned between the first electrode and the first emission component, and the third emission component is configured to emit light; and a second intermediate layer positioned between the third emission component and the first emission component. The third emission component and the second intermediate layer may be interrupted above the groove. The first emission component may completely cover the second intermediate layer above the groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic plan view showing a display device according to one or more embodiments.

[0031] Figure 2 It is shown Figure 1 Schematic exploded perspective view of a portion of a display panel.

[0032] Figure 3 It is shown Figure 2 Schematic plan view of one or more embodiments of one of the pixels.

[0033] Figure 4 It is along Figure 3Schematic cross-sectional view taken along line II'.

[0034] Figure 5 It is shown that the Figure 4 Schematic cross-sectional view of one or more embodiments of an emission structure in one of the first to third light-emitting elements.

[0035] Figure 6 It is shown that the Figure 4 Schematic cross-sectional view of an embodiment of an emission structure in one of the first to third light-emitting elements.

[0036] 7A to 7C Each shows Figure 4 An enlarged schematic cross-sectional view of a portion of a display device.

[0037] Figure 8 It is shown Fig. 7A An enlarged schematic diagram of a portion of EA.

[0038] Fig. 9 is a schematic diagram illustrating one or more embodiments of an apparatus for manufacturing a display device.

[0039] Fig.10 It is shown Fig. 9 Schematic diagram of the first deposition source.

[0040] Fig.11 It is shown Fig. 9 Schematic diagram of the second deposition source.

[0041] Fig.12 Simulation results of the deposition appearance depending on the incident angle of the components of the emitting structure formed on the trench are shown.

[0042] Fig.13 is a schematic block diagram illustrating one or more embodiments of a display system.

[0043] Fig.14 It is shown Fig.13 Schematic perspective view of an application example of a display system.

[0044] Fig.15 Is to show the wear on the user Fig.14 Schematic diagram of a head-mounted display. DETAILED DESCRIPTION

[0045] Hereinafter, one or more embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the following description, only the parts required for understanding the operation according to the present disclosure will be described, and the explanation of other parts will not be provided because they may make the main points of the present disclosure unclear. Therefore, the present disclosure is not limited to the embodiments set forth herein, but can be implemented with other types (kinds). On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and the technical spirit of the present disclosure will be fully conveyed to those skilled in the art.

[0046] It will be understood that, in the case where an element is referred to as "coupled" or "connected" to another element, the element may be directly coupled or directly connected to the other element, or an intermediate element may be present therebetween. The terms used herein are only used to describe the purpose of a particular embodiment, and are not intended to be limited. In the present disclosure, unless the context clearly indicates otherwise, in the case where an element is referred to as "including" or "comprising" a component, the element does not exclude another component, but may also include other components. For the purposes of the present disclosure, statements such as "at least one (kind / person) in ... ", "one (kind / person) in ... " and "selected from ... " modify the entire column of elements before or after a column of elements, without modifying the individual elements in the column. For example, "at least one (kind / person) in X, Y and Z" and "at least one (kind / person) selected from the group consisting of X, Y and Z" can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y and Z (such as, for example, XYZ, XY, XZ and YZ) or any variant thereof. Similarly, a statement such as "at least one of A and B" may include A, B, or A and B. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, a statement such as "A and / or B" may include A, B, or A and B. In addition, when describing embodiments of the present disclosure, "may" refers to "one or more embodiments of the present disclosure."

[0047] Although the terms "first", "second", etc. may be used herein to describe one or more suitable types (kinds) of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed may be referred to as the second element.

[0048] Spatially relative terms such as "under," "below," "below," "below," "above," "on," "above," "higher than," and / or "side" (e.g., as in "sidewall") may be used herein for descriptive purposes, and thereby describe the relationship of one element or feature to another element (or elements) or another feature (or features) as shown in the figures. In addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under" or "below" other elements or features will subsequently be oriented to be "above" the other elements or features. Thus, the term "under" may (e.g., simultaneously) include both "above" and "under" orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or located at other orientations), and therefore, the spatially relative descriptors used herein are interpreted accordingly.

[0049] Various embodiments will be described with reference to illustrations that illustrate idealized embodiments. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments disclosed herein should not be construed as limited to the specific illustrated shapes of the regions, but rather include deviations in shapes that result, for example, from manufacturing. As such, the shapes illustrated in the drawings may not illustrate the actual shapes of regions of the device, and as such, are not intended to be limiting.

[0050] Figure 1 is a schematic plan view showing a display device DD according to one or more embodiments. Figure 1 , for ease of explanation, the structure of the display device DD (eg, a display panel DP provided in the display device DD) is schematically illustrated with a display area DA in which an image is displayed as the center or at the display area DA in which an image is displayed.

[0051] Reference Figure 1 The display panel DP may include a display area DA and a non-display area NDA located around an edge or periphery of the display area DA. The display panel DP may display an image through the display area DA. The non-display area NDA may be disposed around the display area DA.

[0052] The display panel DP may include a substrate SUB, sub-pixels SP, and pads PD.

[0053] In the case where the display panel DP is used as a display screen for a head-mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and / or an augmented reality (AR) device, etc., the display panel DP may be positioned very or substantially close to the user's eyes. In this case, a relatively high density of sub-pixels SP may be required. The substrate SUB may be formed of a silicon substrate (or a silicon wafer) to increase the density of the sub-pixels SP, but is not limited thereto. In a silicon substrate, the sub-pixels SP and / or the display panel DP may be formed on a substrate SUB. A display device DD including a display panel DP formed on a substrate SUB as a silicon substrate may be referred to as an organic light emitting diode on silicon (OLEDoS) display device.

[0054] The sub-pixels SP may be disposed in the display area DA on the substrate SUB. The sub-pixels SP may be arranged in a matrix form in a first direction DR1 and a second direction DR2 intersecting the first direction DR1, but the arrangement of the sub-pixels SP is not limited thereto. For example, the sub-pixels SP may be arranged along rows and columns of the matrix along the first direction DR1 and the second direction DR2. For example, the sub-pixels SP may be arranged in a zigzag pattern along the first direction DR1 and the second direction DR2. The first direction DR1 may represent a row direction, and the second direction DR2 may represent a column direction.

[0055] Two or more sub-pixels SP selected from among the plurality of sub-pixels SP may form one pixel PXL.

[0056] Components for controlling the sub-pixel SP may be disposed on the substrate SUB in the non-display area NDA. For example, lines electrically connected to the sub-pixel SP may be disposed in the non-display area NDA. The lines may include, for example, gate lines and / or data lines, etc.

[0057] A driver electrically connected to the sub-pixel SP to drive the sub-pixel SP may be disposed (or integrated) in the non-display area NDA of the display panel DP. The pad PD may be disposed on the substrate SUB in the non-display area NDA. The pad PD may be electrically connected to the sub-pixel SP through a line. For example, the pad PD may be electrically connected to the sub-pixel SP through a data line.

[0058] The pad PD can electrically connect the display panel DP to other components of the display device DD. In one or more embodiments, the voltage and signal required for the operation of the components included in the display panel DP can be provided from the driver (or driver integrated circuit) through the pad PD. For example, the data line can be electrically connected to the driver through the pad PD.

[0059] In one or more embodiments, the circuit board may be electrically connected to the pad PD through a conductive adhesive component such as an anisotropic conductive film. The circuit board may be a flexible circuit board or a flexible film made of a flexible material. The driver may be mounted on the circuit board and may be electrically connected to the pad PD.

[0060] In one or more embodiments, the display area DA may have one or more suitable shapes. The display area DA may have a closed loop shape including straight edges and / or curved edges. For example, the display area DA may have a shape such as a polygon, a circle, a semicircle, and / or an ellipse, but is not limited thereto.

[0061] In one or more embodiments, the display panel DP may have a flat display surface. In one or more embodiments, the display panel DP may have a display surface that is at least partially rounded. In one or more embodiments, the display panel DP may be bendable, foldable and / or rollable. In the foregoing case, the display panel DP and / or the substrate SUB may include a material having flexible properties.

[0062] Figure 2 It is shown Figure 1 A schematic exploded perspective view of a portion of a display panel DP. Figure 2 In the figure, for the purpose of clear and concise description, the display panel DP is schematically shown. Figure 1 The remaining portions of the display panel DP corresponding to other pixels may also be configured in substantially the same manner.

[0063] Reference Figure 2 , each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3, but is not limited thereto. In one or more embodiments, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels, or may include two sub-pixels.

[0064] Although in Figure 2 2 shows a case where the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 have a rectangular shape and the same size when viewed in a third direction DR3 intersecting the first direction DR1 and the second direction DR2, but the present disclosure is not limited thereto. In one or more embodiments, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be modified to have one or more suitable shapes.

[0065] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, an encapsulation layer TFE, an optical function layer OFL, a capping layer OC, and a cover window CW.

[0066] In one or more embodiments, the substrate SUB may include a silicon wafer substrate formed by a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming a circuit element. For example, the semiconductor material may include silicon, germanium and / or silicon-germanium. The substrate SUB may be provided by a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer and / or a semiconductor-on-insulator (SeOI) layer, etc. In one or more embodiments, the substrate SUB may include a glass substrate. In one or more embodiments, the substrate SUB may include a polyimide (PI) substrate.

[0067] The pixel circuit layer PCL may be disposed on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and a conductive pattern disposed between the insulating layers. The conductive pattern of the pixel circuit layer PCL may be used as at least some of the circuit components and lines, etc. The conductive pattern may include copper, but is not limited thereto.

[0068] The circuit element may include a corresponding sub-pixel circuit in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The sub-pixel circuit may include a transistor and one or more capacitors. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion. In one or more embodiments, in the case where the substrate SUB is formed by a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In one or more embodiments, in the case where the substrate SUB is formed by a glass substrate and / or a polyamide (PA) substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart and / or separated from each other on a plane defined in the first direction DR1 and the second direction DR2. For example, each capacitor may include electrodes spaced apart and / or separated from each other in the third direction DR3, with an insulating layer interposed therebetween.

[0069] The lines of the pixel circuit layer PCL may include signal lines connected to each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, such as gate lines, emission control lines, and data lines. In one or more embodiments, the lines may further include power supply voltage lines.

[0070] The light emitting element layer LDL may include an anode electrode AE, a pixel defining layer PDL, an emission structure EMS, and a cathode electrode CE.

[0071] The anode electrode AE ​​(or first electrode) may be disposed on the pixel circuit layer PCL. The anode electrode AE ​​may contact the circuit elements of the pixel circuit layer PCL. The anode electrode AE ​​may include an opaque conductive material capable of reflecting light, but is not limited thereto.

[0072] The pixel defining layer PDL may be disposed on the anode electrode AE. The pixel defining layer PDL may include an opening OP exposing a corresponding portion of the anode electrode AE. The opening OP in the pixel defining layer PDL may be understood as respective emission regions corresponding to the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3.

[0073] In one or more embodiments, the pixel defining layer PDL may include an inorganic material. In this case, the pixel defining layer PDL may include a plurality of inorganic insulating layers stacked on top of each other. For example, the pixel defining layer PDL may include silicon oxide (SiO x ) and / or silicon nitride (SiN x In one or more embodiments, the pixel defining layer PDL may include an organic material. However, the material of the pixel defining layer PDL is not limited to the aforementioned embodiments.

[0074] The emission structure EMS may be disposed on the anode electrode AE ​​(or first electrode) exposed through the opening OP in the pixel defining layer PDL. The emission structure EMS may include an emission layer configured to generate light, an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes, but is not limited thereto.

[0075] In one or more embodiments, the emission structure EMS may fill the opening OP in the pixel defining layer PDL and may be disposed on the entire surface of the upper portion of the pixel defining layer PDL. In other words, the emission structure EMS may extend over the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. In this case, at least some of the layers in the emission structure EMS may be interrupted or bent in the boundary region between the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. However, the present disclosure is not limited to the foregoing examples. In one or more embodiments, portions of the emission structure EMS corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be separated from each other and disposed in corresponding openings OP in the pixel defining layer PDL.

[0076] The cathode electrode CE (or second electrode) may be disposed on the emission structure EMS. The cathode electrode CE may extend throughout the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3. The cathode electrode CE may be provided as a common electrode of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3.

[0077] The cathode electrode CE may be a thin film metal layer having a thickness that allows light emitted from the emission structure EMS to pass through it. The cathode electrode CE may include (e.g., be) a metal material or a transparent conductive material having a relatively small thickness. In one or more embodiments, the cathode electrode CE may include at least one of one or more suitable transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and / or gallium tin oxide. In one or more embodiments, the cathode electrode CE may include at least one of magnesium and silver and / or a compound thereof. However, the material of the cathode electrode CE is not limited to the aforementioned embodiments.

[0078] One of the anode electrodes AE, the portion of the emission structure EMS overlapping with the one of the anode electrodes AE, and the portion of the cathode electrode CE overlapping with the portion of the emission structure EMS can be understood as constituting a light-emitting element. In other words, each of the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include an anode electrode AE ​​(or a first electrode), a portion of the emission structure EMS overlapping with the one anode electrode AE, and a portion of the cathode electrode CE (or a second electrode) overlapping with the portion of the emission structure EMS. In each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE are transferred to the emission layer of the emission structure EMS, thereby forming excitons. When the excitons transition from an excited state to a ground state, light can be generated. The brightness of the light can be determined according to the amount of current flowing through the emission layer. According to the configuration of the emission layer, the wavelength range of the light to be generated can be determined.

[0079] The encapsulation layer TFE may be disposed on the cathode electrode CE. The encapsulation layer TFE may cover the light emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE may be configured to prevent or reduce the penetration of oxygen and / or water into the light emitting element layer LDL. In one or more embodiments, the encapsulation layer TFE may include a structure formed by alternately stacking one or more inorganic layers and one or more organic layers. For example, the inorganic layer may include silicon nitride, silicon oxide and / or silicon oxynitride (SiO x N y ) etc. For example, the organic layer may include an organic insulating material such as a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin and / or benzocyclobutene (BCB). However, the materials of the organic layer and the inorganic layer of the encapsulation layer TFE are not limited to the aforementioned examples.

[0080] The encapsulation layer TFE may also include aluminum oxide (Alx O y ) film to improve the encapsulation efficiency of the encapsulation layer TFE. The film including aluminum oxide may be positioned on the upper surface of the encapsulation layer TFE facing the optical function layer OFL and / or below the lower surface of the encapsulation layer TFE facing the light emitting element layer LDL.

[0081] The thin film including aluminum oxide may be formed by an atomic layer deposition (ALD) method. However, the present disclosure is not limited to the aforementioned example. The encapsulation layer TFE may also include a thin film formed of at least one of one or more suitable materials suitable for improving encapsulation efficiency.

[0082] The optical function layer OFL may be disposed on the encapsulation layer TFE. The optical function layer OFL may include a color filter layer CFL and a lens array LA.

[0083] The color filter layer CFL may be disposed between the encapsulation layer TFE and the lens array LA. The color filter layer CFL may be configured to filter the light emitted from the emission structure EMS to selectively output light of a wavelength range or color corresponding to each sub-pixel. The color filter layer CFL may include color filters CF corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively. Each of the color filters CF allows light within a wavelength range corresponding to the corresponding sub-pixel to pass through. For example, the color filter corresponding to the first sub-pixel SP1 allows red light to pass through, the color filter corresponding to the second sub-pixel SP2 allows green light to pass through, and the color filter corresponding to the third sub-pixel SP3 allows blue light to pass through. Depending on the light emitted from the emission structure EMS of each sub-pixel, at least some of the color filters CF may not be provided.

[0084] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively. Each of the lenses LS may guide the light emitted from the emission structure EMS along an intended path, thereby improving the light output efficiency. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a higher refractive index than the cover layer OC. In one or more embodiments, the lens LS may include an organic material. For example, the lens LS may include an acrylate material, but is not limited thereto.

[0085] In one or more embodiments, compared to the opening OP of the pixel defining layer PDL, at least some of the color filters CF of the color filter layer CFL and at least some of the lenses LS of the lens array LA may be shifted in a direction parallel to the plane defined in the first direction DR1 and the second direction DR2. For example, in the central area of ​​the display area DA or at the central area of ​​the display area DA, the center of each color filter CF and the center of each lens LS may be aligned or overlapped with the center of the corresponding opening OP of the pixel defining layer PDL. For example, in the central area of ​​the display area DA or at the central area of ​​the display area DA, each opening OP of the pixel defining layer PDL may completely overlap with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. In the area adjacent to the non-display area NDA within the display area DA, the center of the color filter CF and the center of the lens LS may be shifted in the plane direction. For example, in the area adjacent to the non-display area NDA within the display area DA or at the area adjacent to the non-display area NDA within the display area DA, each opening OP of the pixel defining layer PDL may partially overlap with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. Therefore, light emitted from the emission structure EMS located in or at the center of the display area DA can be effectively output in the normal direction of the display surface. Light emitted from the emission structure EMS located around the periphery of the display area DA can be effectively output in a direction inclined at a specific angle relative to the normal direction of the display surface.

[0086] The cover layer OC may be disposed on the lens array LA. The cover layer OC may cover the optical function layer OFL, the encapsulation layer TFE, the emission structure EMS and / or the pixel circuit layer PCL. The cover layer OC may include one or more suitable materials suitable for protecting the lower layer from foreign substances such as dust and / or water. For example, the cover layer OC may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the cover layer OC may include epoxy resin, but is not limited thereto. The cover layer OC may have a lower refractive index than the lens array LA.

[0087] The cover window CW may be disposed on the cover layer OC. The cover window CW may be configured to protect the lower layer. The cover window CW may have a higher refractive index than the cover layer OC. The cover window CW may include glass, but is not limited thereto. In one or more embodiments, the cover window CW may be an encapsulation glass layer configured to protect components disposed thereunder. In one or more embodiments, the cover window CW may not be provided (e.g., may be excluded).

[0088] Figure 3 It is shown Figure 2Schematic plan view of one or more embodiments of one of the pixels PXL1 and PXL2. Figure 3 In the example, for the purpose of clarity and simplicity of explanation, the Figure 2 The remaining pixels may have substantially the same or similar configuration (or structure) as the first pixel PXL1.

[0089] Reference Figure 3 , the first pixel PXL1 may include a first sub-pixel SP1 , a second sub-pixel SP2 , and a third sub-pixel SP3 arranged along the first direction DR1 .

[0090] The first subpixel SP1 may include a first emission area EMA1 and a non-emission area NEA formed around the first emission area EMA1. The second subpixel SP2 may include a second emission area EMA2 and a non-emission area NEA formed around the second emission area EMA2. The third subpixel SP3 may include a third emission area EMA3 and a non-emission area NEA formed around the third emission area EMA3.

[0091] The first emission area EMA1 may be formed from the emission structure EMS (refer to Figure 2 ) may be an area where light is emitted from a portion of the emission structure EMS corresponding to the first sub-pixel SP1. The second emission area EMA2 may be an area where light is emitted from a portion of the emission structure EMS corresponding to the second sub-pixel SP2. The third emission area EMA3 may be an area where light is emitted from a portion of the emission structure EMS corresponding to the third sub-pixel SP3. Figure 2 Each emission region can be understood as a pixel definition layer PDL (refer to Figure 2 ) corresponding to each of the first to third sub-pixels SP1 to SP3 (refer to Figure 2 ).

[0092] The first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may have substantially the same surface area, but are not limited thereto. In one or more embodiments, the second subpixel SP2 may have a larger surface area than the first subpixel SP1. The third subpixel SP3 may have a larger surface area than the second subpixel SP2.

[0093] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may have a polygonal shape. For example, each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may have a rectangular shape or a hexagonal shape, but is not limited thereto. In one or more embodiments, each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may have a circular shape, a semi-elliptical shape, and the like.

[0094] Figure 3 The arrangement of the sub-pixels shown in is an illustrative example, and the present disclosure is not limited thereto. Each pixel may include two or more sub-pixels, and the sub-pixels may be arranged in one or more suitable ways. Each sub-pixel may have one or more suitable shapes. Each of the emission regions of the sub-pixels may also have one or more suitable shapes.

[0095] Figure 4 It is along Figure 3 Schematic cross-sectional view taken along line II'.

[0096] Reference Figure 3 and Figure 4 , the first pixel PXL1 may include a first sub-pixel SP1 , a second sub-pixel SP2 , and a third sub-pixel SP3 .

[0097] Each of the first to third sub-pixels SP1 to SP3 may include a substrate SUB and a pixel circuit layer PCL disposed on the substrate SUB.

[0098] The substrate SUB may include a silicon wafer substrate formed by a semiconductor process. For example, the substrate SUB may include silicon, germanium and / or silicon-germanium.

[0099] The pixel circuit layer PCL may be disposed on a substrate SUB. The substrate SUB and the pixel circuit layer PCL may include corresponding circuit elements of the first sub-pixel SP1 to the third sub-pixel SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 of the first sub-pixel SP1, a transistor T_SP2 of the second sub-pixel SP2, and a transistor T_SP3 of the third sub-pixel SP3. The transistor T_SP1 of the first sub-pixel SP1 may be one of the transistors included in the sub-pixel circuit of the first sub-pixel SP1. The transistor T_SP2 of the second sub-pixel SP2 may be one of the transistors included in the sub-pixel circuit of the second sub-pixel SP2. The transistor T_SP3 of the third sub-pixel SP3 may be one of the transistors included in the sub-pixel circuit of the third sub-pixel SP3. Figure 4 , for the purpose of clarity and concise explanation, one of the transistors of each sub-pixel is shown, and the remaining circuits are not provided.

[0100] The transistor T_SP1 of the first subpixel SP1 may include a source area SRA, a drain area DRA, and a gate electrode GE.

[0101] The source region SRA and the drain region DRA may be disposed in the substrate SUB. The well WL formed by the ion implantation process may be disposed in the substrate SUB. The source region SRA and the drain region DRA may be disposed to be spaced and / or separated from each other in the well WL. The region between the source region SRA and the drain region DRA in the well WL may be defined as a channel region.

[0102] The gate electrode GE may overlap the channel region between the source region SRA and the drain region DRA in the third direction DR3 and may be disposed in the pixel circuit layer PCL. The gate electrode GE may be separated and / or separated from the well WL or the channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE may include a conductive material.

[0103] The plurality of layers included in the pixel circuit layer PCL may include an insulating layer and a conductive pattern disposed between the insulating layers. The conductive pattern may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA via a drain connector DRC passing through one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA via a source connector SRC passing through one or more insulating layers.

[0104] Since the gate electrode GE and the first and second conductive patterns CP1 and CP2 are electrically connected to other circuit elements and / or lines, the transistor T_SP1 of the first subpixel SP1 may be provided as one of transistors constituting a subpixel circuit of the first subpixel SP1.

[0105] Each of the transistor T_SP2 of the second subpixel SP2 and the transistor T_SP3 of the third subpixel SP3 may have substantially the same configuration as the transistor T_SP1 of the first subpixel SP1.

[0106] As described above, the substrate SUB and the pixel circuit layer PCL may include corresponding circuit elements of the first to third sub-pixels SP1 to SP3 .

[0107] The via layer VIAL may be disposed on the pixel circuit layer PCL. The via layer VIAL may cover the pixel circuit layer PCL and have an overall flat surface. The via layer VIAL may be configured to flatten the step portion on the pixel circuit layer PCL. The via layer VIAL may include at least one of silicon oxide, silicon nitride, and silicon carbonitride (SiCN), but is not limited thereto.

[0108] The light emitting element layer LDL may be disposed on the via layer VIAL and may include first, second and third reflective electrodes RE1, RE2 and RE3, a planarization layer PLNL, first, second and third anode electrodes AE1, AE2 and AE3, a pixel defining layer PDL, an emission structure EMS and a cathode electrode CE.

[0109] The first to third reflective electrodes RE1 to RE3 may be respectively disposed in the first to third sub-pixels SP1 to SP3 on the via layer VIAL. For example, the first reflective electrode RE1 may be disposed on the via layer VIAL of the first sub-pixel SP1, the second reflective electrode RE2 may be disposed on the via layer VIAL of the second sub-pixel SP2, and the third reflective electrode RE3 may be disposed on the via layer VIAL of the third sub-pixel SP3. In one or more embodiments, each of the first to third reflective electrodes RE1 to RE3 may contact a circuit element disposed in the pixel circuit layer PCL through a corresponding via hole passing through the via layer VIAL.

[0110] The first to third reflective electrodes RE1 to RE3 may be used as total reflectors provided to reflect light emitted from the emission structure EMS (e.g., in the third direction DR3) toward the display surface (or cover window CW). The first to third reflective electrodes RE1 to RE3 may include a metal material suitable for reflecting light. For example, the first to third reflective electrodes RE1 to RE3 may include at least one of aluminum, silver, magnesium, platinum, palladium, gold, nickel, neodymium, iridium, chromium, and titanium and / or an alloy of two or more materials selected from the foregoing materials. The materials of the first to third reflective electrodes RE1 to RE3 are not limited to the foregoing embodiments.

[0111] In one or more embodiments, a connection electrode may be disposed below each of the first to third reflective electrodes RE1 to RE3. A connection electrode may be provided to improve the electrical connection characteristics between the corresponding reflective electrode and the corresponding circuit element of the pixel circuit layer PCL. The connection electrode may be formed of multiple layers. For example, the multiple layers may include a stacked structure of titanium / titanium nitride / tantalum nitride, but the present disclosure is not limited thereto. In one or more embodiments, a corresponding reflective electrode may be disposed between the layers forming the connection electrode.

[0112] In one or more embodiments, the buffer pattern BFP may be disposed under at least one of the first to third reflective electrodes RE1 to RE3. For example, the buffer pattern BFP may be disposed between the first reflective electrode RE1 and the via layer VIAL. The buffer pattern BFP may include an inorganic material such as silicon carbonitride, but is not limited thereto. Since the buffer pattern BFP is provided, the height of the corresponding reflective electrode in the third direction DR3 may be adjusted. For example, the buffer pattern BFP may adjust the height of the first reflective electrode RE1 between the first reflective electrode RE1 and the via layer VIAL.

[0113] The first to third reflective electrodes RE1 to RE3 can be used as full reflective mirrors, and the cathode electrode CE can be used as a half reflective mirror. By reciprocating between the corresponding reflective electrodes and the cathode electrode CE, the light emitted from the emission structure EMS can be at least partially amplified. The amplified light can be output through the cathode electrode CE. In this way, the distance between each reflective electrode and the cathode electrode CE can be understood as the resonance distance of the light emitted from the emission layer of the corresponding emission structure EMS.

[0114] The first sub-pixel SP1 may have a shorter resonance distance than other sub-pixels (e.g., the second sub-pixel SP2 and the third sub-pixel SP3) through the buffer pattern BFP. In this way, the adjusted resonance distance enables light in a specific wavelength range (e.g., red) to be effectively amplified. Therefore, the first sub-pixel SP1 may effectively and efficiently output light in the corresponding wavelength range.

[0115] Despite Figure 4 , a case where the buffer pattern BFP is provided in the first sub-pixel SP1 but not in the second sub-pixel SP2 and the third sub-pixel SP3 is shown, but the present disclosure is not limited thereto. In one or more embodiments, the buffer pattern BFP may be provided in at least one of the second sub-pixel SP2 and the third sub-pixel SP3 so that the resonance distance of at least one of the second sub-pixel SP2 and the third sub-pixel SP3 may be adjusted. For example, in a case where the first sub-pixel SP1 is a red sub-pixel, the second sub-pixel SP2 is a green sub-pixel, and the third sub-pixel SP3 is a blue sub-pixel, the distance between the first reflective electrode RE1 and the cathode electrode CE may be shorter than the distance between the second reflective electrode RE2 and the cathode electrode CE, and the distance between the second reflective electrode RE2 and the cathode electrode CE may be shorter than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0116] A planarization layer PLNL may be provided to planarize the stepped portion between the first to third reflective electrodes RE1 to RE3. The planarization layer PLNL may be disposed on the via layer VIAL and the first to third reflective electrodes RE1 to RE3. The planarization layer PLNL may cover the entire surface of the first to third reflective electrodes RE1 to RE3 and the via layer VIAL and have a flat surface. In one or more embodiments, the planarization layer PLNL may not be provided.

[0117] The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may be disposed on the planarization layer PLNL. For example, the first anode electrode AE1 may be disposed on the planarization layer PLNL to overlap with the first reflective electrode RE1 in the third direction DR3. The second anode electrode AE2 may be disposed on the planarization layer PLNL to overlap with the second reflective electrode RE2 in the third direction DR3. The third anode electrode AE3 may be disposed on the planarization layer PLNL to overlap with the third reflective electrode RE3 in the third direction DR3.

[0118] When viewed in the third direction DR3, the first to third anode electrodes AE1 to AE3 may be aligned with Figure 3 The first emission area EMA1 to the third emission area EMA3 have similar shapes. For example, when viewed in the third direction DR3, the first anode electrode AE1 may have a similar shape to the first emission area EMA1. When viewed in the third direction DR3, the second anode electrode AE2 may have a similar shape to the second emission area EMA2. When viewed in the third direction DR3, the third anode electrode AE3 may have a similar shape to the third emission area EMA3. However, the present disclosure is not limited to the foregoing examples.

[0119] Each of the first to third anode electrodes AE1 to AE3 may be electrically connected to a corresponding reflective electrode. For example, the first anode electrode AE1 may be electrically connected to the first reflective electrode RE1 through a first via hole VIA1 passing through the planarization layer PLNL. The second anode electrode AE2 may be electrically connected to the second reflective electrode RE2 through a second via hole VIA2 passing through the planarization layer PLNL. The third anode electrode AE3 may be electrically connected to the third reflective electrode RE3 through a third via hole VIA3 passing through the planarization layer PLNL.

[0120] In one or more embodiments, the first to third anode electrodes AE1 to AE3 may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x), at least one of transparent conductive oxides of indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO). However, the material of the first to third anode electrodes AE1 to AE3 is not limited to the aforementioned examples. For example, the first to third anode electrodes AE1 to AE3 may include titanium nitride.

[0121] An insulating layer may also be provided to adjust the height of one or more of the first to third anode electrodes AE1 to AE3. The insulating layer may be disposed between one or more of the first to third anode electrodes AE1 to AE3 and the corresponding reflective electrodes RE1 to RE3. In this case, the planarization layer PLNL and / or the buffer pattern BFP may not be provided.

[0122] The pixel defining layer PDL may be disposed on the planarization layer PLNL and a portion of the first to third anode electrodes AE1 to AE3. The pixel defining layer PDL may include an opening OP exposing respective portions of the first to third anode electrodes AE1 to AE3. The opening OP in the pixel defining layer PDL may define respective emission regions of the first to third sub-pixels SP1 to SP3. The pixel defining layer PDL may be disposed in the non-emission region NEA (refer to Figure 3 ) and limit the reference Figure 3 A first emission area EMA1, a second emission area EMA2 and a third emission area EMA3 are described.

[0123] In one or more embodiments, the pixel defining layer PDL may include a plurality of inorganic insulating layers. Each of the inorganic insulating layers may include at least one of silicon oxide and silicon nitride. For example, the pixel defining layer PDL may include a first inorganic insulating layer to a third inorganic insulating layer stacked in sequence. The first inorganic insulating layer to the third inorganic insulating layer may each include at least one of silicon nitride and silicon oxide. However, the material of the pixel defining layer PDL is not limited to the aforementioned embodiments.

[0124] The spacer SPR may be provided in the boundary area BDA between adjacent sub-pixels. The spacer SPR may cause a discontinuous portion in the emission structure EMS to be generated in the boundary area BDA. For example, the emission structure EMS may be interrupted or bent in the boundary area BDA by the spacer SPR.

[0125] The spacer SPR may be provided in or on the pixel defining layer PDL. The pixel defining layer PDL may include one or more grooves TRCH1 and TRCH2 as the spacer SPR in the boundary area BDA. In one or more embodiments, one or more grooves TRCH1 and TRCH2 may be formed to pass through the pixel defining layer PDL and partially through the planarization layer PLNL. In one or more embodiments, one or more grooves TRCH1 and TRCH2 may be formed to pass through the pixel defining layer PDL and the planarization layer PLNL and partially through the via layer VIAL. In one or more embodiments, one or more grooves TRCH1 and TRCH2 may at least partially pass through the planarization layer PLNL and / or the via layer VIAL, and a portion of the pixel defining layer PDL may be disposed in one or more grooves TRCH1 and TRCH2. In one or more embodiments, one or more grooves TRCH1 and TRCH2 may be formed to partially pass through the pixel defining layer PDL.

[0126] exist Figure 4 , a case where two grooves TRCH1 and TRCH2 are positioned in the boundary area BDA between sub-pixels is shown, but the present disclosure is not limited thereto. For example, a spacer SPR including one groove located in the boundary area BDA may be provided in and / or on the pixel defining layer PDL. In some embodiments, a spacer SPR including three or more grooves located in the boundary area BDA may be provided in and / or on the pixel defining layer PDL.

[0127] Due to the first trench TRCH1 and the second trench TRCH2, discontinuous portions such as the first void VD1 and the second void VD2 may be formed in the emission structure EMS in the boundary area BDA. Some of the multiple layers stacked in the emission structure EMS (or components included in the emission structure EMS) may be interrupted or bent by the first void VD1 and the second void VD2. For example, at least one charge generation layer included in the emission structure EMS may be interrupted by the first void VD1 and the second void VD2. In this way, due to the first trench TRCH1 and the second trench TRCH2, the emission structure EMS included in the first subpixel SP1 to the third subpixel SP3 is at least partially divided into a plurality of portions.

[0128] exist Figure 4, a case where the first void VD1 and the second void VD2 are formed in the emission structure EMS located in the boundary area BDA is shown, but the present disclosure is not limited thereto. For example, a valley having a concave shape may be formed in the emission structure EMS located in the boundary area BDA. Depending on the shapes of the first trench TRCH1 and the second trench TRCH2, the shape of the discontinuous portion (e.g., the first void VD1 and the second void VD2) formed in the emission structure EMS may be changed in one or more suitable ways.

[0129] In one or more embodiments, the emission structure EMS may be formed by processes such as vacuum deposition and / or inkjet printing. In this case, the same material as that of some components included in the emission structure EMS may be positioned on the bottom surface adjacent to the via layer VIAL in the first and second trenches TRCH1 and TRCH2.

[0130] The spacer SPR may be modified in one or more suitable ways to allow the emission structure EMS to have a discontinuous portion in the boundary area BDA. In one or more embodiments, an additional inorganic insulating pattern may be provided on the pixel defining layer PDL in the boundary area BDA without the first trench TRCH1 and the second trench TRCH2. The topmost inorganic insulating pattern from among the additionally stacked inorganic insulating patterns may have a width greater than the width of the inorganic insulating pattern immediately below. For example, in the boundary area BDA, the first to third inorganic insulating patterns may be stacked sequentially from the pixel defining layer PDL. The topmost third inorganic insulating pattern may have a width greater than the width of the second inorganic insulating pattern. In this case, the pixel defining layer PDL may have a "T"-shaped or "I"-shaped cross-section in the boundary area BDA. Depending on the shape of the pixel defining layer PDL, the multiple layers included in the emission structure EMS may be at least partially interrupted or bent in the boundary area BDA.

[0131] The emission structure EMS may be disposed on the anode electrode AE ​​exposed through the opening OP in the pixel defining layer PDL (refer to Figure 2 ) (or the first electrode). The emission structure EMS may fill the opening OP of the pixel defining layer PDL and may be disposed throughout the entire area of ​​the first to third sub-pixels SP1 to SP3. As described above, the emission structure EMS may be at least partially interrupted or bent in the boundary area BDA by the partition SPR. Figure 2), current leaking from each of the first to third sub-pixels SP1 to SP3 to adjacent sub-pixels through the layers included in the emission structure EMS can be reduced. As a result, the first, second, and third light-emitting elements LD1, LD2, and LD3 can operate with relatively high reliability.

[0132] The cathode electrode CE may be disposed on the emission structure EMS. The cathode electrode CE may be commonly provided to the first to third sub-pixels SP1 to SP3. The cathode electrode CE may function as a half mirror that partially transmits and partially reflects light emitted from the emission structure EMS.

[0133] The first anode electrode AE1 (or the first electrode), the portion of the emission structure EMS overlapping with the first anode electrode AE1, and the portion of the cathode electrode CE (or the second electrode) overlapping with the first anode electrode AE1 may form a first light emitting element LD1. The second anode electrode AE2 (or the first electrode), the portion of the emission structure EMS overlapping with the second anode electrode AE2, and the portion of the cathode electrode CE (or the second electrode) overlapping with the second anode electrode AE2 may form a second light emitting element LD2. The third anode electrode AE3 (or the first electrode), the portion of the emission structure EMS overlapping with the third anode electrode AE3, and the portion of the cathode electrode CE (or the second electrode) overlapping with the third anode electrode AE3 may form a third light emitting element LD3.

[0134] The encapsulation layer TFE may be disposed on the cathode electrode CE. The encapsulation layer TFE may prevent or reduce the penetration of oxygen and / or water, etc., into the light emitting element layer LDL.

[0135] The optical function layer OFL may be disposed on the encapsulation layer TFE. In one or more embodiments, the optical function layer OFL may be attached to the encapsulation layer TFE through an adhesive layer APL. For example, the optical function layer OFL may be manufactured by a separate process and attached to the encapsulation layer TFE through an adhesive layer APL. The adhesive layer APL may also perform the function of protecting the lower layer including the encapsulation layer TFE.

[0136] The optical function layer OFL may include a color filter layer CFL and a lens array LA.

[0137] The color filter layer CFL may include first to third color filters CF1 to CF3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. For example, the color filter layer CFL may include a first color filter CF1 corresponding to the first sub-pixel SP1, a second color filter CF2 corresponding to the second sub-pixel SP2, and a third color filter CF3 corresponding to the third sub-pixel SP3. The first to third color filters CF1 to CF3 may transmit light of different wavelength ranges. For example, the first color filter CF1 may transmit red light, the second color filter CF2 may transmit green light, and the third color filter CF3 may transmit blue light. In this case, the first sub-pixel SP1 may be a red sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, and the third sub-pixel SP3 may be a blue sub-pixel.

[0138] In one or more embodiments, the first color filter CF1 to the third color filter CF3 may partially overlap each other in the boundary area BDA. In one or more embodiments, the first color filter CF1 to the third color filter CF3 may be spaced and / or separated from each other. The black matrix may be provided between the first color filter CF1 to the third color filter CF3 that are spaced and / or separated from each other.

[0139] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include first to third lenses LS1 to LS3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. For example, the lens array LA may include a first lens LS1 corresponding to the first sub-pixel SP1, a second lens LS2 corresponding to the second sub-pixel SP2, and a third lens LS3 corresponding to the third sub-pixel SP3. The first to third lenses LS1 to LS3 may guide the light emitted from the first to third light-emitting elements LD1 to LD3 in intended paths, respectively, thereby improving light output efficiency.

[0140] Figure 5 It is shown that the Figure 4 One of the first light emitting element LD1 to the third light emitting element LD3 (for example, selected from Figure 4 Schematic cross-sectional views of one or more embodiments of an emission structure EMS in at least one of the first to third light emitting elements LD1 to LD3.

[0141] Reference Figure 4 and Figure 5 , the emission structure EMS may have a series structure in which the first emission component EU1 and the second emission component EU2 are stacked. Figure 4 In each of the first to third light emitting elements LD1 to LD3 , the emission structure EMS may have substantially the same configuration.

[0142] Each of the first emission component EU1 and the second emission component EU2 may include at least one emission layer configured to generate light in response to a current applied thereto. The first emission component EU1 may include a first emission layer EML1, a first electron transport component ETU1, and a first hole transport component HTU1. The first emission layer EML1 may be disposed between the first electron transport component ETU1 and the first hole transport component HTU1. The second emission component EU2 may include a second emission layer EML2, a second electron transport component ETU2, and a second hole transport component HTU2. The second emission layer EML2 may be disposed between the second electron transport component ETU2 and the second hole transport component HTU2.

[0143] Each of the first hole transport component HTU1 and the second hole transport component HTU2 may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer and / or an electron blocking layer, etc. as required. The first hole transport component HTU1 and the second hole transport component HTU2 may have the same configuration or different configurations.

[0144] Each of the first electron transport assembly ETU1 and the second electron transport assembly ETU2 may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer and / or a hole blocking layer, etc. as needed. The first electron transport assembly ETU1 and the second electron transport assembly ETU2 may have the same configuration or different configurations.

[0145] An intermediate layer (or connecting layer) that may be provided in the form of a charge generation layer CGL may be disposed between the first emission component EU1 and the second emission component EU2, thereby connecting the first emission component EU1 and the second emission component EU2 to each other. Hereinafter, the charge generation layer CGL will be referred to as the intermediate layer CGL. In one or more embodiments, the intermediate layer CGL may have a stacked structure including a p-dopant layer and an n-dopant layer. For example, the p-dopant layer may include a p-type or p-type dopant, such as HAT-CN, TCNQ, or NDP-9, and the n-dopant layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof. However, the structure (or material) of the intermediate layer CGL is not limited to the aforementioned embodiments. In one or more embodiments, the intermediate layer CGL may include a material having a relatively high charge conductivity (or charge mobility) compared to the first emission component EU1 and the second emission component EU2, thereby having conductive properties.

[0146] In one or more embodiments, the first emission layer EML1 and the second emission layer EML2 may generate light of different colors. The light emitted from the first emission layer EML1 and the second emission layer EML2 may be mixed to be visible as white light. For example, the first emission layer EML1 may generate blue light, and the second emission layer EML2 may include a stacked structure including a first sub-emission layer configured to generate red light and a second sub-emission layer configured to generate green light. In this case, a functional layer configured to perform the function of transporting holes and / or blocking the transport of electrons may be further disposed between the first sub-emission layer and the second sub-emission layer.

[0147] In one or more embodiments, the first emission layer EML1 and the second emission layer EML2 may generate light of substantially the same color.

[0148] Figure 6 It is shown that the Figure 4 Schematic cross-sectional view of an embodiment of an emission structure EMS′ in one of the first to third light emitting elements LD1 to LD3.

[0149] Reference Figure 4 and Figure 6 , the emission structure EMS' may have a series structure in which the first emission component EU1', the second emission component EU2' and the third emission component EU3' are stacked. Figure 4 In each of the first to third light emitting elements LD1 to LD3 , the emission structure EMS′ may have substantially the same configuration.

[0150] Each of the first emission component EU1', the second emission component EU2' and the third emission component EU3' may include an emission layer configured to generate light in response to a current applied thereto. The first emission component EU1' may include a first emission layer EML1', a first electron transport component ETU1' and a first hole transport component HTU1'. The first emission layer EML1' may be disposed between the first electron transport component ETU1' and the first hole transport component HTU1'. The second emission component EU2' may include a second emission layer EML2', a second electron transport component ETU2' and a second hole transport component HTU2'. The second emission layer EML2' may be disposed between the second electron transport component ETU2' and the second hole transport component HTU2'. The third emission component EU3' may include a third emission layer EML3', a third electron transport component ETU3' and a third hole transport component HTU3'. The third emission layer EML3' may be disposed between the third electron transport component ETU3' and the third hole transport component HTU3'.

[0151] Each of the first to third hole transport components HTU1' to HTU3' may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer and / or an electron blocking layer, etc. as needed. The first to third hole transport components HTU1' to HTU3' may have the same configuration or different configurations.

[0152] Each of the first to third electron transport assemblies ETU1' to ETU3' may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer and / or a hole blocking layer, etc. as needed. The first to third electron transport assemblies ETU1' to ETU3' may have the same configuration or different configurations.

[0153] The first intermediate layer CGL1' can be arranged between the first emission component EU1' and the second emission component EU2'. The second intermediate layer CGL2' can be arranged between the second emission component EU2' and the third emission component EU3'. In one or more embodiments, the first intermediate layer CGL1' and the second intermediate layer CGL2' may include a material having a relatively high charge conductivity (or charge mobility) compared to the first emission component EU1', the second emission component EU2', and the third emission component EU3' (the charge conductivity (or charge mobility) of each of the first emission component EU1', the second emission component EU2', and the third emission component EU3'), thereby having conductive properties (for example, as a conductor).

[0154] In one or more embodiments, the first emission layer EML1' to the third emission layer EML3' may generate light of different colors. The light emitted from the first emission layer EML1' to the third emission layer EML3' may be mixed to be visible as white light. For example, the first emission layer EML1' may generate blue light, the second emission layer EML2' may generate green light, and the third emission layer EML3' may generate red light.

[0155] In one or more embodiments, two or more emission layers among the first to third emission layers EML1 ′ to EML3 ′ may generate light of substantially the same color.

[0156] With reference Figure 5 and Figure 6 The situations described are different. Figure 4The emission structure EMS may include one emission component in each of the first light emitting element LD1 to the third light emitting element LD3. Herein, each emission component included in the first light emitting element LD1 to the third light emitting element LD3 may be configured to emit light of different colors. For example, the emission component of the first light emitting element LD1 may emit red light, the emission component of the second light emitting element LD2 may emit green light, and the emission component of the third light emitting element LD3 may emit blue light. In this case, as with reference Figure 4 Unlike the described situation, the emission components of the first subpixel SP1 to the third subpixel SP3 may be separated from each other and disposed in corresponding openings OP of the pixel defining layer PDL. As described above, in the case where the emission components of the first subpixel SP1, the emission components of the second subpixel SP2, and the emission components of the third subpixel SP3 are separated from each other and disposed in corresponding openings OP of the pixel defining layer PDL, at least some of the first color filter CF1 to the third color filter CF3 may not be provided.

[0157] 7A to 7C Each shows Figure 4 An enlarged schematic cross-sectional view of a portion of a display device. Figure 8 It is shown Fig. 7A An enlarged schematic diagram of a portion of EA.

[0158] 7A to 7C Each shows an emission structure EMS and a cathode electrode CE in some regions including the first trench TRCH1 and the second trench TRCH2 (eg, a boundary region between the first sub-pixel SP1 and the second sub-pixel SP2). In addition, for the purpose of clarity, 7A to 7C A planarization layer PLNL, a pixel definition layer PDL and an encapsulation layer TFE are each further shown.

[0159] Reference FIG. 7A to FIG. 8 The description will focus on the differences from the above-described embodiments to avoid redundant description.

[0160] Reference Figures 4 to 8 , also refer to Figure 3 , the pixel defining layer PDL may be disposed on the planarization layer PLNL.

[0161] The pixel defining layer PDL may include a first inorganic insulating layer PDL1 (or a first inorganic layer), a second inorganic insulating layer PDL2 (or a second inorganic layer), and a third inorganic insulating layer PDL3 (or a third inorganic layer) sequentially stacked in the third direction DR3, but the configuration of the pixel defining layer PDL is not limited thereto. In one or more embodiments, the pixel defining layer PDL may further include an additional inorganic insulating layer in addition to the aforementioned inorganic insulating layer.

[0162] The first inorganic insulating layer PDL1 and the third inorganic insulating layer PDL3 may include silicon nitride, and the second inorganic insulating layer PDL2 may include silicon oxide. The materials of the first inorganic insulating layer PDL1, the second inorganic insulating layer PDL2, and the third inorganic insulating layer PDL3 are not limited to the aforementioned embodiments. The pixel defining layer PDL including the first inorganic insulating layer PDL1, the second inorganic insulating layer PDL2, and the third inorganic insulating layer PDL3 is disposed adjacent to the opening OP (refer to Figure 4 ) may have a stepped cross section in an area adjacent to the first and second electrodes, but the present disclosure is not limited thereto. In one or more embodiments, as Figure 7B As shown in , the pixel defining layer PDL may not have a stepped cross-section in a region adjacent to the opening OP.

[0163] The trenches TRCH1 and TRCH2 may be positioned between the first sub-pixel SP1 and the second sub-pixel SP2. For example, the first trench TRCH1 and the second trench TRCH2 may be positioned at a boundary area BDA (refer to FIG. 1 ) between the first sub-pixel SP1 and the second sub-pixel SP2. Figure 4 )(or non-emitting area NEA).

[0164] like Fig. 7A As shown in , each of the first trench TRCH1 and the second trench TRCH2 may include a penetration portion passing through at least a portion of the pixel defining layer PDL and a recessed portion located in the planarization layer PLNL, or may be defined (or formed) by the penetration portion and the recessed portion. The first trench TRCH1 and the second trench TRCH2 may be formed by an etching method (e.g., a dry etching method, etc.), but the present disclosure is not limited thereto. In other words, each of the first trench TRCH1 and the second trench TRCH2 may be formed by removing at least a portion of the pixel defining layer PDL and the planarization layer PLNL in a direction from the upper surface of the pixel defining layer PDL toward the lower surface of the planarization layer PLNL. In one or more embodiments, as Figure 7B As shown in FIG. 1 , each of the first trench TRCH1 and the second trench TRCH2 may be formed by removing only at least a portion of the pixel defining layer PDL.

[0165] Each of the first trench TRCH1 and the second trench TRCH2 may be provided in a shape surrounding an emission area of ​​a corresponding sub-pixel in a boundary area BDA between the first sub-pixel SP1 and the second sub-pixel SP2 , but the present disclosure is not limited thereto.

[0166] In one or more embodiments, each of the pixel defining layer PDL and the planarization layer PLNL may include a first surface S1 and a second surface S2 facing each other in the first direction DR1, and each of the first trench TRCH1 and the second trench TRCH2 is interposed therebetween. Each of the pixel defining layer PDL and the planarization layer PLNL may include a third surface S3 connecting the first surface S1 and the second surface S2 to each other. The first surface S1 may be a first sidewall S1 of each of the first trench TRCH1 and the second trench TRCH2. The second surface S2 may be a second sidewall S2 of each of the first trench TRCH1 and the second trench TRCH2. The third surface S3 may be a bottom surface BT of each of the first trench TRCH1 and the second trench TRCH2. Hereinafter, for ease of explanation, the first surface S1 is referred to as the first sidewall S1 of the trench TRCH, the second surface S2 is referred to as the second sidewall S2 of the trench TRCH, and the third surface S3 is referred to as the bottom surface BT of the trench TRCH.

[0167] In one or more embodiments, the width W_T of each of the first trench TRCH1 and the second trench TRCH2 may be in a range from approximately 110 nm to approximately 210 nm, but is not limited thereto. The width W_T of each of the first trench TRCH1 and the second trench TRCH2 may be approximately 210 nm or less. The depth L_T of each of the first trench TRCH1 and the second trench TRCH2 may be in a range from approximately 110 nm to approximately 210 nm. To approximate The depth L_T of each of the first trench TRCH1 and the second trench TRCH2 may be approximately or greater. In one or more embodiments, a ratio of a width W_T to a depth L_T of each trench TRCH may be 1:3 or greater. In one or more embodiments, an angle θ of each trench TRCH may be determined by an inclination of each of the first side wall S1 and the second side wall S2 relative to the bottom surface BT. The angle θ of each trench TRCH may be set in a range from approximately (approximately) 80° to approximately (approximately) 90° so that the first intermediate layer CGL1 and the second intermediate layer CGL2 among the components disposed on the first side wall S1 and the second side wall S2 are interrupted in each trench TRCH.

[0168] The depth L_T and width W_T of each trench TRCH and the thickness of each of the first emission component EU1, the second emission component EU2, and the third emission component EU3 may be set in consideration of the discontinuity of the first intermediate layer CGL1 and the second intermediate layer CGL2 and the connection (and resonance distance) of the cathode electrode CE, etc. For example, in the case where the width W_T of each trench TRCH is greater than 210 nm, the cathode electrode CE may be interrupted by a step difference caused by a component disposed below the cathode electrode CE in the trench TRCH, thereby potentially causing a malfunction of the sub-pixel.

[0169] The emission structure EMS may be disposed on the pixel definition layer PDL. The emission structure EMS may include a first emission component EU1, a second emission component EU2, and a third emission component EU3. The emission structure EMS is in reference to Figure 4 Each of the described first light emitting element LD1, second light emitting element LD2, and third light emitting element LD3 may have substantially the same configuration, but the present disclosure is not limited thereto. In one or more embodiments, the emission structure EMS may be formed by a vacuum deposition method.

[0170] The emission structure EMS may further include a first intermediate layer CGL1 and a second intermediate layer CGL2. The first intermediate layer CGL1 (or first charge generation layer) may be disposed between the first emission component EU1 and the second emission component EU2. The second intermediate layer CGL2 (or second charge generation layer) may be disposed between the second emission component EU2 and the third emission component EU3.

[0171] In one or more embodiments, each of the first emission component EU1, the second emission component EU2, and the third emission component EU3 may include an emission layer configured to generate light in response to a current applied thereto. Figure 6 The second transmitting component EU2 may be the same as the first transmitting component EU1' described above. Figure 6 The third transmitting component EU3 can be the same as the second transmitting component EU2' described in Figure 6 The third transmitting unit EU3' is described identically.

[0172] Each of the first emission component EU1, the second emission component EU2, and the third emission component EU3 may include a hole transport component, an emission layer, an electron transport component, a buffer layer, etc. including a material having a relatively low charge conductivity (or charge mobility) compared to the first intermediate layer CGL1 and the second intermediate layer CGL2. For example, the first emission component EU1 may include a first hole transport component HTU1' (refer to Figure 6)、The first emission layer EML1 '(refer to Figure 6 ) and the first electron transport unit ETU1' (refer to Figure 6 The second emission component EU2 may include a second hole transport component HTU2' (refer to Figure 6 )、the second emission layer EML2 '(refer to Figure 6 ) and the second electron transport unit ETU2' (refer to Figure 6 The third emission element EU3 may include a third hole transport element HTU3' (refer to Figure 6 )、The third emission layer EML3 '(refer to Figure 6 ) and the third electron transport unit ETU3' (refer to Figure 6 ).

[0173] In one or more embodiments, the first emission component EU1, the second emission component EU2, and the third emission component EU3 may include a material (e.g., an insulator) having relatively high insulation compared to the first intermediate layer CGL1 and the second intermediate layer CGL2 (e.g., the insulation of each of the first intermediate layer CGL1 and the second intermediate layer CGL2). In this case, although the first emission component EU1, the second emission component EU2, and the third emission component EU3 are connected to each other above the trench TRCH, current is not transmitted to adjacent sub-pixels.

[0174] The first emission component EU1 and the second emission component EU2 may include an interruption portion (or an opening area) located in the first groove TRCH1 and the second groove TRCH2. The interruption portion may be defined as a portion in which each of the first emission component EU1 and the second emission component EU2 is disconnected in the first groove TRCH1 and the second groove TRCH2 instead of being formed into a substantially continuous structure. In this case, the first emission component EU1 of the first subpixel SP1 and the first emission component EU1 of the second subpixel SP2 may be separated from each other. The second emission component EU2 of the first subpixel SP1 and the second emission component EU2 of the second subpixel SP2 may be separated from each other.

[0175] In one or more embodiments, at least a portion of the third emission component EU3 of the first subpixel SP1 and at least a portion of the third emission component EU3 of the second subpixel SP2 may be interrupted in the first groove TRCH1 and the second groove TRCH2. In more detail, the lower surfaces of the third emission components EU3 of adjacent subpixels (for example, a specific surface of the third emission component EU3 that contacts the second intermediate layer CGL2) may be interrupted in the first groove TRCH1 and the second groove TRCH2. The upper surface of the third emission component EU3 that faces away from the lower surface (for example, a specific surface of the third emission component EU3 that contacts the cathode electrode CE) may be connected to each other. Therefore, the third emission component EU3 is not interrupted in the first groove TRCH1 and the second groove TRCH2. In this case, the third emission component EU3 of the first subpixel SP1 and the third emission component EU3 of the second subpixel SP2 may be connected to each other.

[0176] Each of the first intermediate layer CGL1 and the second intermediate layer CGL2 can generate charges. The first intermediate layer CGL1 can connect the first emission component EU1 and the second emission component EU2. The second intermediate layer CGL2 can connect the second emission component EU2 and the third emission component EU3. In one or more embodiments, the first intermediate layer CGL1 and the second intermediate layer CGL2 may include a material having a relatively high charge conductivity (or charge mobility) compared to the first emission component EU1, the second emission component EU2, and the third emission component EU3, thereby having conductive properties.

[0177] Each of the first intermediate layer CGL1 and the second intermediate layer CGL2 may include an interruption portion (or an opening area) located above the first trench TRCH1 and the second trench TRCH2 (or in the first trench TRCH1 and the second trench TRCH2) in a manner similar to that of the first emission component EU1 and the second emission component EU2. The interruption portion may be defined as a portion in which each of the first intermediate layer CGL1 and the second intermediate layer CGL2 is disconnected in the first trench TRCH1 and the second trench TRCH2 instead of being formed as a portion having a substantially continuous structure. In other words, each of the first intermediate layer CGL1 and the second intermediate layer CGL2 may be interrupted above each of the first trench TRCH1 and the second trench TRCH2. In this case, leakage of current from one sub-pixel to an adjacent sub-pixel through the first intermediate layer CGL1 and the second intermediate layer CGL2 may be reduced or prevented, whereby the sub-pixels may operate with high reliability. Furthermore, in the case where each of the first and second intermediate layers CGL1 and CGL2 is interrupted above each of the first and second trenches TRCH1 and TRCH2 , color mixing between adjacent sub-pixels may be reduced or prevented, whereby each sub-pixel may emit light of a desired color.

[0178] In one or more embodiments, the emission structure EMS may include a first emission component EU1, a first intermediate layer CGL1, a second emission component EU2, a second intermediate layer CGL2, and a third emission component EU3 sequentially stacked in the third direction DR3. The first emission component EU1 may be disposed at a corresponding anode electrode AE ​​(refer to Figure 2 ) (or the first electrode) and the pixel defining layer PDL. The first intermediate layer CGL1 can be disposed on the first emission component EU1. The second emission component EU2 can be disposed on the first intermediate layer CGL1. The second intermediate layer CGL2 can be disposed on the second emission component EU2. The third emission component EU3 can be disposed on the second intermediate layer CGL2. The cathode electrode CE (or the second electrode) can be disposed on the third emission component EU3.

[0179] The first intermediate layer CGL1 can be disposed between the first emission component EU1 and the second emission component EU2, and can be covered by the second emission component EU2. The second intermediate layer CGL2 can be disposed between the second emission component EU2 and the third emission component EU3, and can be covered by the third emission component EU3. In the cross-sectional view, the first intermediate layer CGL1 and the second intermediate layer CGL2 can face each other, and the second emission component EU2 is interposed therebetween.

[0180] The first emission component EU1 may be formed on the anode electrode AE ​​(or the first electrode) and the pixel defining layer PDL, and may also be formed on the first side wall S1 and the second side wall S2 of each of the first trench TRCH1 and the second trench TRCH2. In this document, on the first side wall S1 and the second side wall S2, the end EP1 of the first emission component EU1 (hereinafter referred to as "the first end EP1") may be positioned adjacent to and in contact with the bottom surface BT of the trench TRCH. In one or more embodiments, the first emission component EU1 may be formed on or not formed on the bottom surface BT of each trench TRCH. The position of the first end EP1 of the first emission component EU1 on the first side wall S1 and the second side wall S2 of each trench TRCH may be determined by adjusting the incident angle (or injection angle) of the matrix material (or deposition material) of the first emission component EU1 during the process of forming the first emission component EU1.

[0181] The first intermediate layer CGL1 can be formed on the first emission component EU1, and the first intermediate layer CGL1 can also be formed on the first emission component EU1 even on the first side wall S1 and the second side wall S2 of each trench TRCH. The end EP2 of the first intermediate layer CGL1 (hereinafter, referred to as "the second end EP2") can be positioned farther from the bottom surface BT of the trench TRCH than the first end EP1 of the first emission component EU1. The position of the second end EP2 of the first intermediate layer CGL1 on the first side wall S1 and the second side wall S2 of each trench TRCH can be determined by adjusting the incident angle (or injection angle) of the base material (or deposition material) of the first intermediate layer CGL1 during the process of forming the first intermediate layer CGL1. In this article, the incident angle of the base material of the first intermediate layer CGL1 can be different from the incident angle of the base material of the first emission component EU1. For example, the incident angle of the base material of the first intermediate layer CGL1 can be set to be smaller than the incident angle of the base material of the first emission component EU1.

[0182] The second emission component EU2 may be formed on the first intermediate layer CGL1, and the second emission component EU2 may also be formed on the first intermediate layer CGL1 even on the first side wall S1 and the second side wall S2 of each trench TRCH. The end EP3 of the second emission component EU2 (hereinafter, referred to as "third end EP3") may be positioned closer to the bottom surface BT of the trench TRCH than the second end EP2 of the first intermediate layer CGL1. In this case, as Figure 8 As shown in , in the groove TRCH, the second emission component EU2 can be set to be relatively deeper than the first intermediate layer CGL1. Therefore, the first intermediate layer CGL1 can be covered by the second emission component EU2 in the groove TRCH. In other words, the entire first intermediate layer CGL1 including the second end EP2 of the first intermediate layer CGL1 can be completely covered by the second emission component EU2. The position of the third end EP3 of the second emission component EU2 on the first side wall S1 and the second side wall S2 of each groove TRCH can be determined by adjusting the incident angle (or injection angle) of the matrix material (or deposition material) of the second emission component EU2 during the process of forming the second emission component EU2. In this article, the incident angle of the matrix material of the second emission component EU2 can be different from the incident angle of the matrix material of the first intermediate layer CGL1. For example, the incident angle of the matrix material of the second emission component EU2 can be set to be greater than the incident angle of the matrix material of the first intermediate layer CGL1. The incident angle of the matrix material of the second emission component EU2 may be the same as the incident angle of the matrix material of the first emission component EU1, but the present disclosure is not limited to this.

[0183] The second intermediate layer CGL2 may be formed on the second emission component EU2, and the second intermediate layer CGL2 may also be formed on the second emission component EU2 even on the first side wall S1 and the second side wall S2 of each trench TRCH. The end EP4 (hereinafter, referred to as "fourth end EP4") of the second intermediate layer CGL2 may be positioned farther from the bottom surface BT of the trench TRCH than the third end EP3 of the second emission component EU2. In this case, as Figure 8 As shown in, in the trench TRCH, the second intermediate layer CGL2 can be set to be relatively thinner than the second emission component EU2, so that a portion of the second emission component EU2 can be exposed to the outside. The position of the fourth end EP4 of the second intermediate layer CGL2 on the first side wall S1 and the second side wall S2 of each trench TRCH can be determined by adjusting the incident angle (or injection angle) of the base material (or deposition material) of the second intermediate layer CGL2 during the process of forming the second intermediate layer CGL2. In this article, the incident angle of the base material of the second intermediate layer CGL2 may be different from the incident angle of the base material of the second emission component EU2. For example, the incident angle of the base material of the second intermediate layer CGL2 can be set to be less than the incident angle of the base material of the second emission component EU2. The injection angle of the base material of the second intermediate layer CGL2 may be the same as the injection angle of the base material of the first intermediate layer CGL1, but the present disclosure is not limited to this.

[0184] The third emission component EU3 may be formed on the second intermediate layer CGL2, and the third emission component EU3 may also be formed on the second intermediate layer CGL2 even on the first side wall S1 and the second side wall S2 of each trench TRCH. The end EP5 (hereinafter, referred to as "fifth end EP5") of the third emission component EU3 may be positioned closer to the bottom surface BT of the trench TRCH than the fourth end EP4 of the second intermediate layer CGL2. In this case, as Figure 8As shown in , in the groove TRCH, the third emission component EU3 can be set to be relatively deeper than the second intermediate layer CGL2. Therefore, the second intermediate layer CGL2 can be covered by the third emission component EU3 in the groove TRCH. In other words, the entire second intermediate layer CGL2 including the fourth end EP4 of the second intermediate layer CGL2 can be completely covered by the third emission component EU3. The third emission component EU3 can be arranged on the portion of the second emission component EU2 exposed to the outside. The position of the fifth end EP5 of the third emission component EU3 on the first side wall S1 and the second side wall S2 of each groove TRCH can be determined by adjusting the incident angle (or injection angle) of the matrix material (or deposition material) of the third emission component EU3 during the process of forming the third emission component EU3. In this article, the incident angle of the matrix material of the third emission component EU3 can be different from the incident angle of the matrix material of each of the first intermediate layer CGL1 and the second intermediate layer CGL2. For example, the incident angle of the matrix material of the third emission component EU3 can be set to be greater than the incident angle of the matrix material of each of the first intermediate layer CGL1 and the second intermediate layer CGL2. The incident angle of the matrix material of the third emitting component EU3 may be the same as the incident angle of the matrix material of the first emitting component EU1 and / or the matrix material of the second emitting component EU2 , but the present disclosure is not limited thereto.

[0185] The cathode electrode CE may be disposed on the third emission component EU3. The cathode electrode CE (or the second electrode) may be formed of a metal including a conductive material. In one or more embodiments, the thickness d of the third emission component EU3 may be greater than the thickness of each of the first emission component EU1 and the second emission component EU2. The thickness d of the third emission component EU3 may be the distance between the second intermediate layer CGL2 and the cathode electrode CE. In other words, the thickness d of the third emission component EU3 corresponding to the distance between the second intermediate layer CGL2 and the cathode electrode CE may be greater than the distance between the first intermediate layer CGL1 and the second intermediate layer CGL2 (or the thickness of the second emission component EU2). The reason for the above structure is to prevent or reduce the occurrence of defects caused by a short circuit between the cathode electrode CE and the second intermediate layer CGL2 including a material having a high charge conductivity (or charge mobility) with conductive properties, and to prevent or reduce the discontinuity of the cathode electrode CE caused by the step portion of the lower layer components (e.g., the second intermediate layer CGL2, the second emission component EU2, the first intermediate layer CGL1, and the first emission component EU1). In other words, the third emission component EU3 having a relatively large thickness d can ensure a larger distance between the cathode electrode CE and the second intermediate layer CGL2, thereby preventing or reducing a short circuit defect between the cathode electrode CE and the second intermediate layer CGL2. In addition, due to the third emission component EU3, the step difference of the lower component can be reduced, so that the step coverage of the cathode electrode CE set on the third emission component EU3 can be improved, thereby preventing or reducing the defect of the cathode electrode CE being interrupted in the trench TRCH.

[0186] In one or more embodiments, based on the third direction DR3, the thickness of the first emission component EU1 and the second emission component EU2 may be less than the depth L_T of each of the first trench TRCH1 and the second trench TRCH2. The thickness d of the third emission component EU3 may be greater than the depth L_T of each of the first trench TRCH1 and the second trench TRCH2.

[0187] The void VD may be formed in the first trench TRCH1 and the second trench TRCH2, respectively. Figure 4 The described first void VD1 and second void VD2 are identical.The void VD may be surrounded by the first emission element EU1, the second emission element EU2 and the third emission element EU3 in each trench TRCH.

[0188] According to the aforementioned embodiment, the first intermediate layer CGL1 (or first charge generation layer) including a material having a relatively high charge conductivity (or charge mobility) with conductive properties selected from among the layers constituting the emission structure EMS can be interrupted above each trench TRCH, and can be completely covered by the second emission component EU2 until its end EP2 (or second end EP2) in the corresponding trench TRCH. In addition, the second intermediate layer CGL2 (or second charge generation layer) including a material having a relatively high charge conductivity (or charge mobility) with conductive properties can be interrupted above each trench TRCH, and can be completely covered by the third emission component EU3 until its end EP4 (or fourth end EP4) in the corresponding trench TRCH. Therefore, the short circuit defect between the first intermediate layer CGL1 and the second intermediate layer CGL2 with conductive properties can be reduced or prevented, thereby further improving the reliability of each sub-pixel.

[0189] According to the aforementioned embodiment, the first intermediate layer CGL1 , the second intermediate layer CGL2 , and the cathode electrode CE (or the second electrode) may be electrically insulated from each other.

[0190] In the aforementioned embodiments, the emission structure EMS has been described as having a series structure including the first emission component EU1, the second emission component EU2, and the third emission component EU3 stacked on top of each other, but the structure is not limited thereto. Figure 7C As shown in FIG. 1 , in one or more embodiments, the emission structure EMS may have a series structure including a first emission component EU1 and a second emission component EU2 stacked on top of each other. In this case, the emission structure EMS may be arranged in a manner similar to that of the reference Figure 5 The emission structure EMS described above includes a first intermediate layer CGL1 disposed between the first emission component EU1 and the second emission component EU2. The first intermediate layer CGL1 may be connected to Figure 5 The middle layer CGL is the same.

[0191] In the following, reference will be made to Figure 7C An emission structure EMS including a first emission component EU1 and a second emission component EU2 and a first intermediate layer CGL1 is described.

[0192] Each of the first emission component EU1 and the second emission component EU2 may include an emission layer configured to generate light in response to a current applied thereto. The first emission component EU1 may be connected to the reference Figure 5 The first transmitting component EU1 described above is the same as the first transmitting component EU2 described above. Figure 5The second emission component EU2 is described to be the same. Each of the first emission component EU1 and the second emission component EU2 may include a hole transport component including a material having a relatively low charge conductivity compared to the first intermediate layer CGL1 , an emission layer, an electron transport component, and a buffer layer.

[0193] The first emission component EU1 may include a discontinuity portion in each of the first trench TRCH1 and the second trench TRCH2 In this case, the first emission component EU1 of the first sub-pixel SP1 may be separated from the first emission component EU1 of the second sub-pixel SP2.

[0194] At least a portion of the second emission component EU2 of the first subpixel SP1 and at least a portion of the second emission component EU2 of the second subpixel SP2 may be interrupted in the first groove TRCH1 and the second groove TRCH2. In detail, the lower surface of the second emission component EU2 of the adjacent subpixel (for example, a specific surface of the second emission component EU2 contacting the first intermediate layer CGL1) may be interrupted in the first groove TRCH1 and the second groove TRCH2. The upper surface of the second emission component EU2 facing away from the lower surface (for example, a specific surface of the second emission component EU2 contacting the cathode electrode CE) may be connected to each other. Therefore, the second emission component EU2 is not interrupted in the first groove TRCH1 and the second groove TRCH2. In this case, the second emission component EU2 of the first subpixel SP1 and the second emission component EU2 of the second subpixel SP2 may be connected to each other.

[0195] The first intermediate layer CGL1 may generate charges. The first intermediate layer CGL1 may be connected to a reference Figure 5 The first intermediate layer CGL1 is the same as the intermediate layer CGL described. The first intermediate layer CGL1 can connect the first emission component EU1 and the second emission component EU2. The first intermediate layer CGL1 may include a material with a relatively high charge conductivity, thereby having a conductive property. The first intermediate layer CGL1 may include an interruption portion (or an opening area) located above the first trench TRCH1 and the second trench TRCH2 (or in the first trench TRCH1 and the second trench TRCH2) in a manner similar to that of the first emission component EU1. The first intermediate layer CGL1 may be interrupted above each of the first trench TRCH1 and the second trench TRCH2. In this case, the current can be reduced or prevented from leaking from one sub-pixel to an adjacent sub-pixel through the first intermediate layer CGL1, whereby the sub-pixel can operate with high reliability. In addition, in the case where the first intermediate layer CGL1 is interrupted above each of the first trench TRCH1 and the second trench TRCH2, color mixing between adjacent sub-pixels can be prevented or color mixing between adjacent sub-pixels can be protected.

[0196] The first intermediate layer CGL1 may be formed on the first emission component EU1, and the first intermediate layer CGL1 may also be formed on the first emission component EU1 even on the first sidewall S1 and the second sidewall S2 of each trench TRCH. In each trench TRCH, an end of the first intermediate layer CGL1 may be positioned farther from the bottom surface BT of the trench TRCH than an end of the first emission component EU1.

[0197] The second emission component EU2 can be formed on the first intermediate layer CGL1, and the second emission component EU2 can also be formed on the first intermediate layer CGL1 even on the first side wall S1 and the second side wall S2 of each trench TRCH. In each trench TRCH, the end of the second emission component EU2 can be positioned closer to the bottom surface BT of the trench TRCH than the end of the first intermediate layer CGL1. In this case, on the trench TRCH (or in the trench TRCH), the second emission component EU2 can be set to be relatively deeper than the first intermediate layer CGL1. Therefore, the first intermediate layer CGL1 can be covered by the second emission component EU2 in the trench TRCH. In other words, the entire first intermediate layer CGL1 including the end of the first intermediate layer CGL1 can be completely covered by the second emission component EU2. The second emission component EU2 can be set on the portion of the first emission component EU1 exposed to the outside.

[0198] The cathode electrode CE may be disposed on the second emission element EU2. The cathode electrode CE (or the second electrode) may be formed of a metal including a conductive material.

[0199] The void VD may be formed in each of the first trench TRCH1 and the second trench TRCH2. The void VD may be surrounded by the first emission element EU1 and the second emission element EU2 in each trench TRCH.

[0200] According to the aforementioned embodiment, the first intermediate layer CGL1 having conductive properties and including a material having a relatively high charge conductivity (or charge mobility) selected from the layers constituting the emission structure EMS may be interrupted above each trench TRCH, and may be completely covered by the second emission component EU2 including a material having a relatively low charge conductivity in the corresponding trench TRCH until its end. In this case, the first intermediate layer CGL1 and the cathode electrode CE (or the second electrode) may be electrically insulated from each other. Therefore, the short circuit defect between the first intermediate layer CGL1 and the cathode electrode CE may be reduced or prevented, thereby further improving the reliability of each sub-pixel.

[0201] In the following, reference will be made to Figures 9 to 12 Describes the use of a method for manufacturing a display device (e.g., Figure 1 Device 1 (refer to display device DD) Fig. 9) A method of forming an emission structure EMS on a first sidewall S1 and a second sidewall S2 of a trench TRCH.

[0202] Fig. 9 is a schematic diagram illustrating one or more embodiments of an apparatus 1 for manufacturing a display device. Fig.10 It is shown Fig. 9 Schematic diagram of a first deposition source 10. Fig.11 It is shown Fig. 9 Schematic diagram of the second deposition source 20. Fig.12 The simulation results of the deposition appearance depending on the incident angle of the components of the emission structure EMS formed on the trench TRCH are shown. Fig. 9 , for convenience of explanation, the first deposition chamber CHM1 and the second deposition chamber CHM2 are illustrated as having the same structure.

[0203] Reference FIG. 7A to FIG. 12 , the apparatus 1 for manufacturing a display device may be a deposition apparatus for forming an emission structure EMS. Hereinafter, the apparatus 1 for manufacturing a display device will be referred to as a deposition apparatus.

[0204] The apparatus (eg, depositor) 1 may include a first deposition chamber CHM1 and a second deposition chamber CHM2 separated from each other.

[0205] The first deposition chamber CHM1 may provide a sealed space for depositing (or forming) each of the first intermediate layer CGL1 and the second intermediate layer CGL2 selected from the components of the emission structure EMS on the target substrate DS, each of the first intermediate layer CGL1 and the second intermediate layer CGL2 including a material having a relatively high charge conductivity to have a conductive property. In one or more embodiments, the first deposition chamber CHM1 may provide a sealed space for depositing (or forming) a cathode electrode CE (or a second electrode) including a conductive material on the target substrate DS. The second deposition chamber CHM2 may provide a sealed space for depositing (or forming) each of the first emission component EU1, the second emission component EU2, and the third emission component EU3 on the target substrate DS, each of the first emission component EU1, the second emission component EU2, and the third emission component EU3 including a material having a relatively low charge conductivity (or low charge mobility) compared to the first intermediate layer CGL1 and the second intermediate layer CGL2 selected from the components of the emission structure EMS. The interior of each of the first deposition chamber CHM1 and the second deposition chamber CHM2 may be maintained in a reduced pressure atmosphere.

[0206] The movable plate MP, the first mask assembly MK1, and the first deposition source 10 may be disposed in the inner space of the first deposition chamber CHM1. The movable plate MP, the second mask assembly MK2, and the second deposition source 20 may be disposed in the inner space of the second deposition chamber CHM2. Each of the first deposition chamber CHM1 and the second deposition chamber CHM2 may include one or more gates GA. For example, the target substrate DS may be moved in and out of the corresponding chamber through the gate GA. For example, when the deposition of the material of the first intermediate layer CGL1 on the target substrate DS in the first deposition chamber CHM1 is completed, the target substrate DS may be moved into the second deposition chamber CHM2 through the gate GA of the first deposition chamber CHM1. In addition, when the deposition of the material of the second emission assembly EU2 on the target substrate DS in the second deposition chamber CHM2 is completed, the target substrate DS may be moved into the first deposition chamber CHM1 through the gate GA of the second deposition chamber CHM2.

[0207] The movable plate MP may move in the first deposition chamber CHM1 and the second deposition chamber CHM2 .

[0208] The first mask assembly MK1 may be disposed between the target substrate DS and the first deposition source 10 and may overlap the target substrate DS. The first mask assembly MK1 may be supported by the support assembly SU. A plurality of first openings OPN1 may be defined in the first mask assembly MK1. The deposition material sprayed in the first deposition chamber CHM1 may be deposited on the target substrate DS through the first openings OPN1.

[0209] The second mask assembly MK2 may be disposed between the target substrate DS and the second deposition source 20 and may overlap the target substrate DS. The second mask assembly MK2 may be supported by the support assembly SU. A plurality of second openings OPN2 may be defined in the second mask assembly MK2. The deposition material sprayed in the second deposition chamber CHM2 may be deposited on the target substrate DS through the second openings OPN2.

[0210] The first deposition source 10 may be disposed under the first mask assembly MK1 and receive a deposition material therein. The first deposition source 10 may evaporate or sublimate the deposition material received therein and spray the evaporated or sublimated deposition material onto the target substrate DS. Herein, the first deposition source 10 may receive a deposition material corresponding to the first intermediate layer CGL1, a deposition material corresponding to the second intermediate layer CGL2, and a deposition material corresponding to the cathode electrode CE, respectively.

[0211] The first deposition source 10 may include a first body BO1 and a first angle limiting assembly AC1. The first body BO1 may include a crucible for receiving a deposition material and a first nozzle NOZ1 configured to spray the deposition material onto a target substrate DS. A first nozzle hole NOH1 may be defined in each of the first nozzles NOZ1. The first deposition source 10 may include a first reflector RF1 to reduce or prevent heat from leaking upward from the first body BO1.

[0212] The first angle limiting component AC1 may limit the deposition area of ​​the deposition material ejected toward the target substrate DS through the first nozzle NOZ1. The discharge angle of the deposition material ejected from the first body BO1 may be limited to a specific angle or less by the first angle limiting component AC1. As a result, in the device 1, the incident angle of the deposition material on the target substrate DS during the process of performing deposition may be limited to a specific angle or less, and the patterning accuracy in the epitaxial growth through the first mask component MK1 may be improved. The first angle limiting component AC1 may include a 1-1 angle limiting component AC1_1 and a 1-2 angle limiting component AC1_2, the 1-1 angle limiting component AC1_1 and the 1-2 angle limiting component AC1_2 facing each other, with the first nozzle NOZ1 interposed therebetween. The incident angle of the deposition material (e.g., the deposition material corresponding to the first intermediate layer CGL1 and the deposition material corresponding to the second intermediate layer CGL2) to be ejected onto the target substrate DS may be controlled or selected by adjusting the tilt angles of the 1-1 angle limiting component AC1_1 and the 1-2 angle limiting component AC1_2.

[0213] The second deposition source 20 may be disposed below the second mask assembly MK2 and receive deposition material therein. The second deposition source 20 may evaporate or sublimate the deposition material received therein, and spray the evaporated or sublimated deposition material onto the target substrate DS. In this article, the second deposition source 20 may receive deposition material corresponding to the first emission assembly EU1, deposition material corresponding to the second emission assembly EU2, and deposition material corresponding to the third emission assembly EU3, respectively.

[0214] The second deposition source 20 may include a second body BO2 and a second angle limiting assembly AC2. The second body BO2 may include a crucible for receiving a deposition material and a second nozzle NOZ2 configured to spray the deposition material onto the target substrate DS. A second nozzle hole NOH2 may be defined in each of the second nozzles NOZ2. The second deposition source 20 may include a second reflector RF2 to reduce or prevent heat from leaking upward from the second body BO2.

[0215] The second angle limiting component AC2 can limit the deposition area of ​​the deposition material sprayed toward the target substrate DS through the second nozzle NOZ2. The discharge angle of the deposition material discharged from the second body BO2 can be limited to a specific angle or less by the second angle limiting component AC2. As a result, in the device 1, the incident angle of the deposition material on the target substrate DS during the process of performing the deposition can be limited to a specific angle or less, and the patterning accuracy in the epitaxial growth through the second mask component MK2 can be improved. The second angle limiting component AC2 may include a 2-1st angle limiting component AC2_1 and a 2-2nd angle limiting component AC2_2, the 2-1st angle limiting component AC2_1 and the 2-2nd angle limiting component AC2_2 facing each other, and the second nozzle NOZ2 is interposed therebetween. The incident angle of the deposition material to be sprayed onto the target substrate DS can be controlled or selected by adjusting the tilt angles of the 2-1st angle limiting component AC2_1 and the 2-2nd angle limiting component AC2_2.

[0216] In one or more embodiments, the inclination angle of the first angle limiting component AC1 and the inclination angle of the second angle limiting component AC2 may be different from each other. For example, the inclination angle of the second angle limiting component AC2 may be greater than the inclination angle of the first angle limiting component AC1, but is not limited thereto. The inclination angle of the first angle limiting component AC1 and the inclination angle of the second angle limiting component AC2 may be determined according to the incident angle of the deposition material to be sprayed onto the corresponding target substrate DS.

[0217] In the following, reference will be made to Fig.12 The extent of epitaxial growth of the emission structure EMS formed in the trench TRCH is described for each incident angle.

[0218] Reference Fig.12 , also refer to Figures 9 to 11 , the first incident angle and the second incident angle may be determined in a range from approximately 40° to approximately 85°. For example, the first incident angle may be in a range from approximately 50° to approximately 60°, and the second incident angle may be in a range from approximately 70° to approximately 75°. Compared to the first incident angle, the second incident angle may be a high incident angle. Compared to the second incident angle, the first incident angle may be a low incident angle.

[0219] In addition, Fig.12In the embodiment, embodiments 1 to 6 are embodiments involving adjusting the tilt angles of the first angle limiting component AC1 and the second angle limiting component AC2 so that the components included in the emission structure EMS (for example, the first emission component EU1, the first intermediate layer CGL1, the second emission component EU2, the second intermediate layer CGL2, and the third emission component EU3) are incident on the pixel defining layer PDL (or the target substrate DS) at a first incident angle (or a low incident angle) during the process of forming the emission structure EMS on the pixel defining layer PDL (or the target substrate DS). Embodiments 7 to 12 are embodiments involving adjusting the tilt angles of the first angle limiting component AC1 and the second angle limiting component AC2 so that the components included in the emission structure EMS (for example, the first emission component EU1, the first intermediate layer CGL1, the second emission component EU2, the second intermediate layer CGL2, and the third emission component EU3) are incident on the pixel defining layer PDL (or the target substrate DS) at a second incident angle (or a high incident angle) during the process of forming the emission structure EMS on the pixel defining layer PDL (or the target substrate DS).

[0220] In Example 1 and Example 7, the width of the groove TRCH may be approximately 110nm. In Example 2 and Example 8, the width of the groove TRCH may be approximately 130nm. In Example 3 and Example 9, the width of the groove TRCH may be approximately 150nm. In Example 4 and Example 10, the width of the groove TRCH may be approximately 170nm. In Example 5 and Example 11, the width of the groove TRCH may be approximately 190nm. In Example 6 and Example 12, the width of the groove TRCH may be approximately 210nm.

[0221] In Examples 1 to 12, the first emission component EU1, the first intermediate layer CGL1, the second emission component EU2, and the second intermediate layer CGL2 may be interrupted and discontinuously formed above the groove TRCH, and the third emission component EU3 may be continuously formed without interruption. In addition, in Examples 1 to 12, a portion of the lower surface of the third emission component EU3 may be interrupted and discontinuously formed above the groove TRCH, and the upper surface of the third emission component EU3 may be continuously formed without interruption.

[0222] In Embodiments 1 to 12, the end of the first emission element EU1 may be positioned on the first sidewall S1 and the second sidewall S2 of the trench TRCH. The first emission element EU1 may also be positioned on the bottom surface BT of the trench TRCH.

[0223] Over the trench TRCH, the end of the first intermediate layer CGL1 according to each of Embodiments 1 to 6 is positioned farther from the bottom surface BT of the trench TRCH than the end of the first intermediate layer CGL1 according to each of Embodiments 7 to 12. As a result, it can be checked that the first intermediate layer CGL1 according to each of Embodiments 7 to 12 incident on the pixel defining layer PDL at the second incident angle (or high incident angle) can be formed deeper toward the first side wall S1 and the second side wall S2 of the trench TRCH than the first intermediate layer CGL1 according to each of Embodiments 1 to 6 incident on the pixel defining layer PDL at the first incident angle (or low incident angle).

[0224] Above the trench TRCH, the end of the second emission component EU2 according to each of Embodiments 1 to 6 is positioned farther from the bottom surface BT of the trench TRCH than the end of the second emission component EU2 according to each of Embodiments 7 to 12. As a result, it can be checked that the second emission component EU2 according to each of Embodiments 7 to 12 incident on the first intermediate layer CGL1 at the second incident angle (or high incident angle) can be formed deeper toward the first side wall S1 and the second side wall S2 of the trench TRCH than the second emission component EU2 according to each of Embodiments 1 to 6 incident on the first intermediate layer CGL1 at the first incident angle (or low incident angle).

[0225] Above the trench TRCH, the end of the second intermediate layer CGL2 according to each of Embodiments 1 to 6 is positioned farther from the bottom surface BT of the trench TRCH than the end of the second intermediate layer CGL2 according to each of Embodiments 7 to 12. As a result, it can be checked that the second intermediate layer CGL2 according to each of Embodiments 7 to 12 incident on the second emission component EU2 at the second incident angle (or high incident angle) can be formed deeper toward the first side wall S1 and the second side wall S2 of the trench TRCH than the second intermediate layer CGL2 according to each of Embodiments 1 to 6 incident on the second emission component EU2 at the first incident angle (or low incident angle).

[0226] Above the trench TRCH, a portion of the lower surface of the third emission component EU3 according to each of Embodiments 1 to 12 is interrupted, and the upper surface thereof is not interrupted. As a result, above the trench TRCH, the third emission component EU3 according to each of Embodiments 1 to 12 can cover the end of the second intermediate layer CGL2 while alleviating the step difference caused by the components disposed below the third emission component EU3.

[0227] In the aforementioned embodiment, in order to prevent or reduce the short circuit between the first intermediate layer CGL1 and the second intermediate layer CGL2 including a material having a relatively high charge conductivity and having a conductive property over the trench TRCH, it is considered that Fig.12 According to the simulation results, each of the first intermediate layer CGL1 and the second intermediate layer CGL2 is incident on the pixel defining layer PDL at a first incident angle (or a low incident angle). In some embodiments, the first emission component EU1, the second emission component EU2, and the third emission component EU3, which are disposed on the first intermediate layer CGL1 and the second intermediate layer CGL2 and include a material having a relatively low charge conductivity compared to the first intermediate layer CGL1 and the second intermediate layer CGL2, are incident on the pixel defining layer PDL at a second incident angle (or a high incident angle). In this case, the end EP2 (refer to Figure 8 ) can be positioned at an end EP3 (refer to Figure 8 ) is away from the bottom surface BT of the trench TRCH and can be completely covered by the second emission element EU2. In addition, the end EP4 (refer to Figure 8 ) can be positioned at an end EP5 (refer to Figure 8 ) is away from the bottom surface BT of the trench TRCH and can be completely covered by the third emission element EU3. As a result, the first intermediate layer CGL1 and the second intermediate layer CGL2 having a conductive property can be prevented from being short-circuited in the trench TRCH or the first intermediate layer CGL1 and the second intermediate layer CGL2 having a conductive property can be protected from being short-circuited in the trench TRCH, whereby the sub-pixel can be operated with high reliability, thereby improving the display device DD (refer to Figure 1 ) reliability.

[0228] Furthermore, in the aforementioned embodiments, the incident angles of the first intermediate layer CGL1 and the second intermediate layer CGL2 and the incident angles of the first emission component EU1, the second emission component EU2, and the third emission component EU3 can be controlled or selected by adjusting the tilt angles of the first angle limiting component AC1 and the second angle limiting component AC2 of the device 1. Therefore, without performing a separate additional process, the first intermediate layer CGL1 and the second intermediate layer CGL2 having conductive properties can be prevented from short-circuiting or protected from short-circuiting by adjusting the incident angle of each of the first emission component EU1, the first intermediate layer CGL1, the second emission component EU2, the second intermediate layer CGL2, and the third emission component EU3. As a result, the manufacturing efficiency of the display device DD can be further improved.

[0229] In the following, reference will be made to Figures 13 to 15 Application fields of the display devices 1210 and 1220 according to one or more embodiments are described.

[0230] Fig.13 is a schematic block diagram illustrating one or more embodiments of a display system 1000 .

[0231] Reference Fig.13 , the display system 1000 may include a processor 1100 and one or more display devices 1210 and 1220 .

[0232] The processor 1100 may perform one or more suitable tasks and operations. In one or more embodiments, the processor 1100 may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 may be connected to other components of the display system 1000 through a bus system to control the components.

[0233] exist Fig.13 , it is shown that the display system 1000 includes a first display device 1210 and a second display device 1220. The processor 1100 may be connected to the first display device 1210 through a first channel CH1, and may be connected to the second display device 1220 through a second channel CH2.

[0234] The processor 1100 may transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210 through the first channel CH1. The first display device 1210 may display an image based on the first image data IMG1 and the first control signal CTRL1. Figure 1 The described display devices DD have the same configuration.

[0235] The processor 1100 may transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220 through the second channel CH2. The second display device 1220 may display an image based on the second image data IMG2 and the second control signal CTRL2. Figure 1 The described display devices DD have the same configuration.

[0236] The display system 1000 may include a computing system that provides an image display function, such as a portable computer, a mobile phone, a smart phone, a tablet personal computer (tablet PC), a smart watch, a watch phone, a portable multimedia player, a navigation system, and / or an ultra mobile personal computer (UMPC). In addition, the display system 1000 may include at least one of a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0237] Fig.14 It is shown Fig.13 Schematic perspective view of an application example of the display system 1000.

[0238] Reference Fig.14 , Fig.13 The display system 1000 may be applied to a head-mounted display 2000. The head-mounted display 2000 may be a wearable electronic device that can be worn on the head of a user.

[0239] The head mounted display 2000 may include a head mounted band 2100 and a display device receiving housing 2200. The head mounted band 2100 may be connected to the display device receiving housing 2200. The head mounted band 2100 may include a horizontal band and / or a vertical band to fasten the head mounted display 2000 to the user's head. The horizontal band may surround the sides of the user's head, and the vertical band may surround the top of the user's head. However, the present disclosure is not limited to the foregoing examples. For example, the head mounted band 2100 may be implemented in the form of a glasses frame, a helmet, and the like.

[0240] The display device receiving housing 2200 can receive Fig.13 The display device receiving housing 2200 can also receive the first display device 1210 and the second display device 1220. Fig.13 Processor 1100.

[0241] Fig.15 Is to show the wear on the user Fig.14 Schematic diagram of a head mounted display 2000.

[0242] Reference Fig.15 , the first display device 1210 (refer to Fig.13 ) of the first display panel DP1 and the second display device 1220 (refer to Fig.13 ) is provided in the head mounted display 2000. The head mounted display 2000 may further include one or more lenses LLNS and RLNS.

[0243] In the display device receiving housing 2200, the right eye lens RLNS may be positioned between the first display panel DP1 and the right eye of the user. In the display device receiving housing 2200, the left eye lens LLNS may be positioned between the second display panel DP2 and the left eye of the user.

[0244] The image output from the first display panel DP1 can be viewed by the user's right eye through the right eye lens RLNS. The right eye lens RLNS may refract light emitted from the first display panel DP1 toward the user's right eye. The right eye lens RLNS may perform an optical function to adjust the viewing distance between the first display panel DP1 and the user's right eye.

[0245] The image output from the second display panel DP2 may be viewed by the user's left eye through the left eye lens LLNS. The left eye lens LLNS may refract light emitted from the second display panel DP2 toward the user's left eye. The left eye lens LLNS may perform an optical function to adjust the viewing distance between the second display panel DP2 and the user's left eye.

[0246] In one or more embodiments, each of the right eye lens RLNS and the left eye lens LLNS may include an optical lens having a flat cross section. In one or more embodiments, each of the right eye lens RLNS and the left eye lens LLNS may include a multi-channel lens including sub-regions having different optical characteristics. In this case, each display panel may output images corresponding to the sub-regions of the multi-channel lens, respectively. The user may view the output image through the corresponding sub-regions.

[0247] According to one or more embodiments, the incident angles (or deposition angles) of the layers forming the emission structure arranged above the groove can be different from each other, so that short-circuit defects can be prevented from occurring between layers having conductive properties including materials with relatively high charge conductivity (or charge mobility) among multiple layers, or short-circuit defects can be protected from occurring between layers having conductive properties including materials with relatively high charge conductivity (or charge mobility) among multiple layers, thereby improving the reliability of the display device.

[0248] In addition, according to one or more embodiments, the conductive intermediate layer (or charge generation layer) may be interrupted above the groove formed in the boundary region between adjacent sub-pixels, thereby reducing or preventing current from leaking to adjacent sub-pixels through the intermediate layer.

[0249] The effects, aspects, and features of the embodiments of the present disclosure are not limited to the foregoing, and other one or more suitable effects, aspects, and features are foreseeable herein.

[0250] As used herein, the terms "substantially", "approximately" and similar terms are used as approximate terms, rather than terms of degree, and are intended to illustrate the inherent deviations of measured or calculated values ​​that will be recognized by those of ordinary skill in the art. Taking into account the measurement in question and the errors associated with the measurement of a particular amount (i.e., the limitations of the measurement system), "approximately" or "approximately" as used herein include the stated values ​​and are meant to be within the acceptable deviation range of the specific value determined by those of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10% or ±5% of the stated value. In addition, any numerical range described herein is intended to include all sub-ranges of the same numerical precision contained in the stated range. For example, the range of "1.0 to 10.0" is intended to include all sub-ranges between (and including) the stated minimum value of 1.0 and the stated maximum value of 10.0, that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0 (such as 2.4 to 7.6 as an example). Any maximum numerical limitation stated herein is intended to include all lower numerical limitations subsumed therein, and any minimum numerical limitation stated in this specification is intended to include all higher numerical limitations subsumed therein. Accordingly, applicants reserve the right to amend this specification, including the claims, to expressly recite any sub-ranges included within the ranges expressly recited herein.

[0251] The display device and / or any other related device or component according to the embodiment of the present invention described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuit), software, or a combination of software, firmware and hardware. For example, the various components of the device can be formed on an integrated circuit (IC) chip or on a separate IC chip. In addition, the various components of the device can be implemented on a flexible printed circuit film, a carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. In addition, the various components of the device can be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform various functions described herein. Computer program instructions are stored in a memory that can be implemented in a computing device using a standard memory device such as a random access memory (RAM). Computer program instructions can also be stored in other non-temporary computer-readable media (such as, for example, a compact disc read-only memory (CD-ROM) or a flash drive, etc.). In addition, it should be appreciated by those skilled in the art that, without departing from the scope of the embodiments of the present disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a specific computing device can be distributed on one or more other computing devices.

[0252] Although specific embodiments and application examples have been described, it should be noted that other embodiments and modifications can be derived from the disclosed content provided. Therefore, the technical scope of the present disclosure is not limited to the aforementioned embodiments, but is limited to the broader scope of the attached claims, one or more suitable obvious modifications and equivalent arrangements.

Claims

1. A display device, wherein: The display device comprises: a first sub-pixel; and a second sub-pixel positioned adjacent to the first sub-pixel, wherein each of the first sub-pixel and the second sub-pixel comprises: a first electrode; A pixel defining layer, located on the first electrode; a first emitting component, located on the pixel defining layer and configured to emit light; A first intermediate layer, located on the first emitting assembly; a second emitting component located on the first intermediate layer and configured to emit light; and A second electrode is located on the second emitting component, The groove is formed by recessing at least a portion of the pixel defining layer in a boundary region between the first sub-pixel and the second sub-pixel. wherein the first intermediate layer is interrupted above the groove, and Wherein, the second emission component completely covers the first intermediate layer above the groove.

2. The display device according to claim 1, wherein: The first intermediate layer includes a material having a charge conductivity higher than a charge conductivity of each of the first emission component and the second emission component, and the first intermediate layer has a conductive property.

3. The display device according to claim 2, wherein: The first intermediate layer and the second electrode are electrically insulated from each other.

4. The display device according to claim 2, in, The pixel defining layer includes a first surface, a second surface, and a third surface connecting the first surface to the second surface, the first surface and the second surface face each other, the groove is between the first surface and the second surface, and The first surface includes a first sidewall of the trench, the second surface includes a second sidewall of the trench, and the third surface includes a bottom surface of the trench.

5. The display device according to claim 4, wherein: Ends of the second emission component located on the first side wall and the second side wall are closer to the bottom surface than ends of the first intermediate layer, and the second emission component completely covers the first intermediate layer on the first side wall and the second side wall.

6. The display device according to claim 4, in, The first firing assembly is interrupted in the groove, and The second emission component of the first sub-pixel and the second emission component of the second sub-pixel are connected to each other.

7. The display device according to claim 4, wherein: Each of the first sub-pixel and the second sub-pixel further includes: a third emitting component positioned between the first electrode and the first emitting component, and the third emitting component is configured to emit light; and a second intermediate layer, positioned between the third emitting assembly and the first emitting assembly, wherein the second intermediate layer is interrupted above the groove, and Wherein, the first emission component completely covers the second intermediate layer above the groove.

8. The display device according to claim 7, in, The second intermediate layer includes a material having a charge conductivity higher than a charge conductivity of each of the first emission component, the second emission component, and the third emission component, and the second intermediate layer has an electrically conductive property, and The first intermediate layer, the second intermediate layer and the second electrode are electrically insulated from each other.

9. The display device according to claim 8, in, On the first side wall and the second side wall, an end of the second emission component is closer to the bottom surface than an end of the first intermediate layer, and an end of the first emission component is closer to the bottom surface than an end of the second intermediate layer, and Wherein, on the first side wall and the second side wall, the second emission component completely covers the first middle layer, and the first emission component completely covers the second middle layer.

10. The display device according to claim 8, in, The third firing assembly and the first firing assembly are interrupted in the groove, and The second emission component of the first sub-pixel and the second emission component of the second sub-pixel are connected to each other.

11. The display device according to claim 8, wherein: The trench includes a void surrounded by the first firing assembly, the second firing assembly, and the third firing assembly.

12. The display device according to claim 8, wherein: A distance between the first intermediate layer and the second electrode is greater than a distance between the first intermediate layer and the second intermediate layer.

13. The display device according to claim 7, in, The first emission component includes a first hole transport component, a first emission layer and a first electron transport component. Wherein, the second emission component comprises a second hole transport component, a second emission layer and a second electron transport component, and Wherein, the third emission component includes a third hole transport component, a third emission layer and a third electron transport component.

14. An apparatus for manufacturing a display device, wherein: The display device includes a first sub-pixel and a second sub-pixel, each of the first sub-pixel and the second sub-pixel includes a first electrode, a pixel defining layer sequentially positioned on the first electrode, a first emission component, a first intermediate layer, a second emission component, and a second electrode, and a groove formed by recessing at least a portion of the pixel defining layer in a boundary region between the first sub-pixel and the second sub-pixel, and The device comprises: a first deposition chamber configured to form the first intermediate layer on the pixel defining layer; and a second deposition chamber configured to form each of the first emission component and the second emission component on the pixel defining layer, The first deposition chamber includes a first nozzle assembly configured to spray the deposition material of the first intermediate layer, and a first angle limiting assembly connected to the first nozzle assembly and configured to limit the incident angle of the deposition material. wherein the second deposition chamber comprises a second nozzle assembly configured to eject deposition material of each of the first emission assembly and the second emission assembly, and a second angle limiting assembly connected to the second nozzle assembly and configured to limit an incident angle of the deposition material of each of the first emission assembly and the second emission assembly, and The deposition material of the first intermediate layer and the deposition material of each of the first emission component and the second emission component are incident on the pixel defining layer at different incident angles.

15. The device according to claim 14, wherein: The first intermediate layer includes a material having a charge conductivity higher than a charge conductivity of each of the first emission component and the second emission component, and the first intermediate layer has a conductive property.

16. The device according to claim 15, in, The first angle limiting component is configured to enable the deposition material of the first intermediate layer to be incident on the pixel defining layer at a low incident angle, and The second angle limiting component is configured to enable the deposition material of each of the first emitting component and the second emitting component to be incident on the pixel defining layer at a high incident angle.

17. The device according to claim 15, in, Each of the first subpixel and the second subpixel further includes a second intermediate layer positioned between the second emission component and the second electrode and having a conductive property, and a third emission component positioned between the second intermediate layer and the second electrode, and The first deposition chamber is configured to spray the deposition material of the second intermediate layer onto the second emission component, and the second deposition chamber is configured to spray the deposition material of the third emission component onto the second intermediate layer.

18. The apparatus according to claim 17, wherein: The deposition material of the second intermediate layer and the deposition material of the third emission component are incident at different incident angles.

19. A wearable electronic device, wherein: The wearable electronic device comprises: display panel; and a lens positioned on the display panel, The display panel includes a first sub-pixel and a second sub-pixel positioned adjacent to the first sub-pixel. Wherein, each of the first sub-pixel and the second sub-pixel comprises: a first electrode; A pixel defining layer, located on the first electrode; a first emitting component, located on the pixel defining layer and configured to emit light; A first intermediate layer, located on the first emitting assembly; a second emitting component located on the first intermediate layer and configured to emit light; and A second electrode is located on the second emitting component, The groove is formed by recessing at least a portion of the pixel defining layer in a boundary region between the first sub-pixel and the second sub-pixel. wherein the first intermediate layer is interrupted above the groove, and Wherein, the second emission component completely covers the first intermediate layer above the groove.

20. The wearable electronic device according to claim 19, wherein: Each of the first sub-pixel and the second sub-pixel further includes: a third emitting component positioned between the first electrode and the first emitting component, and the third emitting component is configured to emit light; and a second intermediate layer, positioned between the third emitting assembly and the first emitting assembly, wherein the third emission component and the second intermediate layer are interrupted above the groove, and Wherein, the first emission component completely covers the second intermediate layer above the groove.

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