Display substrate and display device

Abstract

A display substrate (1100) comprises an array substrate (100) and a color film substrate (200) which are oppositely arranged. The array substrate (100) comprises a first substrate (10), a plurality of first signal lines (11) and a plurality of signal line groups (14). The plurality of first signal lines (11) extend along a second direction (Y), the plurality of signal line groups (14) extend along a first direction (X), the plurality of first signal lines (11) and the plurality of signal line groups (14) intersect with each other, and an orthographic projection overlapping area of the signal line groups (14) and the first signal lines (11) on the first substrate (10) forms a convex structure (15) towards one side far away from the first substrate (10). A winding area (16) is arranged at the position where at least one signal line group (14) intersects with the first signal line (11). The color film substrate (200) comprises a second substrate (20) and a plurality of spacers (30), and the spacers (30) are strip-shaped and extend in the first direction (X). The orthographic projection of the spacer (30) on the array substrate (100) partially coincides with the first signal line (11) and the signal line group (14), and does not coincide with the protruding structure (15) in the winding area (16). The arrangement of the winding area (16) can adjust the contact area of the spacer (30) and the array substrate (100) to form a main spacer in the non-winding area (17) and an auxiliary spacer in the winding area (16), thereby simplifying the preparation difficulty of the spacer (30), reducing the preparation cost, and satisfying the use requirements of the display substrate (1100) for the spacer (30).

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, display devices (such as mobile phones, televisions, and computers) have been widely used. Common display devices include liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs). Due to the simpler pixel circuit structure of LCDs (which can include fewer thin-film transistors and capacitors), LCDs have advantages in display products with ultra-high pixel densities (e.g., greater than or equal to 1000 PPI).

[0003] In liquid crystal display devices, spacers are usually used to maintain the stability and uniformity of the liquid crystal box thickness. The design of the spacers also affects the yield of the alignment film and the light output rate of the liquid crystal display substrate. Optimizing the structure of the spacers to improve the performance of the display device is an important research direction of liquid crystal display devices.

[0004] Summary of the Invention

[0005] In one aspect, a display substrate is provided. The display substrate includes an array substrate and a color filter substrate disposed opposite each other. The array substrate includes a first substrate, a plurality of first signal lines disposed on one side of the first substrate, and a plurality of signal line groups. The plurality of first signal lines are spaced apart along a first direction and extend along a second direction. The plurality of signal line groups are spaced apart along the second direction and extend along the first direction. The first direction intersects the second direction. The plurality of first signal lines and the plurality of signal line groups intersect to form a grid structure. The areas where the orthographic projections of the signal line groups and the first signal lines on the first substrate overlap protrude away from the first substrate to form a protruding structure. The signal line groups include a winding area, with the winding area being provided at the location where at least one of the signal line groups intersects with the first signal line. The color filter substrate includes a second substrate and a plurality of spacers. The plurality of spacers are disposed on a side of the second substrate proximal to the array substrate. The spacers are strip-shaped and extend along the first direction. The orthographic projection of the spacer on the array substrate partially overlaps with the first signal line and partially overlaps with the signal line group, and the orthographic projection of the spacer on the array substrate in the winding area does not overlap with the protruding structure.

[0006] In some embodiments, a surface of the spacer away from the second substrate abuts against a portion of the protruding structure.

[0007] In some embodiments, the distance between the surface of the spacer away from the second substrate and the second substrate is equal.

[0008] In some embodiments, within the winding area, the signal line group protrudes along the first direction.

[0009] In some embodiments, the signal line group includes a second signal line, the orthographic projection of the second signal line on the second substrate partially overlaps with the spacer; the dimension of the spacer close to the surface of the array substrate along the second direction is D1, the width of the second signal line along the second direction is D2, and D1 is greater than D2.

[0010] In some embodiments, the signal line group includes a second signal line and a third signal line, and the orthographic projection of the spacer on the array substrate also covers the area between the second signal line and the third signal line; the orthographic projection of the spacer on the array substrate partially overlaps with the second signal line, and the orthographic projection of the spacer on the array substrate partially overlaps with the third signal line.

[0011] In some embodiments, the surface of the spacer near the array substrate has a dimension D1 in the second direction; the second signal line has a dimension D2 in the second direction; the third signal line has a dimension D3 in the second direction; and the interval between the second and third signal lines is D4. D1, D2, D3, and D4 satisfy the following: D2 > D3, D1 = D4 + D3; or D1, D2, D3, and D4 satisfy the following: D3 > D2, D1 = D4 + D2.

[0012] In some embodiments, the winding area is provided at a position where at least one of the second signal lines and / or at least one of the third signal lines crosses the first signal line.

[0013] In some embodiments, the array substrate further includes a first electrode, and the third signal line is connected to the first electrode on one side of the protrusion of the winding area along the first direction.

[0014] In some embodiments, a dimension of the spacer along the first direction is greater than a distance between two adjacent first signal lines.

[0015] In some embodiments, the plurality of spacers include at least one first spacer, wherein an orthographic projection of the first spacer on the array substrate overlaps with at least thirteen of the first signal lines and overlaps with one of the signal line groups. The winding area is provided at at least eleven of the intersections between the at least thirteen first signal lines and the one signal line group.

[0016] In some embodiments, a grid structure formed by a plurality of the first signal lines and a plurality of the signal line groups defines a plurality of pixel areas; and one first spacer is disposed in at least every twenty-four pixel areas.

[0017] In some embodiments, the multiple spacers include at least one second spacer, the orthographic projection of the second spacer on the array substrate has an overlapping area with the three first signal lines and an overlapping area with one signal line group; the second spacer respectively abuts the raised structure formed at the intersection of the three first signal lines and the one signal line group.

[0018] In some embodiments, the plurality of spacers include at least one third spacer, wherein an orthographic projection of the third spacer on the array substrate overlaps with one of the first signal lines and overlaps with one of the signal line groups. The third spacer abuts against the protruding structure formed at the intersection of the first signal line and the signal line group.

[0019] In some embodiments, the plurality of spacers include at least one fourth spacer, wherein an orthographic projection of the fourth spacer on the array substrate overlaps with three of the first signal lines and overlaps with one of the signal line groups. The winding area is provided at the intersection of two of the three first signal lines located on either side and the one signal line group; the fourth spacer abuts against the raised structure formed at the intersection of a middle first signal line among the three first signal lines and the one signal line group.

[0020] In some embodiments, the plurality of spacers include at least one fifth spacer, wherein an orthographic projection of the fifth spacer on the array substrate overlaps with three of the first signal lines and overlaps with one of the signal line groups. The winding area is provided at the intersection of the three first signal lines and the one signal line group; and the fifth spacer does not contact the raised structure formed at the intersection of the three first signal lines and the one signal line group.

[0021] In some embodiments, a grid structure formed by the plurality of first signal lines and the plurality of signal line groups defines a plurality of pixel regions. The array substrate includes a plurality of fourth spacers and a plurality of fifth spacers, with four fourth spacers and four fifth spacers disposed in at least every forty-eight pixel regions.

[0022] In some embodiments, a plurality of the fourth spacers and a plurality of the fifth spacers are arranged in rows along the first direction, and a row includes a plurality of the fourth spacers and a plurality of the fifth spacers arranged alternately; and / or, a plurality of the fourth spacers and a plurality of the fifth spacers are arranged in columns along the second direction, and a column includes the fourth spacers and the fifth spacers arranged alternately.

[0023] In some embodiments, the spacer includes a main spacer area and a first sub-spacer area. The main spacer area abuts against the protruding structure, and the density of the main spacer area's orthographic projection on the array substrate is 50 to 300 μm. 2 / mm 2 The first sub-spacer area has no contact with the protruding structure, and its orthographic projection on the array substrate coincides with the first signal line or the signal line group. The density of the orthographic projection of the sub-spacer area on the array substrate is 5000 to 20000 μm. 2 / mm 2 .

[0024] In some embodiments, the color filter substrate further includes a black matrix. The black matrix is ​​disposed between the second substrate and the spacer, and the orthographic projection of the black matrix on the array substrate covers the orthographic projection of the spacer on the array substrate, the first signal line, and the signal line group.

[0025] In some embodiments, the black matrix includes a first portion and a second portion. The orthographic projection of the first portion on the array substrate covers an end portion of the first signal line close to the signal line group. The second portion is located on a side of the first portion away from the signal line group and is connected to the first portion. The dimension of the first portion in the first direction is larger than the dimension of the second portion in the first direction.

[0026] In some embodiments, the thickness of the first signal line is 0.5 μm to 0.7 μm; and / or the thickness of the signal line group is 0.5 μm to 0.7 μm.

[0027] In some embodiments, the orthographic projection of the spacer on the array substrate partially overlaps with the signal line group or the first signal line; the spacer includes a main spacer area having a first thickness and a third sub-spacer area having a second thickness, and the first thickness is greater than the second thickness; the orthographic projection of the main spacer area on the array substrate has an overlapping area with the first signal line, and the orthographic projection of the main spacer area on the array substrate does not overlap with the signal line group.

[0028] In some embodiments, an orthographic projection of the main spacer area on the array substrate overlaps with at least two of the first signal lines.

[0029] In another aspect, a display device is provided. The display device includes a driving circuit board and a display panel according to any of the above embodiments. The driving circuit board is electrically connected to the display substrate and configured to transmit a control signal to the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0031] FIG1 is a structural diagram of a display device according to some embodiments;

[0032] FIG2 is a structural diagram of a display device according to some embodiments;

[0033] FIG3 is a structural diagram of an array substrate when the signal line group includes a second signal line and a third signal line according to some embodiments;

[0034] FIG4 is a cross-sectional structural diagram along the section line A1-A1 in FIG3;

[0035] FIG5 is a cross-sectional structural diagram along the section line A2-A2 in FIG3;

[0036] FIG6 is an equivalent circuit diagram of an array substrate according to some embodiments;

[0037] FIG7 is a structural diagram of an array substrate when the signal line group includes a second signal line according to some embodiments;

[0038] FIG8 is a cross-sectional structural diagram along the section line A3-A3 in FIG7;

[0039] FIG9 is another equivalent circuit diagram of an array substrate according to some embodiments;

[0040] FIG10 is a structural diagram showing a display substrate including a second spacer according to some embodiments;

[0041] FIG11 is a cross-sectional structural diagram along the section line A4-A4 in FIG10;

[0042] FIG12 is a structural diagram showing a display substrate including a third spacer according to some embodiments;

[0043] FIG13 is a cross-sectional structural diagram along the section line A5-A5 in FIG12;

[0044] FIG14 is a structural diagram showing a display substrate including a fourth spacer according to some embodiments;

[0045] FIG15 is a cross-sectional structural diagram along the section line A6-A6 in FIG14;

[0046] FIG16 is a structural diagram showing a display substrate including a fifth spacer according to some embodiments;

[0047] FIG17 is a cross-sectional structural diagram along the section line A7-A7 in FIG16;

[0048] FIG18 is a diagram illustrating an arrangement structure of a fourth spacer and a fifth spacer according to some embodiments;

[0049] FIG19 is a structural diagram showing a substrate when a spacer is displaced according to some embodiments;

[0050] FIG20 is a graph showing the thickness of a liquid crystal cell after being subjected to an external force when the spacer is not displaced according to some embodiments;

[0051] FIG21 is a diagram showing the thickness of a liquid crystal cell after a spacer is displaced and subjected to an external force according to some embodiments;

[0052] FIG22 is a graph showing deformation data of a spacer after the spacer is displaced and subjected to external force according to some embodiments;

[0053] FIG23 is a structural diagram of a spacer and an array substrate according to some embodiments;

[0054] FIG24 is a cross-sectional structural diagram along the section line A8-A8 in FIG23;

[0055] FIG25 is a structural diagram of a black matrix and an array substrate according to some embodiments;

[0056] FIG26 is a structural diagram showing a projection relationship between a black matrix and a first signal line according to some embodiments;

[0057] FIG27 is a schematic plan view of an array substrate in a display substrate according to some embodiments;

[0058] FIG28 is a cross-sectional structural diagram along the section line B1-B1 in FIG27;

[0059] FIG29 is a cross-sectional structural diagram along the section line B2-B2 in FIG27;

[0060] FIG30 is another schematic plan view of an array substrate according to some embodiments;

[0061] FIG31 is another schematic plan view of an array substrate according to some embodiments;

[0062] FIG32 is another schematic plan view of an array substrate according to some embodiments;

[0063] FIG33 is another schematic plan view of an array substrate according to some embodiments;

[0064] FIG34 is a cross-sectional structural diagram along the section line B3-B3 in FIG27;

[0065] FIG35A is a schematic cross-sectional view of an array substrate after a spacer material layer is deposited; ...

[0066] FIG35B is a schematic cross-sectional view of an array substrate after a photoresist pattern is formed; ...

[0067] FIG35C is a schematic cross-sectional view of the array substrate after the first spacer is formed; ...

[0068] FIG36 is a schematic plan view of an array substrate in a display substrate according to some embodiments;

[0069] FIG37 is a schematic cross-sectional view of a display substrate in the related art;

[0070] FIG38 is a schematic diagram showing a size comparison of the opaque pattern in the array substrate in the related art and the present disclosure. DETAILED DESCRIPTION

[0071] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0072] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least some embodiments or examples of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0073] In this disclosure, terms such as "lower," "below," "above," and "upper," and similar terms are used to explain the relationships between components shown in the drawings. These terms may be relative and described based on directions shown in the drawings, or based on the order in which process steps are formed, but are not limited thereto.

[0074] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0075] The term "opposite" means that the first element may be directly or indirectly opposite to the second element. In the case where a third element is interposed between the first and second elements, the first and second elements may be understood to be indirectly opposite to each other although they are still opposite to each other.

[0076] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0077] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0078] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0079] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0080] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0081] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0082] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0083] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0084] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0085] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0086] 1 , an embodiment of the present disclosure provides a display device, wherein display device 1000 is a product having an image display function. For example, display device 1000 may be any device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images.

[0087] Exemplarily, the display device 1000 can be a television, a laptop computer, a tablet computer, a personal digital assistant (PDA), a mobile phone (cell phone), a watch, a clock, a calculator, a GPS receiver / navigator, a camera, a camera view display (for example, a display of a rearview camera in a vehicle), a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a mixed reality (MR) device, an in-vehicle display, an aircraft display, or any other product or component with a display function.

[0088] In some embodiments, the display device 1000 may be a liquid crystal display (LCD) device, based on its light-emitting type. The display device 1000 may be a flat display device or a curved display device, for example. The display device 1000 may be rectangular or circular, for example. Some embodiments of the present disclosure are described below using a rectangular, flat liquid crystal display device as an example. However, the present disclosure is not limited thereto, and any other display device may also be considered, as long as the same technical concept is applied.

[0089] In some embodiments, referring to FIG2 , the display device 1000 includes a display substrate 1100 (also referred to as a display panel) and a driver circuit board (not shown in the figure). The driver circuit board may include, for example, a timing controller (TCON), a power management chip (DC / DC), and an adjustable resistor divider circuit (generating Vcom) and other driving circuits. The driver circuit board may also include other circuit structures, which are not listed here one by one. The driver circuit board is electrically connected to the display substrate 1100 and is used to transmit a control signal to the display substrate 1100, thereby driving the display substrate 1100 to realize image display. In addition, the display device 1000 may also include a touch structure, an under-screen camera, and an under-screen fingerprint recognition sensor, so that the display device 1000 can realize a variety of different functions such as touch, photo taking, video recording, or fingerprint recognition, which are not listed here one by one.

[0090] Continuing with FIG2 , if the display device 1000 is a liquid crystal display device, the display device 1000 may further include a backlight source 1200 disposed on the backlight side of the display substrate 1100. For example, the backlight source 1200 may be a direct-lit backlight source or an edge-lit backlight source, and is configured to provide light for the display substrate 1100. The display substrate 1100 includes a plurality of sub-pixels, each of which may adjust the amount of light passing through the display substrate 1100 within the sub-pixel, thereby enabling each sub-pixel to display the same or different grayscales, thereby achieving image display.

[0091] Continuing to refer to FIG2 , in the case where the display substrate 1100 is a liquid crystal display substrate, the display substrate 1100 may include an array substrate 100 and a color filter substrate 200 that are arranged opposite to each other, and a liquid crystal layer 300 disposed between the array substrate 100 and the color filter substrate 200, wherein the color filter substrate 200 may also be referred to as an opposing substrate or a packaging substrate. Of course, the structure of the display substrate 1100 is not limited to this, and the display substrate 1100 may also include other structures as long as the same technical concept is adopted. For example, the display substrate 1100 may also include a first alignment film (not shown in the figure) disposed on the side of the array substrate 100 close to the liquid crystal layer 300, and a second alignment film (not shown in the figure) disposed on the side of the color filter substrate 200 close to the liquid crystal layer 300, etc.

[0092] The array substrate 100 may include, for example, a plurality of pixel circuits arranged in an array. The pixel circuit may include at least one thin film transistor (TFT) and at least one capacitor. For example, the pixel circuit may be a "1T1C" circuit, a "2T1C" circuit, or a "3T1C" circuit. "T" refers to a thin film transistor, and the number before "T" refers to the number of thin film transistors; "C" refers to a capacitor, and the number before "C" refers to the number of capacitors. Of course, the structure of the pixel circuit in the embodiments of the present disclosure is not limited to this, as long as the same technical concept is adopted. For example, the array substrate 100 also includes a first electrode and a second electrode, and the above-mentioned capacitor is formed between the first electrode and the second electrode. During operation of the display substrate, an electric field may be formed between the first electrode and the second electrode, and the electric field is used to drive the deflection direction of the liquid crystal molecules in the sub-pixel area, thereby adjusting the grayscale displayed by the sub-pixel. The first electrode may be, for example, a common electrode, and the second electrode may be, for example, a pixel electrode.

[0093] Exemplarily, the array substrate 100 may be an Advanced Super Dimension Switch (ADS) type or a High-Advanced Dimension Switch (HADS) type with a high aperture ratio. ADS technology uses the electric field generated by the edge of a slit electrode (one of the second electrode and the first electrode) in the same plane and the electric field generated between the slit electrode and the plate electrode (the other of the second electrode and the first electrode) to form a multi-dimensional electric field. This allows all aligned liquid crystal molecules between the slit electrodes and directly above the electrodes in the liquid crystal cell to rotate, thereby improving the operating efficiency of the liquid crystal and increasing light transmission efficiency. The technology also offers advantages such as high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low color difference, and no push mura.

[0094] The color filter substrate 200 may include, for example, a black matrix (not shown) and a filter portion. The black matrix includes a plurality of openings, each of which corresponds to a sub-pixel and is configured to form a light-emitting region for each sub-pixel. The filter portion is configured to filter light incident on the color filter substrate 200 so that each sub-pixel emits light of a single color. Different sub-pixels can emit light of the same or different colors, thereby enabling the display substrate 1100 to achieve color display. For example, the filter portion may include a red filter portion, a green filter portion, and a blue filter portion. In this way, different sub-pixels can emit red, green, and blue light, respectively, so that the display substrate achieves color display.

[0095] The display substrate 1100 further includes a plurality of spacers, which are disposed between the array substrate 100 and the color filter substrate 200 and within the liquid crystal layer 300. The spacers are supported on the array substrate 100 at one end (lower surface) near the array substrate, and supported on the color filter substrate 200 at one end (upper surface) near the color filter substrate 200. The spacers are configured to support the array substrate 100 and the color filter substrate 200 to maintain the thickness of the liquid crystal layer 300 between the array substrate 100 and the color filter substrate 200. For example, the spacers can be formed on the color filter substrate 200.

[0096] A display substrate provided in the related art has a spacer having a cylindrical or polygonal structure, that is, the spacer has a circular or polygonal cross-section parallel to the array substrate. Under normal circumstances (when the display substrate is not under pressure), the orthographic projection of the spacer on the array substrate at least partially overlaps with the signal line of the array substrate. Under the action of external force, the display substrate may cause the spacer to slide and deviate from its original position. During the sliding process, the spacer may scratch the first alignment film on the array substrate, thereby causing light leakage in the scratched area of ​​the first alignment film of the display substrate. In order to avoid the above-mentioned light leakage problem, a larger black matrix pattern is generally designed, that is, the distance between the boundary of the orthographic projection of the black matrix on the array substrate and the boundary of the orthographic projection of the spacer on the array substrate is larger. In this way, the black matrix can block the scratched area of ​​the first alignment film and reduce the risk of light leakage from the display substrate. However, the arrangement of the above-mentioned spacers and black matrix will result in a larger area of ​​the black matrix, affecting (reducing) the aperture ratio of the display substrate, which is not conducive to improving the luminous efficiency of the display substrate. In addition, the spacers usually include main spacers and auxiliary spacers. The height (dimensions along the direction perpendicular to the array substrate) between the main spacers and the auxiliary spacers has a certain difference. When the display substrate is not under pressure, the main spacers support the liquid crystal box. When subjected to external force, the main spacers deform. When the deformation of the main spacers is greater than or equal to the height difference between the main spacers and the auxiliary spacers, the auxiliary spacers begin to support the liquid crystal box to prevent the main spacers from deforming too much and being difficult to recover, resulting in the appearance of pressure spots (mura). The main spacers and auxiliary spacers of unequal heights are usually made of the same material and formed by a half-tone mask. The preparation of the main spacers and auxiliary spacers is difficult and costly.

[0097] 3, 4, and 5, to address at least one of the aforementioned technical issues, some embodiments of the present disclosure provide a display substrate 1100 comprising an array substrate 100 and a color filter substrate 200. The array substrate 100 comprises a first substrate 10, a plurality of first signal lines 11 disposed on one side of the first substrate 10, and a plurality of signal line groups 14. The color filter substrate 200 comprises a second substrate 20 and a plurality of spacers 30.

[0098] Among them, the first substrate 10 and / or the second substrate 20 can be a rigid substrate. Exemplarily, the rigid substrate can be, for example, a glass substrate or a polymethyl methacrylate (PMMA) substrate. The first substrate 10 and / or the second substrate 20 can also be a flexible substrate. Exemplarily, the flexible substrate can be, for example, a polyethylene terephthalate (PET) substrate, a polyimide (PI) substrate, or a polyethylene naphthalate diformic acid glycol ester (PEN) substrate. It is understandable that the types of the first substrate 10 and the second substrate 20 include multiple types, and the types of the first substrate 10 and the second substrate 20 can be the same or different. The first substrate 10 and the second substrate 20 can be selected and set according to actual needs, and the embodiments of the present disclosure will not list them one by one.

[0099] The plurality of first signal lines 11 are spaced apart along a first direction X and extend along a second direction Y. The plurality of signal line groups 14 are spaced apart along the second direction Y and extend along the first direction X. The plurality of first signal lines 11 and the plurality of signal line groups 14 intersect with each other to form a grid structure, wherein each grid of the grid structure defines a pixel area 101. The first direction X intersects the second direction Y. Exemplarily, the first direction X and the second direction Y are perpendicular to each other.

[0100] It should be noted that the first signal line 11 and the signal line group 14 are arranged in different layers, and at least one insulating layer is included between the film layer where the first signal line 11 is located and the film layer where the signal line group 14 is located to separate the first signal line 11 from the signal line group 14 and prevent a short circuit between the first signal line 11 and the signal line group 14. Exemplarily, the first signal line 11 can be arranged on the side of the signal line group 14 close to the first substrate 10 (as shown in FIG4 ), or the first signal line 11 can be arranged on the side of the signal line group 14 away from the first substrate 10 (as shown in FIG7 and FIG8 ). In addition, the array substrate 100 may further include one or more full-surface film layers, the thickness of the full-surface film layer on the array substrate is roughly uniform, and does not affect the surface morphology of the array substrate 100. Therefore, the full-surface film layer is not shown in the drawings provided in the embodiments of the present disclosure. Exemplarily, the array substrate may include a semiconductor layer, a first conductive layer (such as a film layer where the first signal line / signal line group is located), a second conductive layer (such as a film layer where the signal line group / first signal line is located), a first electrode layer, a second electrode layer, and at least one insulating layer arranged between adjacent conductive layers, and the insulating layer may be the above-mentioned full-surface film layer.

[0101] In an embodiment of the present application, the array substrate 100 is not filled with a flat layer (PLN) at least on the side where the first signal line 11 and the signal line group 14 are away from the first substrate 10, that is, the first signal line 11 and the signal line group 14 do not include a flat layer on the side away from the first substrate 10. Based on this, a height difference formed by the first signal line 11 and the signal line group 14 can be formed on the surface of the array substrate 100 close to the color film substrate 200.

[0102] In some embodiments, the pixel area 101 may include a red pixel area, a green pixel area, or a blue pixel area. Each pixel area 101 may correspond to a filter portion in the color filter substrate, and each type of pixel area corresponds to each type of filter portion. The orthographic projection of the filter portion on the array substrate is located within the range of the pixel area 101, and the boundary of the filter portion's projection may be a certain distance from the boundary of the pixel area.

[0103] In some embodiments, referring to Figures 3 and 6, each pixel region 101 is controlled by one of the first signal lines 11 and a signal line group 14 that surround the pixel region 101. For example, under the control of the second signal line 12 of the signal line group 14, the first signal line 11 transmits a data signal to the second electrode of the pixel region 101, thereby charging the liquid crystal capacitor Clc and the storage capacitor Cst. An electric field is generated between the second electrode and the first electrode to drive the liquid crystal molecules in the liquid crystal layer to deflect. The deflection angle of the liquid crystal molecules can control the polarization direction of light passing through the pixel region 101 and, in conjunction with the polarizer, achieve different grayscale displays.

[0104] For example, referring to FIG6 , the plurality of first signal lines 11 may be data signal lines. In this case, one first signal line 11 is electrically connected to a column of pixel circuits, and the first signal line 11 is configured to transmit a data signal to the column of pixel circuits. The signal line group 14 includes at least a second signal line 12. For example, the second signal line 12 may be a scan signal line. In this case, one second signal line 12 is electrically connected to a row of pixel circuits. The second signal line 12 is configured to transmit a gate signal to the pixel circuit to control the first signal line 11 from transmitting the data signal to the pixel circuit. For example, the pixel circuit may include a first transistor T1 and a storage capacitor Cst. The storage capacitor Cst may be formed by a first electrode 21 and a second electrode. The first electrode 21 may be a common electrode, and the second electrode 22 may be a pixel electrode. In this case, the gate of the first transistor T1 may be electrically connected to the second signal line 12, one of the source and drain may be electrically connected to the first signal line 11, and the other may be electrically connected to one electrode of the storage capacitor formed by the second electrode 22. The second signal line 12 is used to control the on or off state of the first transistor T1 , thereby controlling the first signal line 11 to write a data signal into the storage capacitor Cst.

[0105] Referring to Figures 3, 4, and 5, the area where the orthographic projections of the signal line group 14 and the first signal line 11 on the first substrate 10 overlap protrudes toward the side away from the first substrate 10 to form a raised structure 15. The raised structure 15 is a structure on the surface of the array substrate 100 near the color filter substrate 200 that protrudes toward the side away from the first substrate 10 compared to its adjacent area. The raised structure 15 may include, but is not limited to, a columnar, conical, or rectangular parallelepiped shape.

[0106] The signal line group 14 includes a winding area 16, and a winding area 16 is provided at the location where at least one signal line group 14 intersects with the first signal line 11. The extension direction of the signal line group 14 within the winding area 16 is different from that of the other portions; in other words, the signal line group 14 deviates from its extension direction (first direction X) within the winding area 16. Based on this, the raised structure 15 (second raised structure 152) formed in the above-mentioned winding area 16 is staggered in the second direction Y from the raised structure 15 (first raised structure 151) formed in the location where no winding area is provided (which can also be referred to as the non-winding area 17). In this way, among the multiple raised structures 15 formed between the same signal line group 14 and multiple first signal lines 11, the first raised structure 151 and the second raised structure 152 are not on a straight line parallel to the first direction X.

[0107] Referring to Figures 3, 4, and 5, multiple spacers 30 of the color filter substrate 200 are disposed on a side of the second substrate 20 near the array substrate 100. The spacers 30 are strip-shaped and extend along a first direction X. The orthographic projection of the spacers 30 on the array substrate 100 partially overlaps with the first signal line 11 and partially overlaps with the signal line group 14. Because the spacers 30 extend along the first direction X, the orthographic projection of the spacers 30 on the array substrate 100 can partially overlap with at least one protruding structure 15 (first protruding structure 151) that is not located in the winding area 16 (non-winding area 17). In addition, the orthographic projection of the spacers 30 in the winding area 16 on the array substrate 100 does not overlap with the protruding structure 15 (second protruding structure 152).

[0108] Exemplarily, the spacer 30 is in contact with the raised structure 15 (first raised structure 151) that is not located in the winding area 16. And the spacer 30 is not in contact with the raised structure 15 (second raised structure 152) in the winding area 16. In the present application, the thickness of the signal line group 14 and the first signal line 11 itself is combined with the long strip spacer 30 to form different spacers in the winding area 16 and the non-winding area 17, that is, a main spacer is formed in the non-winding area 17, and a secondary spacer is formed in the winding area 16, which is conducive to simplifying the preparation difficulty of the spacer 30 and reducing the preparation cost of the spacer 30. In addition, the setting of the winding area 16 can adjust the contact area between the spacer 30 and the array substrate 100, which is conducive to improving the ratio of the main spacer (main spacer area) and the secondary spacer (secondary spacer area) formed by the spacer 30 to meet the display substrate's use requirements for the spacer 30.

[0109] In some embodiments, the thickness of the first signal line 11 (the dimension perpendicular to the direction of the first substrate 10) is 0.5μm to 0.7μm; this is conducive to increasing the height difference (step difference) formed between the first signal line 11 and the first substrate 10, and thus is conducive to forming a raised structure 15 on the surface of the array substrate 100 away from the first substrate 10. Exemplarily, the thickness of the first signal line 11 is 0.5μm, 0.55μm, 0.6μm or 0.7μm, etc., which are not listed one by one in the embodiments of the present disclosure. In some embodiments, the thickness of the signal line group 14 is 0.5μm to 0.7μm, which is conducive to increasing the height difference between the area where the signal line group 14 is located and the first substrate 10, and thus is conducive to forming a raised structure (first sub-spacer area) formed by the signal line group 14 on the surface of the array substrate 100 away from the first substrate 10. Exemplarily, the thickness of the signal line group 14 is 0.5 μm, 0.55 μm, 0.6 μm or 0.7 μm, etc., which will not be listed one by one in the embodiments of the present disclosure.

[0110] Exemplarily, the material of the first signal line 11 may include a conductive material, which may include a metal material, such as one or more of titanium, aluminum, copper, molybdenum, niobium, nickel and alloys thereof, or the first signal line 11 may also be a metal stacked structure. Exemplarily, the first signal line 11 may include one of a titanium-aluminum-titanium (Ti / Al / Ti) laminated structure, a molybdenum-aluminum (Mo / Al) laminated structure, a molybdenum-aluminum-molybdenum (Mo / Al / Mo) laminated structure, a molybdenum-niobium-titanium (MoNb / Ti) laminated structure, a molybdenum-niobium-titanium-copper (MoNb / Ti / Cu) laminated structure, a molybdenum-niobium-copper (MoNb / Cu) laminated structure, a molybdenum-nickel-titanium-copper (MTD / Cu) laminated structure, a molybdenum-niobium-copper-molybdenum-titanium-nickel (MoNb / Cu / MTD) laminated structure, a molybdenum-nickel-titanium-copper-molybdenum-nickel-titanium (MTD / Cu / MTD) laminated structure, a molybdenum-neodymium-copper laminated structure, a MoNb-copper-MoNb laminated structure, and an AlNb-molybdenum-AlNd laminated structure, or a combination thereof. Exemplarily, the material of the signal line group 14 may include a conductive material. The conductive material is described above and will not be described in detail here. In addition, the material and structure of the signal line group 14 can be the same as or different from those of the first signal line 11 , and can be set according to actual needs.

[0111] In some embodiments, referring again to Figures 3, 4, and 5, the spacer 30 abuts against a portion of the raised structure 15 away from the surface 301 of the color filter substrate 200, and the portion of the spacer 30 abutting against the raised structure 15 away from the surface 301 of the color filter substrate 200 forms a main spacer region 302. Furthermore, the orthographic projection of the spacer 30 on the array substrate 100 overlaps with the first signal line 11 or the signal line group 14, but does not overlap with the raised structure 15, forming a first sub-spacer region 303. The orthographic projection of the spacer 30 on the array substrate 100 overlaps with the region between the second signal line 12 and the third signal line 13 in the signal line group 14, forming a second sub-spacer region 304.

[0112] One end of the raised structure 15 (first raised structure 151) near the color filter substrate 200 abuts against the main spacer region 302 of the spacer 30. The area of ​​the first signal line 11 or signal line group 14 that is not the raised structure 15 and is near the color filter substrate 200 is a distance f from the spacer 30. The area between the second signal line 12 and the third signal line 13 in the signal line group 14 is a distance g from the spacer 30. In some embodiments, g>f>0. Thus, the spacer 30 cooperates with the first signal line 11 and the signal line group 14 to form a main spacer region (main spacer) 302, a first sub-spacer region (first sub-spacer) 303, and a second sub-spacer region (second sub-spacer) 304 with step differences. In other words, the spacer 30 can form different spacer regions by forming a height difference on the surface of the array substrate 100 near the color filter substrate 200.

[0113] When the display substrate 1100 is in a normal state (without pressure), the main spacer region 302 of the spacer 30 provides support for the liquid crystal cell thickness. When the display substrate 1100 is pressed, the color filter substrate 200 is squeezed toward the side closer to the array substrate 100, causing the spacer 30 to deform. The first sub-spacer region 303 of the spacer 30 begins to support the liquid crystal cell thickness. Specifically, the spacer 30 contacts the upper surface of the array substrate 100 where the second signal line 12 and the third signal line 13 are located (the surface close to the color filter substrate). As the compressive force on the display substrate 1100 increases, the degree of compression of the color filter substrate 200 against the array substrate 100 increases, further increasing the deformation of the spacer 30. At this point, the second sub-spacer region 304 also begins to support the liquid crystal cell thickness. Specifically, the spacer 30 also contacts the upper surface of the array substrate 100 between the second signal line 12 and the third signal line 13.

[0114] In some embodiments, as shown in FIG4 , the spacers 30 are located at equal distances from the color filter substrate 200 (the second substrate 200) and the surface 301 thereof, which is distal to the color filter substrate 200. Thus, by arranging the undulating structure on the surface of the array substrate 100 near the color filter substrate 200 and aligning the position of the spacers 30, the spacers 30 can function as both a primary spacer (primary spacer region 302) and a secondary spacer (first secondary spacer region 303 or second secondary spacer region 304). This eliminates the need for a halftone mask to form spacers 30 having varying thicknesses. For example, the spacers 30 can be formed through a coating and patterning process, wherein a conventional mask (compared to a halftone mask) can be used to pattern the spacers 30. This significantly reduces the difficulty and cost of preparing the spacers 30, thereby reducing the cost of the display substrate.

[0115] In some embodiments, referring to FIG3 , the signal line group 14 may include a second signal line 12 and a third signal line. When the signal line group 14 includes the second signal line 12 and the third signal line 13, the second signal line 12 and the third signal line 13 extend along the length direction of the signal line group 14, i.e., the first direction X, in the non-winding area 17. The second signal line 12 bends a distance away from the third signal line 13 in the winding area 16, then extends along the length direction of the signal line group 14, bypasses the first signal line 11, and then bends and extends toward the third signal line 13 to a position collinear with the second signal line 12 in the non-winding area 17. The second signal line 12 then continues to extend along the length direction of the signal line group 14. That is, the second signal line 12 protrudes along the second direction Y in the winding area 16 to avoid the spacer 30. Within the winding area 16, the third signal line 13 bends a distance away from the second signal line 12, then extends along the length of the signal line group 14. After bypassing the raised structure 15, it bends and extends toward the second signal line 12 to a position collinear with the third signal line 13 in the non-winding area 17. It then continues to extend along the length of the signal line group 14. In other words, within the winding area 16, the third signal line 13 protrudes along the second direction Y to avoid the spacer 30. In this way, the original main spacer area 302 within the winding area 16 is transformed into the first sub-spacer area 303. In other words, the winding area 16 can reduce the main spacer area 302 and increase the first sub-spacer area 303.

[0116] For example, the distance that the second signal line 12 bends away from the third signal line 13 within the winding area 16 is h, the maximum alignment deviation between the array substrate 100 and the color filter substrate 200 in the second direction Y is e, and h is greater than or equal to e. The structure in the winding area 16 where the second signal line 12 and the third signal line 13 sandwich the spacer 30 effectively prevents displacement of the spacer 30 in the second direction Y.

[0117] In some embodiments, referring to Figures 3 and 6 , the signal line group 14 includes a second signal line 12 and a third signal line 13. The structure and function of the second signal line 12 are described above and are not further described here. The third signal line 13 is configured to be connected to the first electrode. The third signal line 13 is also configured to provide a stable voltage to one end of the liquid crystal capacitor Clc and the storage capacitor Cst, thereby maintaining a stable voltage difference between the liquid crystal capacitor Clc and the storage capacitor Cst, thereby maintaining a directional deflection angle of the liquid crystal molecules.

[0118] In some embodiments, a connection via is provided near the intersection of the third signal line 13 and the first signal line 11, and the third signal line 13 is connected to the first electrode through the connection via. The connection via is provided near the intersection of the third signal line 13 and the first signal line 11. When light leakage occurs due to the connection via, the black matrix 21 can block the light leaking from the connection via, thereby reducing the adverse effect of the connection via on the display effect of the display substrate 1100.

[0119] 3 and 6 , a signal line group 14 includes a second signal line 12 and a third signal line 13. The second signal line 12 controls the connection between the plurality of first signal lines 11 and the second electrodes of a row of pixel regions 101 via a row of thin-film transistors. The third signal line 13 provides a stable voltage to one end of the liquid crystal capacitor Clc and the storage capacitor Cst of an adjacent row of pixel regions 101.

[0120] In some embodiments, referring to FIG. 3 , the orthographic projection of the spacer 30 on the array substrate 100 covers the area between the second signal line 12 and the third signal line 13 in the signal line group 14. Furthermore, the orthographic projection of the spacer 30 on the array substrate 100 partially overlaps with the second signal line 12, and the orthographic projection of the spacer 30 on the array substrate 100 partially overlaps with the third signal line 13. That is, within the length of the spacer 30, the orthographic projection on the array substrate 100 simultaneously covers a portion of the second signal line 12, a portion of the third signal line 13, and the area between the second signal line 12 and the third signal line 13.

[0121] In some embodiments, referring to Figures 3 and 5 , the dimension of the spacer 30 near the surface 301 of the array substrate 100 in the second direction Y is D1, the dimension of the second signal line 12 in the second direction Y is D2, the dimension of the third signal line 13 in the second direction Y is D3, and the spacing between the second signal line 12 and the third signal line 13 is D4. If the dimension D3 of the third signal line 13 in the second direction Y is greater than the dimension D2 of the second signal line 12 in the second direction Y (D3>D2), D1 = D4+D2. Alternatively, if the dimension D2 of the second signal line 12 in the second direction Y is greater than the dimension D3 of the third signal line 13 in the second direction Y (D2>D3), D1 = D4+D3. In other words, the dimension D1 of the spacer 30 near the surface 301 of the array substrate 100 in the second direction Y is equal to the sum of the spacing D4 between the second signal line 12 and the third signal line 13 and the smaller dimension of the second signal line 12 or the third signal line 13 in the second direction Y. In this way, even if there is a certain alignment deviation between the spacer 30 and the array substrate 100, when the spacer at least partially covers the area between the second signal line 12 and the third signal line 13, the total contact area between the spacer 30 and the second signal line 12 and the third signal line 13 remains unchanged. In this way, it can be ensured that the spacer 30 provides stable support for the liquid crystal layer 300, thereby ensuring that the liquid crystal layer 300 can maintain a stable thickness, thereby ensuring the display effect of the display substrate.

[0122] In some embodiments, as shown in FIG3 , the signal line group 14 is provided with a plurality of winding areas 16 along its length direction (first direction X). A winding area 16 is provided at a position where at least one signal line group 14 intersects with the first signal line 11. That is, a winding area 16 is provided at a position where at least one second signal line 12 and / or at least one third signal line 13 intersects with the first signal line 11. The orthographic projection of the spacer 30 in the winding area 16 on the array substrate 100 has no overlapping area with the protruding structure 15 (second protruding structure 15). The winding area 16 is conducive to reducing the number of the first protruding structures 151 and increasing the number of the second protruding structures 152. By adjusting the number and density of the winding areas 16, the contact density between the spacer 30 and the protruding structure 15 can be changed, that is, the density of the orthographic projection of the main spacer area 302 and the first sub-spacer area 303 on the array substrate 100 is adjusted.

[0123] In some embodiments, referring to Figures 7, 8, and 9, the signal line group 14 includes a second signal line 12, or one second signal line 12 constitutes one signal line group 14, and the signal line group 14 does not include the third signal line 13. In this case, the second signal line 12 controls the connection between the first signal line 11 and the liquid crystal capacitor Clc and the storage capacitor Cst (second electrode), that is, the second signal line 12 controls whether the first signal line 11 charges the liquid crystal capacitor Clc and the storage capacitor Cst. In this case, the liquid crystal capacitor Clc and the storage capacitor Cst can also be connected to the common voltage signal terminal COM, which is used to provide a continuous and stable voltage signal. Exemplarily, one signal line group 14 includes one second signal line 12. The second signal line 12 controls the connection and disconnection between multiple first signal lines 11 and the second electrodes of a row of pixel areas 101. Multiple first electrodes (common electrodes) of multiple sub-pixels can be interconnected to form a whole and form the above-mentioned common voltage signal terminal COM. The common voltage signal terminal COM can be electrically connected to the signal line (such as the common voltage signal line) in the peripheral area.

[0124] The orthographic projection of the spacer 30 on the array substrate 100 covers the second signal line 12 in the signal line group 14. That is, the orthographic projection of the spacer 30 on the array substrate 100 covers the second signal line 12 within the length range of the spacer 30.

[0125] For example, the width of the surface 301 of the spacer 30 proximate the array substrate 100 in the second direction Y can be D1, and the width of the second signal line 12 in the second direction Y can be D2, where D1 is greater than D2. The alignment deviation between the array substrate 100 and the color filter substrate 200 is e. That is, during the assembly process of the array substrate 100 and the color filter substrate 200, the maximum alignment deviation between the array substrate 100 and the color filter substrate 200 in the second direction Y is e. In some embodiments, D1 is greater than or equal to D2 + 2e. That is, the orthographic projection of the spacer 30 on the array substrate 100 covers the second signal line 12 in the signal line group 14, and the distance between the two sides of the orthographic projection of the spacer 30 on the array substrate 100 is greater than or equal to e. In this way, when a slight deviation occurs during the assembly process of the array substrate 100 and the color filter substrate 200, the width of the portion where the orthographic projection of the spacer 30 on the array substrate 100 overlaps with the second signal line 12 remains D2. In this way, it can be ensured that the spacers 30 can provide stable support for the liquid crystal layer, thereby ensuring that the liquid crystal layer can maintain a stable thickness, thereby ensuring the display effect of the display substrate.

[0126] In some embodiments, referring to Figures 7 and 8 , the side of the spacer 30 facing away from the second substrate 20 is equidistant from the color filter substrate 200. The overlapping region of the first signal line 11 and the signal line group 14 forms a plurality of raised structures 15 protruding toward the color filter substrate 200. The side of the spacer 30 facing away from the second substrate 20 abuts against some of these raised structures 15. Thus, the spacer 30 forms distinct spacer regions within itself, cooperating with the first signal line 11 and the signal line group 14.

[0127] Illustratively, the portion of the spacer 30 on the side away from the second substrate 20 that abuts against a portion of the raised structure 15 forms a main spacer region 302. The portion of the spacer 30's orthographic projection on the array substrate 100 that overlaps with the first signal line 11 or signal line group 14 but does not overlap with the raised structure 15 forms a first sub-spacer region 303. The portion of the spacer 30's orthographic projection on the array substrate 100 that overlaps with the area of ​​the array substrate 100 other than the second signal line 12 forms a second sub-spacer region 304.

[0128] The side of the raised structure 15 closest to the color filter substrate 200 abuts against the spacer 30. The area of ​​the first signal line 11 or signal line group 14 not adjacent to the raised structure 15 and close to the color filter substrate 200 is a distance f from the spacer 30. The distance between the portion of the array substrate 100 not adjacent to the second signal line 12 and the spacer 30 is g. With g > f > 0, the spacer 30, the first signal line 11, and the signal line group 14 form a stepped main spacer region 302, a first sub-spacer region 303, and a second sub-spacer region 304.

[0129] In the normal state, the main spacer region 302 of the spacer 30 provides support for the liquid crystal cell thickness. When the display substrate is pressed, the color filter substrate 200 recesses toward the array substrate 100, and the first secondary spacer region 303 contributes to supporting the liquid crystal cell thickness. When the display substrate is pressed strongly, the color filter substrate 200 recesses further toward the array substrate 100, and the second secondary spacer region 304 also begins to contribute to supporting the liquid crystal cell thickness.

[0130] 7 , the signal line group 14 is provided with multiple winding areas 16 along its length. A winding area 16 is provided at the intersection of at least one signal line group 14 and the first signal line 11. The orthographic projection of the spacer 30 on the array substrate 100 within the winding area 16 does not overlap with the raised structure 15.

[0131] For example, the signal line group 14 includes a second signal line 12. The second signal line 12 extends along the length direction of the signal line group 14, i.e., the first direction X, in the non-winding area 17. Within the winding area 16, the second signal line 12 bends a distance perpendicular to the length direction of the signal line group 14, then extends along the length direction of the signal line group 14, bypasses the raised structure 15, bends back, and extends to a position colinear with the second signal line 12 in the non-winding area 17. The second signal line 12 then continues to extend along the length direction of the signal line group 14. In other words, within the winding area 16, the second signal line 12 protrudes along the second direction Y to avoid the spacer 30. In this way, the original main spacer area 302 within the winding area 16 becomes the first secondary spacer area 303.

[0132] In some embodiments, the distance that the second signal line 12 is bent in the direction perpendicular to the length direction of the signal line group 14 (the second direction Y) in the winding area 16 is h, and the maximum alignment deviation between the array substrate 100 and the color film substrate 200 in the second direction Y is e, and h is greater than or equal to e.

[0133] In some embodiments, referring to Figures 3 and 7 , the dimension of the spacer 30 along the first direction X is greater than the distance between two adjacent first signal lines 11. This facilitates the spacer 30 to abut against the area on the array substrate 100 where the first signal lines 11 are located, thereby reducing the risk of the spacer 30 contacting the pixel area 101, thereby reducing the risk of the spacer scratching the alignment film in the pixel area 101, and reducing the risk of light leakage due to the spacer 30 sliding.

[0134] Below, taking the example of the signal line group 14 including the second signal line 12 and the third signal line 13, and the signal line group 14 being arranged on the side of the first signal line 11 close to the first substrate 10, the structure and size of the spacer 30 are exemplarily described. Of course, the embodiments of the present disclosure are not limited to this, and it can be considered that the signal line group 14 is composed of the second signal line 12, and it can be considered that the signal line group 14 is arranged on the side of the first signal line 11 away from the first substrate 10.

[0135] In some embodiments, referring to FIG3 , the plurality of spacers 30 include at least one first spacer 31. The orthographic projection of the first spacer 31 on the array substrate 100 overlaps with at least thirteen first signal lines 11 and one signal line group 14. FIG3 exemplarily illustrates only three first signal lines 11. At least eleven of the intersections of the at least thirteen first signal lines 11 with the one signal line group 14 are provided with winding areas 16.

[0136] In some embodiments, a first spacer 31 is provided for every twenty-four pixel areas 101 on the display substrate 1100. For example, in a display substrate 1100 arranged in two rows and twelve columns, one first spacer 31 spans at least thirteen first signal lines 11 along its length, meaning that the first spacer 31 spans twelve pixel areas 101 along its length. The orthographic projection of the first spacer 31 on the array substrate 100 overlaps with the thirteen first signal lines 11 and one signal line group 14. At least eleven of the intersections between the thirteen first signal lines 11 and the signal line group 14 are provided with a winding area 16. Thus, the area ratio of the main spacer area 302 to the first sub-spacer area 303 is approximately 1:100. With this ratio, the main spacer area 302 and the first sub-spacer area 303 can both support the thickness of the liquid crystal cell and prevent dark spots under external pressure.

[0137] Of course, the arrangement of the first spacers 31 and the arrangement of the winding area 16 can be determined according to actual needs. For example, a first spacer 31 may be provided for an average of 23, 24, 25, 26, or 27 pixel areas 101. One first spacer 31 spans 12, 13, 14, 15, or 16 first signal lines 11 along its length, that is, the first spacer 31 spans 11, 12, 13, 14, or 15 pixel areas 101 along its length.

[0138] The number of the winding areas 16 may also be 11, 12, 13, 14 or 15. As long as the density of the orthographic projection of the main spacer area 302 on the array substrate 100 is 50 to 300 μm 2 / mm 2 , and the density of the orthographic projection of the first sub-spacer region 303 on the array substrate 100 is 5000-20000 μm 2 / mm 2 The density of the orthographic projections of the main spacer area 302 / first sub-spacer area 303 on the array substrate 100 refers to the ratio of the area of ​​the orthographic projections of the main spacer area 302 / first sub-spacer area 303 on the array substrate 100 to the area of ​​the orthographic projections of the surface of the array substrate close to the color filter substrate on the first substrate 10.

[0139] In some embodiments, the density of the orthographic projection of the main spacer region 302 on the array substrate 100 is 50-300 μm. 2 / mm 2 In this way, the main spacer area 302 can play a good supporting role on the thickness of the liquid crystal cell and is not easy to produce pressure spots under the action of external force. For example, the density of the orthographic projection of the main spacer area 302 on the array substrate 100 can be 50 to 100 μm. 2 / mm2 Alternatively, the density of the orthographic projection of the main spacer region 302 on the array substrate 100 is 100 to 170 μm 2 / mm 2 Alternatively, the density of the orthographic projection of the main spacer region 302 on the array substrate 100 is 170 to 300 μm 2 / mm 2 For example, the density of the orthographic projection of the main spacer area 302 on the array substrate 100 is 50 μm 2 / mm 2 , 80μm 2 / mm 2 , 100μm 2 / mm 2 , 150μm 2 / mm 2 , 170μm 2 / mm 2 , 200μm 2 / mm 2 or 300 μm 2 / mm 2 Etc., the embodiments of the present disclosure will not list them one by one.

[0140] The density of the orthographic projection of the first sub-spacer region 303 on the array substrate 100 is 5000-20000 μm 2 / mm 2 In this way, after the main spacer area 302 is squeezed and deformed, the first sub-spacer area 303 can effectively support the thickness of the liquid crystal cell. For example, the density of the orthographic projection of the first sub-spacer area 303 on the array substrate 100 can be 5000 to 8000 μm. 2 / mm 2 Alternatively, the density of the orthographic projection of the first sub-spacer region 303 on the array substrate 100 is 8000 to 12000 μm 2 / mm 2 Alternatively, the density of the orthographic projection of the first sub-spacer region 303 on the array substrate 100 is 12000 to 20000 μm 2 / mm 2 For example, the density of the orthographic projection of the first sub-spacer region 303 on the array substrate 100 is 5000 μm 2 / mm 2 , 6500μm 2 / mm 2 , 8000μm 2 / mm 2 , 10000μm 2 / mm 2 , 12000μm 2 / mm 2, 16000μm 2 / mm 2 or 20000μm 2 / mm 2 Etc., the embodiments of the present disclosure will not list them one by one.

[0141] It should be understood that the density of the orthographic projection of the main spacer area 302 on the array substrate 100 is too large (for example, greater than 300 μm). 2 / mm 2 ), which may result in poor deformation ability of the second spacer 32 and inability to effectively absorb external pressure through deformation, causing the display substrate to easily break under pressure or produce pressure spots. The density of the orthographic projection of the main spacer area 302 on the array substrate 100 is too small (for example, less than 50 μm 2 / mm 2 ) may result in a poor supporting effect of the second spacer 32, which is not conducive to maintaining the cell thickness of the liquid crystal layer. In addition, the density of the orthographic projection of the first sub-spacer area 303 on the array substrate 100 is too large (for example, greater than 20000 μm 2 / mm 2 ), which may result in a lower ability of the first sub-spacer area 303 to deform, and it cannot effectively absorb external pressure through deformation, causing the display substrate to easily break under pressure or produce pressure spots. Conversely, it may result in a poor supporting effect of the second spacer 32, which is not conducive to maintaining the cell thickness of the liquid crystal layer. In the embodiment of the present disclosure, the density of the orthographic projection of the main spacer area 302 on the array substrate 100 is 50 to 300 μm 2 / mm 2 , and the density of the orthographic projection of the first sub-spacer region 303 on the array substrate 100 is 5000-20000 μm 2 / mm 2 , which can ensure that the main spacer area 302 plays a good supporting role on the thickness of the liquid crystal box and is not easy to produce pressing spots under the action of external force.

[0142] In some embodiments, the first spacer 31 is connected to a portion of the protruding structure 15 , and a distance between a surface of the first spacer 31 away from the second substrate 20 and the second substrate 20 is equal.

[0143] In some embodiments, referring to Figures 10 and 11 , the plurality of spacers 30 may further include a plurality of second spacers 32. The orthographic projections of the second spacers 32 on the array substrate 100 overlap with the three first signal lines 11 and with one signal line group 14. The second spacers 32 abut against the protruding structures 15 formed at the intersections of the three first signal lines 11 and the one signal line group 14. In other words, the intersections of the three first signal lines 11 and the one signal line group 14 each constitute a non-winding region 17.

[0144] Compared to the first spacer 31, the density of the main spacer area 302 formed by the second spacer 32 (the ratio of the main spacer area 302 to the total area of ​​the spacer) is greater. Under the condition of equal distribution density, the external force required to deform the second spacer 32 is greater. Based on this, the density of the main spacer area 302 can be adjusted by adjusting (for example, reducing) the density and number of the second spacers 32 in the display substrate to adjust the density of the main spacer area 302 so that the density of the main spacer area 302 on the array substrate 100 is 50 to 300 μm. 2 / mm 2 .

[0145] Exemplarily, in the case where the plurality of spacers 30 only include the second spacer 32, a second spacer 32 may be provided for every 25 to 40 pixel areas 101. Of course, the arrangement density and distribution pattern of the second spacers 32 are not limited and can be flexibly set as needed. In addition, the display substrate may include the first spacer 31 and the second spacer 32 at the same time, and the distribution density of the first spacer 31 and the second spacer 32, as well as the relative position between the first spacer 31 and the second spacer 32, etc., can be flexibly set as needed, as long as the density of the positive projection of the main spacer area 302 formed by the first spacer 31 and the second spacer 32 on the array substrate 100 is 50 to 300 μm. 2 / mm 2 , and the density of the orthographic projection of the first sub-spacer region 303 on the array substrate 100 is 5000-20000 μm 2 / mm 2 That's it.

[0146] In some embodiments, referring to Figures 10 and 11 , the side of the second spacer 32 facing away from the second substrate 20 is equidistant from the second substrate 20. The overlapping region of the first signal line 11 and the signal line group 14 forms a plurality of raised structures 15 protruding toward the color filter substrate 200. The side of the spacer 30 facing away from the second substrate 20 abuts against some of the raised structures 15. In this way, the second spacer 32 can form distinct spacer regions within itself, cooperating with the first signal line 11 and the signal line group 14.

[0147] In some embodiments, referring to Figures 12 and 13 , the plurality of spacers 30 further include at least one third spacer 33. The orthographic projection of the third spacer 33 on the array substrate 100 overlaps with a first signal line 11 and a signal line group 14. The third spacer 33 abuts against a protruding structure 15 formed at the intersection of the first signal line 11 and the signal line group 14.

[0148] Compared to the second spacer 32, the area ratio of the main spacer region 302 formed by the third spacer 33 to the first sub-spacer region 303 is reduced (closer to 1:100), which helps to reduce the density of the main spacer region 302 (the ratio of the main spacer region 302 to the total area of ​​the spacer) and increase the density of the first sub-spacer region 303. Based on this, the density of the main spacer region 302 can be adjusted by adjusting the density and number of the third spacers 33 in the display substrate, so that the third spacers 33 meet the density of the main spacer region 302's orthographic projection on the array substrate 100 of 50 to 300 μm. 2 / mm 2 , and the density of the orthographic projection of the first sub-spacer region 303 on the array substrate 100 is 5000-20000 μm 2 / mm 2 For example, the size of the third spacer 33 can be reduced so that both ends of the third spacer 33 do not overlap with the first signal line 11, and in order to increase the density of the first sub-spacer area 303, the ends of the third spacer 33 can be made as close as possible to the first signal lines 11 at both ends.

[0149] Exemplarily, the multiple spacers 30 of the display substrate may include only the above-mentioned third spacer 33. In this case, a third spacer 33 may be provided for every 15 to 30 pixel areas 101. Of course, the arrangement density and distribution pattern of the third spacers 33 are not limited and can be flexibly set as needed. In addition, the display substrate may include a second spacer 32 and a third spacer 33 at the same time, and the distribution density of the second spacer 32 and the third spacer 33, as well as the relative position between the second spacer 32 and the third spacer 33, can be flexibly set as needed, as long as the density of the positive projection of the main spacer area 302 formed by the second spacer 32 and the third spacer 33 on the array substrate 100 is 50 to 300 μm. 2 / mm 2 , and the density of the orthographic projection of the first sub-spacer region 303 on the array substrate 100 is 5000-20000 μm 2 / mm 2 That's it.

[0150] In some embodiments, referring to Figures 12 and 13 , the side of the third spacer 33 facing away from the second substrate 20 is equidistant from the second substrate 20. The overlapping region of the first signal line 11 and the signal line group 14 forms a plurality of raised structures 15 protruding toward the color filter substrate 200. The side of the third spacer 33 facing away from the second substrate 20 abuts against some of these raised structures 15. The dimension of the third spacer 33 in the first direction X can be greater than the distance between two adjacent first signal lines 11. In this way, the third spacer 33 can form distinct spacer regions within itself, in coordination with the first signal line 11 and the signal line group 14.

[0151] In some embodiments, referring to Figures 14 and 15 , the plurality of spacers 30 include at least one fourth spacer 34. The orthographic projection of the fourth spacer 34 on the array substrate 100 overlaps with three first signal lines 11 and one signal line group 14. Winding regions 16 are provided at the intersections of two of the three first signal lines 11 with the signal line group 14. For example, as shown in Figure 14 , winding regions 16 are provided at the intersections of two of the three first signal lines 11 located on either side with the signal line group 14, while a non-winding region 17 is provided at the intersection of the middle first signal line 11 with the signal line group 14. The fourth spacer 34 abuts against a raised structure 15 (first raised structure 151) formed at the intersection of one of the three first signal lines 11 (the middle first signal line 11) with the signal line group 14.

[0152] Compared with the second spacer 32 and the third spacer 33, the ratio of the area of ​​the main spacer region 302 formed by the fourth spacer 34 to the first sub-spacer region 303 is further reduced (closer to 1:100), which is conducive to reducing the area ratio of the main spacer region 302 and increasing the area ratio of the first sub-spacer region 303. Based on this, the density and number of the fourth spacers 34 in the display substrate can be adjusted to adjust the density of the main spacer region 302 and the first sub-spacer region 303 formed by the fourth spacer 34, so that the fourth spacer 34 satisfies the density of the orthographic projection of the main spacer region 302 on the array substrate 100 to be 50 to 300 μm. 2 / mm 2 , and the density of the orthographic projection of the first sub-spacer region 303 on the array substrate 100 is 5000-20000 μm 2 / mm 2 .

[0153] In some embodiments, referring to Figures 14 and 15 , the side of the fourth spacer 34 facing away from the second substrate 20 is equidistant from the second substrate 20. The overlapping region of the first signal line 11 and the signal line group 14 forms a plurality of raised structures 15 protruding toward the color filter substrate 200. The side of the fourth spacer 34 facing away from the second substrate 20 abuts against some of these raised structures 15. The dimension of the fourth spacer 34 in the first direction X can be greater than the distance between two adjacent first signal lines 11. In this way, the third spacer 33 can form distinct spacer regions within itself, in conjunction with the first signal line 11 and the signal line group 14.

[0154] In some embodiments, referring to Figures 16 and 17 , the plurality of spacers 30 include at least one fifth spacer 35 . The orthographic projection of the fifth spacer 35 on the array substrate 100 overlaps with three first signal lines 11 and one signal line group 14 . Winding regions 16 are provided at the intersections of the three first signal lines 11 and one signal line group 14 . The fifth spacer 35 does not contact the raised structures 15 (second raised structures 152 ) formed at the intersections of the three first signal lines 11 and one signal line group 14 . In other words, the area where the orthographic projection of the fifth spacer 35 on the array substrate 100 overlaps with the first signal lines 11 or the signal line group 14 forms the first sub-spacer region 303 , and the fifth spacer 35 is not used to form the main spacer region 302 .

[0155] Compared to the second spacer 32, the third spacer 33, and the fourth spacer 34, the fifth spacer 35 does not form the main spacer area 302 and is only used to form the first sub-spacer area 303. The fifth spacer 35 is used to increase the density of the orthographic projection of the first sub-spacer area 303 on the array substrate 100. The density of the orthographic projection of the first sub-spacer area 303 on the array substrate 100 is 5000 to 20000 μm. 2 / mm 2 .

[0156] Exemplarily, the fifth spacer 35 can be used together with at least one of the first spacer 31, the second spacer 32, the third spacer 33, and the fourth spacer 34. That is, when the display substrate 1100 includes the fifth spacer 35, it may also include at least one of the first spacer 31, the second spacer 32, the third spacer 33, and the fourth spacer 34. For example, the multiple spacers 30 of the display substrate 1100 may include multiple second spacers 32 and multiple fifth spacers 35, or the multiple spacers 30 may include multiple third spacers 33 and multiple fifth spacers 35; or the multiple spacers 30 may include multiple second spacers 32, multiple third spacers 33, and multiple fifth spacers 35. The embodiments of the present disclosure do not list the combinations of the multiple spacers mentioned above one by one.

[0157] In some embodiments, referring to Figures 16 and 17 , the side of the fifth spacer 35 facing away from the second substrate 20 is equidistant from the second substrate 20. The overlapping region of the first signal line 11 and the signal line group 14 forms a plurality of raised structures 15 protruding toward the color filter substrate 200. The side of the fifth spacer 35 facing away from the second substrate 20 does not abut against the raised structures 15. The dimension of the fifth spacer 35 in the first direction X can be greater than the distance between two adjacent first signal lines 11. In this way, the third spacer 33 can form distinct spacer regions within itself, in conjunction with the first signal line 11 and the signal line group 14.

[0158] Compared with the first spacer 31, the second spacer 32, the third spacer 33, the fourth spacer 34 and the fifth spacer 35 have smaller dimensions in the first direction X. After the array substrate and the color filter substrate form a liquid crystal box, more gaps are formed between the second spacer 32, the third spacer 33, the fourth spacer 34 and the fifth spacer 35, which is conducive to the flow of liquid crystal in the liquid crystal box, that is, it is conducive to filling liquid crystal in the liquid crystal box.

[0159] In some embodiments, referring to FIG. 18 , the multiple spacers 30 of the display substrate 1100 include multiple fourth spacers 34 and multiple fifth spacers 35. Four fourth spacers 34 and four fifth spacers 35 are provided for at least every forty-eight pixel regions 101. Alternatively, the multiple spacers 30 consist of multiple fourth spacers 34 and multiple fifth spacers 35. The number and distribution density of the fourth spacers 34 can be adjusted to adjust the density of the orthographic projections of the main spacer regions 302 on the array substrate 100. The number and distribution density of the fifth spacers 35 can be adjusted to adjust the density of the orthographic projections of the first sub-spacer regions 303 on the array substrate 100, so that the density ratio of the main spacer regions 302 to the first sub-spacer regions 303 is close to 1:100. This ratio of the contact density between the main spacer regions 302 and the first sub-spacer regions 303 ensures both support for the liquid crystal cell thickness and the absence of dark spots under external pressure.

[0160] It should be noted that FIG. 18 provided in the embodiment of the present disclosure is only used to illustrate the arrangement manner and arrangement density of the fourth spacer 34 and the fifth spacer 35 , and is not used to reflect the corresponding relationship and projection relationship between each spacer and the pixel area 101 .

[0161] In some embodiments, referring to FIG. 18 , when the color filter substrate 200 includes a plurality of fourth spacers 34 and a plurality of fifth spacers 35 , the plurality of fourth spacers 34 and the plurality of fifth spacers 35 are arranged in rows along the first direction X, with each row including the plurality of fourth spacers 34 and the plurality of fifth spacers 35 arranged alternately, and / or the plurality of fourth spacers 34 and the plurality of fifth spacers 35 are arranged in columns along the second direction Y, with each column including the fourth spacers 34 and the fifth spacers 35 arranged alternately. This helps improve the distribution uniformity of the main spacer region 302 and the first sub-spacer region 303, improves the stress uniformity between the array substrate 100 and the color filter substrate 200, and reduces the risk of localized excessive stress between the array substrate 100 and the color filter substrate 200.

[0162] It should be noted that, in some embodiments, the color filter substrate 200 may include at least one of the first spacer 31, the second spacer 32, the third spacer 33, and the fourth spacer 34. Furthermore, the fifth spacer 35 cannot form the main spacer region 302. Therefore, the fifth spacer 35 must be used together with at least one of the first spacer 31, the second spacer 32, the third spacer 33, and the fourth spacer 34. In the embodiments of the present disclosure, the various possible combinations are not listed one by one.

[0163] In some embodiments, the spacer 30 (the first spacer 31, the second spacer 32, the third spacer 33, the fourth spacer 34, or the fifth spacer 35) spans across multiple first signal lines 11 along its length. As shown in FIG19 , when the spacer 30 undergoes a significant displacement in the second direction Y, for example, when the spacer 30 displaces in the second direction Y to the point where it no longer overlaps with the signal line group 14, the first signal line 11 can still provide support for the spacer 30. That is, when the spacer 30 undergoes a significant displacement in the second direction Y, it loses the main spacer region 302 and the first sub-spacer region 303 formed by overlapping with the signal line group 14, but does not lose the first sub-spacer region 303 formed by overlapping with the first signal line 11. Therefore, the significant displacement of the spacer 30 in the second direction Y will not scratch the alignment film located in the pixel region 101 on the array substrate 100.

[0164] Exemplarily, the arrangement of the spacers 30 can be determined according to needs. For example, one main spacer area 302 and six to twelve first sub-spacer areas 303 can be set in the twenty-four pixel areas 101 arranged in three rows and eight columns. Alternatively, one main spacer area 302 and six to twelve first sub-spacer areas 303 can be set in the twenty-four pixel areas 101 arranged in four rows and six columns. It is only necessary to satisfy that the spacers 30 are evenly arranged on the entire surface and that the contact density ratio between the main spacer area 302 and the first sub-spacer area 303 is close to 1:100. Of course, the arrangement of the above-mentioned spacers 30 and the arrangement of the winding area 16 can be determined according to actual needs.

[0165] 20 and 21 show the thickness of the liquid crystal cell of the display substrate in the main spacer region 302 and the first sub-spacer region 303 with different contact densities after the spacer 30 is subjected to external force with and without displacement.

[0166] 20 and 21 are the contact density (μm) of the first sub-spacer region 303. 2 / mm 2 ), the vertical axis is the thickness of the liquid crystal cell (μm). The six lines from top to bottom in FIG20 represent the contact density of the main spacer area 302 of 100μm 2 / mm 2 , 150μm2 / mm 2 , 200μm 2 / mm 2 , 250μm 2 / mm 2 , 300μm 2 / mm 2 , 350μm 2 / mm 2 The six lines from top to bottom in FIG21 represent the contact density of the main spacer area 302 of 350μm 2 / mm 2 , 300μm 2 / mm 2 , 250μm 2 / mm 2 , 200μm 2 / mm 2 , 150μm 2 / mm 2 , 100μm 2 / mm 2 It is obvious that as the contact density of the first sub-spacer region 303 increases, the thickness of the liquid crystal cell gradually increases after the display substrate is subjected to external force. When the contact density of the main spacer region 302 is 200 μm 2 / mm 2 The contact density of the first auxiliary spacer area 303 is 20000 μm 2 / mm 2 The spacer 30 can provide better support for the thickness of the liquid crystal cell.

[0167] FIG22 shows the display substrate with different contact densities between the main spacer area 302 and the first sub-spacer area 303, and the deformation of the spacer 30 after the spacer 30 is subjected to external force when the spacer 30 is displaced. The horizontal axis in FIG21 is the contact density of the first sub-spacer area 303 (μm 2 / mm 2 ), the vertical axis is the liquid crystal cell deformation (μm). The six lines from top to bottom in Figure 22 represent the contact density of the main spacer area 302 of 100μm 2 / mm 2 , 150μm 2 / mm 2 , 200μm 2 / mm 2 , 250μm 2 / mm 2 , 300μm 2 / mm 2 , 350μm 2 / mm 2The thickness of the first signal line 11 is generally between 0.5 μm and 0.7 μm, and the thickness of the signal line group 14 is between 0.5 μm and 0.7 μm. It can be clearly seen that when the contact density of the first sub-spacer area 303 is greater than 15000 μm 2 / mm 2 , the contact density of the main spacer area 302 is greater than 150μm 2 / mm 2 When the spacer 30 is deformed, the amount of deformation is significantly smaller than the thickness of the first signal line 11. At this time, the displacement of the spacer 30 will not scratch the alignment film.

[0168] In some embodiments, referring to Figures 23 and 24 , the orthographic projection of the spacer 30 on the array substrate 100 partially overlaps with the signal line group 14. The side of the spacer 30 facing away from the second substrate 20 is at unequal distances from the color filter substrate 200. The spacer 30 includes a main spacer region 302 having a first thickness and a first sub-spacer region 303 having a second thickness, where the first thickness is greater than the second thickness. The orthographic projection of the main spacer region 302 onto the array substrate 100 overlaps with the first signal line 11, while the orthographic projection of the main spacer region 302 onto the array substrate does not overlap with the signal line group 14. The orthographic projection of the main spacer region 302 onto the array substrate 100 covers at least two first signal lines 11 along the length of the spacer 30. The orthographic projection of the first sub-spacer region 303 onto the array substrate 100 partially overlaps with the first signal line 11 and partially overlaps with the signal line group 14.

[0169] Continuing to refer to Figures 23 and 24, the signal line group 14 is provided with a plurality of winding areas 16 along its length. A winding area 16 is provided at the position where at least one signal line group 14 intersects with the first signal line 11. Within the winding area 16, the signal line group 14 avoids the area where the spacer 30 overlaps with the first signal line 11. That is, the spacer 30, the signal line group 14, and the first signal line 11 do not overlap at the same time. At the same time, the winding area 16 is also provided at the position of the orthographic projection of the main spacer area 302 on the array substrate 100. Within the winding area 16, the signal line group 14 avoids the range covered by the orthographic projection of the main spacer area 302 on the array substrate 100. The maximum alignment deviation between the array substrate 100 and the color filter substrate 200 in the second direction Y is e. Therefore, the distance between the signal line group 14 in the winding area 16 and the area where the spacer 30 overlaps with the first signal line DL is greater than e, and the distance between the signal line group 14 in the winding area 16 and the area covered by the orthographic projection of the main spacer area 302 on the array substrate 100 is greater than e. That is, the orthographic projection of the first sub-spacer area 303 in the winding area 16 on the array substrate 100 overlaps with the first signal line 11, and the orthographic projection of the first sub-spacer area 303 in the non-winding area 17 on the array substrate 100 overlaps with the signal line group 14.

[0170] In some embodiments, referring to FIG25 , the orthographic projection of the black matrix 21 on the array substrate 100 covers the spacer 30, the first signal line 11, and the signal line group 14. The color filter substrate 200 further includes a black matrix 21, which is disposed between the second substrate 20 and the spacer 30, and the orthographic projection of the black matrix 21 on the array substrate 100 covers the orthographic projection of the spacer 30 on the array substrate 100, as well as the first signal line 11 and the signal line group 14. Exemplarily, the orthographic projection of the black matrix 21 on the array substrate 100 covers the area of ​​the non-pixel area 101. The black matrix 21 is also configured to separate different pixel areas 101 to reduce the risk of cross-color between different pixel areas, affecting the final display effect. The black matrix 21 can also prevent the spacer 30 from slipping, causing abnormal display of the panel, and shielding the distance from scratches.

[0171] In some embodiments, referring to Figures 25 and 26, the black matrix 21 includes a first portion 211 and a second portion 212. The orthographic projection of the first portion 211 on the array substrate 100 covers the end of the first signal line 11 near the signal line group 14. The second portion 212 is located on the side of the first portion 211 away from the signal line group 14 and is connected to the first portion 211. The dimension L1 of the first portion 211 in the first direction X is greater than the dimension L2 of the second portion 212 in the first direction X, that is, L1>L2. When the display substrate is subjected to external force, the spacer 30 may slide and displace. For example, the spacer may abut the area of ​​the end of the first signal line 11 near the signal line group 14 and scratch the alignment film in this area. L1>L2 helps to increase the dimension of the first portion 211 along the first direction X so that the first portion 211 can block the above-mentioned area and reduce the risk of light leakage in this area.

[0172] It should be understood that in some display substrates actually manufactured, the array substrate may further include a flat layer located on the side of the first signal line and the signal line group away from the first substrate. In this case, a height difference caused by the thickness of the first signal line and the signal line group itself cannot be formed on the surface of the array substrate, that is, a convex structure cannot be formed in the area where the first signal line and the signal line group overlap. For example, the array substrate may include a first conductive layer (such as a film layer where the first signal line / signal line group is located), a buffer layer, a semiconductor layer, a gate insulating layer, a second conductive layer (such as a film layer where the signal line group / first signal line is located), a first insulating layer, a first electrode layer, a second insulating layer, a second electrode layer, and a third insulating layer, which are sequentially arranged on the first substrate. Among them, at least one of the first insulating layer and the second insulating layer may be a flattening layer. In the case where the display substrate includes this array substrate, how to arrange spacers to prevent the spacers from scratching the pixel area alignment film and to reduce the preparation cost of preparing spacers of different thicknesses is an important technical problem faced in the related art.

[0173] To address this technical problem, some embodiments of the present application further provide a display substrate. Referring to Figures 27, 28, and 29, the display substrate includes an array substrate 100 and a color filter substrate 200. The array substrate 100 includes a first base substrate 110 and a sub-spacer 36 disposed on one side of the first base substrate 110. The sub-spacer 36 can be disposed on the side of the first base substrate 110 facing the color filter substrate 200. The sub-spacer 36 is located between two adjacent pixel regions 101 in a first direction X and extends along a second direction Y.

[0174] It should be noted that the first substrate 110 may include the above-mentioned first substrate and multiple film layers including at least one flat layer disposed on the first substrate, forming a substantially flat surface structure. For example, the first substrate 110 includes the above-mentioned first substrate, a first conductive layer, a buffer layer, a semiconductor layer, a gate insulating layer, a second conductive layer, a first insulating layer, a first electrode layer, a second insulating layer, a second electrode layer, and a third insulating layer disposed in sequence away from the first substrate. Of course, the structure of the first substrate 110 is not limited to this, and any other substrate including at least one flat layer and capable of forming a substantially flat surface may be considered.

[0175] As shown in Figures 27 and 28, the color filter substrate 200 includes a second substrate 20 and a spacer 30 disposed on the second substrate 20. The spacer 30 is disposed on a side of the second substrate 20 facing the array substrate 100 and extends along a first direction X. The spacer 30 abuts against the sub-spacer 36 corresponding to the i-th row of pixel regions 101, and also abuts against the sub-spacer 36 corresponding to the i+1-th row of pixel regions 101, where i is a natural number greater than or equal to 1. That is, for the same spacer 30, a surface 301 of the spacer 30 that is close to the array substrate 100 (hereinafter referred to as the first surface 301) contacts the surface of the sub-spacer 36 corresponding to the i-th row of pixel regions 101 that is close to the color filter substrate 200 (i.e., the upper surface of the sub-spacer 36), and the first surface 301 contacts the upper surface of the sub-spacer 36 corresponding to the i+1-th row of pixel regions 101. In FIG. 27 , the spacer 30 abuts against the sub-spacer 36 a corresponding to the pixel region 101 in the i-th row, and the spacer 30 abuts against the sub-spacer 36 b corresponding to the pixel region 101 in the (i+1)-th row.

[0176] In the embodiment of the present disclosure, a sub-spacer 36 is formed on a side of the first base substrate 110 close to the color filter substrate 200. The sub-spacer 36 is located between two adjacent pixel areas 101 in the first direction X, and extends along the second direction Y. In this way, the sub-spacer 36 can form a step structure on the surface of the array substrate 100 that is protruding compared to other parts of the surface, that is, the sub-spacer 36 can form a protrusion equivalent to a protrusion structure. The spacer 30 extends along the first direction X, and the spacer 30 is respectively in contact with the sub-spacers 36 in two adjacent rows of pixel areas 101 (the spacer 30 is in contact with both the sub-spacer 36a and the sub-spacer 36b at the same time). In this way, there is a gap S between the spacer 30 and the surface of the array substrate 100 located in the pixel area 101. Even if the display substrate slides under the action of external force, the spacer 30 can still be in contact with the sub-spacer 36, which can reduce the risk of the spacer 30 contacting the alignment film in the pixel area 101, thereby reducing the problem of the alignment film in the pixel area 101 being scratched, and can effectively prevent light leakage caused by the scratched alignment film.

[0177] For example, the contact area between the spacer 30 and the sub-spacer 36a corresponding to the i+1th row of pixel area 101 is S1, and the contact area between the spacer 30 and the sub-spacer 36b corresponding to the i+1th row of pixel area 101 is S2. Then, the total contact area between the spacer 30 and the sub-spacer 36 can be S1+S2.

[0178] In the display substrate provided by the embodiment of the present disclosure, when the color filter substrate 200 and the array substrate 100 produce an alignment deviation, resulting in an alignment deviation between the spacer 30 and the sub-spacer 36 along the second direction Y, since the spacer 30 is simultaneously in contact with the sub-spacer 36a corresponding to the i-th row of pixel areas 101 and the sub-spacer 36b corresponding to the i+1-th row of pixel areas 101, and the sub-spacer 36 extends along the second direction Y, as shown in Figure 27, when the spacer 30 moves upward relative to the sub-spacer 36, the contact area between the spacer 30 and the sub-spacer 36a increases by ΔS1, and the contact area between the spacer 30 and the sub-spacer 36b decreases by ΔS2, ΔS1=ΔS2, and the total contact area between the spacer 30 and the sub-spacer 36 remains S1+S2. When the spacer 30 moves downward relative to the sub-spacer 36, the contact area between the spacer 30 and the sub-spacer 36a decreases by ΔS3, and the contact area between the spacer 30 and the sub-spacer 36b increases by ΔS4. ΔS3 = ΔS4, and the total contact area between the spacer 30 and the sub-spacer 36 remains S1 + S2. Therefore, in the display substrate provided by the embodiment of the present disclosure, when the spacer 30 and the sub-spacer 36 have an alignment deviation in the second direction Y, the total contact area between the spacer 30 and the sub-spacer 36 can remain unchanged, ensuring that the total contact area between the spacer 30 and the sub-spacer 36 is not affected by the alignment deviation, ensuring the supporting strength of the spacer 30 and the sub-spacer 36, and facilitating the maintenance of uniform liquid crystal cell thickness.

[0179] As shown in FIG27 , in a row of pixel regions 101, a sub-spacer 36 is located between two adjacent pixel regions 101. Therefore, a row of pixel regions 101 may correspond to multiple sub-spacers 36. The spacer 30 may abut against a sub-spacer 36 corresponding to the i-th row of pixel regions 101, and the spacer 30 may abut against a sub-spacer 36 corresponding to the i+1-th row of pixel regions 101. For example, in FIG27 , the first surface 301 abuts against the sub-spacer 36a corresponding to the i-th row of pixel regions 101, and the first surface 301 abuts against the sub-spacer 36b corresponding to the i+1-th row of pixel regions 101.

[0180] In some embodiments, as shown in FIG27 , in a row of pixel regions 101, a sub-spacer 36 is located between two adjacent pixel regions 101. Therefore, a row of pixel regions 101 may correspond to multiple sub-spacers 36. The spacer 30 may abut against a sub-spacer 36 corresponding to the i-th row of pixel regions 101, and the spacer 30 may abut against a sub-spacer 36 corresponding to the i+1-th row of pixel regions 101. For example, in FIG27 , the first surface 301 abuts against the sub-spacer 36a corresponding to the i-th row of pixel regions 101, and the first surface 301 abuts against the sub-spacer 36b corresponding to the i+1-th row of pixel regions 101.

[0181] In one example, as shown in FIG27 , two adjacent rows of pixel areas 101 are staggered, and two adjacent rows of sub-spacers 36 are staggered. The sub-spacers 36 a and 36 b that abut the same spacer 30 are two adjacent sub-spacers 36 in the two adjacent rows of sub-spacers 36 in the first direction X. In other words, the sub-spacers 36 a and 36 b are adjacent in the first direction X.

[0182] In some embodiments, referring to FIG. 30 , a display substrate may include multiple pixel regions 101 arranged in multiple rows and columns. Two sub-spacers 36 abutting the same spacer 30 are located between the same two columns of pixel regions 101. Sub-spacers 36a and 36b abutting the same spacer 30 may be located between the same two columns of pixel regions 101, with both sub-spacers 36a and 36b located between the j-th and j+1-th columns of pixel regions 101.

[0183] In some embodiments, referring to Figures 27, 30, and 31, the gap between the sub-spacer 36 corresponding to the pixel region 101 in the i-th row and the sub-spacer 36 corresponding to the pixel region 101 in the (i+1)th row in the second direction Y is less than or equal to 0, that is, the gap between the sub-spacer 36a and the sub-spacer 36b in the second direction Y is less than or equal to 0. Setting the gap between the sub-spacer 36 corresponding to the pixel region 101 in the i-th row and the sub-spacer 36 corresponding to the pixel region 101 in the (i+1)th row in the second direction Y to be less than or equal to 0 can make the total contact area between the spacer 30 and the sub-spacer 36 in the second direction Y greater than or equal to the size of the first surface 301 in the second direction Y, thereby increasing the total contact area between the spacer 30 and the sub-spacer 36, improving the support strength of the spacer, and facilitating improved cell thickness uniformity.

[0184] For example, as shown in FIG27 , when the lower boundary of the sub-spacer 36a is flush with the upper boundary of the sub-spacer 36b, the gap between the sub-spacers 36a and 36b in the second direction Y is equal to 0. As shown in FIG31 , when the sub-spacers 36a and 36b overlap in the second direction Y, or when the projections of the sub-spacers 36a and 36b along the first direction X coincide, the gap between the sub-spacers 36a and 36b in the second direction Y is less than 0. As shown in FIG30 , when the plurality of pixel areas 101 are arranged in multiple rows and columns, the sub-spacers 36a and 36b in adjacent rows are connected together, that is, the gap between the sub-spacers 36a and 36b in the second direction Y is equal to 0.

[0185] In some embodiments, as shown in FIG27 , a dimension L1 of the first surface 301 in the first direction X is greater than or equal to a spacing K1 between two adjacent pixel regions 101 in the first direction X. In this manner, when the spacer 30 is misaligned relative to the sub-spacer 36 in the first direction X, for example, when the spacer 30 moves rightward relative to the sub-spacer 36 so that the spacer 30 abuts the sub-spacer 36 c, the abutting area between the spacer 30 and the sub-spacer 36 c increases from 0 to ΔS5, while the abutting area between the spacer 30 and the sub-spacer 36 a remains unchanged or decreases by ΔS6, where ΔS6 ≤ ΔS5. Consequently, when the spacer 30 moves rightward relative to the sub-spacer 36, the total abutting area between the spacer 30 and the sub-spacer 36 remains unchanged or increases. When the spacer 30 moves leftward relative to the sub-spacer 36, the total abutting area between the spacer 30 and the sub-spacer 36 remains unchanged or increases.

[0186] In the disclosed embodiment, the dimension L1 of the first surface 301 in the first direction X is set to be greater than or equal to the spacing K1 between two adjacent pixel regions 101 in the first direction X. This ensures that the total contact area between the spacer 30 and the sub-spacer 36 remains unchanged or increases when the spacer 30 and the sub-spacer 36 produce an alignment deviation in the first direction X, further ensuring the supporting strength of the spacer 30 and the sub-spacer 36, which is conducive to maintaining the uniformity of the cell thickness. Furthermore, when the spacer 30 slides along the second direction Y, the spacer 30 will not completely slide between two adjacent sub-spacers 36, thereby ensuring that the spacer 30 overlaps at least one sub-spacer 36, thereby preventing the spacer 30 from scratching the alignment film located in the pixel region 101 on the array substrate 100 and reducing the risk of light leakage from the display substrate.

[0187] In addition, the thickness of the spacer 30 will also affect the coating of the alignment film (second alignment film) on the color filter substrate, thereby causing disorder in the liquid crystal layer near the spacer 30. In the present application, while the thickness of the liquid crystal layer (the gap between the array substrate and the color filter substrate) remains unchanged, by providing the sub-spacer 36 on the array substrate 100, it is also beneficial to reduce the size of the spacer 30 in a direction perpendicular to the second substrate 20, that is, to reduce the thickness of the spacer 30, reduce the disorder of the liquid crystal layer caused by the alignment film at the location of the spacer 30, and reduce the area of ​​the light leakage area caused by the spacer 30, which is beneficial to improve the aperture ratio of the display substrate.

[0188] In some embodiments, as shown in Figures 27-31 , when the array substrate 100 includes sub-spacers 36, the array substrate 100 also includes a light shielding layer 120. The light shielding layer 120 is disposed on the side of the first base substrate 110 proximate to the color filter substrate 200, and the sub-spacers 36 are located on the side of the light shielding layer 120 proximate to the color filter substrate 200. In other words, the light shielding layer 120 is disposed between the first base substrate 110 and the sub-spacers 36. The orthographic projection of the light shielding layer 120 on the first base substrate 110 does not overlap with the orthographic projection of the corresponding pixel area 101 on the first base substrate 110. In other words, the light shielding layer 120 is located outside the pixel area 101. The orthographic projection of the sub-spacers 36 on the first base substrate 110 is located within the orthographic projection of the light shielding layer 120 on the first base substrate 110. The light shielding layer 120 can reduce cross-color between adjacent pixels and improve display performance. Exemplarily, the orthographic projection of the black matrix 21 on the array substrate 100 overlaps with a portion of the light shielding layer 120 ; for example, the orthographic projection of the black matrix 21 on the array substrate 100 covers the light shielding layer 120 .

[0189] In some embodiments, as shown in Figure 27, the edges of the sub-spacers 36 are retracted by the same distance relative to the corresponding edges of the light-shielding layer 120; in other words, the distances between the edges of the orthographic projection of the sub-spacers 36 on the first base substrate 110 and the corresponding edges of the orthographic projection of the light-shielding layer 120 on the first base substrate 110 are the same.

[0190] As shown in FIG27 , the light shielding layer 120 may include a first light shielding strip 121 and a second light shielding strip 122 . The first light shielding strip 121 extends along a first direction X and is located between two adjacent rows of pixel regions 101 . The second light shielding strip 122 extends along a second direction Y and is located between two adjacent pixel regions 101 in the first direction X. At least a portion of the sub-spacer 36 is located on the second light shielding strip 122 .

[0191] Exemplarily, the edges of the sub-spacer 36 are retracted by the same distance relative to the corresponding edges of the light-shielding layer 120. It can be understood that, as shown in Figure 27, the distance between the left edge of the sub-spacer 36 and the left edge of the corresponding second light-shielding strip 122 is the first distance; the distance between the right edge of the sub-spacer 36 and the right edge of the corresponding second light-shielding strip 122 is the first distance; the distance between the upper edge of the sub-spacer 36 and the upper edge of the corresponding first light-shielding strip 121 is the first distance; and the distance between the lower edge of the sub-spacer 36 and the lower edge of the corresponding first light-shielding strip 121 is the first distance.

[0192] The difference between the dimension W1 of the second light-shielding strip 122 in the first direction X and the dimension W2 of the sub-spacer 36 in the first direction X is the same as the dimension W3 of the first light-shielding strip 121 in the second direction Y. For example, W1 can be approximately 2.6 μm, and W2 can be approximately 1 μm. The values ​​of W1 and W2 can be set as needed and are not specifically limited here.

[0193] For example, the orthographic projection of the sub-spacer 36 on the first base substrate 110 may be located within two boundaries of the second light-shielding strip 122 parallel to the second direction Y. The orthographic projection of the first surface 301 on the first base substrate 110 may be located within the orthographic projection of the first light-shielding strip 121 on the first base substrate 110. Thus, the sub-spacer 36 and the spacer 30 do not affect the light transmittance of the display substrate.

[0194] In some embodiments, the sub-spacer 36 is aligned with the center of the second light-shielding strip 122. A dimension L2 of the sub-spacer 36 in the second direction Y is greater than a dimension L3 of the pixel area 101 in the second direction Y. A distance K3 between an edge of the sub-spacer 36 parallel to the first direction X and the corresponding edge of the first light-shielding strip 121 is half the dimension W3 of the first light-shielding strip 121 in the second direction Y. The distance between an edge of the sub-spacer 36 and the corresponding edge of the second light-shielding strip 122 is half the dimension W3 of the first light-shielding strip 121 in the second direction Y. In other words, each edge of the sub-spacer 36 is retracted relative to the corresponding edge of the light-shielding layer 120 by a distance that is half the dimension W3 of the first light-shielding strip 121 in the second direction Y.

[0195] Exemplarily, the light shielding layer 120 may be made of a blackened metal material, which may be a metal material having a light shielding rate greater than a first threshold value, and the first threshold value may be, for example, 80%, 85%, 90% or 95%, etc., which will not be listed one by one in the embodiments of the present disclosure. The blackened metal material includes, but is not limited to, at least one of molybdenum (Mo), aluminum (Al), molybdenum niobium (MoNb), and molybdenum nickel titanium (MTD). The sub-spacer 36 may be made of an inorganic material and / or an organic material, wherein the inorganic material may include one or more of metal oxides and blackened metal materials; the metal oxide may include, but is not limited to, silicon nitride, silicon oxide, titanium nitride, molybdenum nitride, molybdenum oxide, niobium oxide, niobium nitride, etc. The light shielding layer 120 and the sub-spacer 36 may be formed by a mask process, for example, by wet etching plus dry etching, and by utilizing the difference in etching bias between the sub-spacer 36 and the light shielding layer 120, the light shielding layer 120 and the sub-spacer 36 are formed into a step shape.

[0196] In the array substrate 100 of the embodiment of the present disclosure, each edge of the sub-spacer 36 is retracted by the same distance relative to the corresponding edge of the light-shielding layer 120. Therefore, when the sub-spacers 36 are manufactured on the light-shielding layer 120, a self-alignment process can be used to manufacture the sub-spacers 36, ensuring that the distances between the boundaries of the light-shielding layer 120 and the corresponding boundaries of the sub-spacers 36 are the same, thereby reducing the impact of process fluctuations on the size of the sub-spacers 36, and further reducing the impact of process fluctuations on the aperture ratio.

[0197] Exemplarily, the light shielding layer 120 may be connected to the first electrode (common electrode) of the array substrate, so that the light shielding layer 120 may serve as the common electrode layer of the array substrate 100 .

[0198] In some embodiments, as shown in Figures 28 and 29, the color filter substrate 200 may further include a black matrix 21. The black matrix 21 is located on the side of the second substrate 20 facing the array substrate 100, and the spacers 30 are located on the side of the black matrix 21 facing away from the second substrate 20. The orthographic projection of the spacers 30 on the second substrate 20 is located within the orthographic projection of the black matrix 21 on the second substrate 20.

[0199] In one example, the dimension L1 of the first surface 301 of the spacer 30 in the first direction X is 6 μm, and the dimension W5 of the first surface 301 in the second direction Y is approximately 1 μm. The dimension of the surface of the spacer 30 adjacent to the second substrate 20 in the first direction X is approximately 7 μm, and the dimension of the surface of the spacer 30 adjacent to the second substrate 20 in the second direction Y is approximately 2 μm. The dimension L5 of the black matrix 21 in the first direction X is approximately 10.1 μm, and the dimension W5 of the black matrix 21 in the second direction Y is approximately 5.1 μm. The height of the first spacer is approximately 0.6 μm, and the height of the spacer 30 is approximately 1.3 μm.

[0200] In some embodiments, as shown in Figures 27 and 28, the portion of the spacer 30 on the first surface 301 away from the second substrate 20 that abuts the sub-spacer 36 forms a main spacer area 302. In addition, the orthographic projection of the first surface 301 on the array substrate 100 is located at a position that coincides with the light-shielding layer 120 and the portion that does not contact the sub-spacer 36 can form a first sub-spacer area 303.

[0201] In some embodiments, referring to Figures 27 and 28, the side of the spacer 30 that is away from the second substrate 20 is at an equal distance from the second substrate 20. The first surface 301 of the spacer 30 that is away from the second substrate 20 abuts against the sub-spacer 36. The spacer 30 can cooperate with the sub-spacer 36 to form different spacer regions within itself.

[0202] When the display substrate 1100 is in a normal state (without pressure), the main spacer region 302 of the spacer 30 provides support for the liquid crystal cell thickness. When the display substrate 1100 is pressed, the color filter substrate 200 is squeezed toward the side closer to the array substrate 100, causing the spacer 30 to deform. The first sub-spacer region 303 of the spacer 30 begins to support the liquid crystal cell thickness, that is, the spacer 30 contacts the light shielding layer 120 on the array substrate 100.

[0203] The size of the spacer 30 along the first direction X can be set as needed. In other embodiments, referring to FIG. 32 , the size of the spacer 30 along the first direction X can be greater than the distance between two pixel regions 101. For example, the orthographic projection of the spacer 30 on the array substrate 100 abuts against at least three sub-spacers 36 in the same row. For example, the orthographic projection of the spacer 30 on the array substrate 100 abuts against any number of sub-spacers 36 in the same row, such as three, four, six, eight, or ten.

[0204] The arrangement density of the spacers 30 is negatively correlated with their length along the first direction X. For example, as the length of the spacers 30 along the first direction X increases, the number of the spacers 30 decreases. By adjusting the arrangement density and arrangement mode of the spacers 30, the density of the orthographic projection of the main spacer area 302 on the array substrate 100 can be 50 to 300 μm. 2 / mm 2 , and the density of the orthographic projection of the first sub-spacer region 303 on the array substrate 100 is 5000-20000 μm 2 / mm 2 , to ensure that the main spacer area 302 plays a good supporting role on the thickness of the liquid crystal cell and is not prone to producing pressing spots under the action of external force.

[0205] Of course, in order to adjust the ratio between the main spacer area 302 and the first sub-spacer area 303 formed by the spacer 30, referring to FIG33 , the array substrate 100 may further include multiple winding areas 16. Within the winding area 16, the orthographic projection of the spacer 30 on the array substrate 100 overlaps with the first light shielding strip 121 and does not contact the sub-spacer 36.

[0206] Exemplarily, the winding area 16 is located within the light-shielding layer 120 and does not overlap with the sub-spacers 36. For example, the winding area 16 may be located on the first light-shielding strip 121 and opposite at least one sub-spacer 36. The end of at least one sub-spacer 36 along the second direction Y does not extend onto the first light-shielding strip 121 to form the winding area 16. By increasing the number of winding areas 16, the area proportion of the first sub-spacer area 303 formed by the spacers 30 can be increased, and the area proportion of the main spacer area 302 can be reduced, so that the area ratio of the main spacer area 302 to the first sub-spacer area 303 is close to 1:100. Under this ratio, the main spacer area 302 and the first sub-spacer area 303 can both meet the requirements of supporting the thickness of the liquid crystal cell and eliminating dark spots under external pressure.

[0207] In the embodiment of the present disclosure, the length of the spacers 30 along the second direction X, the arrangement and density of the spacers 30 , and the number and distribution density of the winding areas 16 provided on the array substrate are not listed one by one.

[0208] The embodiment of the present disclosure further provides a method for preparing a display substrate, where the display substrate includes a plurality of rows of pixel areas 101 . The method includes steps S11 to S13 .

[0209] In step S11, an array substrate 100 is prepared. This step may include forming a sub-spacer 36 on one side of a first base substrate 110, wherein the sub-spacer 36 is located between two adjacent pixel regions 101 in a first direction X and extends along a second direction Y. The first direction X is the direction in which a row of pixel regions 101 is located.

[0210] In step S12, a color filter substrate 200 is provided. The color filter substrate 200 includes a second substrate 20 and a spacer 30 disposed on one side of the second substrate 20. The spacer 30 extends along a first direction X.

[0211] In step S13, the color filter substrate 200 is aligned with the array substrate 100, the spacer 30 is in contact with the sub-spacer 36 corresponding to the i-th row of pixel area 101, and the spacer 30 is in contact with the sub-spacer 36 corresponding to the i+1-th row of pixel area 101, where i is a natural number greater than or equal to 1.

[0212] In some embodiments, the array substrate 100 further includes a light shielding layer 120 , which is disposed on a side of the first base substrate 110 facing the sub-spacer 36 . The sub-spacer 36 is located on a side of the light shielding layer 120 facing the color filter substrate 200 .

[0213] A sub-spacer 36 is formed on one side of the first base substrate 110, including: depositing a light-shielding material layer and a spacer material layer in sequence on one side of the first base substrate 110; forming a photoresist pattern 40 on a side of the spacer material layer away from the first base substrate 110, wherein the orthographic projection of the photoresist pattern 40 on the first base substrate 110 coincides with the orthographic projection of the light-shielding layer 120 on the first base substrate 110; etching the spacer material layer 36' using a wet etching process, and the remaining spacer material forms a sub-spacer 36, wherein the edge of the sub-spacer 36 is retracted by a preset distance M relative to the corresponding edge of the photoresist pattern 40; and etching the light-shielding material layer using a dry etching process to remove the light-shielding material outside the area where the photoresist pattern 40 is located, and the light-shielding material located in the area where the photoresist pattern 40 is located forms the light-shielding layer 120.

[0214] Figure 34 is a schematic diagram of the B3-B3 cross-section in Figure 27. The following uses Figure 34 as an example to further illustrate the preparation process of the array substrate 100. It is understood that the "patterning" mentioned herein includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping when the patterned material is an inorganic material or metal, and includes processes such as mask exposure and development when the patterned material is an organic material. The evaporation, deposition, coating, and coating mentioned herein are all mature preparation processes in the relevant art.

[0215] A light shielding material layer 120' and a spacer material layer 36' are sequentially deposited on one side of the first base substrate 110, as shown in FIG35A , which is a schematic cross-sectional view of the array substrate after the spacer material layer is deposited. For example, the light shielding material layer may include a first metal, and the spacer material layer may include a second metal. The light shielding material layer and the spacer material layer may be made of different materials.

[0216] Photoresist is coated on the side of the spacer material layer away from the first base substrate 110; the photoresist is exposed and developed to form a photoresist pattern 40, and the orthographic projection of the photoresist pattern 40 on the first base substrate 110 coincides with the orthographic projection of the light-shielding layer 120 on the first base substrate 110, as shown in FIG35B , which is a cross-sectional schematic diagram after the photoresist pattern is formed in the array substrate.

[0217] The spacer material layer 36' is etched using a wet etching process, and the remaining spacer material forms a sub-spacer 36. The edge of the sub-spacer 36 is retracted by a preset distance M relative to the corresponding edge of the photoresist pattern 40, as shown in Figure 35C. Figure 35C is a cross-sectional schematic diagram after the first spacer is formed in the array substrate.

[0218] A dry etching process is used to etch the light-shielding material layer 120' to remove the light-shielding material outside the area where the photoresist pattern 40 is located. The light-shielding material located in the area where the photoresist pattern 40 is located forms a light-shielding layer 120. The light-shielding layer 120 is located in an area outside the pixel area 101. After stripping the photoresist pattern, the array substrate shown in Figures 34 and 27 is obtained. The orthographic projection of the light-shielding layer 120 on the first base substrate 110 coincides with the orthographic projection boundary of the photoresist pattern 40 on the first base substrate 110. Because the sub-spacers 36 are formed using the photoresist pattern 40 and a wet etching process, each edge of the sub-spacer 36 is retracted by the same distance relative to the corresponding edge of the light-shielding layer 120.

[0219] It should be noted that during the process of etching the spacer material layer using a wet etching process, the wet etching process will not etch the light-shielding material layer. Exemplarily, the material of the light-shielding layer 120 may include a first metal, and the material of the sub-spacer 36 may include a second metal. For example, the first metal may be titanium (Ti), and the second metal may be molybdenum (Mo). A suitable wet etching process can be selected according to the material of the sub-spacer 36 and the material of the light-shielding layer 120, so that the wet etching process can etch the spacer material without etching the light-shielding layer material. The material of the light-shielding layer 120 and the material of the sub-spacer 36 can be selected in conjunction with the wet etching process, so that the wet etching process can etch the spacer material without etching the light-shielding layer material.

[0220] In an array substrate fabricated using the method of an embodiment of the present disclosure, as shown in FIG27 , each edge of the sub-spacer 36 is retracted by the same distance relative to the corresponding edge of the light-shielding layer 120. The difference between the dimension W1 of the second light-shielding strip 122 in the first direction X and the dimension W2 of the sub-spacer 36 in the first direction X is equal to the dimension W3 of the first light-shielding strip 121 in the second direction Y. The sub-spacer 36 is centrally aligned with the second light-shielding strip 122. The dimension L2 of the sub-spacer 36 in the second direction Y is greater than the dimension L3 of the pixel area 101 in the second direction Y. The distance K3 between the edge of the sub-spacer 36 parallel to the first direction X and the corresponding edge of the first light-shielding strip 121 is half the dimension W3 of the first light-shielding strip 121 in the second direction Y. The distance between the edge of the sub-spacer 36 and the corresponding edge of the second light-shielding strip 122 is half the dimension W3 of the first light-shielding strip 121 in the second direction Y. With this arrangement, a self-alignment process can be used during the wet etching process to ensure that the boundaries of the sub-spacers 36 are retracted by the same distance compared to the boundaries of the light-shielding layer 120, thereby achieving W1-W2=W3, K3=W3*(1 / 2), and a preset distance M=W3*(1 / 2), thereby ensuring that the sub-spacers 36 are aligned with the centers of the second light-shielding strips 122, which is beneficial to improving the dimensional accuracy of the light-shielding layer 120 and the sub-spacers 36.

[0221] Figure 36 is a planar schematic diagram of an array substrate in a display substrate according to an embodiment of the present disclosure. Figure 36 also shows a schematic diagram of the first surface 301 and the black matrix 21. Taking the display substrate with a sub-pixel size of 6μm*8μm in reality (i.e., K4=6μm, L4=8μm in Figure 34) as an example, the size W1 of the second shading strip 122 in the first direction X is approximately 2.6μm, the size W3 of the first shading strip 121 in the second direction Y is approximately 1.6μm, and the L2 of the sub-spacer 36 formed by the self-alignment process is approximately 1μm, and W2 is approximately 8μm. Correspondingly, the size of the first surface 301 of the spacer 30 in the second direction Y is approximately 1μm, and the size of the first surface 301 in the first direction X is approximately 6μm. The required size W5 of the black matrix 21 is approximately 5.1μm, and L5 is approximately 10.1μm. The density of the total contact area between the sub-spacer 36 and the spacer 30 is set to be approximately 320μm 2 / mm 2 , it is calculated that the aperture ratio of the display substrate is approximately 37.8%.

[0222] Figure 37 is a cross-sectional schematic diagram of a display substrate in a related art, and Figure 38 is a schematic diagram comparing the sizes of opaque patterns in an array substrate in the related art and in the array substrate in the present disclosure. Figure 38 shows the projection of the black matrix 21 of the present disclosure on the array substrate 100 and the projection of the light-shielding layer 120 pattern in the related art. In Figure 38, the resolution of the present disclosure and the related art is the same.

[0223] As shown in FIG37 , the array substrate 100 includes a first base substrate 110, a light shielding layer 120, and a sub-spacer 36. The sub-spacer 36 is circular in shape, and the spacer 30 is circular in shape. In related art, it is necessary to consider the effect of alignment deviation on the contact area between the sub-spacer 36 and the spacer 30. When the alignment deviation M2 is approximately 3 μm and the diameter M1 of the first surface 301 of the spacer 30 is approximately 1 μm, in order to ensure that the contact area between the sub-spacer 36 and the spacer 30 remains unchanged within the alignment deviation, the diameter of the sub-spacer 36 (2*M2+M1) is approximately 7 μm. Correspondingly, the size M4 of the light shielding layer 120 is at least approximately 8.6 μm. Obviously, in the related technology of Figure 37, for a group of sub-spacers 36 and spacers 30 abutting each other, the maximum diameter Q of the opaque pattern is about 8.6μm; in the present disclosure, for a group of sub-spacers 36 and spacers 30 abutting each other, the maximum size W5*L5 of the opaque pattern is about 5.1μm*10.1μm. Therefore, for the convenience of comparison, the size of the shading layer 120 in the related technology and the size W5*L5 of the black matrix 21 in the present disclosure are drawn in Figure 38.

[0224] The total contact area density of the sub-spacer 36 and the spacer 30 is set to be about 320 μm2 / mm 2 , the aperture ratio of the display substrate is calculated to be approximately 37.1%. Moreover, when the alignment deviation is greater than 3 μm, the contact area between the sub-spacer 36 and the spacer 30 becomes smaller, resulting in insufficient support force and the risk of cell gap deviation.

[0225] From the above comparison, it can be seen that under the same resolution and the same alignment deviation, compared with the related technology, the technical solution disclosed in the present invention improves the aperture ratio of the display substrate, and the alignment deviation will not cause the contact area between the sub-spacer 36 and the spacer 30 to decrease, so that the contact area between the sub-spacer 36 and the spacer 30 is not affected by the alignment deviation, thereby ensuring the supporting strength of the sub-spacer 36 and the spacer 30, which is conducive to maintaining the uniformity of the box thickness.

[0226] In Figure 37 , M3 is approximately 0.8 μm, the upper diameter M5 of the spacer 30 is approximately 2 μm, the distance M6 between the upper edge of the spacer 30 and the corresponding edge of the black matrix 21 is approximately 1.55 μm, and M7 is approximately 5.1 μm. In Figure 38 , the diameter Q is approximately 8.6 μm.

[0227] The above description is only a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present disclosure should be included in the scope of protection of the present disclosure. For example, the above-mentioned multiple embodiments provided by the present disclosure can be implemented separately, or the above-mentioned multiple embodiments can be combined without conflict. Therefore, the scope of protection of the present disclosure shall be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising an array substrate and a color filter substrate arranged opposite to each other; wherein: The array substrate comprises: A first substrate and a plurality of first signal lines arranged on one side of the first substrate, wherein the plurality of first signal lines are arranged at intervals along a first direction and extend along a second direction, wherein the first direction intersects the second direction; and A plurality of signal line groups are arranged at intervals along the second direction and extend along the first direction; the plurality of first signal lines and the plurality of signal line groups cross each other to form a grid structure, and an area where the orthographic projections of the signal line groups and the first signal lines on the first substrate overlap protrude toward a side away from the first substrate to form a protruding structure; the signal line groups include winding areas, and the winding area is provided at a position where at least one of the signal line groups crosses the first signal line; The color film substrate includes a second substrate and a plurality of spacers, wherein the plurality of spacers are arranged on a side of the second substrate close to the array substrate, the spacers are strip-shaped and extend along the first direction, the orthographic projection of the spacers on the array substrate partially overlaps with the first signal line and partially overlaps with the signal line group, and the orthographic projection of the spacers on the array substrate in the winding area does not overlap with the protruding structure.

2. The display substrate according to claim 1, wherein: The surface of the spacer away from the second substrate abuts against a portion of the protruding structure.

3. The display substrate according to claim 1 or 2, wherein: The distance between the surface of the spacer away from the second substrate and the second substrate is equal.

4. The display substrate according to any one of claims 1 to 3, wherein: In the winding area, the signal line group protrudes along the first direction.

5. The display substrate according to claim 3 or 4, wherein: The signal line group includes a second signal line, and the orthographic projection of the second signal line on the second substrate partially overlaps with the spacer; The dimension of the spacer along the second direction near the surface of the array substrate is D1, the width of the second signal line along the second direction is D2, and D1 is greater than D2.

6. The display substrate according to claim 3 or 4, wherein: The signal line group includes a second signal line and a third signal line, and the orthographic projection of the spacer on the array substrate also covers the area between the second signal line and the third signal line; The orthographic projection of the spacer on the array substrate partially overlaps with the second signal line, and the orthographic projection of the spacer on the array substrate partially overlaps with the third signal line.

7. The display substrate according to claim 6, wherein: The size of the spacer near the surface of the array substrate in the second direction is D1; ​​the size of the second signal line in the second direction is D2, the size of the third signal line in the second direction is D3, and the interval between the second signal line and the third signal line is D4. D1, D2, D3 and D4 satisfy: D2>D3, D1=D4+D3; or, D1, D2, D3 and D4 satisfy: D3>D2, D1=D4+D2.

8. The display substrate according to claim 6 or 7, wherein: The winding area is provided at a position where at least one of the second signal lines and / or at least one of the third signal lines crosses the first signal line.

9. The display substrate according to claim 8, wherein: The array substrate further includes a first electrode, and the third signal line is connected to the first electrode at one side of the protrusion of the winding area along the first direction.

10. The display substrate according to any one of claims 1 to 9, wherein: The size of the spacer along the first direction is greater than the distance between two adjacent first signal lines.

11. The display substrate according to claim 10, wherein: The multiple spacers include at least one first spacer, the orthographic projection of the first spacer on the array substrate has an overlapping area with at least thirteen of the first signal lines, and has an overlapping area with one of the signal line groups; the winding area is provided at at least eleven of the intersections between the at least thirteen first signal lines and the one signal line group.

12. The display substrate according to claim 11, wherein: A grid structure formed by a plurality of the first signal lines and a plurality of the signal line groups defines a plurality of pixel areas; and at least one first spacer is disposed in every twenty-four pixel areas.

13. The display substrate according to any one of claims 10 to 12, wherein: The multiple spacers include at least one second spacer, whose orthographic projection on the array substrate has an overlapping area with the three first signal lines and an overlapping area with one signal line group; the second spacers are respectively abutted against the protruding structures formed at the intersections of the three first signal lines and the one signal line group.

14. The display substrate according to any one of claims 10 to 13, wherein: The multiple spacers include at least one third spacer, the orthographic projection of the third spacer on the array substrate has an overlapping area with one of the first signal lines and an overlapping area with one of the signal line groups; the third spacer abuts against the protruding structure formed at the intersection of the first signal line and the signal line group.

15. The display substrate according to any one of claims 10 to 14, wherein: The multiple spacers include at least one fourth spacer, the orthographic projection of the fourth spacer on the array substrate has an overlapping area with the three first signal lines and an overlapping area with one signal line group; two winding areas are provided at the intersection of the three first signal lines and the one signal line group; the fourth spacer abuts against the protruding structure formed at the intersection of one of the three first signal lines and the signal line group.

16. The display substrate according to any one of claims 11 to 15, wherein: The multiple spacers include at least one fifth spacer, the orthographic projection of the fifth spacer on the array substrate has an overlapping area with the three first signal lines, and has an overlapping area with one signal line group; the winding area is provided at the intersection of the three first signal lines and the one signal line group; the fifth spacer has no contact with the protruding structure formed at the intersection of the three first signal lines and the one signal line group.

17. The display substrate according to claim 16, wherein: A grid structure formed by the plurality of first signal lines and the plurality of signal line groups defines a plurality of pixel areas; The array substrate includes a plurality of fourth spacers and a plurality of fifth spacers, and at least four of the fourth spacers and four of the fifth spacers are arranged in every forty-eight pixel regions.

18. The display substrate according to claim 17, wherein: A plurality of the fourth spacers and a plurality of the fifth spacers are arranged in a row along the first direction, and a row includes a plurality of the fourth spacers and a plurality of the fifth spacers that are alternately arranged; and / or, A plurality of the fourth spacers and a plurality of the fifth spacers are arranged in a row along the second direction, and one row includes the fourth spacers and the fifth spacers that are alternately arranged.

19. The display substrate according to any one of claims 11 to 18, wherein: The spacer comprises: A main spacer area, the main spacer area abuts against the protruding structure, and the density of the orthographic projection of the main spacer area on the array substrate is 50 to 300 μm 2 / mm 2 ; a first sub-spacer region, wherein the first sub-spacer region has no contact with the protruding structure, and an orthographic projection on the array substrate coincides with the first signal line or the signal line group; and a density of an orthographic projection of the first sub-spacer region on the array substrate is 5000 to 20000 μm 2 / mm 2 .

20. The display substrate according to any one of claims 10 to 19, wherein: The color film substrate also includes: A black matrix is ​​disposed between the second substrate and the spacer, and an orthographic projection of the black matrix on the array substrate covers an orthographic projection of the spacer on the array substrate, the first signal line, and the signal line group.

21. The display substrate according to claim 20, wherein: The black matrix comprises: a first part, wherein an orthographic projection of the first part on the array substrate covers an end of the first signal line close to the signal line group; a second part, the second part is located at a side of the first part away from the signal line group and connected to the first part; A size of the first portion in the first direction is greater than a size of the second portion in the first direction.

22. The display substrate according to claim 1, wherein: The thickness of the first signal line is 0.5 μm to 0.7 μm; and / or, The signal line group has a thickness of 0.5 μm to 0.7 μm.

23. The display substrate according to claim 1, wherein: The orthographic projection of the spacer on the array substrate overlaps with the signal line group or the first signal line in part; the spacer includes a main spacer area with a first thickness and a third sub-spacer area with a second thickness, and the first thickness is greater than the second thickness; the orthographic projection of the main spacer area on the array substrate has an overlapping area with the first signal line, and the orthographic projection of the main spacer area on the array substrate does not overlap with the signal line group.

24. The display substrate according to claim 23, wherein: The orthographic projection of the main spacer area on the array substrate overlaps with at least two of the first signal lines.

25. A display device comprising: The display substrate according to any one of claims 1 to 24; The driving circuit board is electrically connected to the display substrate and is configured to transmit a control signal to the display substrate.

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