Display substrate and display device

Abstract

The display substrate comprises an array substrate and a color film substrate. The array substrate comprises a first substrate, a first conductive layer, a first insulating layer, a first via hole, a semiconductor layer and a connecting electrode. The first conductive layer comprises first signal lines and first patterns which are distributed at intervals. The first insulating layer is arranged on the side, away from the first substrate, of the first conductive layer. The first via hole at least penetrates through the first insulating layer and at least exposes part of the first signal line. The semiconductor layer includes a semiconductor pattern. The semiconductor pattern includes a first portion, a second portion, and a channel structure between the first portion and the second portion. The orthographic projection of the first part on the first substrate is partially overlapped with the orthographic projection of the first signal line on the first substrate, and the orthographic projection of the channel structure on the first substrate is located in the range of the orthographic projection of the first pattern on the first substrate. The connecting electrode is arranged on the side, away from the first substrate, of the semiconductor layer, at least part of the connecting electrode is located in the first via hole, and the connecting electrode is connected with the first part and the first signal line.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, display devices have been widely used, and people's requirements for display devices are getting higher and higher; among them, high pixel density (Pixels Per Inch; PPI for short) is an important development direction of display devices. Common display devices may include liquid crystal display devices (Liquid Crystal Display; LCD for short) and organic light-emitting diode display devices (Organic Light-Emitting Diode; OLED for short). Thanks to the simpler pixel circuit structure of liquid crystal display devices (which can contain fewer thin-film transistors and capacitors), liquid crystal display devices have more advantages in ultra-high pixel density (such as greater than or equal to 1000PPI). As the pixel density increases, the aperture ratio of the display device gradually decreases, resulting in a decrease in the transmittance (transmittance / light transmittance) of the display device. How to improve the aperture ratio and light transmittance of the display device is an important technical problem facing liquid crystal display devices.

[0003] Summary of the Invention

[0004] In one aspect, a display substrate is provided. The display substrate includes an array substrate and a color filter substrate. The array substrate includes a first substrate, a first conductive layer, a first insulating layer, a first via, a semiconductor layer, and a connecting electrode. The first conductive layer is disposed on one side of the first substrate and includes spaced-apart first signal lines and a first pattern. The first insulating layer is disposed on a side of the first conductive layer away from the first substrate. The first via at least penetrates the first insulating layer and exposes at least a portion of the first signal line. The semiconductor layer is disposed on a side of the first insulating layer away from the first substrate and includes a semiconductor pattern. The semiconductor pattern includes a first portion, a second portion, and a channel structure located between the first and second portions. The orthographic projection of the first portion on the first substrate partially overlaps with the orthographic projection of the first signal line on the first substrate, and the orthographic projection of the channel structure on the first substrate is located within the orthographic projection of the first pattern on the first substrate. The connecting electrode is disposed on a side of the semiconductor layer away from the first substrate. At least a portion of the connecting electrode is located within the first via and is connected to the first portion and the first signal line, respectively.

[0005] In some embodiments, the array substrate further includes a first electrode, which is disposed on a side of the film layer where the connecting electrode is located away from the first substrate, and the orthographic projection of the first electrode on the first substrate covers the orthographic projection of the first signal line on the first substrate.

[0006] In some embodiments, the first electrode includes a first extension segment, the first extension segment extending in the same direction as the first signal line extending in the same direction. The orthographic projection of the first extension segment on the first substrate overlaps the orthographic projection of the first signal line on the first substrate, and a first gap is defined between adjacent boundaries of the orthographic projections of the first extension segment and the first signal line on the first substrate. The first gap is 2 μm to 5 μm.

[0007] In some embodiments, the semiconductor layer further includes a second electrode connected to the second portion and integrally disposed with the second portion.

[0008] In some embodiments, an orthographic projection of the second electrode on the first substrate has a second interval from an orthographic projection of the first pattern on the first substrate, and has a third interval from an orthographic projection of the first signal line on the first substrate.

[0009] In some embodiments, the first insulating layer includes a first groove portion that is concave toward the first substrate, the first groove portion being at least partially located between the first signal line and the first pattern. The second interval is greater than or equal to 2 μm; and / or the third interval is greater than or equal to 5 μm.

[0010] In some embodiments, the array substrate further comprises a planar layer located between the first conductive layer and the first insulating layer, wherein a surface of the planar layer away from the first substrate is a planar surface. The orthographic projections of the first conductive layer, the second spacer, and the third spacer on the first substrate are located within the orthographic projection of the planar layer on the first substrate. The second spacer is greater than or equal to 1 μm; and / or the third spacer is greater than or equal to 3 μm.

[0011] In some embodiments, the first insulating layer includes a first groove portion that is recessed toward the first substrate, with at least a portion of the first groove portion located between the first signal line and the first pattern. The first groove portion includes two opposing first sidewalls. The first portion includes two first sub-portions covering the two first sidewalls, and a second sub-portion covering other areas of the first insulating layer. The thickness of the first sub-portion is less than that of the second sub-portion.

[0012] In some embodiments, the array substrate further includes a second insulating layer, the second insulating layer being disposed between the semiconductor layer and the film layer where the connecting electrode is located. The first sub-portion of the two first sub-portions, which is closer to the first signal line, is a target sub-portion, the first via penetrates the second insulating layer and exposes the target sub-portion, the connecting electrode covers the target sub-portion, and the dimension of the channel structure in a direction perpendicular to the first substrate is greater than or equal to

[0013] In some embodiments, the array substrate further includes a second insulating layer, the second insulating layer being disposed between the semiconductor layer and the film layer where the connecting electrode is located. The first sub-section of the two first sub-sections, which is closer to the first signal line, is a target sub-section, the first via hole also penetrates the second insulating layer, and there is a gap between the first via hole and the target sub-section; the dimension of the channel structure in a direction perpendicular to the first substrate is greater than or equal to

[0014] In some embodiments, the array substrate further includes a second insulating layer disposed between the semiconductor layer and the film layer where the connecting electrode is located. The first sub-portion of the two first sub-portions, which is closer to the first signal line, is a target sub-portion. The first via penetrates the second insulating layer and exposes the target sub-portion. There is a gap between the connecting electrode and the target sub-portion. The dimension of the channel structure in a direction perpendicular to the first substrate is greater than or equal to

[0015] In some embodiments, along a direction perpendicular to the first substrate, a size of the first conductive layer is 0.4 μm to 0.8 μm; and / or, in a cross section perpendicular to the first substrate and perpendicular to the extension direction of the edge of the first conductive layer, a first angle is provided between the side wall of the first conductive layer and the first substrate, and the first angle is less than or equal to 50°.

[0016] In some embodiments, the array substrate further comprises a planar layer, the planar layer being located between the first conductive layer and the first insulating layer, wherein a surface of the planar layer away from the first substrate is a planar surface. The planar layer covers at least the first signal line, the first pattern, and the space between the first signal line and the first pattern. The semiconductor layer further comprises a second electrode, the second electrode being connected to the second portion and integrally disposed therewith, wherein an orthographic projection of the second electrode on the first substrate at least partially does not overlap with an orthographic projection of the planar layer on the first substrate.

[0017] In some embodiments, in a cross section perpendicular to the first substrate and perpendicular to the extension direction of the sidewalls of the planar layer, a second angle is formed between the sidewalls of the planar layer and the first substrate, and the second angle is less than or equal to 50°. Furthermore, a distance between a surface of the planar layer remote from the first substrate and the first substrate is 0.4 μm to 0.8 μm.

[0018] In some embodiments, the first conductive layer includes a plurality of first signal lines, which are spaced apart along the first direction and extend along the second direction. The array substrate further includes a plurality of signal line groups, which are spaced apart along the second direction and extend along the first direction. The plurality of first signal lines and the plurality of signal line groups intersect to form a grid structure, and the area where the orthographic projections of the signal line groups and the first signal lines on the first substrate overlap protrudes toward the side away from the first substrate to form a columnar structure. The color filter substrate includes a spacer; the spacer is strip-shaped and extends along the first direction, and the orthographic projection of the spacer on the array substrate partially overlaps with the first signal line and the signal line group. The signal line group includes a winding area, and the winding area is provided at the location where at least one of the signal line groups intersects with the first signal line. The orthographic projection of the spacer on the array substrate within the winding area does not overlap with the columnar structure.

[0019] In some embodiments, a side of the spacer away from the color filter substrate abuts against a portion of the columnar structure.

[0020] In some embodiments, the side of the spacer away from the color filter substrate is at the same distance from the color filter substrate.

[0021] In some embodiments, the signal line group in the winding area protrudes toward the first direction.

[0022] In some embodiments, a dimension of the spacer along the first direction is greater than a distance between two adjacent first signal lines.

[0023] In some embodiments, the signal line group and the connection electrode are made of the same material and are disposed in the same layer.

[0024] In some embodiments, the signal line group includes a second signal line, the orthographic projection of the second signal line on the color filter substrate coincides with the spacer. The second signal line has a dimension C1 in the second direction, and the end of the spacer near the array substrate has a dimension C4 in the second direction, where C4 is greater than C1.

[0025] In some embodiments, the signal line group includes a second signal line and a third signal line, and the orthographic projection of the spacer on the array substrate covers the area between the second signal line and the third signal line; the orthographic projection of the spacer on the array substrate partially overlaps with the second signal line; and the orthographic projection of the spacer on the array substrate partially overlaps with the third signal line.

[0026] In some embodiments, the dimension of the second signal line in the second direction is C1, the dimension of the third signal line in the second direction is C2, the interval between the second signal line and the third signal line is C3, and the dimension of the end of the spacer near the array substrate in the second direction is C4. C1, C2, C3, and C4 satisfy the following: C2>C1, C4=C3+C1; or C1, C2, C3, and C4 satisfy the following: C1>C2, C4=C3+C2.

[0027] In some embodiments, the winding area is provided at a position where at least one of the second signal lines and / or at least one of the third signal lines crosses the first signal line.

[0028] In some embodiments, the array substrate includes a first electrode, and the third signal line is connected to the first electrode on one side of the protrusion in the winding area along the first direction.

[0029] In some embodiments, the orthographic projection of one of the spacers on the array substrate has an overlapping area with at least thirteen of the first signal lines, and has an overlapping area with one of the signal line groups; the winding area is provided at at least eleven of the intersections of the at least thirteen first signal lines and the one signal line group.

[0030] In some embodiments, a grid structure formed by a plurality of the first signal lines and a plurality of the signal line groups defines a plurality of pixel areas; and at least one spacer is disposed in every twenty-four pixel areas.

[0031] In some embodiments, the orthographic projection of the spacer on the array substrate partially overlaps with the signal line group or the first signal line. The spacer includes a main spacer region having a first thickness and a secondary spacer region having a second thickness, wherein the first thickness is greater than the second thickness. The orthographic projection of the main spacer region on the array substrate overlaps with the first signal line, but does not overlap with the signal line group.

[0032] In some embodiments, an orthographic projection of the main spacer area on the array substrate overlaps with at least two of the first signal lines.

[0033] In some embodiments, the color filter substrate further includes a black matrix; the orthographic projection of the black matrix on the array substrate covers the spacer, the first signal line, and the signal line group.

[0034] In some embodiments, the black matrix includes a first part, the orthographic projection of the first part on the array substrate covers the semiconductor pattern, the first pattern, and the area where the signal line group and the first signal line overlap; the first part and the surface of the spacer close to the array substrate have a fourth interval between their mutually adjacent boundaries in the orthographic projection on the array substrate, and the fourth interval is 20μm to 40μm.

[0035] In some embodiments, the black matrix also includes a second part, the orthographic projection of the second part on the array substrate covers an area of ​​the signal line group that is staggered with the first pattern and the semiconductor pattern in the second direction, and the part of the black matrix covering the same signal line group includes the first part and the second part that are staggered along the first direction; the second part and the signal line group have a fifth interval between their mutually adjacent boundaries in the orthographic projection on the array substrate, and the fifth interval is 3μm to 6μm.

[0036] In some embodiments, the first insulating layer includes a first groove portion that is concave toward the first substrate, with at least a portion of the first groove portion being located between the first signal line and the first pattern. The black matrix further includes a third portion, the orthographic projection of the third portion on the array substrate covering the first signal line, and a sixth interval between the third portion and the first signal line, where the orthographic projections of the third portion on the first substrate are close to each other, is defined, and the sixth interval is 0.5 μm to 2 μm.

[0037] In some embodiments, the transmittance of the display substrate is greater than or equal to 6%.

[0038] In some embodiments, the array substrate further comprises a planar layer located between the first conductive layer and the first insulating layer, wherein a surface of the planar layer away from the first substrate is a planar surface. The planar layer comprises a first planar portion, which covers the first signal line. The black matrix comprises a third portion, whose orthographic projection on the array substrate covers the first planar portion, and a seventh interval is defined between adjacent boundaries of the third portion and the first planar portion in their orthographic projections on the first substrate, wherein the seventh interval is 0.5 μm to 2 μm.

[0039] In some embodiments, the transmittance of the display substrate is greater than or equal to 9%.

[0040] In another aspect, a display device is provided, comprising the display substrate according to any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0042] FIG1 is a structural diagram of a display device according to some embodiments;

[0043] FIG2 is a structural diagram of a display substrate according to some embodiments;

[0044] FIG3 is a planar structural diagram of an array substrate according to some embodiments;

[0045] FIG4 is a partial enlarged view of the A1 area in FIG3 ;

[0046] FIG5 is a cross-sectional view taken along the section line B1-B1 in FIG4;

[0047] FIG6 is a planar structural diagram of a pixel region according to some embodiments;

[0048] FIG7 is another planar structural diagram of an array substrate according to some embodiments;

[0049] FIG8 is a partial enlarged view of the A2 area in FIG7;

[0050] FIG9 is a cross-sectional view taken along the section line B2-B2 in FIG8;

[0051] FIG10 is a cross-sectional view taken along section line B3-B3 in FIG3;

[0052] 11 and 12 are diagrams showing a manufacturing process of an array substrate according to some embodiments;

[0053] FIG13 is a partial enlarged view of a thin film transistor according to some embodiments;

[0054] FIG14 is another partial enlarged view of a thin film transistor according to some embodiments;

[0055] FIG15 is a cross-sectional view taken along section line B4-B4 in FIG14;

[0056] FIG16 is another partial enlarged view of a thin film transistor according to some embodiments;

[0057] FIG17 is a cross-sectional view taken along section line B5-B5 in FIG16;

[0058] FIG18 is a cross-sectional structural diagram of an array substrate according to some embodiments;

[0059] FIG19 is another cross-sectional structural diagram of an array substrate according to some embodiments;

[0060] FIG20A is another partial enlarged view of a thin film transistor according to some embodiments;

[0061] FIG20B is another partial enlarged view of a thin film transistor according to some embodiments;

[0062] FIG21 is a cross-sectional view taken along section line B6-B6 in FIG3;

[0063] FIG22 is a cross-sectional view taken along section line B7-B7 in FIG7;

[0064] FIG23 is a top view of a partial structure of a display substrate according to some embodiments;

[0065] FIG24 is a cross-sectional view taken along section line B8-B8 in FIG23;

[0066] FIG25 is a partial structural diagram of a display substrate after being compressed according to some embodiments;

[0067] FIG26 is a top view of another partial structure of a display substrate according to some embodiments;

[0068] FIG27 is an equivalent circuit diagram of an array substrate according to some embodiments;

[0069] FIG28 is a graph showing the thickness of a liquid crystal cell after being subjected to an external force when the spacer is not displaced according to some embodiments;

[0070] FIG29 is a diagram showing the thickness of a liquid crystal cell after a spacer is displaced and subjected to an external force according to some embodiments;

[0071] FIG30 is a graph showing deformation data of a spacer after the spacer is displaced and subjected to external force according to some embodiments;

[0072] FIG31 is a top view of another partial structure of a display substrate according to some embodiments;

[0073] FIG32 is a cross-sectional view taken along section line B9-B9 in FIG31;

[0074] FIG33 is another equivalent circuit diagram of an array substrate according to some embodiments;

[0075] FIG34 is a top view of another partial structure of a display substrate according to some embodiments;

[0076] FIG35 is a cross-sectional view taken along section line B10-B10 in FIG34;

[0077] FIG36 is a cross-sectional view taken along section line C1-C1 in FIG26;

[0078] FIG37 is a cross-sectional view taken along section line C2-C2 in FIG26;

[0079] FIG38 is a cross-sectional view taken along section line C3-C3 in FIG26;

[0080] FIG39 is another cross-sectional view along the section line C3-C3 in FIG26. DETAILED DESCRIPTION

[0081] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0082] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0083] In this disclosure, terms such as "lower," "below," "above," and "upper," and similar terms are used to explain the relationships between components shown in the drawings. These terms may be relative and described based on directions shown in the drawings, or based on the order in which process steps are formed, but are not limited thereto.

[0084] The term "opposite" means that the first element may be directly or indirectly opposite to the second element. In the case where a third element is interposed between the first and second elements, the first and second elements may be understood to be indirectly opposite to each other although they are still opposite to each other.

[0085] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0086] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0087] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0088] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0089] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0090] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0091] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0092] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0093] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0094] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0095] 1 , an embodiment of the present disclosure provides a display device, wherein display device 1000 is a product having an image display function. For example, display device 1000 may be any device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images.

[0096] Exemplarily, the display device 1000 can be a television, a laptop computer, a tablet computer, a personal digital assistant (PDA), a mobile phone (cell phone), a watch, a clock, a calculator, a GPS receiver / navigator, a camera, a camera view display (for example, a display of a rearview camera in a vehicle), a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a mixed reality (MR) device, an in-vehicle display, an aircraft display, or any other product or component with a display function.

[0097] In some embodiments, the display device 1000 may be a liquid crystal display (LCD) device, depending on the type of light emission. The display device 1000 may be a flat display device or a curved display device, for example, depending on the type of drive of the display device and the form of the display device 1000. The display device 1000 may be rectangular or circular, for example. Some embodiments of the present disclosure are described below using a rectangular, flat liquid crystal display device as an example. However, the present disclosure is not limited thereto, and any other display device may also be considered, as long as the same technical concept is applied.

[0098] In some embodiments, referring to FIG2 , the display device 1000 includes a display substrate 1100 (also referred to as a display panel) and a driver circuit board (not shown in the figure). The driver circuit board may include, for example, a timing controller (TCON), a power management chip (DC / DC), and an adjustable resistor divider circuit (generating Vcom) and other driving circuits. The driver circuit board may also include other circuit structures, which are not listed here one by one. The driver circuit board is electrically connected to the display substrate 1100 and is used to transmit a control signal to the display substrate 1100, thereby driving the display substrate 1100 to realize image display. In addition, the display device 1000 may also include a touch structure, an under-screen camera, and an under-screen fingerprint recognition sensor, so that the display device 1000 can realize a variety of different functions such as touch, photo taking, video recording or fingerprint recognition, which are not listed here one by one.

[0099] Continuing with FIG. 2 , if the display device 1000 is a liquid crystal display device, the display device 1000 may further include a backlight source 1200 disposed on the backlight side of the display substrate 1100. For example, the backlight source 1200 may be a direct-lit backlight source or an edge-lit backlight source, and is configured to provide light for the display substrate 1100. The display substrate 1100 includes a plurality of sub-pixels, each of which can adjust the amount of light passing through the display substrate 1100, thereby enabling each sub-pixel to display the same or different grayscales, thereby achieving image display.

[0100] Continuing to refer to FIG2 , in the case where the display substrate 1100 is a liquid crystal display substrate, the display substrate 1100 may include an array substrate 100 and a color filter substrate 200 that are arranged opposite to each other, and a liquid crystal layer 300 disposed between the array substrate 100 and the color filter substrate 200, wherein the color filter substrate 200 may also be referred to as an opposing substrate or a packaging substrate. Of course, the structure of the display substrate 1100 is not limited to this, and the display substrate 1100 may also include other structures as long as the same technical concept is adopted. For example, the display substrate 1100 may also include a first alignment film (not shown in the figure) disposed on the side of the array substrate 100 close to the liquid crystal layer 300, and a second alignment film (not shown in the figure) disposed on the side of the color filter substrate 200 close to the liquid crystal layer 300, etc.

[0101] The array substrate 100 can be an Advanced Super Dimension Switch (ADS) type or a high-aperture ratio High-Advanced Dimension Switch (HADS) type. ADS technology uses the electric field generated by the edges of slit electrodes in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer to form a multi-dimensional electric field, enabling all oriented liquid crystal molecules between the slit electrodes and directly above the electrodes in the liquid crystal cell to rotate, thereby improving the operating efficiency of the liquid crystal and increasing light transmission efficiency. It also has advantages such as high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low color difference, and no push mura. Furthermore, the array substrate 100 can include a display area and a peripheral area disposed around the display area. The display area can include multiple pixel circuits, pixel electrodes, and a first electrode, while the peripheral area can include, for example, a gate driver on array (GOA).

[0102] The color filter substrate 200 may include a filter and a black matrix. The filter is used to filter light incident on the color filter substrate 200 so that each sub-pixel emits light of a single color (e.g., red, green, or blue). Different sub-pixels can emit light of the same or different colors, thereby enabling the display substrate 1100 to achieve color display. The black matrix is ​​used to cover the transistors and signal lines on the array substrate to improve the contrast of the display substrate.

[0103] In liquid crystal display devices, the transmittance of the display substrate 1100 is an important indicator. Improving the transmittance of the display substrate 1100 not only increases the brightness of the display device, but also reduces the power consumption of the display device's backlight source 1200, thereby reducing the overall power consumption of the display device. Conventional ADS liquid crystal display substrates include multiple signal lines located on an array substrate and a black matrix located on a color filter substrate. The orthographic projection of the black matrix on the array substrate covers the multiple signal lines to reduce light leakage from the signal lines and the areas surrounding the signal lines. However, due to the size of the black matrix in the color filter substrate, the transmittance of the display substrate is relatively low.

[0104] Figure 3 is a partial structural diagram of the display area when the array substrate does not include a planar layer. Figure 4 is a partial structural diagram of the thin film transistor area of ​​the array substrate. Figure 5 is a cross-sectional structural diagram of the thin film transistor area when the array substrate does not include a planar layer.

[0105] Referring to Figures 3, 4, and 5, to improve the transmittance of a display substrate, some embodiments of the present disclosure provide an array substrate 100. The array substrate 100 includes a first substrate 110 and a first conductive layer SD, a first insulating layer BUF, a semiconductor layer ACT, and a connecting electrode 20, which are sequentially arranged in a direction away from the first substrate 110. Furthermore, the array substrate 100 further includes a first via V1 that penetrates at least the first insulating layer BUF.

[0106] Exemplarily, the first substrate 110 may be a rigid substrate. The rigid substrate may be, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate. The first substrate 110 may also be a flexible substrate. For example, the flexible substrate may be a PET (Polyethylene terephthalate) substrate, a PI (Polyimide) substrate, or a PEN (Polyethylene naphthalate two formic acid glycol ester) substrate. Exemplarily, the first substrate 110 may be a transparent substrate, so that light emitted by the backlight source can pass through the first substrate 110, which is beneficial to improving the transmittance of the array substrate 100.

[0107] The first conductive layer SD is disposed on one side of the first substrate 110 and includes first signal lines DL and first patterns LS that are spaced apart. In the embodiments of the present disclosure, the first signal lines DL and the first patterns LS are formed from the same material and disposed on the same layer. For example, the first patterns LS and the first signal lines DL are formed using the same mask and / or the same material in the same patterning process.

[0108] The first signal line DL and the first pattern LS are both arranged on the side of the semiconductor layer ACT close to the first substrate 110. On the one hand, this helps to reduce the parasitic capacitance between the first signal line DL and other structures (such as the first electrode 21 and the second electrode 22), thereby improving the pixel density and refresh rate of the array substrate 100, and helps to reduce the power consumption of the first signal line DL and reduce the overall power consumption of the array substrate 100. On the other hand, it helps to increase the distance between the first signal line DL and the liquid crystal layer. It can also reduce the impact of the electric field generated by the first signal line DL on the liquid crystal molecules of the liquid crystal layer, reduce the area of ​​the light leakage area caused by the first signal line DL, and help to reduce the size of the black matrix used to shield the first signal line DL, thereby improving the aperture ratio of the display substrate and improving the transmittance of the display substrate.

[0109] Exemplarily, the first signal line DL is provided on the first substrate 110, and the first signal line DL may be a data signal line configured to transmit a data signal. Of course, in some other examples, the first signal line DL may also be used to transmit other signals, as long as the same technical idea is adopted. The first pattern LS may be a light-shielding pattern, which may be configured to block the channel structure 13 of the semiconductor layer ACT to reduce the light directed toward the channel structure 13 and reduce the risk of drift of the thin film transistor under the illumination of the backlight source. Exemplarily, the orthographic projection of the first pattern LS on the first substrate 110 overlaps at least partially (for example, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 98%, at least 99% or 100%) with the orthographic projection of the channel structure 13 on the first substrate 110.

[0110] In some embodiments, the material of the first conductive layer SD may include a conductive material, and the conductive material may include a metal material, for example, one or more of metal titanium, aluminum, copper, molybdenum, niobium, nickel and alloys thereof, or the first conductive layer SD may also be a metal stacked structure. Exemplarily, the first conductive layer SD may include a titanium-aluminum-titanium (Ti / Al / Ti) stacked structure, a molybdenum-aluminum (Mo / Al) stacked structure, a molybdenum-aluminum-molybdenum (Mo / Al / Mo) stacked structure, a molybdenum-niobium-titanium (MoNb / Ti) stacked structure, a molybdenum-niobium-titanium-copper (MoNb / Ti / Cu) stacked structure, a molybdenum-niobium-copper (MoNb / Cu) stacked structure, a molybdenum-nickel-titanium-copper (MTD / Cu) stacked structure, a molybdenum-niobium-copper-molybdenum-titanium-nickel (MoNb / Cu / MTD) stacked structure, a molybdenum-nickel-titanium-copper-molybdenum-nickel-titanium (MTD / Cu / MTD) stacked structure, a molybdenum-neodymium-copper stacked structure, a MoNb-copper-MoNb stacked structure, and an AlNb-molybdenum-AlNd stacked structure, or a combination thereof. Of course, the embodiments of the present disclosure are not limited thereto, and the first conductive layer SD may also consider any other suitable metal or metal stacked structure. In addition, the thickness of the first conductive layer SD may be (angstrom; )~ For example, the thickness of the first conductive layer SD may be or Etc., the embodiments of the present disclosure will not list them one by one.

[0111] The first insulating layer BUF is disposed on a side of the first conductive layer SD away from the first substrate 110. The first insulating layer BUF may include an insulating material. The first insulating layer BUF may be used to cover at least a portion of the first signal line DL to prevent the first signal line DL from short-circuiting with a conductive structure disposed above the first signal line DL (e.g., the second signal line 32).

[0112] For example, the material of the first insulating layer BUF may include a silicon oxide compound (SiOx, x>0). In some embodiments, the value of x may be 1 or 2. The material of the first insulating layer BUF may also include a silicon nitride compound (SiNy, y>0). In some embodiments, the value of y may be 1-2, such as SiN and SiN1.33. The first insulating layer BUF may be a single layer or a stacked layer structure. In some embodiments, the first insulating layer BUF is a stacked layer structure including a silicon oxide compound and a silicon nitride compound. In addition, the thickness of the first insulating layer BUF may be 100 nm to 700 nm. For example, the thickness of the first insulating layer BUF may be 100 nm, 300 nm, 550 nm, or 700 nm, etc., which are not listed one by one in the embodiments of the present disclosure.

[0113] The first via hole V1 penetrates at least the first insulating layer BUF and exposes at least a portion of the first signal line DL to facilitate connecting the first signal line DL to the semiconductor layer ACT (first portion 11). The first portion 11 is configured to be connected to the first signal line DL through the first via hole V1, so that the first signal line DL can transmit a data signal to the first portion 11.

[0114] The semiconductor layer ACT is located on a side of the first insulating layer BUF away from the first substrate 110. The semiconductor layer ACT includes a plurality of semiconductor patterns 10, each of which is configured to form a thin film transistor (TFT). That is, a thin film transistor may include one semiconductor pattern 10. Figures 4 and 5 both exemplarily illustrate a thin film transistor and one semiconductor pattern 10. The semiconductor pattern 10 may include a first portion 11, a second portion 12, and a channel structure 13 located between the first portion 11 and the second portion 12. The channel structure 13 is configured to form the channel structure of a TFT. One of the first portion 11 and the second portion 12 is configured to form the source electrode (or source connection region) of the TFT, and the other is configured to form the drain electrode (or drain connection region) of the TFT.

[0115] In some embodiments, the orthographic projection of the first portion 11 on the first substrate 110 partially overlaps with the orthographic projection of the first signal line DL on the first substrate 110. In this way, the formation of a first via hole V1 with a larger depth between the first portion 11 and the first signal line DL during the preparation process of the array substrate 100 (see below) can be reduced, thereby reducing the difficulty of the connecting electrode 20 climbing the side wall of the first via hole V1, which is beneficial to improving the continuity of the connecting electrode 20 in the first via hole V1 and ensuring the connection stability between the first portion 11 and the first signal line DL.

[0116] The orthographic projection of the channel structure 13 on the first substrate 110 is located within the range of the orthographic projection of the first pattern LS on the first substrate 110. Based on this, the first pattern LS can block the light from the backlight source to the channel structure 13 to a great extent, thereby reducing the risk of threshold voltage drift of the channel structure 13 under lighting conditions.

[0117] For example, as shown in Figure 4, the orthographic projection of the first pattern LS on the first substrate 110 completely covers the orthographic projection of the channel structure 13 on the first substrate 110, and at least part of the boundary of the orthographic projection of the first pattern LS on the first substrate 110 (the entire boundary of the first pattern LS in Figure 4) does not overlap with the boundary of the orthographic projection of the channel structure 13 on the first substrate 110. That is, the area of ​​the first pattern LS is larger than the area of ​​the channel structure 13, so that the first pattern LS can block as much light as possible from being directed to the channel structure 13.

[0118] In some embodiments, the semiconductor layer ACT includes a Hall mobility of 10-30 cm 2 In some embodiments, the semiconductor layer ACT includes a metal oxide material with a Hall mobility greater than or equal to 30 cm 2 / Vs metal oxide materials.

[0119] For example, the semiconductor layer ACT can be manufactured using various suitable semiconductor materials and various suitable manufacturing methods. In other words, the material of the semiconductor layer ACT can include at least one of various suitable semiconductor materials. In some embodiments, the semiconductor material includes M1OaNb, where M1 is a single metal or a combination of multiple metals, a>0 and b≥0, O represents oxygen, and N represents nitrogen. In other words, the semiconductor material is a metal oxide material or a metal oxynitride material. Suitable metal oxide materials include, but are not limited to, one or more of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxide (In-free OS), rare earth-doped oxides (Ln-OS, such as rare earth-doped IGZO / IZO), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O. The material of the semiconductor layer ACT can be amorphous, partially crystalline, single crystal, or polycrystalline, and can also have a single-layer or multi-layer structure.

[0120] Suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or combinations thereof. In one example, the material of the semiconductor layer ACT includes indium gallium zinc oxide (IGZO).

[0121] In some embodiments, the first portion 11, the second portion 12, and the channel structure 13 are an integral structure, and the materials of the channel structure 13, the first portion 11, and the second portion 12 all include M1OaNb. The first portion 11 and the second portion 12 differ from the channel structure 13 in that the first portion 11 and the second portion 12 undergo a process (conductorization process) to make them more conductive. The conductivity of the channel structure 13 is different from the conductivity of the first portion 11 and the conductivity of the second portion 12.

[0122] For example, the channel structure 13 may include a semiconductor material, and the second portion 12 and the first portion 11 may include a doped semiconductor material. In this way, the second portion 12 and the first portion 11 may form a conductor, and the channel structure 13 may form a semiconductor.

[0123] In one example, when the materials of the channel structure 13, the first portion 11, and the second portion 12 all include M1OaNb, the M1OaNb in the first portion 11 and the second portion 12 undergo a light doping process (e.g., a light doping ion implantation process). In another example, when the materials of the channel structure 13, the first portion 11, and the second portion 12 include M1OaNb, the M1OaNb in the first portion 11 and the second portion 12 undergo an annealing process. In another example, when the materials of the channel structure 13, the first portion 11, or the second portion 12 include M1OaNb, the M1OaNb in the first portion 11 or the second portion 12 undergoes an oxide replenishment process. Exemplarily, a process in the range of about 1×10 15 atoms / cm 3 to about 1×10 20 atoms / cm 3 The doping concentration range is about 1×10 15 atoms / cm 3 to about 1×10 16 atoms / cm 3 , about 1×10 16 atoms / cm 3 to about 1×10 17 atoms / cm 3 , about 1×10 17 atoms / cm 3 to about 1×10 18 atoms / cm 3 , about 1×10 18 atoms / cm 3 to about 1×10 20 atoms / cm 3 , and about 1×10 19 atoms / cm 3 to about 1×10 20 atoms / cm 3 , to perform a light doping process. Exemplarily, the light doping process is performed using an N-type dopant to enhance conductivity. Examples of N-type dopants may include elements from Group VA of the periodic table, including but not limited to nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). Protective gas elements such as argon (Ar), helium (He), oxygen (O), hydrogen (H), and fluorine (F) may also be used to perform the light doping process.

[0124] FIG6 is a structural diagram of the array substrate 100 after the first electrode 21 is removed based on FIG3 .

[0125] In some embodiments, referring to Figures 5 and 6, the semiconductor layer ACT also includes a second electrode 22, which is connected to the second portion 12 and is integrally arranged with the second portion 12. The second electrode 22 is arranged on the same layer as the semiconductor pattern 10, which is beneficial to simplifying the preparation process of the array substrate 100 (the number of masks of the array substrate 100 can be reduced to 6 masks), reducing the thickness and preparation cost of the array substrate 100, and is beneficial to improving the light transmittance of the array substrate.

[0126] Exemplarily, the second electrode 22 may be a pixel electrode of the array substrate 100 . One second electrode 22 is electrically connected to one thin film transistor (the second portion 12 of the semiconductor pattern 10 ) and is configured to receive a data signal transmitted by the first signal line DL.

[0127] For example, the second electrode 22 comprises the same material and is fabricated in the same layer as the first and second portions 11 and 12. To improve the conductivity of the second electrode 22, the second electrode 22 may be fabricated using the same conductive process as the first and second portions 11 and 12, so that the conductivity of the second electrode 22 is comparable to that of the first and second portions 11 and 12 and greater than the conductive lines of the channel structure 13. For the conductive process that can be used for the second electrode 22, refer to the conductive process that can be used for the first and second portions 11 and 12, and will not be further described here.

[0128] Furthermore, to improve the transmittance of the array substrate 100, the second electrode 22 may be formed of a transparent conductive material. A transparent conductive material refers to a conductive material having a light transmittance greater than a first threshold value. The first threshold value may be, for example, 80%, 85%, 90%, 95%, or other suitable values, which are not listed here. In other words, the semiconductor layer ACT is made of a transparent semiconductor material, which includes one or more of the semiconductor materials described above, which are not further described here.

[0129] In some embodiments, referring to FIG. 6 , a dimension L1 of the second electrode 22 along the first direction X is less than or equal to 1000 μm, and / or a dimension L2 of the second electrode 22 along the second direction Y is less than or equal to 1000 μm. This helps improve the uniformity of the conductive treatment of the second electrode 22 during the conductive treatment process. In other words, the conductivity of the second electrode 22 can be made substantially uniform across the second electrode 22, which helps improve the conductivity of the second electrode 22.

[0130] For example, the dimension L1 of the second electrode 22 along the first direction X can be 300 μm, 600 μm, 750 μm, 900 μm, or 1000 μm, etc.; the dimension L2 of the second electrode 22 along the second direction Y can be 400 μm, 600 μm, 800 μm, 950 μm, or 1000 μm, etc., which are not listed one by one in the embodiments of the present disclosure. The dimension L1 of the second electrode 22 along the first direction X and the dimension L2 along the second direction Y can be equal, or the dimension L1 of the second electrode 22 along the first direction X and the dimension L2 along the second direction Y can be different. For example, the dimension L2 of the second electrode 22 along the second direction Y is greater than the dimension L1 of the second electrode 22 along the first direction X. In this way, the second electrode 22 can form a substantially rectangular structure.

[0131] In some embodiments, the first insulating layer BUF is an inorganic insulating layer, typically formed using a thin film deposition process. Referring to FIG. 5 , the first insulating layer BUF can be directly disposed on the first conductive layer SD. For example, the first insulating layer BUF is in direct contact with the first conductive layer SD. In this case, the first insulating layer BUF includes a first groove 41 that is concave toward the first substrate 110 (concave from top to bottom in FIG. 5 ). At least a portion of the first groove 41 is located between the first signal line DL and the first pattern LS. In other words, the surface of the first insulating layer BUF has an undulating topography that matches the topography of the surface of the first conductive layer SD away from the first substrate 110. This simplifies the fabrication process of the array substrate 100 and reduces the difficulty and cost of fabricating the array substrate 100.

[0132] Figure 7 is a local structural diagram of the display area when the array substrate includes a flat layer; Figure 8 is a local enlarged diagram of the position of the thin film transistor when the array substrate includes a flat layer; Figure 9 is a cross-sectional structural diagram of the thin film transistor when the array substrate includes a flat layer.

[0133] In other embodiments, referring to Figures 7, 8, and 9, the array substrate 100 further includes a planarization layer SOG, which is located between the first conductive layer SD and the first insulating layer BUF. The surface of the planarization layer SOG away from the first substrate 110 is a planar surface. Exemplarily, the orthographic projection of the planarization layer SOG on the first substrate 110 at least covers the orthographic projection of the first conductive layer SD on the first substrate 110, that is, the planarization layer SOG at least covers the first signal line DL and the first pattern LS. This helps improve the planarization of the portion of the first insulating layer BUF that covers the first conductive layer SD, thereby improving the planarization of the portion where the semiconductor layer ACT overlaps the first conductive layer SD. This reduces the risk of uneven thickness or even local fracture of the semiconductor layer ACT due to height differences on the surface where the semiconductor layer ACT is located, thereby improving the performance of the semiconductor layer ACT.

[0134] Exemplarily, the flat layer SOG can fill the gap between the first signal line DL and the first pattern LS, so that the surface of the first insulating layer BUF between the first signal line DL and the first pattern LS and away from the first substrate 110 is flat, which is beneficial to reducing the uneven thickness of the first part 11 in the area between the first signal line DL and the first pattern LS, improving the uniformity of the thickness of the first part 11, and thereby improving the connection reliability between the first part 11 and the first signal line DL.

[0135] Exemplarily, the planarization layer SOG may be an organic insulating layer. For example, the material of the planarization layer SOG may be a silicon-on-glass bonding structure (Silicon On Glass; SOG for short) material.

[0136] 5 and 9 , the array substrate 100 further includes a second insulating layer GI. The second insulating layer GI is located on a side of the semiconductor layer ACT away from the first insulating layer BUF. For example, the second insulating layer GI is located between the semiconductor layer ACT and the connecting electrode 20 .

[0137] The material of the second insulating layer GI may include an insulating material, and the insulating material may be, for example, silicon oxide. Of course, the second insulating layer GI is not limited thereto, and any other suitable material may also be used. The second insulating layer GI may be a single layer or a multilayer structure. In addition, the thickness of the second insulating layer GI may be For example, the thickness of the second insulating layer GI may be or Etc., the embodiments of the present disclosure will not list them one by one.

[0138] In some embodiments, referring to Figures 4 and 5 or Figures 8 and 9 , the array substrate 100 further includes a connecting electrode 20, which is located on a side of the semiconductor layer ACT away from the first substrate 110. At least a portion of the connecting electrode 20 is located within the first via hole V1, and the connecting electrode 20 is electrically connected to the first signal line DL and the first portion 11, respectively, thereby electrically connecting the first signal line DL and the first portion 11. In other words, the first portion 11 is configured to be electrically connected to the first signal line DL via the connecting electrode 20, and the first portion 11 is indirectly electrically connected to the first signal line DL via the connecting electrode 20.

[0139] In some embodiments, referring to FIG. 7 , the array substrate 100 further includes a plurality of signal line groups 30 , which are spaced apart along the second direction Y and extend along the first direction X. The plurality of first signal lines DL and the plurality of signal line groups 30 intersect to form a grid structure, each of which defines a pixel area 101 .

[0140] The pixel area 101 can be a red pixel area, a green pixel area, or a blue pixel area. Each pixel area 101 is controlled by one of the first signal lines DL and a signal line group 30 that surround the pixel area 101. For example, under the control of the signal line group 30, the first signal line DL transmits a data signal to the second electrode 22 of the pixel area 101. An electric field can be generated between the second electrode 22 and the first electrode 21 to drive the liquid crystal molecules in the liquid crystal layer to deflect. The deflection angle of the liquid crystal molecules can control the polarization direction of light passing through the pixel area 101 and, in conjunction with the polarizer, achieve different grayscale displays.

[0141] FIG7 only exemplarily illustrates a portion of two signal line groups 30 and four first signal lines DL in the array substrate. In the embodiment of the present disclosure, the length direction (extension direction) of the signal line group 30 is a first direction X, and the length direction (extension direction) of the first signal line DL is a second direction Y. The first direction X and the second direction Y intersect with each other, and exemplarily, the first direction X and the second direction Y are perpendicular to each other. Where at least one orthographic projection of the signal line group 30 and the first signal line DL overlap, the signal line group 30 may extend along the first direction X, forming a primary spacer region for the spacer at this projection. Where at least one orthographic projection of the signal line group 30 and the first signal line DL overlaps, the signal line group 30 may be a fold line, which may form a recess on the signal line group 30. The recess is recessed toward a side away from the center of the signal line group 30 along the second direction Y, and is configured to form a secondary spacer region. The specific shape and structure of the signal line group 30 will be described below.

[0142] In some embodiments, referring to Figures 4 and 8, the signal line group 30 includes at least a second signal line 32. Exemplarily, the second signal line 32 is configured to transmit a gate signal to the thin film transistor TFT. The second signal line 32 includes a main extension portion 321 and a gate portion 322. The main extension portion 321 extends along a first direction X, and the gate portion 322 protrudes from the main extension portion 321 along a second direction Y to form a gate of the thin film transistor. The main extension portion 321 and the gate portion 322 include the same material and are located on the same layer. Exemplarily, the main extension portion 321 and the gate portion 322 are an integral structure. In this case, the gate portion 322 can be regarded as a branch structure extending outward (perpendicular to the extension direction X of the second signal line 32) from the main extension portion 321.

[0143] 8 and 9 , the size of the gate portion 322 can define the area of ​​the channel structure 13. Exemplarily, the orthographic projection of the channel structure 13 on the first substrate 110 is within the range of the orthographic projection of the gate portion 322 on the first substrate 110. Alternatively, the portion of the semiconductor pattern 10 where the orthographic projection on the first substrate 110 overlaps with the orthographic projection of the gate portion 322 on the first substrate 110 constitutes the channel structure 13. The portion of the semiconductor pattern 10 located on the side of the channel structure 13 closer to the first via V1 constitutes the first portion 11, and the portion of the semiconductor pattern 10 located on the side of the channel structure 13 farther from the first via V1 constitutes the second portion 12.

[0144] A thin film transistor may include a gate portion 322, a first portion 11, a second portion 12, and a channel structure 13. One of the first portion 11 and the second portion 12 forms the source connection region of the thin film transistor (for example, the first portion 11 forms the source connection region), and the other forms the drain connection region of the thin film transistor (for example, the second portion 12 forms the drain connection region). The channel structure 13 forms the channel of the thin film transistor, and the gate portion 322 forms the gate of the thin film transistor. The thin film transistor is turned on or off under the control of the gate portion 322. In other words, under the control of the gate portion 322, the channel structure 13 electrically connects the first portion 11 and the second portion 12 (the thin film transistor is turned on), or, under the control of the gate portion 322, the channel structure 13 electrically insulates the first portion 11 and the second portion 12 (the thin film transistor is turned off).

[0145] In some embodiments, the first pattern LS can also be used to transmit electrical signals. In this case, the first pattern LS can be electrically connected to the second signal line 32. The first pattern LS constitutes the gate of the thin-film transistor, and the thin-film transistor has a dual-gate structure. Alternatively, in other embodiments, the first pattern LS may not be used to transmit electrical signals. For example, the first pattern LS is electrically insulated from the second signal line 32. In this case, the thin-film transistor has a top-gate structure including the gate portion 322.

[0146] In some embodiments, referring to FIG9 , the connecting electrode 20 and the signal line group 30 include the same material and are arranged in the same layer, or in other words, the connecting electrode 20 and the second signal line 32 include the same material and are arranged in the same layer. For example, the connecting electrode 20 and the signal line group 30 are formed using the same mask and / or the same material in the same patterning process. Compared with using an additional film layer and process to prepare the connecting electrode 20, the connecting electrode 20 and the signal line group 30 include the same material and are arranged in the same layer, which is conducive to simplifying the preparation process of the array substrate 100 and reducing the preparation cost of the array substrate 100. For example, in the embodiment of the present disclosure, the film layer where the connecting electrode 20 and the signal line group 30 are located is the gate conductive layer Gate.

[0147] In some embodiments, referring to FIG9 , the first portion 11 , the channel structure 13 , and the second portion 12 are arranged substantially in a straight line. In other words, the first portion 11 , the channel structure 13 , and the second portion 12 extend substantially in a straight line. This helps reduce the width of the thin-film transistor (the dimension along the second direction Y), thereby reducing the area of ​​the black matrix on the color filter substrate, thereby increasing the aperture ratio of the display substrate and thereby improving the transmittance of the display substrate.

[0148] It should be noted that the orthographic projection of the black matrix on the color filter substrate on the array substrate at least covers the thin film transistors. The black matrix can reduce the ambient light incident on the thin film transistors, thereby reducing the reflection of ambient light by the thin film transistors and improving the display quality of the display substrate.

[0149] In some embodiments, referring to FIG9 , the first portion 11, the channel structure 13, and the second portion 12 extend substantially along the first direction X. That is, the arrangement direction of the first portion 11, the channel structure 13, and the second portion 12 is substantially parallel to the extension direction of the second signal line 32, and the first portion 11, the channel structure 13, and the second portion 12 are disposed close to the second signal line 32. This greatly reduces the space occupied by the thin-film transistor and the second signal line 32 in the second direction Y, and also greatly reduces the area of ​​the black matrix on the color filter substrate, thereby improving the aperture ratio of the display substrate and, in turn, the transmittance of the display substrate.

[0150] In some embodiments, the material connecting the electrode 20 and the signal line group 30 may include a metal material. For example, the connecting electrode 20 and the signal line group 30 may be a metal laminate structure. The metal laminate structure may refer to the metal laminate structure of the first signal line DL mentioned above, which will not be described in detail here. The material connecting the electrode 20 and the signal line group 30 may be the same as the material of the first signal line DL, or the material connecting the electrode 20 and the signal line group 30 may be different from the material of the first signal line DL. In addition, the thickness of the connecting electrode 20 and the signal line group 30 may be 200nm to 1200nm. For example, the thickness of the connecting electrode 20 and the signal line group 30 may be 200nm, 500nm, 950nm or 1200nm, etc. The embodiments of the present disclosure will not list them one by one.

[0151] In some embodiments, referring to FIG. 3 and FIG. 10 , the array substrate further includes a first electrode 21. The first electrode 21 is disposed on a side of the film layer where the connection electrode 20 is located, away from the first substrate 110. The orthographic projection of the first electrode 21 on the first substrate 110 covers the orthographic projection of the first signal line DL on the first substrate 110. Thus, the first electrode 21 can shield the liquid crystal layer from the electric field generated by the first signal line DL, thereby reducing the area of ​​light leakage from the liquid crystal layer caused by voltage fluctuations of the first signal line DL, thereby facilitating a reduction in the area of ​​the black matrix on the color filter substrate.

[0152] Exemplarily, the first electrode 21 can be a common electrode of the array substrate 100. In this way, when the array substrate 100 is working, the first electrode 21 is connected to the constant voltage signal end, and the voltage on the first electrode 21 will not be affected by the voltage fluctuation of the first signal line DL, thereby reducing the risk of voltage fluctuation on the first electrode 21.

[0153] In some embodiments, as shown in Figures 3 and 4, the first electrode 21 also covers at least a portion of the pixel area 101. For example, the first electrode 21 includes a plurality of slit openings (Slit) 23, so that the first electrode 21 forms a plurality of slit electrodes 24, which facilitates the array substrate 100 to form an ADS type array substrate.

[0154] The material of the first electrode 21 may include, for example, a transparent conductive material to allow light emitted from the backlight to pass through the first electrode 21. Transparent conductive materials include, but are not limited to, at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and IGZO. Furthermore, the thickness of the first electrode 21 may be 40 nm to 135 nm. For example, the thickness of the first electrode 21 may be 40 nm, 80 nm, 100 nm, or 135 nm, etc., which are not listed in detail in the embodiments of the present disclosure.

[0155] In some embodiments, referring to FIG3 and FIG10 , the first electrode 21 includes a first extension segment 24. The first extension segment 24 extends in the same direction as the first signal line DL. The orthographic projection of the first extension segment 24 on the first substrate 110 overlaps the orthographic projection of the first signal line DL on the first substrate 110. A first gap D1 is defined between the boundary of the orthographic projection of the first extension segment 24 on the first substrate 110 and the boundary of the orthographic projection of the first signal line DL on the first substrate 110. The first gap D1 is 2 μm to 5 μm. This significantly improves the coverage of the first signal line DL by the first extension segment 24, enhances the shielding effect of the first extension segment 24 on the electric field of the first signal line DL, and significantly reduces the impact of the electric field generated by the first signal line DL on the liquid crystal layer. This helps reduce the width of the portion of the black matrix on the color filter substrate that covers the first signal line DL, thereby increasing the aperture ratio of the display substrate. For example, the value of the first gap D1 can be 2 μm, 3 μm, 4 μm, 4.5 μm, or 5 μm, etc., which are not listed in detail in the embodiments of the present disclosure.

[0156] In some embodiments, referring to Figures 4 and 8, the orthographic projection of the second electrode 22 on the first substrate 110 and the orthographic projection of the first pattern LS on the first substrate 110 have a second interval D2. The second interval D2 is beneficial to reducing the parasitic capacitance between the second electrode 22 and the first pattern LS, and is beneficial to reducing the risk of signal interference between the gate portion 322 and the second electrode 22.

[0157] Continuing with reference to FIG4 and FIG8 , a third distance D3 is defined between the orthographic projection of the second electrode 22 on the first substrate 110 and the orthographic projection of the first signal line DL on the first substrate 110. The third distance D3 facilitates increasing the spacing between the second electrode 22 and the first signal line DL, reducing the risk of a short circuit between the second electrode 22 and the first signal line DL, and lowering the magnitude of parasitic capacitance generated between the second electrode 22 and the first signal line DL. This, in turn, reduces signal crosstalk between the second electrode 22 and the first signal line DL. For example, this can reduce the magnitude of voltage fluctuations on the second electrode 22 caused by voltage fluctuations on the first signal line DL.

[0158] In some embodiments, referring to Figures 4 and 5, when the first insulating layer BUF is directly disposed on the first conductive layer SD, that is, the first insulating layer BUF includes a first groove portion 41 that is concave in a direction close to the first substrate 110, and the first groove portion 41 is at least partially located between the first signal line DL and the first pattern LS, the undulating morphology of the first insulating layer BUF is close to the edge position of the first pattern LS, and at this time the second interval D2 is greater than or equal to 2μm, that is, D2≥2μm; this can not only greatly reduce the risk of signal interference between the gate portion 322 and the second electrode 22, but also reduce the risk of residual second electrode 22 at the edge position close to the first pattern LS, which is beneficial to reducing the development difficulty during the preparation process of the semiconductor layer ACT, and is beneficial to improving the flatness of the second electrode 22 at the edge position close to the first pattern LS (hereinafter referred to as the first region), improving the electric field uniformity of the first region, and reducing the risk of light leakage in the liquid crystal layer in the first region.

[0159] For example, the second interval D2 may be in the range of 2 μm to 3 μm, or in the range of 3 μm to 4 μm, or in the range of 4 μm to 6 μm, etc. For example, the second interval D2 may be 2 μm, 2.5 μm, 3 μm, 3.5 μm, or 4 μm, etc., which are not listed in detail in the embodiments of the present disclosure.

[0160] It should be understood that, as shown in FIG5 , when the first insulating layer BUF is directly disposed on the first conductive layer SD, the surface of the first insulating layer BUF away from the first substrate 110 exhibits an undulating topography at the edges of the first pattern LS and the first signal line DL. The semiconductor layer ACT is prepared by forming a continuous, unbroken initial semiconductor layer on the surface of the first insulating layer BUF. The initial semiconductor layer also exhibits an undulating topography at the edges of the first pattern LS and the first signal line DL. The distance between the portion of the initial semiconductor layer above the first pattern LS and the first substrate 110 is greater than the distance between the portion of the initial semiconductor layer within the pixel region and the first substrate 110. A photoresist is then coated on the initial semiconductor layer. The thickness of the photoresist above the first pattern LS is less than the thickness of the photoresist within the pixel region 101. The photoresist layer is then patterned through exposure and development processes. During this process, the second gap D2 prevents the formation of thick photoresist at the edges of the first pattern LS, which is difficult to remove by development, thereby preventing the problem of residual first electrode 21 at the edges of the first pattern LS.

[0161] 4 and 5 , when the first insulating layer BUF is directly disposed on the first conductive layer SD, that is, when the first insulating layer BUF includes a first groove portion 41 that is concave in a direction close to the first substrate 110 and the first groove portion 41 is at least partially located between the first signal line DL and the first pattern LS, the undulating topography of the first insulating layer BUF is also located at the edge of the first signal line DL. At this time, the third interval D3 is greater than or equal to 4 μm, that is, D3 ≥ 4 μm. This not only greatly reduces the risk of a short circuit between the second electrode 22 and the first signal line DL and the magnitude of the parasitic capacitance generated between the second electrode 22 and the first signal line DL, but also reduces the risk of residual second electrode 22 at the edge near the first signal line DL, which is beneficial to reducing the difficulty of developing the semiconductor layer ACT during preparation, and is beneficial to improving the flatness of the second electrode 22 at the edge near the first signal line DL (hereinafter referred to as the first region), improving the electric field uniformity in the first region, and reducing the risk of light leakage from the liquid crystal layer in the first region.

[0162] For example, the third interval D3 may be in the range of 4 μm to 5 μm, or in the range of 5 μm to 7 μm, or in the range of 7 μm to 10 μm, etc. For example, the third interval D3 may be 4 μm, 5 μm, 6.5 μm, 7 μm, or 8 μm, etc., which are not listed in detail in the embodiments of the present disclosure.

[0163] In some embodiments, referring to Figures 8 and 9 , when the array substrate 100 further includes a planarization layer SOG positioned between the first conductive layer SD and the first insulating layer BUF, the surface of the planarization layer SOG facing away from the first substrate 110 is flat. The orthographic projections of the first conductive layer SD, the second space D2, and the third space D3 on the first substrate 110 are within the orthographic projections of the planarization layer SOG on the first substrate 110. In other words, the planarization layer SOG covers the first conductive layer SD, the second space D2, and the third space D3. In this case, the first insulating layer BUF is positioned on the planarization layer SOG within the second space D2 and the third space D3. The portion of the first insulating layer BUF located within the second space D2 and the third space D2, as well as the portion located above the first conductive layer (the first signal line DL and the first pattern LS), has no undulating topography on the surface facing away from the first substrate 110. Therefore, the semiconductor layer ACT does not face difficulties developing thick photoresist within the second space D2 and the third space D3. Therefore, the second space D2 is greater than or equal to 1 μm, i.e., D2 ≥ 1 μm. When the second interval D2 is small, it can also ensure that there is no residual risk of the second electrode 22 near the edge position of the first pattern LS, and can reduce the parasitic capacitance generated between the second electrode 22 and the first pattern LS, and can greatly increase the area ratio of the second electrode 22, which is beneficial to improving the pixel density of the array substrate.

[0164] For example, the second interval D2 may be in the range of 1 μm to 2 μm, or in the range of 2 μm to 4 μm, or in the range of 4 μm to 6 μm, etc. For example, the second interval D2 may be 1 μm, 2 μm, 3 μm, 3.5 μm, or 5 μm, etc., which are not listed in detail in the embodiments of the present disclosure.

[0165] In some embodiments, when the array substrate 100 further includes a planarization layer SOG located between the first conductive layer SD and the first insulating layer BUF, referring again to Figures 8 and 9 , the third distance D3 is greater than or equal to 3 μm, i.e., D3 ≥ 3 μm. This reduces the risk of a short circuit between the second electrode 22 and the first signal line DL, reduces the magnitude of the parasitic capacitance generated between the second electrode 22 and the first signal line DL, and helps increase the area ratio of the second electrode 22, thereby increasing the pixel density of the array substrate.

[0166] For example, the third interval D3 may be in the range of 3 μm to 4 μm, or in the range of 4 μm to 6 μm, or in the range of 6 μm to 10 μm, etc. For example, the third interval D3 may be 3 μm, 5 μm, 6 μm, 7.5 μm, or 9 μm, etc., which are not listed in detail in the embodiments of the present disclosure.

[0167] In some embodiments, as shown in Figure 5, when the first insulating layer BUF is directly disposed on the first conductive layer SD, the surface of the first insulating layer BUF changes with the undulating morphology of the surface on which it is located, and the first insulating layer BUF includes a first groove portion 41 that is concave inward toward the first substrate 110, and at least a portion of the first groove portion 41 is located between the first signal line DL and the first pattern LS, or in other words, at least a portion of the orthographic projection of the first groove portion 41 on the first substrate 110 is located between the orthographic projection of the first signal line DL and the first pattern LS on the first substrate 110.

[0168] The first groove portion 41 includes two opposing first sidewalls 42. In a cross section perpendicular to the first substrate 110 and parallel to the arrangement direction of the first signal lines DL and the first patterns LS (first direction X) (as shown in FIG5 ), the first sidewalls 42 form an acute angle with the first substrate 110. In other words, the first sidewalls 42 are inclined sidewalls.

[0169] Continuing to refer to Figure 5, the first portion 11 of the semiconductor pattern 10 includes two first sub-portions 14 covering the two first sidewalls 42, and a second sub-portion 15 covering other areas of the first insulating layer BUF. The thickness of the first sub-portion 14 is less than the thickness of the second sub-portion 15. The semiconductor layer ACT is usually prepared by a thin film deposition process. Since the first sidewall 42 is an inclined sidewall, the thickness of the material of the semiconductor layer ACT deposited on the first sidewall 42 is relatively small. The thickness of the first sub-portion 14 and the second sub-portion 15 refers to the dimension along the direction perpendicular to the surface on which they are located. For example, the thickness of the first sub-portion 14 refers to the dimension of the first sub-portion 14 along the direction perpendicular to the first sidewall 42; the thickness of the second sub-portion 15 refers to the dimension of the second sub-portion 15 in the third direction Z.

[0170] In some embodiments, in a cross section perpendicular to the first substrate 110 and perpendicular to the extension direction of the edge of the first conductive layer SD (the cross section shown in FIG5 ), the sidewall 16 of the first conductive layer SD has a first angle α with the first substrate 110, and the first angle α is less than or equal to 50°. This helps reduce the inclination of the first sidewall 42, thereby facilitating the deposition of the semiconductor layer ACT on the first sidewall 42 and reducing the risk of the semiconductor layer ACT breaking on the first sidewall 42 (discontinuous deposition or film thickness not meeting requirements). In other words, it helps increase the thickness of the first sub-portion 14 on the first sidewall 42 and reduce the thickness of the portion of the semiconductor layer ACT located on the plane (such as the thickness of the channel structure 13 and the second electrode 22), thereby reducing the preparation cost of the semiconductor layer ACT and improving the transmittance of the second electrode 22.

[0171] For example, the first angle α may be in the range of 40° to 50°, or in the range of 30° to 40°. For example, the value of the first angle α may be 30°, 35°, 40°, 45°, 47°, or 50°, etc., which are not listed in detail in the embodiments of the present disclosure.

[0172] In some embodiments, the ratio K of the thickness of the first sub-portion 14 to the thickness of the second sub-portion 15 is greater than or equal to 40%, that is, the thickness retention rate of the semiconductor layer ACT at the first sidewall 42 is greater than or equal to 40%. Exemplarily, the range of K can be 40% to 50%, or the range of K can be 50% to 60%, or the range of K can be 60% to 80%. For example, the ratio K of the thickness of the first sub-portion 14 to the thickness of the second sub-portion 15 can be 40%, 45%, 50%, 60% or 70%, etc., and the embodiments of the present disclosure will not give examples one by one. Among them, the ratio K of the thickness of the first sub-portion 14 to the thickness of the second sub-portion 15 is negatively correlated with the size of the first angle α, that is, the larger the value of the first angle α, the smaller the ratio K of the thickness of the first sub-portion 14 to the thickness of the second sub-portion 15.

[0173] In some embodiments, the thickness of the first sub-portion 14 is greater than or equal to In this way, the risk of the first sub-section 14 being broken can be reduced, and the resistance of the first sub-section 14 can be guaranteed to meet the use requirements. For example, the thickness of the first sub-section 14 is Alternatively, the thickness of the first sub-section 14 is Alternatively, the thickness of the first sub-section 14 is For example, the thickness of the first sub-section 14 can be or Etc., the embodiments of the present disclosure do not list them one by one.

[0174] In some embodiments, referring to Figures 8 and 9, when the array substrate 100 further includes a flat layer SOG, the flat layer SOG is located between the first conductive layer SD and the first insulating layer BUF, and the semiconductor layer ACT includes a second electrode 22 layer, the flat layer SOG can only cover the area of ​​the first conductive layer SD. In this way, the influence of the flat layer SOG on the transmittance of the pixel area 101 can be greatly reduced, which is beneficial to improving the light transmittance of the array substrate.

[0175] Referring to Figure 9, the first insulating layer BUF will form an undulating topography at the edge of the flat layer SOG. For example, the first insulating layer BUF will form a second side wall 43 at the edge of the flat layer SOG. In a cross section perpendicular to the first substrate 110 and perpendicular to the extension direction of the side wall of the flat layer SOG (the cross section shown in Figure 9), the second side wall 43 has an acute angle with the first substrate 110, that is, the second side wall 43 is an inclined side wall.

[0176] In some embodiments, in a cross section perpendicular to the first substrate 110 and perpendicular to the extension direction of the sidewall of the planar layer SOG (such as the cross section shown in FIG9 ), a second angle β is formed between the sidewall of the planar layer SOG and the first substrate 110, and the second angle β is less than or equal to 50°. This helps reduce the inclination of the second sidewall 43, facilitates deposition of the semiconductor layer ACT on the second sidewall 43, reduces the risk of fracture of the semiconductor layer ACT on the second sidewall 43 (discontinuous deposition or film thickness not meeting requirements), and helps reduce the thickness of the portion of the semiconductor layer ACT located on the plane (such as the thickness of the channel structure 13 and the second electrode 22), helps reduce the preparation cost of the semiconductor layer ACT, and improves the transmittance of the second electrode 22.

[0177] For example, the second angle β may be in the range of 40° to 50°, or in the range of 30° to 40°. For example, the value of the second angle β may be 30°, 35°, 40°, 45°, 47°, or 50°, etc., which are not listed in detail in the embodiments of the present disclosure.

[0178] In some embodiments, taking the array substrate 100 as an example in which the flat layer SOG is not included, referring to Figures 11 and 12, the preparation process of the array substrate 100 includes: forming a first conductive layer SD, a first insulating layer BUF, a semiconductor layer ACT, and a second insulating layer GI on the first substrate 110 in sequence; then forming a first via hole V1, a portion of the first via hole V1 passes through the second insulating layer GI and the first insulating layer BUF, and exposes a portion of the first signal line DL, and a portion of the first via hole V1 passes through the second insulating layer GI and exposes a portion of the first portion 11 (as shown in Figure 11). Then, an initial gate line layer is prepared to form a continuous entire layer, and the initial gate line layer covers the first via hole V1. Thereafter, the initial gate line layer is patterned to form a connecting electrode 20 and a signal line group 30 (as shown in Figure 12). Among them, the connecting pattern 20 can be entirely located in the first via hole V1 (as shown in Figure 12), or partially located in the first via hole V1 and partially covered on the surface of the second insulating layer GI (as shown in Figure 15).

[0179] In some embodiments, as shown in FIG12 and FIG13, the first sub-portion 14 of the two first sub-portions 14 close to the first signal line DL is the target sub-portion 14A, the first via hole V1 penetrates the second insulating layer GI and exposes the target sub-portion 14A, and the connecting electrode 20 covers the target sub-portion 14A. At this time, in the process of forming the first via hole V1, part of the first sub-portion 14 may be etched away, thereby reducing the thickness of the first sub-portion 14. The dimension of the channel structure 13 in the direction perpendicular to the first substrate 110 (the third direction Z) is greater than or equal to This ensures that even if part of the target sub-portion 14A is removed during the formation of the first via hole V1, it will not break, which helps improve the continuity and conductivity of the target sub-portion 14A. In addition, the first via hole V1 occupies a smaller area, which helps improve the pixel density of the array substrate 100.

[0180] For example, the size of the channel structure 13 in the third direction Z can be Alternatively, the dimension of the channel structure 13 in the third direction Z may be Alternatively, the dimension of the channel structure 13 in the third direction Z may be In this way, the thickness of the channel structure 13 can be reduced as much as possible while ensuring the continuity of the first sub-section 14, reducing the consumption of the semiconductor layer ACT and reducing the thickness of the second electrode 22, which is conducive to improving the transmittance of the second electrode 22. For example, the size of the channel structure 13 in the third direction Z can be or Etc., the embodiments of the present disclosure will not list them one by one.

[0181] It should be noted that, in the semiconductor layer ACT, the thickness of the channel structure 13 is the thickness of the deposited semiconductor material during the preparation of the semiconductor layer ACT. During the patterning of the second insulating layer GI, the first part 11, the second part 12 and the second electrode 22 may be partially removed; therefore, in some embodiments, the thickness of the first part 11, the second part 12 and the second electrode 22 are all less than or equal to the thickness of the channel structure 13.

[0182] In other embodiments, referring to FIG14 and FIG15, the first sub-portion 14 of the two first sub-portions 14 that is close to the first signal line DL is the target sub-portion 14A, and the first via hole V1 penetrates the second insulating layer GI, and there is a gap between the first via hole V1 and the target sub-portion 14A. In this case, during the formation of the first via hole V1, the target sub-portion 14A will not be etched, which is conducive to maintaining the thickness of the target sub-portion 14A. The dimension of the channel structure 13 in the direction perpendicular to the first substrate 110 (the third direction Z) is greater than or equal to In this way, while ensuring the continuity and conductivity of the target sub-portion 14A, the thickness of the semiconductor layer ACT can be reduced, the consumables of the semiconductor layer ACT can be reduced, and the thickness of the second electrode 22 can be reduced, which is beneficial to improving the transmittance of the second electrode 22.

[0183] It should be noted that after forming the connecting electrode 20, the method for preparing the array substrate further includes patterning the second insulating layer GI. During the process of patterning the second insulating layer GI, the second insulating layer above the first sub-portion 14 may also be etched and removed. In this process, part of the first sub-portion 14 may be etched and removed simultaneously. In this process, the etching degree of the first sub-portion 14 is small, and the thickness reduction amount of the first sub-portion 14 is small (for example, ), the size of the channel structure 13 in the direction perpendicular to the first substrate 110 (the third direction Z) is greater than or equal to

[0184] For example, the size of the channel structure 13 in the third direction Z can be Alternatively, the dimension of the channel structure 13 in the third direction Z may be Alternatively, the dimension of the channel structure 13 in the third direction Z may be In this way, the thickness of the channel structure 13 can be reduced as much as possible while ensuring the continuity of the first sub-section 14, reducing the consumption of the semiconductor layer ACT and reducing the thickness of the second electrode 22, which is conducive to improving the transmittance of the second electrode 22. For example, the size of the channel structure 13 in the third direction Z can be or Etc., the embodiments of the present disclosure will not list them one by one.

[0185] In some embodiments, referring to FIG16 and FIG17 , the first sub-portion 14 of the two first sub-portions 14 that is close to the first signal line DL is the target sub-portion 14A, the first via hole V1 penetrates the second insulating layer GI and exposes the target sub-portion 14A, and there is a gap between the connecting electrode 20 and the target sub-portion 14A. In this case, during the process of forming the first via hole V1 and in the subsequent process of patterning the second insulating layer GI, part of the target sub-portion 14A may be etched away. The dimension of the channel structure 13 in the direction perpendicular to the first substrate is greater than or equal to In this way, the risk of the target sub-portion 14A being etched through and broken can be greatly reduced.

[0186] For example, the size of the channel structure 13 in the third direction Z can be Alternatively, the dimension of the channel structure 13 in the third direction Z may be Alternatively, the dimension of the channel structure 13 in the third direction Z may be For example, the size of the channel structure 13 in the third direction Z can be or Etc., the embodiments of the present disclosure will not list them one by one.

[0187] In some embodiments, after forming the connecting electrode 20, the second insulating layer GI can be patterned, as shown in Figures 5, 9, 12, 15 and 17. At this time, the second insulating layer GI basically does not extend on the entire array substrate 100, and the position of the second insulating layer GI basically coincides with the position of the signal line group 30.

[0188] In some other embodiments, after the connection electrode 20 is formed, the second insulating layer GI may not be patterned. Referring to FIG. 18 , in this case, the second insulating layer GI substantially extends over the entire array substrate 100 .

[0189] In some embodiments, referring to Figure 9, when the second insulating layer GI does not basically extend on the entire array substrate 100, the connecting electrode 20 can be completely located within the range of the first via hole V1. At this time, the side of the connecting electrode 20 close to the first substrate 110 does not include the second insulating layer GI.

[0190] In some embodiments, referring to Figures 12 and 15, when the second insulating layer GI does not basically extend on the entire array substrate 100, the connecting electrode 20 can be partially located within the range of the first via hole V1 and partially located outside the range of the first via hole V1. At this time, the connecting electrode 20 and the first insulating layer BUF (as shown in Figure 12), and / or, the connecting electrode 20 and the first part 11 include at least a portion of the second insulating layer GI (as shown in Figure 15).

[0191] In some embodiments, referring to FIG. 15 , the connection electrode 20 may expose at least a portion of the first portion 11, for example, a portion of the connection electrode 20 located on a side close to the channel structure 13. In this case, the surface of the first portion 11 away from the first substrate 110 includes a second groove 17 that is recessed toward the side close to the first substrate 110. The second groove 17 may be formed during the process of forming the connection electrode 20 and patterning the second insulating layer GI.

[0192] In some embodiments, when the second insulating layer GI extends substantially over the entire array substrate 100, referring to FIG19 , the connection electrode 20 may be completely located within the range of the first via hole V1. In this case, the side of the connection electrode 20 closer to the first substrate 110 does not include the second insulating layer GI. Alternatively, referring to FIG18 , the connection electrode 20 may be partially located within the range of the first via hole V1 and partially located outside the first via hole V1. In this case, at least a portion of the connection electrode 20 is located on the surface of the second insulating layer GI away from the first substrate 110.

[0193] It is understandable that the relative positional relationship among the connecting electrode 20 , the first via hole V1 , the first portion 11 and the first signal line DL is not limited to the above embodiment, as long as the same technical concept is adopted.

[0194] For example, referring to FIG20A , the orthographic projections of the first portion 11 and the first signal line DL on the first substrate 110 partially overlap, the orthographic projection of the first via V1 on the substrate 110 is within the range of the orthographic projection of the first signal line DL on the first substrate 110, the connecting electrode 21 completely covers the first via V1, and the edge of the connecting electrode 21 extends beyond the edge of the first via V1. For example, referring to FIG20B , the orthographic projections of the first portion 11 and the first signal line DL on the first substrate 110 partially overlap, the orthographic projection of the first via V1 on the substrate 110 is within the range of the first signal line DL and partially between the first signal line DL and the first pattern LS, the connecting electrode 20 covers the edges of the first via V1 on both sides in the first direction X, and is within the range of the first via V1 at both ends in the second direction Y. Of course, the embodiments of the present disclosure are not limited to this, and any other feasible implementations are contemplated, and the embodiments of the present disclosure will not be listed one by one here.

[0195] In some embodiments, referring to Figures 21 and 22 , the area 201 where the orthographic projections of the signal line group 30 and the first signal line DL on the first substrate 110 overlap (hereinafter referred to as the main spacer area) protrudes toward a side away from the first substrate 110 to form a columnar structure 50. In other words, the surface of the array substrate 100 away from the first substrate 110 protrudes in the main spacer area 201 in a direction away from the first substrate 110 (from bottom to top in Figures 21 and 22 ) to form the columnar structure 50. The columnar structure 50 is configured to support spacers on the color filter substrate.

[0196] In some embodiments, referring to FIG. 21 , when the first insulating layer BUF is directly disposed on the first conductive layer SD, the size of the first conductive layer SD is 0.4 μm to 0.8 μm along a direction perpendicular to the first substrate 110 (third direction Z). This helps increase the height difference (step difference) between the first signal line DL and the first substrate 110, thereby facilitating the formation of the columnar structure 50 in the main spacer region 201 of the array substrate 100, away from the first substrate 110. For example, the size of the first conductive layer SD is 0.4 μm, 0.5 μm, 0.65 μm, 0.7 μm, or 0.8 μm, etc., which are not listed in detail in the embodiments of the present disclosure.

[0197] In some embodiments, referring to FIG. 22 , when the array substrate 100 further includes a planarization layer SOG, the planarization layer SOG is located between the first conductive layer SD and the first insulating layer BUF, and the planarization layer SOG at least covers the first signal line DL, the first pattern LS, and the space (second space D2) between the first signal line DL and the first pattern LS, the orthographic projection of the second electrode 22 on the first substrate 110 does not at least partially overlap with the orthographic projection of the planarization layer SOG on the first substrate 110. This can, on the one hand, reduce the area of ​​the planarization layer SOG within the pixel region 101, thereby improving the transmittance of the pixel region 101. On the other hand, it facilitates forming a height difference between the edge of the planarization layer SOG and the first substrate 110, thereby facilitating the formation of the columnar structure 50 in the main spacer region 201 of the array substrate 100, on the surface away from the first substrate 110. For example, the size of the first conductive layer SD is 0.4 μm, 0.55 μm, 0.6 μm, 0.7 μm, or 0.8 μm, etc., which are not enumerated in the embodiments of the present disclosure.

[0198] As shown in Figure 22, when the array substrate 100 also includes a flat layer SOG, the thickness of the first conductive layer SD can be unlimited, which is beneficial to reducing the thickness of the first conductive layer SD and reducing the width of the first signal line DL, thereby improving the aperture ratio of the array substrate 100 and improving the transmittance of the array substrate 100.

[0199] In some embodiments, the array substrate 100 also includes an alignment film (not shown in the figure) arranged on the side of the first electrode 21 away from the first substrate 110. The alignment film is used to limit the initial deviation angle of the liquid crystal molecules in the liquid crystal layer so that the liquid crystal molecules in the liquid crystal layer can be arranged at a certain angle in the absence of an electric field.

[0200] In the following embodiments, some embodiments of the present disclosure are illustrated by taking the case where the first insulating layer BUF is directly disposed on the first conductive layer SD (the array substrate 100 does not include the flat layer SOG) as an example, but the embodiments of the present disclosure are not limited thereto.

[0201] In some embodiments, referring to Figures 23 to 26 , the array substrate 100 includes a plurality of first signal lines DL spaced apart along a first direction X, and a plurality of signal line groups 30 spaced apart along a second direction Y. The plurality of first signal lines DL extend along the second direction Y, and the plurality of signal line groups 30 extend along the first direction X. The plurality of first signal lines DL and the plurality of signal line groups 30 intersect to form a grid structure.

[0202] The color filter substrate 200 includes a plurality of strip-shaped spacers 230. Exemplarily, the plurality of strip-shaped spacers 230 are disposed on a side of the color filter substrate 200 that is close to the array substrate 100 and extend along the first direction X. The orthographic projections of the spacers 230 on the array substrate 100 partially overlap with the signal line group 30 and the first signal line DL.

[0203] The present application utilizes the thickness of the signal line group 30 and the first signal line DL itself in conjunction with the long strip spacer 230 to form a structure that supports the liquid crystal layer (liquid crystal box thickness). When the spacer 230 is displaced, the spacer 230 can be supported by the first signal line DL and the signal line group 30 to prevent the spacer 230 from scratching the portion of the alignment film located within the pixel area 101.

[0204] Referring to FIG. 24 , the color filter substrate 200 further includes a second substrate 210 and a filter layer 220. The second substrate 210 can be a rigid substrate. For example, the rigid substrate can be a glass substrate or a PMMA (Polymethyl methacrylate) substrate. The second substrate 210 can also be a flexible substrate. For example, the flexible substrate can be a PET (Polyethylene terephthalate) substrate, a PI (Polyimide) substrate, or a PEN (Polyethylene naphthalate two formic acid glycol ester) substrate. It is understood that the second substrate 210 can be of various types and can be selected and configured according to actual needs, and the embodiments of the present disclosure do not impose any limitations on this.

[0205] A filter layer 220 is provided on the side of the second substrate 210 near the array substrate 100. The filter layer 220 includes a black matrix 60 and a filter unit (not shown). The filter unit is provided corresponding to the pixel area 101. The orthographic projection of the filter unit on the array substrate 100 covers the pixel area 101. The filter unit includes a red filter unit, a green filter unit, and a blue filter unit. Different pixel areas 101 correspond to different filter units.

[0206] The orthographic projection of the black matrix 60 on the array substrate 100 covers the area of ​​the non-pixel area 101. Exemplarily, the orthographic projection of the black matrix 60 on the array substrate 100 covers the first signal line DL, the signal line group 30, the first pattern LS, etc., and the black matrix 60 also covers the spacer 230 structure on the color filter substrate 200. The black matrix 60 is also configured to separate different pixel areas 101 to reduce the risk of cross-color between different pixel areas, affecting the final display effect. The black matrix 60 can also prevent the spacer 230 from slipping and causing abnormal display of the panel and shielding the scratch distance. Among them, an alignment film (not shown in the figure) is provided on the side of the color filter substrate 200 close to the array substrate 100.

[0207] The liquid crystal layer 300 is supported between the array substrate 100 and the color filter substrate 200 by spacers 230. The spacer 230 is supported on the array substrate 100 at one end (lower end) near the array substrate, and on the color filter substrate 200 at one end (upper end) near the color filter substrate 200, thereby maintaining a certain thickness of the liquid crystal layer 300. For example, the spacer 230 can be fabricated on the color filter substrate 200.

[0208] In some embodiments, referring to Figures 23 to 27 , the signal line group 30 includes a second signal line 32 and a third signal line 33. The structure and function of the second signal line 32 are described above and are not further described here. The third signal line 33 is configured to be connected to the first electrode. The third signal line 33 is also configured to provide a stable voltage to one end of the liquid crystal capacitor Clc and the storage capacitor Cst, thereby maintaining a stable voltage difference between the liquid crystal capacitor Clc and the storage capacitor Cst, thereby maintaining a directional deflection angle of the liquid crystal molecules.

[0209] Illustratively, a signal line group 30 includes a second signal line 32 and a third signal line 33. The second signal line 32 controls the connection between the first signal line DL of a row of pixel regions 101 and the second electrode of the row of pixel regions 101 through a row of thin film transistors, and the third signal line 33 provides a stable voltage to one end of the liquid crystal capacitor Clc and the storage capacitor Cst of an adjacent row of pixel regions 101.

[0210] In some embodiments, referring to FIG. 23 , the orthographic projection of the spacer 230 on the array substrate 100 covers the area between the second signal line 32 and the third signal line 33 in the signal line group 30. Furthermore, the orthographic projection of the spacer 230 on the array substrate 100 partially overlaps with the second signal line 32, and the orthographic projection of the spacer 230 on the array substrate 100 partially overlaps with the third signal line 33. That is, within the length of the spacer 230, the orthographic projection on the array substrate 100 simultaneously covers a portion of the second signal line 32, a portion of the third signal line 33, and the area between the second signal line 32 and the third signal line 33.

[0211] In some embodiments, referring to FIG. 23 , the dimension of the second signal line 32 in the second direction Y is C1, the dimension of the third signal line 33 in the second direction Y is C2, the spacing between the second signal line 32 and the third signal line 33 is C3, and the dimension of the end of the spacer 230 near the array substrate 100 in the second direction Y is C4. If the dimension C2 of the third signal line 33 in the second direction Y is greater than the dimension C1 of the second signal line 32 in the second direction Y (C2>C1), C4=C3+C1. Alternatively, if the dimension C1 of the second signal line 32 in the second direction Y is greater than the dimension C2 of the third signal line 33 in the second direction Y (C1>C2), C4=C3+C2. In other words, the dimension C4 of the end of the spacer 230 near the array substrate 100 in the second direction Y is equal to the sum of the spacing C3 between the second signal line 32 and the third signal line 33 and the smaller dimension of the second signal line 32 or the third signal line 33 in the second direction Y. In this way, even if there is a certain alignment deviation between the spacer 230 and the array substrate 100, when the spacer at least partially covers the area between the second signal line 32 and the third signal line 33, the total contact area between the spacer 230 and the second signal line 32 and the third signal line 33 remains unchanged. In this way, it can be ensured that the spacer 230 provides stable support for the liquid crystal layer 300, thereby ensuring that the liquid crystal layer 300 can maintain a stable thickness, thereby ensuring the display effect of the display substrate.

[0212] In some embodiments, the side of the spacer 230 facing away from the color filter substrate 200 is equidistant from the color filter substrate 200 (the second substrate 210). The length of the spacer 230 is greater than the distance between two adjacent first signal lines DL. The overlapping region of the first signal lines DL and the signal line group 30 forms a plurality of columnar structures 50 protruding toward the color filter substrate 200. The side of the spacer 230 facing away from the color filter substrate 200 abuts against some of the columnar structures 50. In this way, the spacer 230 cooperates with the first signal lines DL and the signal line group 30 to form distinct spacer regions.

[0213] The portion of the spacer 230 that abuts against a portion of the columnar structure 50 on a side away from the color filter substrate 200 forms a main spacer region 201. The portion of the spacer 230 whose orthographic projection on the array substrate 100 overlaps with the first signal line DL or the signal line group 30 but does not overlap with the columnar structure 50 forms a first sub-spacer region 202. The portion of the spacer 230 whose orthographic projection on the array substrate 100 overlaps with the region between the second signal line 32 and the third signal line 33 in the signal line group 30 forms a second sub-spacer region 203.

[0214] The side of the columnar structure 50 closest to the color filter substrate 200 abuts against the spacer 230. The distance f between the side of the first signal line DL or the signal line group 30 where the non-columnar structure 50 is closest to the color filter substrate 200 and the spacer 230 is . The distance g between the area between the second signal line 32 and the third signal line 33 in the signal line group 30 and the spacer 230 is . g>f>0. Thus, the spacer 230, the first signal line DL, and the signal line group 30 form a stepped main spacer region 201, a first sub-spacer region 202, and a second sub-spacer region 203.

[0215] When the display substrate is in a normal state, the main spacer region 201 of the spacer 230 provides support for the liquid crystal cell thickness. When the display substrate 1100 is pressed, the color filter substrate 200 is squeezed toward the array substrate 100, the spacer 230 is squeezed and deformed, and the first secondary spacer region 202 contributes to supporting the liquid crystal cell thickness. Specifically, the spacer 230 contacts the upper surface of the array substrate 100 where the second signal line 32 and the third signal line 33 are located (the surface close to the color filter substrate). When the display substrate is pressed strongly, the degree of squeezing of the color filter substrate 200 against the array substrate 100 increases, and the degree of deformation of the spacer 230 increases. At this time, the second secondary spacer region 203 also begins to contribute to supporting the liquid crystal cell thickness. Specifically, the spacer 230 also contacts the upper surface of the array substrate between the second signal line 32 and the third signal line 33.

[0216] In some embodiments, the signal line group 30 is provided with multiple winding areas 34 along its length (first direction X). A winding area 34 is provided at the location where at least one signal line group 30 intersects with a first signal line DL. A winding area 34 is provided at the location where at least one second signal line 32 and / or at least one third signal line 33 intersects with a first signal line DL. The orthographic projection of the spacer 230 on the array substrate 100 within the winding area 34 does not overlap with the columnar structure 50.

[0217] Exemplarily, the signal line group 30 includes a second signal line 32 and a third signal line 33. The second signal line 32 and the third signal line 33 extend in the non-winding area 35 along the length direction of the signal line group 30, that is, the first direction X. In the winding area 34, the second signal line 32 bends a distance away from the third signal line 33, and then extends along the length direction of the signal line group 30. After bypassing the first signal line DL, it bends and extends in the direction close to the third signal line 33 to a position colinear with the second signal line 32 in the non-winding area 35, and then continues to extend along the length direction of the signal line group 30, that is, in the winding area 34, the second signal line 32 protrudes along the second direction Y to avoid the spacer 230. Within the winding area 34, the third signal line 33 bends a distance away from the second signal line 32, then extends along the length of the signal line group 30. After bypassing the columnar structure 50, it bends toward the second signal line 32 and extends to a position collinear with the third signal line 33 in the non-winding area 35. It then continues to extend along the length of the signal line group 30. In other words, within the winding area 34, the third signal line 33 bulges along the second direction Y to avoid the spacer 230. In this way, the original primary spacer area 201 within the winding area 34 becomes the first secondary spacer area 202.

[0218] For example, the distance that the second signal line 32 bends away from the third signal line 33 within the winding area 34 is h, the maximum alignment deviation between the array substrate 100 and the color filter substrate 200 in the second direction Y is e, and h is greater than or equal to e. The structure in the winding area 34 where the second signal line 32 and the third signal line 33 sandwich the spacer 230 effectively prevents displacement of the spacer 230 in the second direction Y.

[0219] In some embodiments, a spacer 230 is provided for every 24 pixel areas 101 on the display substrate 1100. For example, in a display substrate 1100 arranged in two rows and twelve columns, one spacer 230 spans at least thirteen first signal lines DL along its length, meaning that the spacer 230 spans twelve pixel areas 101 along its length. The orthographic projection of the spacer 230 on the array substrate 100 overlaps with the thirteen first signal lines DL and one signal line group 30. At least eleven of the intersections between the thirteen first signal lines DL and the signal line group 30 have winding areas 34 provided. Thus, the contact density ratio between the main spacer area 201 and the first sub-spacer area 202 is close to 1:100. This ratio of the main spacer area 201 and the first sub-spacer area 202 ensures both support for the liquid crystal cell thickness and the absence of dark spots under external pressure.

[0220] Of course, the arrangement of the above-mentioned spacers 230 and the arrangement of the winding areas 34 can be determined according to actual needs. For example, a spacer 230 may be provided for an average of 23, 24, 25, 26 or 27 pixel areas 101. One spacer 230 spans 12, 13, 14, 15 or 16 first signal lines DL in its length direction, that is, the spacer 230 spans 11, 12, 13, 14 or 15 pixel areas 101 in its length direction. The number of winding areas 34 can also be 11, 12, 13, 14 or 15. As long as it satisfies the contact density of the main spacer area 201 is close to 200μm 2 / mm 2 The contact density of the first sub-spacer region 202 is close to 20000 μm 2 / mm 2 That's it.

[0221] The spacer 230 spans across multiple first signal lines DL along its length. As shown in FIG25 , when the spacer 230 undergoes a significant displacement in the second direction Y, for example, when the spacer 230 displaces in the second direction Y to the point where it no longer overlaps with the signal line group 30, the first signal lines DL can still provide support for the spacer 230. Specifically, when the spacer 230 undergoes a significant displacement in the second direction Y, the first sub-spacer area 202 formed by the main spacer area 201 overlapping with the signal line group 30 is lost, but the first sub-spacer area 202 formed by the first signal lines DL is not lost. Therefore, a significant displacement of the spacer 230 in the second direction Y will not scratch the alignment film on the array substrate 100.

[0222] For example, the arrangement of the spacers 230 can be determined according to needs. For example, one main spacer region 201 and six to twelve first sub-spacer regions 202 can be provided in the twenty-four pixel regions 101 arranged in three rows and eight columns. Alternatively, one main spacer region 201 and six to twelve first sub-spacer regions 202 can be provided in the twenty-four pixel regions 101 arranged in four rows and six columns, etc. It is sufficient that the spacers 230 are evenly arranged across the entire surface and that the contact density ratio between the main spacer region 201 and the first sub-spacer region 202 is close to 1:100.

[0223] 28 and 29 show the thickness of the liquid crystal cell of the display substrate in the main spacer region 201 and the first sub-spacer region 202 with different contact densities after the spacer 230 is subjected to external force with and without displacement.

[0224] 28 and 29 are the contact density (μm) of the first sub-spacer region 202. 2 / mm 2 ), the vertical axis is the thickness of the liquid crystal cell (μm). The six lines from top to bottom in Figure 28 represent the contact density of the main spacer area 201 of 100μm 2 / mm 2 , 150μm 2 / mm 2 , 200μm 2 / mm 2 , 250μm 2 / mm 2 , 300μm 2 / mm 2 , 350μm 2 / mm 2 The six lines from top to bottom in FIG29 represent the contact density of the main spacer area 201 of 350 μm 2 / mm 2 , 300μm 2 / mm 2 , 250μm 2 / mm 2 , 200μm 2 / mm 2 , 150μm 2 / mm 2 , 100μm 2 / mm 2 It is obvious that as the contact density of the first auxiliary spacer area 202 increases, the thickness of the liquid crystal cell gradually increases after the display substrate is subjected to external force. When the contact density of the main spacer area 201 is 200μm 2 / mm 2 The contact density of the first auxiliary spacer area 202 is 20000 μm 2 / mm 2 The spacer 230 can provide better support for the thickness of the liquid crystal cell.

[0225] FIG30 shows a display substrate with different contact densities between the main spacer region 201 and the first sub-spacer region 202, and the deformation of the spacer 230 after the spacer 230 is subjected to external force when the spacer 230 is displaced. The horizontal axis in FIG30 is the contact density of the first sub-spacer region 202 (μm 2 / mm 2 ), the vertical axis is the liquid crystal cell deformation (μm). The six lines from top to bottom in Figure 30 represent the contact density of the main spacer area 201 of 100μm 2 / mm 2 , 150μm 2 / mm 2 , 200μm 2 / mm 2 , 250μm 2 / mm 2 , 300μm 2 / mm 2 , 350μm 2 / mm 2The thickness of the first signal line DL is generally between 0.55 μm and 0.65 μm, and the thickness of the signal line group 30 is between 0.65 μm and 0.75 μm. It can be clearly seen that when the contact density of the first sub-spacer area 202 is greater than 15000 μm 2 / mm 2 , the contact density of the main spacer area 201 is greater than 150μm 2 / mm 2 When the spacer 230 is deformed, the amount of deformation is significantly smaller than the thickness of the first signal line DL. In this case, the displacement of the spacer 230 will not scratch the alignment film.

[0226] The third signal line 33 is provided with a second via hole V2 (as shown in FIG. 4 ) near the intersection thereof with the first signal line DL. The third signal line 33 is connected to the first electrode layer 21 through the second via hole V2. The second via hole V2 is provided near the intersection of the third signal line 33 and the first signal line DL. When light leakage occurs due to the second via hole V2, the black matrix 60 can block the light leaking from the second via hole V2, thereby reducing the adverse effect of the second via hole V2 on the display effect of the display substrate 1100.

[0227] 31 , 32 , and 33 , the signal line group 30 includes a second signal line 32. The second signal line 32 controls the connection between the first signal line DL and the liquid crystal capacitor Clc and the storage capacitor Cst (the second electrode 22). In other words, the second signal line 32 controls whether the first signal line DL charges the liquid crystal capacitor Clc and the storage capacitor Cst.

[0228] Illustratively, one signal line group 30 includes one second signal line 32. The second signal line 32 controls the connection between the first signal line DL of a row of pixel regions 101 and the second electrode 22 of the pixel region in that row. The second signal line 32 of an adjacent row of pixel regions 101 provides a stable voltage to one end of the liquid crystal capacitor Clc and the storage capacitor Cst.

[0229] The orthographic projection of the spacer 230 on the array substrate 100 covers the second signal line 32 in the signal line group 30. That is, the orthographic projection of the spacer 230 on the array substrate 100 covers the second signal line 32 within the length range of the spacer 230.

[0230] For example, the width of the spacer 230 may be C4, the width of the second signal line 32 may be C1, and the alignment deviation between the array substrate 100 and the color filter substrate 200 may be e. That is, during the alignment process of the array substrate 100 and the color filter substrate 200, the maximum alignment deviation between the array substrate 100 and the color filter substrate 200 in the second direction Y is e. Therefore, C4 is greater than C1. In some embodiments, C4 is greater than or equal to C1+2e. That is, the orthographic projection of the spacer 230 on the array substrate 100 covers the second signal line 32 in the signal line group 30, and the distance between the two sides of the orthographic projection of the spacer 230 on the array substrate 100 is greater than or equal to e. In this way, when a slight deviation occurs during the alignment process of the array substrate 100 and the color filter substrate 200, the width of the portion where the orthographic projection of the spacer 230 on the array substrate 100 overlaps with the second signal line 32 remains C1. In this way, it can be ensured that the spacers 230 can provide stable support for the liquid crystal layer 300, thereby ensuring that the liquid crystal layer 300 can maintain a stable thickness, thereby ensuring the display effect of the display substrate.

[0231] In some embodiments, the side of the spacer 230 facing away from the color filter substrate 200 is equidistant from the color filter substrate 200. The overlapping region of the first signal line DL and the signal line group 30 forms a plurality of columnar structures 50 protruding toward the color filter substrate 200. The side of the spacer 230 facing away from the color filter substrate 200 abuts against some of the columnar structures 50. In this way, the spacer 230 forms distinct padding regions within itself, in conjunction with the first signal line DL and the signal line group 30. The portion of the spacer 230 facing away from the color filter substrate 200 that abuts against some of the columnar structures 50 forms a primary padding region 201. The orthographic projection of the spacer 230 on the array substrate 100 overlaps with the first signal line DL or the signal line group 30, while the portion that does not overlap with the columnar structures 50 forms a first secondary padding region 202.

[0232] The portion of the spacer 230 whose orthographic projection on the array substrate 100 overlaps with the area of ​​the array substrate 100 not including the second signal line 32 forms the second sub-spacer region 203. The side of the columnar structure 50 that is closest to the color filter substrate 200 abuts the spacer 230. The distance f between the area of ​​the first signal line DL or the signal line group 30 that is not including the columnar structure 50 and that is closest to the color filter substrate 200 and the spacer 230 is . The distance g between the area of ​​the array substrate 100 that is not including the second signal line 32 and the spacer 230 is . g>f>0. Thus, the spacer 230, the first signal line DL, and the signal line group 30 cooperate to form a main spacer region 201, a first sub-spacer region 202, and a second sub-spacer region 203 with step differences.

[0233] In the normal state, the main spacer region 201 of the spacer 230 provides support for the liquid crystal cell thickness. When the display substrate is pressed, the color filter substrate 200 recesses toward the array substrate 100, and the first secondary spacer region 202 contributes to supporting the liquid crystal cell thickness. When the display substrate is pressed strongly, the color filter substrate 200 recesses further toward the array substrate 100, and the second secondary spacer region 203 also begins to contribute to supporting the liquid crystal cell thickness.

[0234] The signal line group 30 is provided with a plurality of winding areas 34 along its length. A winding area 34 is provided at the location where at least one signal line group 30 intersects with the first signal line DL. The orthographic projection of the spacer 230 on the array substrate 100 in the winding area 34 does not overlap with the columnar structure 50. Exemplarily, the signal line group 30 includes a second signal line 32. The second signal line 32 extends along the length direction of the signal line group 30, i.e., the first direction X, in the non-winding area 35. Within the winding area 34, the second signal line 32 bends a distance perpendicular to the length direction of the signal line group 30, then extends along the length direction of the signal line group 30, bypasses the columnar structure 50, bends back and extends to a position colinear with the second signal line 32 in the non-winding area 35, and then continues to extend along the length direction of the signal line group 30. That is, within the winding area 34, the second signal line 32 protrudes along the second direction Y to avoid the spacer 230. In this way, the original main spacer area 201 in the winding area 34 is transformed into the first sub-spacer area 202 .

[0235] In some embodiments, the distance that the second signal line 32 is bent in the winding area 34 in a direction perpendicular to the length direction of the signal line group 30 (the second direction Y) is h, and the maximum alignment deviation between the array substrate 100 and the color film substrate 200 in the second direction Y is e, and h is greater than or equal to e.

[0236] In some embodiments, a spacer 230 is provided for every twelve pixel areas 101 on the display substrate. For example, in twelve pixel areas 101 arranged in a row and twelve columns, one spacer 230 spans at least thirteen first signal lines DL along its length, meaning that the spacer 230 spans all twelve pixel areas 101 along its length. The orthographic projection of the spacer 230 on the array substrate 100 overlaps with the thirteen first signal lines DL and one signal line group 30. At least eleven of the intersections between the thirteen first signal lines DL and the signal line group 30 have winding areas 34 provided. As a result, the contact density ratio between the main spacer area 201 and the first sub-spacer area 202 is close to 1:100. This ratio of contact density between the main spacer area 201 and the first sub-spacer area 202 ensures both support for the liquid crystal cell thickness and the absence of dark spots under external pressure.

[0237] In some embodiments, the arrangement of the spacers 230 can be determined according to needs. For example, one main spacer area 201 and six to twelve first sub-spacer areas 202 can be set in the twelve pixel areas 101 arranged in two rows and six columns. Alternatively, one main spacer area 201 and six to twelve first sub-spacer areas 202 can be set in the twenty-four pixel areas 101 arranged in three rows and four columns. It is only necessary to ensure that the spacers 230 are evenly arranged on the entire surface and that the contact density ratio between the main spacer area 201 and the first sub-spacer area 202 is close to 1:100. Of course, the arrangement of the above-mentioned spacers 230 and the arrangement of the winding area 34 can be determined according to actual needs. For example, one spacer 230 can be set for an average of 12, 13, 14, 15 or 16 pixel areas 101. One spacer 230 spans 12, 13, 14, 15, or 16 first signal lines DL in its length direction, that is, the spacer 230 spans 11, 12, 13, 14, or 15 pixel areas 101 in its length direction. The number of winding areas 34 can also be 11, 12, 13, 14, or 15. As long as the contact density of the main spacer area 201 is close to 200 μm, 2 / mm 2 The contact density of the first sub-spacer region 202 is close to 20000 μm 2 / mm 2 That's it.

[0238] The spacer 230 spans across multiple first signal lines DL along its length (first direction X). When the spacer 230 undergoes a significant displacement in the second direction Y, for example, when the spacer 230 displaces in the second direction Y to the point where it no longer overlaps with the signal line group 30, the surface of the area where the first signal lines DL are located still provides support for the spacer 230. Specifically, when the spacer 230 undergoes a significant displacement in the second direction Y, the first sub-spacer area 202 formed by the overlap of the main spacer area 201 with the signal line group 30 is lost, but the first sub-spacer area 202 formed by the overlap with the first signal lines DL is not lost. Therefore, a significant displacement of the spacer 230 in the second direction Y will not scratch the alignment film on the array substrate 100.

[0239] As shown in Figures 27 and 34-35, in some embodiments, the orthographic projection of the spacer 230 on the array substrate 100 partially overlaps with the signal line group 30. The side of the spacer 230 facing away from the color filter substrate 200 is at unequal distances from the color filter substrate 200. The spacer 230 includes a main spacer region 201 having a first thickness and a first sub-spacer region 202 having a second thickness, where the first thickness is greater than the second thickness. The orthographic projection of the main spacer region 201 on the array substrate 100 overlaps with the first signal lines DL, while the orthographic projection of the main spacer region 201 onto the array substrate does not overlap with the signal line group 30. The orthographic projection of the main spacer region 201 onto the array substrate 100 covers at least two first signal lines DL along the length of the spacer 230. The orthographic projection of the first sub-spacer region 202 onto the array substrate 100 partially overlaps with the first signal lines DL and partially overlaps with the signal line group 30.

[0240] The signal line group 30 is provided with multiple winding areas 34 along its length. A winding area 34 is provided at the location where at least one signal line group 30 intersects with the first signal line DL. Within the winding area 34, the signal line group 30 avoids the area where the spacer 230 overlaps with the first signal line DL. That is, the spacer 230, the signal line group 30, and the first signal line DL do not overlap at the same time. Furthermore, the winding area 34 is also provided at the location of the orthographic projection of the main spacer area 201 on the array substrate 100. Within the winding area 34, the signal line group 30 avoids the area covered by the orthographic projection of the main spacer area 201 on the array substrate 100. The maximum alignment deviation between the array substrate 100 and the color filter substrate 200 in the second direction Y is e. Therefore, the distance between the signal line group 30 in the winding area 34 and the area where the spacer 230 overlaps with the first signal line DL is greater than e, and the distance between the signal line group 30 in the winding area 34 and the area covered by the orthographic projection of the main spacer area 201 on the array substrate 100 is greater than e. That is, the orthographic projection of the first sub-spacer area 202 in the winding area 34 on the array substrate 100 overlaps with the first signal line DL, and the orthographic projection of the first sub-spacer area 202 in the non-winding area 35 on the array substrate 100 overlaps with the signal line group 30.

[0241] In some embodiments, a spacer 230 is provided for every 24 pixel areas 101 on the display substrate. For example, in a display substrate with 24 pixel areas 101 arranged in two rows and twelve columns, one spacer 230 spans at least 13 first signal lines DL along its length, meaning that the spacer 230 spans 12 pixel areas 101 along its length. The orthographic projection of the spacer 230 on the array substrate 100 overlaps with the 13 first signal lines DL and one signal line group 30. A winding area 34 is provided at each intersection of the 13 first signal lines DL and one signal line group 30. Each spacer 230 is provided with a main spacer area 201. As a result, the contact density ratio between the main spacer area 201 and the first sub-spacer area 202 is close to 1:100. This ratio of contact density between the main spacer area 201 and the first sub-spacer area 202 ensures both support for the liquid crystal cell thickness and the absence of dark spots under external pressure.

[0242] Exemplarily, the arrangement of the spacers 230 can be determined according to needs. For example, one main spacer area 201 and six to twelve first sub-spacer areas 202 can be set in the twenty-four pixel areas 101 arranged in three rows and eight columns. Alternatively, one main spacer area 201 and six to twelve first sub-spacer areas 202 can be set in the twenty-four pixel areas 101 arranged in four rows and six columns. It is only necessary to ensure that the spacers 230 are evenly arranged on the entire surface and that the contact density ratio between the main spacer area 201 and the first sub-spacer area 202 is close to 1:100. Of course, the arrangement of the above-mentioned spacers 230 and the arrangement of the winding area 34 can be determined according to actual needs. One spacer 230 can be set for an average of 23, 24, 25, 26 or 27 pixel areas 101. One spacer 230 spans 12, 13, 14, 15, or 16 first signal lines DL in its length direction, that is, the spacer 230 spans 11, 12, 13, 14, or 15 pixel areas 101 in its length direction. The number of winding areas 34 can also be 11, 12, 13, 14, or 15. As long as the contact density of the main spacer area 201 is close to 200 μm, 2 / mm 2 The contact density of the first sub-spacer region 202 is close to 20000 μm 2 / mm 2That's it. The spacer 230 spans across multiple first signal lines DL in its length direction. When the spacer 230 has a large displacement in the second direction Y, for example, when the spacer 230 is displaced in the second direction Y to the point where it does not overlap with the signal line group 30, the first signal line DL can still support the spacer 230. That is, when the spacer 230 has a large displacement in the second direction Y, it will lose the first sub-spacer area 202 formed by the main spacer area 201 overlapping with the signal line group 30, but the first sub-spacer area 202 formed by overlapping with the first signal line DL will not be lost. At the same time, since the main spacer area 201 of the spacer 230 overlaps with the first signal line DL, its supporting capacity will not be lost due to the displacement of the spacer 230 in the second direction Y. Therefore, the large displacement of the spacer 230 in the second direction Y will not scratch the alignment film on the array substrate 100.

[0243] In some embodiments, referring to FIG. 26 and FIG. 36 , the orthographic projection of the black matrix 60 on the array substrate 100 covers the spacers 230 , the first signal lines DL, and the signal line group 30 .

[0244] As shown in FIG36 , the black matrix 60 further includes a first portion 61. The orthographic projection of the first portion 61 on the array substrate 100 covers the region where the semiconductor pattern 10, the first pattern LS, the signal line group 30, and the first signal line DL overlap, as well as the region where the signal line group 30 is positioned opposite the semiconductor pattern 10 and the first pattern LS in the second direction Y. A fourth distance D4 is defined between the adjacent boundaries of the first portion 61 and the surface 231 of the spacer 230 proximate to the array substrate 100, as projected on the array substrate 100. The fourth distance D4 is 20 μm to 40 μm. In this way, the first portion 61 can shield the region where the semiconductor pattern 10, the first pattern LS, the signal line group 30 and the first signal line DL overlap, as well as the region where the signal line group 30 is positioned opposite the semiconductor pattern 10 and the first pattern LS in the second direction Y, thereby reducing the risk of light leakage around these regions.

[0245] For example, the fourth interval D4 may be in the range of 20 μm to 30 μm, or in the range of 30 μm to 40 μm. For example, the fourth interval D4 may be 20 μm, 25 μm, 30 μm, 35 μm, or 40 μm, which are not listed in detail in the embodiments of the present disclosure.

[0246] In some embodiments, referring to Figures 26 and 37, the black matrix 60 further includes a second portion 62. The orthographic projection of the second portion 62 on the array substrate 100 covers the region of the signal line group 30 that is offset from the first pattern LS and the semiconductor pattern 10 in the second direction Y. Furthermore, the portion of the black matrix 60 covering the same signal line group 30 includes a first portion 61 and a second portion 62 that are alternately arranged along the first direction X. A fifth distance D5 is defined between the adjacent boundaries of the second portion 62 and the signal line group 30 in their orthographic projections on the array substrate 100. The fifth distance D5 is 3 μm to 6 μm. This allows the second portion 62 to shield the region of the signal line group 30 that is offset from the first pattern LS and the semiconductor pattern 10 in the second direction Y, thereby reducing the risk of light leakage from both sides of the region along the second direction Y. For example, the value of the fifth distance D5 can be 3 μm, 4 μm, 3.5 μm, 5 μm, or 6 μm, etc., which are not listed in detail in the embodiments of the present disclosure.

[0247] In some embodiments, referring to Figures 26 and 38 , when the first insulating layer BUF is directly disposed on the first conductive layer SD, and the first insulating layer BUF includes a first groove 41 that is concave in a direction toward the first substrate 110, with the first groove 41 at least partially located between the first signal line DL and the first pattern LS, the black matrix 60 further includes a third portion 63. The orthographic projection of the third portion 63 on the array substrate 100 covers the first signal line DL, and a sixth distance D6 is defined between the adjacent boundaries of the orthographic projections of the third portion 63 and the first signal line DL on the first substrate 110. The sixth distance D6 is 0.5 μm to 2 μm. The third portion 63 can shield the first signal line DL from reflection of ambient light and reduce the risk of light leakage on both sides of the first signal line DL due to the step difference in the run of the first signal line DL. For example, the value of the sixth distance D6 can be 0.5 μm, 1 μm, 1.5 μm, or 2 μm, etc., which are not listed in detail in the embodiments of the present disclosure.

[0248] In some embodiments, referring to Figures 26 and 39 , when the array substrate 100 further includes a planarization layer SOG positioned between the first conductive layer SD and the first insulating layer BUF, the surface of the planarization layer SOG facing away from the first substrate 110 is flat, and the planarization layer SOG includes a first planar portion S1 that covers the first signal line DL. The black matrix 60 includes a third portion 63, whose orthographic projection on the array substrate 100 covers the first planar portion S1. A seventh distance D7 is defined between the adjacent boundaries of the orthographic projections of the third portion 63 and the first planar portion S1 on the first substrate 110. The seventh distance D7 is 0.5 μm to 2 μm. The third portion 63 shields the first signal line DL from ambient light and reduces the risk of light leakage on both sides of the first signal line DL due to the step created by the planarization layer SOG. For example, the value of the seventh distance D7 can be 0.5 μm, 1 μm, 1.5 μm, or 2 μm, etc., which are not listed in detail in the embodiments of the present disclosure.

[0249] In some embodiments, when the first insulating layer BUF of the array substrate 100 is directly disposed on the first conductive layer SD, and the display substrate includes the array substrate and the color filter substrate described in any of the above embodiments, the transmittance of the display substrate is greater than or equal to 6%. For example, the transmittance of the display substrate is 6%, 6.5%, 6.6%, 7%, 8%, or 8.5%, etc., which are not listed in detail in the embodiments of the present disclosure.

[0250] For example, when the display substrate is lit (the display substrate displays the maximum grayscale), the brightness of more than 9 points on the display substrate is tested using a CCD device, and then the brightness detected at each point is divided by the backlight brightness at the corresponding position, and the average value is taken to obtain the transmittance of the display substrate. Through actual testing, it is found that the transmittance of the display substrate of the embodiment of the present disclosure can reach at least 6%, which is more than 50% higher than that of the conventional ADS display substrate. In some embodiments, when the array substrate 100 further includes a flat layer SOG, the flat layer SOG is located between the first conductive layer SD and the first insulating layer BUF, and the display substrate includes the array substrate and the color film substrate described in any of the above embodiments, the transmittance of the display substrate is greater than or equal to 9%. For example, the transmittance of the display substrate is 9%, 9.5%, 10%, 10.5% or 11%, etc., and the embodiments of the present disclosure will not be listed one by one.

[0251] For example, with the display substrate illuminated (displaying maximum grayscale), a CCD device is used to test the brightness of more than nine points on the display substrate. The brightness measured at each point is then divided by the backlight brightness at the corresponding position, and the average is taken to obtain the transmittance of the display substrate. Actual testing has found that the transmittance of the display substrate of the present disclosure embodiment can reach at least 9%, which is more than 40% higher than that of conventional display substrates.

[0252] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising an array substrate and a color filter substrate; wherein: The array substrate comprises: a first substrate; A first conductive layer, disposed on one side of the first substrate, comprising first signal lines and first patterns that are spaced apart; A first insulating layer, disposed on a side of the first conductive layer away from the first substrate; a first via hole, at least passing through the first insulating layer and exposing at least a portion of the first signal line; a semiconductor layer, arranged on a side of the first insulating layer away from the first substrate, comprising a semiconductor pattern; the semiconductor pattern comprising a first portion, a second portion and a channel structure located between the first portion and the second portion; an orthographic projection of the first portion on the first substrate partially overlaps with an orthographic projection of the first signal line on the first substrate, and an orthographic projection of the channel structure on the first substrate is located within a range of an orthographic projection of the first pattern on the first substrate; A connecting electrode is disposed on a side of the semiconductor layer away from the first substrate. At least a portion of the connecting electrode is located in the first via hole and is respectively connected to the first portion and the first signal line.

2. The display substrate according to claim 1, wherein: The array substrate further includes a first electrode, which is disposed on a side of the film layer where the connecting electrode is located away from the first substrate, and an orthographic projection of the first electrode on the first substrate covers an orthographic projection of the first signal line on the first substrate.

3. The display substrate according to claim 2, wherein: The first electrode includes a first extension segment, the extension direction of the first extension segment is the same as the extension direction of the first signal line, the orthographic projection of the first extension segment on the first substrate covers the orthographic projection of the first signal line on the first substrate, and there is a first interval between the boundaries close to each other in the orthographic projection of the first extension segment and the first signal line on the first substrate, and the first interval is 2μm to 5μm.

4. The display substrate according to any one of claims 1 to 3, wherein: The semiconductor layer further includes a second electrode connected to the second portion and integrally provided with the second portion.

5. The display substrate according to claim 4, wherein: An orthographic projection of the second electrode on the first substrate has a second interval from an orthographic projection of the first pattern on the first substrate, and has a third interval from an orthographic projection of the first signal line on the first substrate.

6. The display substrate according to claim 5, wherein: The first insulating layer includes a first groove portion that is concave in a direction close to the first substrate, and the first groove portion is at least partially located between the first signal line and the first pattern; The second interval is greater than or equal to 2 μm; and / or the third interval is greater than or equal to 5 μm.

7. The display substrate according to claim 5, wherein: The array substrate further comprises a flat layer, the flat layer is located between the first conductive layer and the first insulating layer, and a surface of the flat layer away from the first substrate is a flat surface; The orthographic projections of the first conductive layer, the second interval and the third interval on the first substrate are located within the range of the orthographic projection of the planar layer on the first substrate; the second interval is greater than or equal to 1 μm; and / or the third interval is greater than or equal to 3 μm.

8. The display substrate according to any one of claims 1 to 5, wherein: The first insulating layer includes a first groove portion that is concave in a direction close to the first substrate, and at least a portion of the first groove portion is located between the first signal line and the first pattern; the first groove portion includes two first side walls that are oppositely arranged; The first portion includes two first sub-portions covering the two first side walls, and a second sub-portion covering other areas of the first insulating layer, and a thickness of the first sub-portion is smaller than a thickness of the second sub-portion.

9. The display substrate according to claim 8, wherein: The array substrate further comprises a second insulating layer, wherein the second insulating layer is arranged between the semiconductor layer and the film layer where the connecting electrode is located; The first sub-section of the two first sub-sections close to the first signal line is a target sub-section, the first via penetrates the second insulating layer and exposes the target sub-section, the connecting electrode covers the target sub-section, and the size of the channel structure in a direction perpendicular to the first substrate is greater than or equal to 10. The display substrate according to claim 8, wherein: The array substrate further comprises a second insulating layer, wherein the second insulating layer is arranged between the semiconductor layer and the film layer where the connecting electrode is located; The first sub-section of the two first sub-sections close to the first signal line is a target sub-section, the first via hole also penetrates the second insulating layer, and there is a gap between the first via hole and the target sub-section; the size of the channel structure in a direction perpendicular to the first substrate is greater than or equal to 11. The display substrate according to claim 8, wherein: The array substrate further comprises a second insulating layer, wherein the second insulating layer is arranged between the semiconductor layer and the film layer where the connecting electrode is located; The first sub-section of the two first sub-sections close to the first signal line is a target sub-section, the first via penetrates the second insulating layer and exposes the target sub-section, and the connecting electrode is spaced apart from the target sub-section; the size of the channel structure in a direction perpendicular to the first substrate is greater than or equal to 12. The display substrate according to any one of claims 8 to 11, wherein: Along the direction perpendicular to the first substrate, the size of the first conductive layer is 0.4 μm to 0.8 μm; and / or, In a cross section perpendicular to the first substrate and perpendicular to the extension direction of the edge of the first conductive layer, a first angle is formed between the sidewall of the first conductive layer and the first substrate, and the first angle is less than or equal to 50°.

13. The display substrate according to any one of claims 1 to 3, wherein: The array substrate further includes a flat layer, the flat layer is located between the first conductive layer and the first insulating layer, and the surface of the flat layer away from the first substrate is a flat surface; the flat layer at least covers the first signal line, the first pattern, and the interval between the first signal line and the first pattern; The semiconductor layer further includes a second electrode, which is connected to the second portion and integrally arranged with the second portion, and an orthographic projection of the second electrode on the first substrate at least partially does not overlap with an orthographic projection of the planar layer on the first substrate.

14. The display substrate according to claim 13, wherein: In a cross section perpendicular to the first substrate and perpendicular to the extension direction of the side wall of the planar layer, a second angle is provided between the side wall of the planar layer and the first substrate, and the second angle is less than or equal to 50°; and / or, a spacing between a surface of the planar layer away from the first substrate and the first substrate is 0.4 μm to 0.8 μm.

15. The display substrate according to any one of claims 1 to 14, wherein: The first conductive layer includes a plurality of first signal lines, which are arranged at intervals along a first direction and extend along a second direction; The array substrate further includes a plurality of signal line groups, which are spaced apart along the second direction and extend along the first direction; The plurality of first signal lines and the plurality of signal line groups cross to form a grid structure, and an area where the orthographic projections of the signal line group and the first signal line overlap on the first substrate protrudes toward a side away from the first substrate to form a columnar structure; The color filter substrate includes a spacer; the spacer is in a strip shape and extends along the first direction, and the orthographic projection of the spacer on the array substrate partially overlaps with the first signal line and the signal line group; The signal line group includes a winding area, and the winding area is arranged at a position where at least one of the signal line groups intersects with the first signal line. The orthographic projection of the spacer in the winding area on the array substrate does not overlap with the columnar structure.

16. The display substrate according to claim 15, wherein: The side of the spacer away from the color filter substrate abuts against a portion of the columnar structure.

17. The display substrate according to claim 16, wherein: The side of the spacer away from the color film substrate is at the same distance from the color film substrate.

18. The display substrate according to claim 15, wherein: The signal line group in the winding area protrudes toward the first direction.

19. The display substrate according to claim 15, wherein: The size of the spacer along the first direction is greater than the distance between two adjacent first signal lines.

20. The display substrate according to claim 15, wherein: The signal line group and the connection electrode are made of the same material and are arranged in the same layer.

21. The display substrate according to any one of claims 17 to 20, wherein: The signal line group includes a second signal line, and the orthographic projection of the second signal line on the color filter substrate coincides with the spacer; The size of the second signal line in the second direction is C1, and the size of the end of the spacer close to the array substrate in the second direction is C4, and C4 is larger than C1.

22. The display substrate according to any one of claims 17 to 20, wherein: The signal line group includes a second signal line and a third signal line, and the orthographic projection of the spacer on the array substrate covers the area between the second signal line and the third signal line; The orthographic projection of the spacer on the array substrate partially overlaps with the second signal line; The orthographic projection of the spacer on the array substrate partially overlaps with the third signal line.

23. The display substrate according to claim 22, wherein: The size of the second signal line in the second direction is C1, the size of the third signal line in the second direction is C2, the interval between the second signal line and the third signal line is C3, and the size of the end of the spacer close to the array substrate in the second direction is C4; C1, C2, C3 and C4 satisfy: C2>C1, C4=C3+C1; or, C1, C2, C3 and C4 satisfy: C1>C2, C4=C3+C2.

24. The display substrate according to claim 22, wherein: The winding area is provided at a position where at least one of the second signal lines and / or at least one of the third signal lines crosses the first signal line.

25. The display substrate according to claim 24, wherein: The array substrate includes a first electrode, and the third signal line is connected to the first electrode at one side of the protrusion in the winding area along the first direction.

26. The display substrate according to claim 20, wherein: The orthographic projection of one of the spacers on the array substrate has an overlapping area with at least thirteen of the first signal lines and an overlapping area with one of the signal line groups; the winding area is provided at at least eleven of the intersections between the at least thirteen first signal lines and the one signal line group.

27. The display substrate according to claim 26, wherein: A grid structure formed by a plurality of the first signal lines and a plurality of the signal line groups defines a plurality of pixel areas; at least one spacer is disposed in every twenty-four pixel areas.

28. The display substrate according to claim 16, wherein: The orthographic projection of the spacer on the array substrate overlaps with the signal line group or the first signal line in part; the spacer includes a main spacer area with a first thickness and a sub-spacer area with a second thickness, and the first thickness is greater than the second thickness; the orthographic projection of the main spacer area on the array substrate has an overlapping area with the first signal line, and the orthographic projection of the main spacer area on the array substrate does not overlap with the signal line group.

29. The display substrate according to claim 28, wherein: The orthographic projection of the main spacer area on the array substrate overlaps with at least two of the first signal lines.

30. The display substrate according to any one of claims 16 to 29, wherein: The color filter substrate further includes a black matrix; the orthographic projection of the black matrix on the array substrate covers the spacers, the first signal lines and the signal line group.

31. The display substrate according to claim 30, wherein: The black matrix includes a first part, and the orthographic projection of the first part on the array substrate covers the semiconductor pattern, the first pattern, and the overlapping area of ​​the signal line group and the first signal line; the first part and the surface of the spacer close to the array substrate in the orthographic projection on the array substrate have a fourth interval between the mutually adjacent boundaries, and the fourth interval is 20μm to 40μm.

32. The display substrate according to claim 30 or 31, wherein: The black matrix also includes a second part, the orthographic projection of the second part on the array substrate covers an area of ​​the signal line group that is staggered with the first pattern and the semiconductor pattern in the second direction, and the part of the black matrix covering the same signal line group includes the first part and the second part that are staggered along the first direction; the second part and the signal line group have a fifth interval between their mutually adjacent boundaries in the orthographic projection on the array substrate, and the fifth interval is 3μm to 6μm.

33. The display substrate according to any one of claims 30 to 32, wherein: The first insulating layer includes a first groove portion that is concave in a direction close to the first substrate, and at least a portion of the first groove portion is located between the first signal line and the first pattern; The black matrix also includes a third part, the orthographic projection of the third part on the array substrate covers the first signal line, and there is a sixth interval between the boundaries of the third part and the first signal line close to each other in the orthographic projection on the first substrate, and the sixth interval is 0.5μm to 2μm.

34. The display substrate according to claim 33, wherein: The transmittance of the display substrate is greater than or equal to 6%.

35. The display substrate according to any one of claims 30 to 32, wherein: The array substrate further includes a flat layer, the flat layer is located between the first conductive layer and the first insulating layer, and the surface of the flat layer away from the first substrate is a flat surface; the flat layer includes a first flat portion, and the first flat portion covers the first signal line; The black matrix includes a third portion, the orthographic projection of the third portion on the array substrate covers the first flat portion, and there is a seventh interval between mutually adjacent boundaries of the third portion and the first flat portion in the orthographic projection on the first substrate, and the seventh interval is 0.5 μm to 2 μm.

36. The display substrate according to claim 35, wherein: The transmittance of the display substrate is greater than or equal to 9%.

37. A display device comprising: The display substrate according to any one of claims 1 to 36; The driving circuit board is electrically connected to the display substrate and is configured to transmit a control signal to the display substrate.

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