Solid state storage device and performance maintaining method thereof

Abstract

The invention relates to a solid-state storage device and an efficiency maintaining method thereof. The invention provides a solid state storage device. The solid state storage device is configured to be electrically connected to a host. The solid-state storage device comprises a controller, a volatile memory and a non-volatile memory. The controller divides the non-volatile memory into a plurality of functional regions. The controller sets a functional area weight value corresponding to the priority of each functional area, and uses a weight cycle mechanism to execute the number of access instructions of each functional area according to the functional area weight value of each functional area. The controller sets a submission queue weight value corresponding to each submission queue in each functional area. The controller is configured to increase a commit queue weight value corresponding to a particular commit queue to maintain the particular commit queue at a predetermined performance in response to a performance of the particular commit queue in a particular functional region of the functional regions being below a performance threshold.

Description

Technical Field

[0001] The present invention relates to a solid-state storage device, and more particularly to a solid-state storage device and a performance maintaining method thereof. Background Art

[0002] Solid state storage devices use non-volatile memory to store data. With the development of technology, they have been widely used in different computer systems. However, the traditional single-root I / O virtualization (SR-IOV) architecture can only calculate the performance of each endurance group in the non-volatile memory when executing access instructions. When there is a need to improve the performance of the commit queue corresponding to a specific namespace in a specific endurance group, the traditional single-root I / O virtualization architecture cannot perform relevant settings for the commit queue to improve the performance when executing the access instructions of the commit queue. Summary of the invention

[0003] Therefore, the present invention provides a solid-state storage device and a performance maintenance method thereof to solve the above-mentioned problems.

[0004] In one embodiment, the present invention provides a solid-state storage device configured to be electrically connected to a host. The solid-state storage device includes: a controller; a volatile memory electrically connected to the controller; and a non-volatile memory electrically connected to the controller. The controller is configured to divide the non-volatile memory into a plurality of functional areas. The controller is configured to set a functional area weight value corresponding to the priority of each functional area, and use a weight cycle mechanism to execute the number of access instructions of each functional area according to the functional area weight value of each functional area. The controller is configured to set a submission queue weight value corresponding to each submission queue in each functional area. In response to the performance of a specific submission queue in a specific functional area of ​​the functional areas being lower than a performance threshold, the controller is configured to increase the submission queue weight value corresponding to the specific submission queue to maintain the specific submission queue at a predetermined performance.

[0005] In another embodiment, the present invention further provides a performance maintenance method for a solid-state storage device, which is electrically connected to a host and includes a controller, a volatile memory, and a non-volatile memory. The method includes: using the controller to divide the non-volatile memory into multiple functional areas; using the controller to set a functional area weight value corresponding to the priority of each functional area, and using a weight cycle mechanism to execute the number of access instructions of each functional area according to the functional area weight value of each functional area; using the controller to set a submission queue weight value corresponding to each submission queue in each functional area; and in response to the performance of a specific submission queue in a specific functional area among the functional areas being lower than a performance threshold, using the controller to increase the submission queue weight value corresponding to the specific submission queue to maintain the specific submission queue at a predetermined performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram of a computer system according to an embodiment of the present invention.

[0007] Figure 2A FIG. 4 is a schematic diagram of a single-root input / output virtualization architecture of a solid-state storage device according to an embodiment of the present invention.

[0008] Figure 2B According to the present invention Figure 2A A schematic diagram of the submission queue and completion queue corresponding to each namespace in an embodiment of the present invention.

[0009] Figure 2C According to the present invention Figure 2A Schematic diagram of a submission queue and a completion queue in a solid-state storage device in an embodiment of the present invention.

[0010] Figure 3 FIG. 4 is a schematic diagram of a single-root input / output virtualization architecture of a solid-state storage device according to another embodiment of the present invention.

[0011] Figure 4A Schematic diagram of a command capture mechanism defined by the NVMe standard according to an embodiment of the present invention.

[0012] Figure 4B FIG. 4 is a schematic diagram of a command capture mechanism defined by the NVMe standard according to another embodiment of the present invention.

[0013] Figure 5 FIG. 4 is a flow chart of a method for maintaining performance of a solid-state storage device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0014] The following description is a preferred implementation of the invention, and its purpose is to describe the basic spirit of the invention, but it is not intended to limit the invention. The actual content of the invention must refer to the following claims.

[0015] It must be understood that the words "comprise", "include" and the like used in this specification are intended to indicate the existence of specific technical features, values, method steps, operation processing and / or components, but do not exclude the addition of more technical features, values, method steps, operation processing, components, or any combination of the above.

[0016] The words "first", "second", "third", etc. used in the claims are used to modify the components in the claims and are not used to indicate a priority order, a prior relationship, or that one component precedes another component, or a temporal sequence in executing method steps. They are only used to distinguish components with the same name.

[0017] The term "configured to" may describe or claim that various units, circuits, or other components are "configured to" perform a task or tasks. In such contexts, the term "configured to" is used to imply structure by indicating that the units / circuits / components include structure (e.g., circuitry) that performs those task(s) during operation. Thus, even when a given unit / circuit / component is not currently operating (e.g., not turned on), the unit / circuit / component may still be said to be configured to perform the task. The units / circuits / components used with the term "configured to" include hardware - e.g., circuits, memory (storing program instructions executable to perform operations), etc. In addition, "configured to" may include generic structures (e.g., generic circuitry) that are manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in a manner capable of performing the task(s) to be solved. "Configured to" may also include adapting a manufacturing process (eg, a semiconductor manufacturing facility) to produce devices (eg, integrated circuits) adapted to perform or execute one or more tasks.

[0018] Figure 1 is a block diagram of a computer system according to an embodiment of the present invention.

[0019] like Figure 1As shown, the computer system 1 includes a solid-state storage device 10 and a host 20, wherein the solid-state storage device 10 is electrically connected to the host 20 via a bus 11 to perform command and data transmission. In some embodiments, the bus 11 can be a Universal Serial Bus (USB), a Serial Advanced Technology Attachment (SATA) bus, a Peripheral Component Interconnect Express (PCI Express, PCIe) bus, etc., but the present disclosure is not limited thereto.

[0020] The solid-state storage device 10 includes a controller 102, a volatile memory 106, and a non-volatile memory 108. The controller 102 is electrically connected to the volatile memory 106 and the non-volatile memory 108, and is used to control data access of the volatile memory 106 and the non-volatile memory 108. In some embodiments, the controller 102 may be, for example, a general-purpose processor, a microcontroller, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), etc., but the present disclosure is not limited thereto.

[0021] The volatile memory 106 includes, for example, a dynamic random access memory (DRAM) and / or a static random access memory (SRAM), but the present disclosure is not limited thereto. In some embodiments, the volatile memory 106 may be disposed outside the controller 102, for example. In other embodiments, the volatile memory 106 may be integrated into the controller 102, for example. The non-volatile memory 108 may be, for example, a NAND flash memory for storing write data provided by the host 20.

[0022] The host 20 includes, for example, a processor 202 and a system memory 204, and the processor 202 is electrically connected to the system memory 204. In some embodiments, the processor 202 includes, for example, a central processing unit (CPU), a general purpose processor, a microprocessor, etc., but the disclosure is not limited thereto. In addition, the processor 202 includes a controller (not shown) for controlling data access to the system memory 204. The system memory 204 includes, for example, a dynamic random access memory, but the disclosure is not limited thereto.

[0023] In some embodiments, the host 20 may support the non-volatile memory communication protocol (NVM Express, NVMe), and the system memory 204 is configured with a submission queue (SQ) 2041, a completion queue (CQ) 2042, a data buffer 2043 and a virtual machine 2044. The submission queue 2041 is used to record the access instructions issued by the processor 202, and the completion queue 2042 is used to record the status of the solid-state storage device 10 responding to the completed access instructions. The data buffer 2043 is used to store the data that the host 20 wants to write to the solid-state storage device 10 and to store the data read by the host 20 from the solid-state storage device 10.

[0024] The virtual machine 2044 includes, for example, one or more virtual machines (such as Figure 2B The virtual machines VM0 to VM3 shown in the figure are shown in the figure, and each virtual machine can be regarded as a computer within a computer, and each virtual machine can execute applications and programs, and is almost isolated from other virtual machines executed on the same host. In detail, in the field of computer science, a virtual machine refers to a special software that can establish an environment between a computer platform and an end user, and the end user operates other software based on the environment established by the virtual machine software. A virtual machine is an emulator of a computer system, which can provide the functions of a physical computer by simulating a complete computer system with complete hardware system functions and executed in a completely isolated environment through software.

[0025] In some embodiments, the solid-state storage device 10 may support, for example, the non-volatile memory communication protocol (NVM Express, NVMe), and the controller 102 may retrieve access instructions, such as write instructions, read instructions, etc., from the submission queue 2041 of the host 20. The volatile memory 106 is configured with a submission queue 1061 and a completion queue 1062. The submission queue 1061 is used to record the access instructions retrieved from the host 20, and the completion queue 1062 is used to record the status of the access instructions completed by the solid-state storage device 10.

[0026] The non-volatile memory 108 includes a plurality of blocks, and each block includes a plurality of pages. For example, the non-volatile memory 108 includes 1024 blocks, and each block includes 64 pages. Assuming that the capacity of each page is 16Kbytes, the capacity of each block is 1Mbyte. The above data is only for illustration, and the manufacturer of the non-volatile memory 108 can determine the number of pages in each block and the capacity of each page.

[0027] Figure 2A FIG. 4 is a schematic diagram of a single-root input / output virtualization architecture of a solid-state storage device according to an embodiment of the present invention. Figure 2B According to the present invention Figure 2A Schematic diagram of the submission queue, completion queue and virtual machine of the host in an embodiment of the present invention. Figure 2C According to the present invention Figure 2A Schematic diagram of a submission queue and a completion queue in a solid-state storage device in an embodiment of the present invention.

[0028] In some embodiments, the single-root I / O virtualization architecture (SR-IOV) of the non-volatile memory 108 is as follows: Figure 2A As shown, the single-root input / output virtualization architecture includes endurance groups Endg0 and Endg1. Single-root input / output virtualization means that a physical PCIe device (such as solid-state storage device 10) can be virtualized to simulate multiple accessible PCIe devices. It should be noted that a person with ordinary knowledge in the field of the present invention should understand that the endurance groups in the non-volatile memory 108 are not limited to two, and the non-volatile memory 108 can also have one endurance group or more than two endurance groups.

[0029] like Figure 2A As shown, the non-volatile memory 108 includes a plurality of function areas Func0, Func1, Func2 and Func3, wherein the function areas Func0 and Func1 belong to the endurance group Endg0, the function area Func3 belongs to the endurance group Endg1, and the function area Func2 spans the endurance groups Endg0 and Endg1. In some embodiments, each of the function areas Func0-Func3 can be regarded as a physical function area (physical function) or a virtual function area (virtual function), and respectively corresponds to the virtual machines VM0-VM3 (or application programs) executed by the host 20. That is, each of the virtual machines VM0-VM3 can control the data access of the corresponding physical function area and virtual function area in the solid-state storage device 10 through each physical PCIe port on the solid-state storage device 10.

[0030] In some embodiments, the NAND memory cells in the non-volatile memory 108 can be divided into single-level cells (SLC) and triple-level cells (TLC), and the single-level cells can be classified into endurance group Endg0, and the triple-level cells can be classified into endurance group Endg1. In other embodiments, the non-volatile memory 108 includes a plurality of non-volatile memory sets (NVM sets), and each non-volatile memory set can include one or more namespaces, wherein each functional area Func0~Func3, for example, has a corresponding non-volatile memory set.

[0031] like Figure 2A As shown, the functional area Func0 includes namespaces NS0 and NS1, the functional area Func1 includes namespaces NS2 and NS3, the functional area Func2 includes namespaces NS4 and NS5, and the functional area Func3 includes namespaces NS6 and NS7. For the host 20, each namespace NS0-NS7 can be regarded as a physical disk volume, that is, the namespace NS0-NS7 can divide the non-volatile memory 108 into separately addressable logical storage spaces. In some embodiments, each of the namespaces NS0-NS7 has a separate namespace ID. In other embodiments, some of the namespaces NS0-NS7 share the same namespace ID.

[0032] In addition, if Figure 2B As shown, each namespace NS0-NS7 has a separate submission queue 2041 (eg, SQ0-SQ7) and completion queue 2042 (eg, CQ0-CQ7) in the system memory 204 of the host 20. Figure 2C As shown, each namespace NS0-NS7 also has a respective commit queue 1061 (eg, LSQ0-LSQ7) and completion queue 1062 (eg, LCQ0-LCQ7) in the volatile memory 106 of the solid-state storage device 10. Figure 2B As shown, the submit queue 2041 of the host 20 includes submit queues SQ0-SQ7, and the completion queue 2042 includes completion queues CQ0-CQ7. In addition, the submit queue 1061 of the solid-state storage device 10 includes submit queues LSQ0-LSQ7, and the completion queue 1062 includes completion queues LCQ0-LCQ7. In one embodiment, the submit queues LSQ0-LSQ7 correspond to the submit queues SQ0-SQ7, and the completion queues LCQ0-LCQ7 correspond to the completion queues CQ0-CQ7.

[0033] For example, when the controller 102 retrieves an access instruction corresponding to the namespace NS0 from the submit queue SQ0 of the host 20, the controller 102 stores the retrieved access instruction of the namespace NS0 in the submit queue LSQ0, wherein the access instruction includes information such as the durability group number, the functional area number, and the namespace number corresponding to the namespace NS0, but the present invention is not limited thereto. When a specific access instruction in the submit queue LSQ0 has been executed by the controller 102, the controller 102 writes the instruction completion information corresponding to the specific access instruction to the completion queue LCQ0, and deletes the specific access instruction from the submit queue LSQ0. Then, the controller 102 writes the instruction completion information corresponding to the specific access instruction to the completion queue CQ0 of the host 20, and deletes the specific access instruction from the submit queue SQ0 of the host 20. The relevant operations of the controller 102 to retrieve and execute the access instructions corresponding to other namespaces NS1 to NS7 can be inferred in a similar manner, so the details are not repeated here. In another embodiment, the submission queues LSQ0-LSQ7 do not correspond one-to-one to the submission queues SQ0-SQ7, and the completion queues LCQ0-LCQ7 do not correspond one-to-one to the completion queues CQ0-CQ7. The order of using the submission queues LSQ0-LSQ7 and the completion queues LCQ0-LCQ7 depends on the time when the controller 102 captures, executes and completes the access instructions.

[0034] like Figure 2A As shown, the namespace NS0 has transmission paths 210 and 220, which means that the controller 102 can retrieve the access instruction of the submit queue SQ0 from the host 20 through the transmission path 210 to store it in the submit queue LSQ0 of the volatile memory 106, and can write the instruction completion information corresponding to the access instruction that has been executed in the submit queue LSQ0 to the completion queue CQ0 of the host 20 through the transmission path 220. In addition, when the controller 102 executes the access instruction (such as a write instruction or a read instruction) of the namespace NS0 in the submit queue LSQ0, it can control the data access of the namespace NS0 through the transmission paths 210 and 220, for example, it can obtain the write data of the write instruction from the data buffer 2043 of the host 20, or execute the read instruction to read the corresponding data from the namespace NS0 and write it to the data buffer 2043 of the host 20.

[0035] In some embodiments, the endurance group Endg0 includes namespaces NS0-NS4, and the write execution delay of the endurance group Endg0 takes into account the write execution delay of the entire namespaces NS0-NS4, wherein the write execution delay represents the time interval between the controller 102 storing the access instructions captured from the host 20 in the corresponding commit queues LSQ0-LSQ4 and actually executing the access instructions stored in the commit queues LSQ0-LSQ4. For example, when the controller 102 actually executes the access instructions of each functional area Func0-Func2 in the endurance group Endg0, the controller 102 can calculate the bandwidth of the data stream 231 when executing the access instructions related to the endurance group Endg0 to obtain the performance P_endg0 (e.g., write performance) of the endurance group Endg0. Similarly, the endurance group Endg1 includes namespaces NS5-NS7, and the write execution delay of the endurance group Endg1 takes into account the write execution delay of the entire namespaces NS5-NS7. In addition, when the controller 102 actually executes access instructions of each functional area Func2-Func3 in the endurance group Endg1, the controller 102 can calculate the bandwidth of the data flow 232 when executing the access instructions related to the endurance group Endg1 to obtain the performance P_endg1 (eg, write performance) of the endurance group Endg1.

[0036] Figure 3 FIG. 4 is a schematic diagram of a single-root input / output virtualization architecture of a solid-state storage device according to another embodiment of the present invention. Figure 4A Schematic diagram of a command capture mechanism defined by the NVMe standard according to an embodiment of the present invention. Figure 4B This is a schematic diagram of the instruction capture mechanism defined by the NVMe standard in another embodiment of the present invention. Figure 3 and Figures 4A-4B .

[0037] Figure 3 The SR-IOV architecture is similar to Figure 2A The difference of SR-IOV architecture is Figure 3In the SR-IOV architecture, the controller 102 can calculate the performance of each functional area Func0~Func3, and can calculate the performance of each submission queue corresponding to each namespace in each functional area Func0~Func3, for example, submission queues SQ0 and SQ1 correspond to namespaces NS0 and NS1 in the functional area Func0, submission queues SQ2 and SQ3 correspond to namespaces NS2 and NS3 in the functional area Func1, submission queues SQ4 and SQ5 correspond to namespaces NS4 and NS5 in the functional area Func2, and submission queues SQ6 and SQ7 correspond to namespaces NS6 and NS7 in the functional area Func3. In addition, the controller 102 can set the priority of each functional area Func0~Func3, for example, high priority (high priority, which can be represented by H), medium priority (medium priority, which can be represented by M) or low priority (low priority, which can be represented by L), and the functional area weight value corresponding to the priority of each functional area Func0~Func3. The controller 102 can also set the submission queue weight value of each submission queue corresponding to each namespace in each functional area Func0-Func3.

[0038] For example, the NVMe standard specification defines two command fetch mechanisms, such as the Round Robin (RR) mechanism and the Weighted Round Robin mechanism. Figure 4A As shown, the WRR mechanism is as follows Figure 4B For ease of explanation, Figure 4A This illustrates that the solid state storage device 10 retrieves instructions from the commit queues SQ0-SQ7 through the RR mechanism, which can be applied to Figure 2ASR-IOV architecture. However, a person with ordinary skill in the art will appreciate that the submit queue 2041 of the host 20 may include different numbers of submit queues. Specifically, when the submit queues SQ0 to SQ7 of the host 20 have all stored access instructions, the controller 102 of the solid-state storage device 10 may, after receiving a notification from the host 20 (for example, based on the doorbell registers corresponding to each submit queue SQ0 to SQ7), retrieve access instructions from the submit queues SQ0 to SQ7, and store the retrieved access instructions in the corresponding submit queues LSQ0 to LSQ7. When the controller 102 performs the RR mechanism on the access instructions stored in the submit queues SQ0 to SQ7 (i.e., corresponding to LSQ0 to LSQ7), the controller 102 performs operations S40 to S47 in turn to retrieve a predetermined number of access instructions from the submit queues SQ0 to SQ7, respectively, and store the retrieved access instructions in the submit queues LSQ0 to LSQ7, respectively. The controller 102 then executes a predetermined number of access instructions (eg, 10 access instructions) in the commit queues LSQ0 - LSQ7 .

[0039] It should be noted that in Figure 4A In the RR mechanism, the controller 102 does not consider the functional area weight value of each functional area Func0~Func3, and each commit queue SQ0~SQ7 (corresponding to LSQ0~LSQ7) has the same commit queue weight value (for example: 10), that is, the same number of access instructions, and the controller 102 will repeat operations S40~S47 according to the set commit queue weight value of the commit queue SQ0~SQ7 (corresponding to LSQ0~LSQ7).

[0040] For ease of explanation, in the following embodiments, the operation of the controller 102 fetching and executing a predetermined number of access instructions (i.e., corresponding to the commit queue weight value of the commit queue SQ0) from the commit queue SQ0 means that the controller 102 fetches the predetermined number of access instructions from the commit queue SQ0, writes the fetched access instructions to the commit queue LSQ0 of the solid-state storage device 10, and then executes the predetermined number of access instructions in the commit queue LSQ0. The operation of the controller 102 fetching and executing a predetermined number of access instructions from other commit queues SQ1 to SQ7 can also be inferred in a similar manner.

[0041] Figure 4BIt is to illustrate that the solid-state storage device 10 can execute the WRR mechanism on functional areas with different priorities, and can execute the WRR mechanism on submission queues with different priorities in each functional area. For the convenience of explanation, the functional area Func0 has a high priority (H), the functional area Func1 has a medium priority (M), and the functional area Func2 has a low priority (L). In addition, the functional areas Func0, Func1 and Func2 all have corresponding functional area weight values ​​Func_WEI_H, Func_WEI_M and Func_WEI_L. In detail, the controller 102 retrieves and executes the access instructions of each functional area Func0, Func1 and Func2 from the submission queues SQ0~SQ5 according to the corresponding functional area weight values ​​Func_WEI_H, Func_WEI_M and Func_WEI_L of each functional area Func0, Func1 and Func2.

[0042] Assuming that the functional area weight values ​​Func_WEI_H, Func_WEI_M and Func_WEI_L corresponding to the functional areas Func0, Func1 and Func2 are 250, 150 and 100 respectively, under the WRR mechanism, the controller 102 will preferentially execute the 250 access instructions of the functional area Func0 (operation S60), then execute the 150 access instructions of the functional area Func1 (operation S61), and then execute the 100 access instructions of the functional area Func2 (operation S62). In addition, the submission queues SQ0 and SQ1 corresponding to the namespaces NS0 and NS1 in the functional area Func0 have high priority and medium priority respectively, and the submission queue weight values ​​corresponding to the submission queues SQ0 and SQ1 are 150 and 100 respectively. When the controller 102 executes 250 access instructions of the functional area Func0, under the WRR mechanism, the controller 102 preferentially fetches and executes 150 access instructions of the commit queue SQ0 (operation S50), and then fetches and executes 100 access instructions of the commit queue SQ1 (operation S51).

[0043] Figure 4BThe WRR mechanism of the controller 102 can be divided into steps 1 to 7, for example. First, the controller 102 performs operation S60 to select a functional area Func0 with a high priority according to the WRR mechanism (step 1), and fetches and executes a total of 250 access instructions from the commit queues SQ0 and SQ1 corresponding to the functional area Func0, or until there are no access instructions in the commit queues SQ0 and SQ1 (step 2). Next, the controller 102 performs operation S61 to select a functional area Func1 with a medium priority according to the WRR mechanism (step 3), and fetches and executes a total of 150 access instructions from the commit queues SQ2 and SQ3 corresponding to the functional area Func1, or until there are no access instructions in the commit queues SQ2 and SQ3 (step 4). Finally, the controller 102 performs operation S62 to select the functional area Func2 with a low priority according to the WRR mechanism (step 5), and fetches and executes a total of 100 access instructions from the submit queues SQ4 and SQ5 corresponding to the functional area Func2, or until there are no access instructions in the submit queues SQ4 and SQ5 (step 6). In step 7, the controller 102 repeats the above steps 1 to 6.

[0044] When the controller 102 repeatedly executes the above steps 1 to 6, the controller 102 can simultaneously calculate the performance P_endgN_F_pri corresponding to the functional areas with high priority, medium priority and low priority in the endurance group N, which can be expressed by formula (1), for example:

[0045]

[0046] Among them, if the functional area Func0 in the durability group 0 has a high priority, P_endgN_F_pri can be expressed as P_endg0_0_H, and so on. Func_num_pri represents the number of functional areas of a certain priority. If the functional areas Func1 and Func2 are both medium priorities, Func_num_M=2, and so on. Func_WEI_pri represents the functional area weight value corresponding to the priority of each functional area. If the functional area Func0 is a high priority and its functional area weight value is 250, Func_WEI_pri can be expressed as Func_WEI_H=250, and so on. Func_totalWEI represents the sum of the functional area weight values ​​corresponding to the functional areas with high priority, medium priority and low priority. If Func_WEI_H = 250, Func_WEI_M = 150, and Func_WEI_L = 100, then Func_totalWEI = 250 + 150 + 100 = 500. P_endgN represents the performance corresponding to the durability group N, which can be obtained by summing up the performance of each submission queue corresponding to the durability group N.

[0047] In some embodiments, in addition to using the WRR mechanism between functional areas of different priorities, the controller 102 may also use the WRR mechanism for each submission queue corresponding to each functional area of ​​each priority. The performance P_SQ_pri of each submission queue corresponding to a functional area with a specific priority can be expressed by formula (2):

[0048]

[0049] Among them, SQ_num_pri represents the number of submission queues of a certain priority. For the sake of convenience, the submission queues LSQ0 and LSQ1 corresponding to the functional area Func0 are taken as examples. If the submission queue LSQ0 is of high priority and the submission queue LSQ1 is of medium priority, then SQ_num_H=1 and SQ_num_M=1, and so on. SQ_WEI_pri represents the submission queue weight value corresponding to the priority of each submission queue. If the submission queue SQ0 is of high priority and the submission queue SQ1 is of medium priority, the submission queue weight values ​​corresponding to the submission queues SQ0 and S1 are 150 and 100, then SQ_WEI_H=150, and SQ_WEI_M=100, and so on. SQ_totalWEI represents the sum of the corresponding submission queue weight values ​​of the submission queues with high priority, medium priority and low priority. If SQ_WEI_H=150 and SQ_WEI_M=100, then SQ_totalWEI=150+100=250. P_endgN_F_pri represents the corresponding performance of a specific functional area with high priority, medium priority or low priority in endurance group N. For example, when the controller 102 executes the access instruction of each functional area Func0~Func3, the controller 102 can calculate the data bandwidth of the corresponding data streams DS_F0, DS_F1, (DS_F2_1+DS_F2_2) and DS_F3 of each functional area Func0~Func3 to obtain the corresponding performance of each functional area Func0~Func3.

[0050] In some embodiments, assuming that the functional area Func0 has a high priority and the namespaces NS0 and NS1 in the functional area Func0 correspond to the submission queues SQ0 and SQ1, the controller 102 may also set the priorities corresponding to the submission queues SQ0 and SQ1, for example, high priority, medium priority or low priority. For ease of explanation, the submission queues SQ0 and SQ1 corresponding to the functional area Func0 having a high priority have a high priority and a medium priority respectively, which means that the submission queue SQ0 is a submission queue having a high priority in the functional area Func0 having a high priority.

[0051] In some embodiments, for example, when the controller 102 executes the access instructions of the submit queues SQ0 and SQ1 corresponding to the functional area Func0, the controller 102 can also calculate the data bandwidth on the transmission paths 310 and 311 to obtain the performance of the submit queues SQ0 and SQ1, such as Figure 3 The performance P_SQ_pri is shown.

[0052] In some embodiments, some applications (or virtual hosts) executed by the host 20 have extremely high write time requirements or read time requirements, such as real-time video streaming applications, autonomous driving systems, automatic braking systems, etc. When it is necessary to write the scene images captured by one or more image sensors to the solid-state storage device 10 in real time, and the solid-state storage device 10 must ensure that the data is programmed into the non-volatile memory 108 within the write time requirements specified by the application, the corresponding functional area of ​​such applications can be set by the controller 102 to have high priority. In addition, some applications (or virtual hosts) executed by the host 20 do not have particularly strict write time requirements and / or read time requirements, such as audio and video playback programs, etc., so the corresponding functional areas of such applications can be set by the controller 102 to have low priority. If some applications (or virtual hosts) executed by the host 20 have general write time requirements and / or read time requirements, the corresponding functional areas of such applications can be set by the controller 102 to have medium priority. Those with ordinary knowledge in the field of the present invention should understand that the types of the above-mentioned applications are only for illustration purposes, but the present invention is not limited thereto.

[0053] In some embodiments, the controller 102 may set a performance threshold for a high-priority commit queue corresponding to a high-priority functional area (e.g., the commit queue SQ0 / LSQ0 corresponding to the functional area Func0). When the performance of the commit queue calculated by the controller 102 is lower than the performance threshold, the controller 102 increases the commit queue weight value corresponding to the commit queue to maintain the commit queue at a predetermined performance (e.g., which can be represented by a predetermined bandwidth (bytes / second)). For example, assuming that the functional area Func0 is a high-priority functional area, its functional area weight value is 250, and the commit queues SQ0 and SQ1 have high priority and medium priority, respectively, and their corresponding commit queue weight values ​​are 150 and 100, respectively. If the application executed by the host 20 corresponding to the functional area Func0 has a very high write time requirement and / or read time requirement, the commit queue weight value of the commit queue SQ0 needs to be set to more than 130 to maintain the performance of the commit queue SQ0 at a write time and / or read time that meets the requirements of the application. However, when the solid-state storage device 10 has a large amount of access load, the controller 102 may cause a performance loss of the submit queue SQ0 due to the delay caused by the large amount of access load when executing the WRR mechanism, such as reducing the performance of the submit queue SQ0 to less than a predetermined ratio (e.g., 90%) of the original performance (e.g., 100 MB / s) of the submit queue SQ0. At this time, the controller 102 sets the submit queue weight value corresponding to the submit queue SQ0 to be adjusted (e.g., increased to 165) to maintain the performance of the submit queue SQ0 at the predetermined performance (i.e., maintaining the data bandwidth when executing the access instruction of the submit queue SQ0) to meet the write time and / or read time required by the application.

[0054] exist Figure 2A In the architecture, the controller 102 can only calculate the performance of each durability group separately. Depending on the virtual machine running on the host 20, if a specific commit queue in a specific functional area in a specific durability group is highly important to the specific virtual machine running on the host 20 (for example, it has a very strict write time requirement and / or read time requirement) or there is a demand for higher performance for the specific commit queue, the controller 102 Figure 2A Under the architecture, it is not possible to individually set the functional area weight value corresponding to each functional area Func0~Func3, let alone individually set the submission queue weight value (SQ weight) of the submission queue corresponding to each namespace in each functional area Func0~Func3. Therefore, it is also impossible to adjust the performance of any submission queue corresponding to each functional area Func0~Func3.

[0055] exist Figure 3In the architecture, the controller 102 can not only calculate the performance corresponding to each durability group, but also calculate the performance of each functional area in each durability group, and can also calculate the performance of each submission queue in each functional area. In addition, the controller 102 can also individually set the functional area weight value corresponding to each functional area Func0~Func3, and individually set the submission queue weight value of the submission queue corresponding to each namespace in each functional area Func0~Func3, so the controller 102 can adjust the performance of any submission queue corresponding to each functional area Func0~Func3. In other words, when there is a demand for the performance of a specific submission queue in a specific functional area, the controller 102 can improve the performance of the specific submission queue by adjusting the submission queue weight value corresponding to the specific submission queue, or maintain the specific submission queue at a predetermined performance.

[0056] Figure 5 This is a flow chart of a method for maintaining the performance of a solid-state storage device according to an embodiment of the present invention. Figure 3 and Figure 5 .

[0057] In step 510, the controller 102 divides the non-volatile memory 108 into a plurality of functional areas. For example, the non-volatile memory 108 may include functional areas Func0-Func3, which correspond to virtual machines VM0-VM3 executed by the host 20, respectively, wherein the virtual machines VM0-VM3 may control data access of the functional areas Func0-Func3, respectively.

[0058] In step 520, the controller 102 sets a functional area weight value corresponding to the priority of each functional area, and uses a weighted round-robin mechanism to execute the corresponding number of access instructions for each functional area according to the functional area weight value of each functional area. Figure 4B As shown, the functional area Func0 has a high priority (H), the functional area Func1 has a medium priority (M), and the functional area Func2 has a low priority (L). In addition, the functional areas Func0, Func1, and Func2 all have corresponding functional area weight values ​​Func_WEI_H, Func_WEI_M, and Func_WEI_L. The controller 102 retrieves and executes the access instructions of each functional area Func0, Func1, and Func2 from the submission queues LSQ0-LSQ5 according to the corresponding functional area weight values ​​Func_WEI_H, Func_WEI_M, and Func_WEI_L of each functional area Func0, Func1, and Func2.

[0059] In step 530, the controller 102 sets the submission queue weight value corresponding to the priority of each submission queue in each functional area. For example, in addition to using the WRR mechanism between functional areas with different priorities, the controller 102 can also use the WRR mechanism for each submission queue corresponding to each functional area with different priorities. Figure 4B As shown, different submission queues (e.g., SQ0 and SQ1) in a specific functional area (e.g., functional area Func0) may have different priorities and corresponding submission queue weight values, and the controller 102 may execute the WRR mechanism of the specific functional area according to the submission queue weight values ​​corresponding to each submission queue in the specific functional area, such as Figure 4B As shown in operations S50 and S51.

[0060] In step 540, in response to the performance of the specific submission queue in the specific functional area being lower than the performance threshold, the controller 102 increases the submission queue weight value corresponding to the specific submission queue to maintain the specific submission queue at a predetermined performance. For example, the controller 102 may set a performance threshold for a specific submission queue with a high priority corresponding to a functional area with a high priority (e.g., submission queue SQ0 corresponding to functional area Func0). When the performance of the specific submission queue calculated by the controller 102 is lower than the performance threshold, the controller 102 increases the submission queue weight value corresponding to the specific submission queue to maintain the specific submission queue at a predetermined performance (e.g., represented by a predetermined bandwidth (bytes / second)).

[0061] Although the present invention is disclosed as above with preferred embodiments, it is not intended to limit the scope of the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the definition of the appended claims.

[0062] Explanation of symbols

[0063] 1 Computer System

[0064] 10 Solid-state storage device

[0065] 11 Bus

[0066] 20 Host

[0067] 102 Controller

[0068] 106 Volatile Memory

[0069] 108 Non-volatile memory

[0070] 202 Processor

[0071] 204 System Memory

[0072] 210-217, 220-227 transmission path

[0073] 231, 232 Data Stream

[0074] 310-317, 320-327 transmission paths

[0075] 331, 332 Data Flow

[0076] 500 Methods

[0077] Steps 510-540

[0078] 1061 Submission Queue

[0079] 1062 Completed Queue

[0080] 2041 Submission Queue

[0081] 2042 Completed Queue

[0082] 2043 Data Buffer

[0083] 2044 Virtual Machine

[0084] CQ0-CQ7, LCQ0-LCQ7 completed queue

[0085] DS_F0, DS_F1, DS_F2_1, DS_F2_2, DS_F3 data flow

[0086] Endg0, Endg1 durability group

[0087] Func0, Func1, Func2, Func3 functional area

[0088] NS0-NS7 Namespace

[0089] P_SQ_pri, P_endg0_0_pri, P_endg0, P_endg1 performance

[0090] S40-S47, S50-S55, S60-S62 Operation

[0091] SQ0-SQ7, LSQ0-LSQ7 submission queue

[0092] VM0-VM3 virtual machines

Claims

1. A solid-state storage device configured to be electrically connected to a host, the solid-state storage device comprising: Controller; a volatile memory electrically connected to the controller; as well as A non-volatile memory is electrically connected to the controller, wherein: The controller is configured to divide the non-volatile memory into a plurality of functional areas; The controller is configured to set a functional area weight value corresponding to the priority of each functional area, and uses a weighted cycle mechanism to execute the number of access instructions of each functional area according to the functional area weight value of each functional area; The controller is configured to set a corresponding submission queue weight value for each submission queue in each functional area; as well as In response to a performance of a specific submission queue of a specific functional area among the functional areas being lower than a performance threshold, the controller is configured to increase the submission queue weight value corresponding to the specific submission queue to maintain the specific submission queue at a predetermined performance.

2. The solid-state storage device according to claim 1, wherein: The specific functional area has a high priority among the functional areas, and the specific submission queue has a high priority in the specific functional area.

3. The solid-state storage device according to claim 1, wherein: The data access to each functional area in the non-volatile memory is controlled by one of the plurality of virtual machines executed by the host.

4. The solid-state storage device according to claim 1, wherein: The controller is configured to use a weighted round-robin mechanism to execute the number of access instructions of each commit queue of the specific functional area according to the commit queue weight value of each commit queue of the specific functional area.

5. The solid-state storage device according to claim 1, wherein: The controller is further configured to calculate the data bandwidth when executing access instructions of each commit queue in each functional area to obtain the performance of each commit queue in each functional area.

6. The solid-state storage device according to claim 5, wherein: The controller is further configured to aggregate the performance of each submission queue in each functional area to obtain the performance of each functional area.

7. A method for maintaining performance of a solid-state storage device, the solid-state storage device being electrically connected to a host and comprising a controller, a volatile memory and a non-volatile memory, the method comprising: Using the controller to divide the non-volatile memory into a plurality of functional areas; The controller is used to set a functional area weight value corresponding to the priority of each functional area, and a weight cycle mechanism is used to execute the number of access instructions of each functional area according to the functional area weight value of each functional area; The controller is used to set the corresponding submission queue weight value of each submission queue in each functional area; as well as In response to the performance of a specific submission queue of a specific functional area among the functional areas being lower than a performance threshold, the controller is used to increase a corresponding submission queue weight value of the specific submission queue to maintain the specific submission queue at a predetermined performance.

8. The method of claim 7, wherein: The specific functional area has a high priority among the functional areas, and the specific submission queue has a high priority in the specific functional area.

9. The method of claim 7, wherein: The data access to each functional area in the non-volatile memory is controlled by one of the plurality of virtual machines executed by the host.

10. The method of claim 7, further comprising: The controller uses a weighted round-robin mechanism according to the commit queue weight values ​​of each commit queue of the specific functional area to execute the access instruction quantity of each commit queue of the specific functional area.

11. The method of claim 7, further comprising: The controller is used to calculate the data bandwidth when executing access instructions of each commit queue in each functional area to obtain the performance of each commit queue in each functional area.

12. The method of claim 11, further comprising: The controller is used to sum up the performance of each submission queue in each functional area to obtain the performance of each functional area.

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