Memory controller and operating method thereof, memory system

Abstract

This disclosure provides a memory controller and its operating method, as well as a memory system. The memory controller includes a register and a processor coupled to the register; the register is configured to cache a first logical address group; wherein the first logical address group is used to indicate N consecutive first logical addresses, where N is an integer greater than 1; the N first logical addresses correspond to N pieces of first data with the same data type; the processor is configured to generate a first identifier code based on the first logical address group and cache the first identifier code in the register; wherein the first identifier code is used to indicate the data type of the N pieces of first data.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory controller and its operating method, and a memory system. Background Technology

[0002] In recent years, the semiconductor integrated circuit industry has experienced rapid development. With the continuous advancement of semiconductor manufacturing processes, the feature size of semiconductor devices has been shrinking, and the integration density of memory has become increasingly higher, resulting in more and more powerful performance. Among them, volatile memory requires power to maintain its data, while non-volatile memory can retain the stored data when no power is supplied.

[0003] While smaller device sizes significantly increase memory capacity, this also makes improving memory space utilization and reliability increasingly challenging. Summary of the Invention

[0004] This disclosure provides a memory controller and its operation method, as well as a memory system.

[0005] In a first aspect, this disclosure provides a memory controller, the memory controller including a cache and a processor coupled to the cache;

[0006] The cache is configured to cache a first logical address group; wherein the first logical address group is used to indicate N consecutive first logical addresses, where N is an integer greater than 1; the N first data corresponding to the N first logical addresses have the same data type;

[0007] The processor is configured to generate a first identifier code based on the first logical address group and cache the first identifier code in the cache; wherein the first identifier code is used to indicate the data type of N pieces of the first data.

[0008] In some embodiments, the first logical address group includes a starting logical address and a logical address length; wherein, the starting logical address is the first or the Nth of a series of N consecutive first logical addresses; the processor is specifically configured to:

[0009] The starting logical address and the length of the logical address are determined based on N consecutive first logical addresses.

[0010] In some embodiments, the cache is further configured to cache a second logical address group; wherein the second logical address group is used to indicate M consecutive second logical addresses, where M is an integer greater than 1; the M second data corresponding to the M second logical addresses have the same data type; the data type of the second data is different from the data type of the first data;

[0011] The processor is further configured to generate a second identifier based on the second logical address group and cache the second identifier in the cache; wherein the second identifier is used to indicate the data type of the M pieces of the second data; the second identifier is different from the first identifier.

[0012] In some embodiments, the cache is further configured to cache P third logical addresses, where P is an integer greater than 0; wherein the P third logical addresses are not contiguous.

[0013] The processor is further configured to generate P corresponding third identifiers based on P of the third logical addresses, and cache the third identifiers in the cache; wherein the third identifiers are used to indicate the data type of the third data corresponding to the third logical address.

[0014] In some embodiments, the memory controller is configured to receive a plurality of logical addresses and data corresponding to the plurality of logical addresses; wherein the logical addresses include the first logical address and / or the third logical address;

[0015] The processor is also configured to:

[0016] Determine whether the received multiple logical addresses are consecutive and whether the data corresponding to the multiple logical addresses are of the same data type, and generate a determination result;

[0017] When the judgment result indicates that multiple logical addresses are consecutive and the data corresponding to the multiple logical addresses are of the same data type, the first identifier code is generated based on the judgment result.

[0018] In some embodiments, the processor is further configured to:

[0019] When the judgment result indicates that multiple logical addresses are not contiguous, multiple third identifier codes are generated based on the judgment result.

[0020] In some embodiments, the processor is further configured to:

[0021] When the sum of the capacity of the first identifier and the capacity of N first data entries reaches a preset capacity, the first identifier and the N first data entries in the cache are stored in the memory device.

[0022] or,

[0023] Based on a power-off command from the host and / or the detection of an abnormal power outage, the first identifier and N records of the first data in the buffer are stored in the memory device.

[0024] In a second aspect, this disclosure provides a method for operating a memory controller, the memory controller including a cache and a processor coupled to the cache, the method comprising:

[0025] The cache caches a first logical address group; wherein the first logical address group is used to indicate N consecutive first logical addresses, where N is an integer greater than 1; the N first data corresponding to the N first logical addresses have the same data type;

[0026] The processor generates a first identifier code based on the first logical address group and caches the first identifier code in the cache; wherein, the first identifier code is used to indicate the data type of N pieces of the first data.

[0027] In some embodiments, the first logical address group includes a starting logical address and a logical address length; wherein, the starting logical address is the first or the Nth of a series of N consecutive first logical addresses; the operation method further includes:

[0028] The processor determines the starting logical address and the logical address length based on N consecutive first logical addresses.

[0029] In some embodiments, the operating method further includes:

[0030] The buffer caches a second logical address group; wherein the second logical address group is used to indicate M consecutive second logical addresses, where M is an integer greater than 1; the M second logical addresses correspond to M pieces of second data with the same data type; the data type of the second data is different from the data type of the first data;

[0031] The processor generates a second identifier code based on the second logical address group and caches the second identifier code in the cache; wherein, the second identifier code is used to indicate the data type of the M pieces of the second data; the second identifier code is different from the first identifier code.

[0032] In some embodiments, the operating method further includes:

[0033] The cache caches P third logical addresses, where P is an integer greater than 0; wherein the P third logical addresses are not consecutive.

[0034] The processor generates P corresponding third identifiers based on the P third logical addresses, and caches the third identifiers in the cache; wherein, the third identifier is used to indicate the data type of the third data corresponding to the third logical address.

[0035] In some embodiments, the operating method further includes:

[0036] Receive multiple logical addresses and data corresponding to the multiple logical addresses; wherein, the logical addresses include the first logical address and / or the third logical address;

[0037] The processor determines whether the received multiple logical addresses are consecutive and whether the data corresponding to the multiple logical addresses are of the same data type, and generates a determination result;

[0038] When the judgment result indicates that multiple logical addresses are consecutive and the data corresponding to the multiple logical addresses are of the same data type, the processor generates the first identifier code based on the judgment result.

[0039] In some embodiments, the operating method further includes:

[0040] When the judgment result indicates that multiple logical addresses are not contiguous, the processor generates multiple third identifier codes based on the judgment result.

[0041] In some embodiments, the operating method further includes:

[0042] The processor stores the first identifier and the N first data entries in the cache into a memory device based on the sum of the capacities of the first identifier and the N first data entries reaching a preset capacity.

[0043] or,

[0044] The processor, based on a power-down command from the host and / or the detection of an abnormal power outage, stores the first identifier and N records of the first data in the cache into a memory device.

[0045] Thirdly, this disclosure provides a memory system, the memory system comprising: a memory device and a memory controller coupled to the memory device; the memory controller comprising a cache and a processor coupled to the cache;

[0046] The cache is configured to cache a first logical address group; wherein the first logical address group is used to indicate N consecutive first logical addresses, where N is an integer greater than 1; the N first data corresponding to the N first logical addresses have the same data type;

[0047] The processor is configured to generate a first identifier code based on the first logical address group and cache the first identifier code in the cache; wherein, the first identifier code is used to indicate the data type of N pieces of the first data;

[0048] The processor is also configured to store the first identifier and N records of the first data in the cache to the memory device.

[0049] In some embodiments, the first logical address group includes a starting logical address and a logical address length; wherein, the starting logical address is the first or the Nth of a series of N consecutive first logical addresses; the processor is specifically configured to:

[0050] The starting logical address and the length of the logical address are determined based on N consecutive first logical addresses.

[0051] In some embodiments, the cache is further configured to cache P third logical addresses, where P is an integer greater than 0; wherein the P third logical addresses are not contiguous.

[0052] The processor is further configured to generate P corresponding third identifiers based on P of the third logical addresses, and cache the third identifiers in the corresponding caches; wherein the third identifiers are used to indicate the data type of the third data corresponding to the third logical address.

[0053] In some embodiments, the memory controller is configured to receive a plurality of logical addresses and data corresponding to the plurality of logical addresses; wherein the logical addresses include the first logical address and / or the third logical address;

[0054] The processor is also configured to:

[0055] Determine whether the received multiple logical addresses are consecutive and whether the data corresponding to the multiple logical addresses are of the same data type, and generate a determination result;

[0056] When the judgment result indicates that multiple logical addresses are consecutive and the data corresponding to the multiple logical addresses are of the same data type, the first identifier code is generated based on the judgment result.

[0057] In some embodiments, the processor is further configured to:

[0058] When the judgment result indicates that multiple logical addresses are not contiguous, multiple third identifier codes are generated based on the judgment result.

[0059] In some embodiments, the processor is further configured to:

[0060] When the sum of the capacity of the first identifier and the capacity of N first data entries reaches a preset capacity, the first identifier and the N first data entries in the cache are stored in the memory device.

[0061] or,

[0062] Based on a power-off command from the host and / or the detection of an abnormal power outage, the first identifier and N records of the first data in the buffer are stored in the memory device.

[0063] In this embodiment, N first logical addresses are consecutive, and the data types of the N first data corresponding to the N first logical addresses are the same. The processor is configured to generate a first identifier code based on the first logical address group and cache the first identifier code in the cache. Thus, only one first identifier code is needed to indicate the data types of the N first data entries. On the one hand, this reduces the storage capacity occupied by the identifier code in the cache, improving the storage space utilization of the cache; on the other hand, in the event of a power failure, the memory controller can quickly store the data and identifier code in the cache into a non-volatile memory device, reducing the risk of data error and loss, thereby improving the reliability of the memory. Attached Figure Description

[0064] Figure 1 A schematic diagram of a system with a memory provided for an embodiment of this disclosure;

[0065] Figure 2a A schematic diagram of a memory card provided in an embodiment of this disclosure;

[0066] Figure 2b A schematic diagram of a solid state drive (SSD) provided in an embodiment of this disclosure;

[0067] Figure 3 A schematic diagram of a memory system provided in an embodiment of this disclosure;

[0068] Figure 4 A schematic diagram illustrating an identifier and logical address stored in a cache and memory device, provided for embodiments of this disclosure;

[0069] Figure 5 A schematic diagram of a first identifier and a first logical address group stored in a cache and memory device, provided for an embodiment of this disclosure;

[0070] Figure 6 A schematic diagram of a second identifier and a second logical address group stored in a cache and memory device, provided for embodiments of this disclosure;

[0071] Figure 7 This is a schematic diagram of a third identifier and a third logical address stored in a cache and memory device, as provided in an embodiment of this disclosure. Detailed Implementation

[0072] To facilitate understanding of this disclosure, exemplary embodiments of the disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the disclosure are shown in the drawings, it should be understood that the disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the disclosure and to fully convey the scope of the disclosure to those skilled in the art.

[0073] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with this disclosure, certain technical features well-known in the art are not described; that is, not all features of the actual embodiments, nor well-known functions and structures, may be described herein.

[0074] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0075] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit the scope of this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0076] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0077] Figure 1 A schematic diagram of a system 100 having memory according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0078] like Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory device 104.

[0079] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital Memory Card (SD Card), Compact Flash Card (CF Card), Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as solid-state drives (SSDs) or embedded multimedia cards (eMMCs), used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0080] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and write (also known as programming) operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECCs) relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with a host (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with the host 108 through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), Peripheral Component Interconnect Express (PCIE), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced System Device Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0081] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a general-purpose flash memory package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2aIn one example shown, the memory controller 106 and a single memory device 104 can be integrated into the memory card 202. The memory card 202 may include a PC card (Personal Computer Memory Card International Association, PCMCIA), a CF card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Reduced-Size MMC (RS-MMC), a Multimedia Card Micro (MMCmicro), an SD card (SD, miniSD, microSD, SDHC), Universal Flash Storage (UFS), etc. The memory card 202 may also include a connection between the memory card 202 and a host (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0082] In embodiments of this disclosure, each of the memory chips (dies) may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), trinary-level cells (TLC), quad-level cells (QLC), and penta-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices may include one or more arrays of memory cells, such as SLC arrays, MLC arrays, TLC arrays, QLC arrays, or any combination of such arrays.

[0083] Figure 3This is a schematic diagram of a memory system 300 provided in an embodiment of the present disclosure. The memory system 300 includes a memory controller 310 and at least one memory device 320 coupled to the memory controller 310. The memory controller 310 includes a processor 311 and a cache 312. The memory system 300 includes, but is not limited to, solid-state drives, such as enterprise SSDs (eSSDs). The memory device 320 can be a non-volatile storage device, such as NAND flash memory, NOR flash memory, etc. The memory controller 310 may include one or more integrated circuits and / or discrete components, caches, or combinations thereof in hardware. The memory controller 310 can be configured to receive data and commands from a host 400 and operate on the memory device 320, such as read, erase, and write operations. The processor 311 in the memory controller 310 can be a microcontroller, a special-purpose logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC)), etc. The register 312 can be a static random access memory (SRAM), dynamic random access memory (DRAM), etc. The following explanation uses SRAM as an example.

[0084] Figure 4 This diagram illustrates an identifier and logical address in a register 312 and a memory device 320, as provided in an embodiment of this disclosure. The register 312 can be used to cache multiple data entries (not in...). Figure 4 As shown in the diagram, the buffer 312 contains Q logical addresses to physical addresses (L2P) corresponding to multiple data entries, where each data entry corresponds to a logical address and a physical address. The logical addresses of these multiple data entries can be consecutive (i.e., sequential data) or non-consecutive (i.e., random data). For example, buffer 312 contains Q logical addresses Ltu1 to Ltu... Q Each logical address in the array is associated with Q physical addresses Fla1 to Fla1. QEach physical address in the register corresponds one-to-one, and Q is an integer greater than 0. The register 312 can also store Q identifiers (Opcodes). Each identifier (Opcode) indicates the data type of a piece of data corresponding to a logical address, facilitating the tracking of the source of each piece of data. These data types include, but are not limited to, trimmed data, host data, garbage collection (GC) data, or wear leveling (WL) data. It is understood that the data types indicated by any two identifiers (Opcodes) can be the same or different; that is, the data types of any two pieces of data can be the same or different. In some embodiments, each identifier occupies 4 bytes of storage space, each logical address occupies 4 bytes of storage space, and each physical address also occupies 4 bytes of storage space.

[0085] Since the cache 312 is generally a volatile memory with a small storage capacity, the logical address to physical address mapping information in the cache 312, as well as the multiple identifiers corresponding to multiple data entries, can be transferred to the memory device 320 under certain conditions. For example, when the sum of the storage capacity of the identifiers, logical addresses, physical addresses, and data (or any combination of one or more of these) in the cache 312 reaches a preset capacity, the processor 311 can transfer the identifiers, logical addresses, physical addresses, and data in the cache 312 to the memory device 320. Furthermore, the processor 311 can also transfer the identifiers, logical addresses, physical addresses, and data in the cache 312 to the memory device 320 based on a power-off command from the host 400 and / or the detection of an abnormal power failure.

[0086] Understandably, each piece of data requires an identifier (Opcode) to mark its data type, and each piece of data also needs a corresponding logical address to establish a mapping relationship between logical address and physical address. For example, Q pieces of data require 4Q bytes of storage space to store Q identifiers, and also require 4Q bytes of storage space to store Q logical addresses. This results in a large amount of storage space occupied by the identifiers and logical addresses in the cache 312 and the memory device 320, leading to low utilization of the storage space in both. Furthermore, due to the large storage space occupied by the identifiers and logical addresses, when the processor 311 receives a power-off command from the host 400, the transfer of the identifiers and logical addresses from the cache 312 to the memory device 320 is slow, thus affecting the operating efficiency of the memory system 300. In the event of an abnormal power outage, the slow transfer of the identifiers and logical addresses from the cache 312 to the memory device 320 may lead to data errors and data loss, affecting the reliability of the memory system 300.

[0087] In view of this, in order to solve one or more of the above-mentioned technical problems, this disclosure provides a memory.

[0088] like Figure 3 As shown, this disclosure provides a memory controller 310, which includes a cache 312 and a processor 311 coupled to the cache 312;

[0089] The buffer 312 is configured to cache a first logical address group; wherein, the first logical address group is used to indicate N consecutive first logical addresses, where N is an integer greater than 1; the data types of the N first data corresponding to the N first logical addresses are the same;

[0090] The processor 311 is configured to generate a first identifier code based on the first logical address group and cache the first identifier code in the cache 312; wherein the first identifier code is used to indicate the data type of N pieces of the first data.

[0091] In this disclosure embodiment, reference is made to Figure 5The first logical address group Ltulist1 indicates N consecutive first logical addresses. The processor 311 can generate a first identifier code Opcode1 based on the N consecutive logical addresses and the same data type of the first data, and the first logical address group Ltulist1. The first identifier code Opcode1 is then cached in the cache 312. It can be understood that the N first data items here are sequential data. For example, the data type represented by the first identifier code Opcode1 includes, but is not limited to, trimmed data, host data, garbage collection data, or wear-leveling data.

[0092] Thus, N pieces of initial data only need to be identified by a single first identifier, Opcode1, to mark their data type, compared to... Figure 4 The embodiment shown (where each piece of data requires an identifier to mark the data type) can greatly reduce the storage space occupied by the identifier, resulting in higher storage space utilization of the cache 312 and the memory device 320. Furthermore, when the processor 311 receives a power-off command from the host 400 (i.e., a normal power-off of the memory system), the first identifier, Opcode1, is transferred from the cache 312 to the memory device 320 quickly, reducing the operation time required for a normal power-off and thus improving the efficiency of the memory system 300. In the event of an abnormal power-off, because the first identifier, Opcode1, is transferred from the cache 312 to the memory device 320 quickly, the possibility of data errors and data loss is low, thereby improving the reliability of the memory system 300.

[0093] It should be noted that the first logical address group Ltulist1 stored in the cache 312 can also be generated by the processor 311. For details, please refer to the following embodiments.

[0094] Furthermore, for random data (i.e., multiple data entries with non-contiguous logical addresses), or when any two logically adjacent data entries in a sequence have different data types (e.g., Ltu1 and Ltu2 are contiguous but have different data types), the processor 311 can still use... Figure 4 The illustrated embodiment generates a corresponding identifier for each piece of data, thereby achieving compatibility with both sequential and random data.

[0095] In some embodiments, such as Figure 5 As shown, the first logical address group Ltulist1 includes a starting logical address StartLtu1 and a logical address length LtuCnt1; wherein, the starting logical address is the first or the Nth of a series of consecutive first logical addresses; the processor is specifically configured as follows:

[0096] The starting logical address StartLtu1 and the logical address length LtuCnt1 are determined based on N consecutive first logical addresses.

[0097] In this embodiment of the disclosure, the processor may further determine the starting logical address StartLtu1 and the logical address length LtuCnt1 based on N consecutive first logical addresses. For example, the N consecutive first logical addresses are Ltu1, Ltu2, ..., Ltu... N-1 Ltu N The processor can convert Ltu1 or Ltu N The starting logical address StartLtu (i.e., the first or last first logical address) is determined, and N is determined as the logical address length LtuCnt1. Thus, the starting logical address StartLtu1 and the logical address length LtuCnt1 constitute the first logical address group Ltulist1, and N consecutive first logical addresses can be represented using the starting logical address StartLtu1 and the logical address length LtuCnt1. It is understandable that, compared to... Figure 4 Each piece of data requires a corresponding logical address to establish an L2P mapping relationship. Here, the first N pieces of data only require a starting logical address StartLtu1 and a logical address length LtuCnt1 to establish an L2P mapping relationship, thus further compressing the storage space occupied by logical addresses in the cache. While improving the storage space utilization of the cache and memory device, the processor can also quickly store the identifier and logical address (L2P mapping information) in the cache into a non-volatile memory device, reducing the risk of data errors and loss, thereby improving the reliability of the memory system.

[0098] In some embodiments, such as Figure 6 As shown, the buffer 312 is further configured to cache a second logical address group Ltulist2; wherein, the second logical address group Ltulist2 is used to indicate M consecutive second logical addresses, where M is an integer greater than 1; the M second data corresponding to the M second logical addresses have the same data type; the data type of the second data is different from the data type of the first data;

[0099] The processor is further configured to generate a second identifier code Opcode2 based on the second logical address group Ltulist2, and cache the second identifier code Opcode2 in the cache 312; wherein, the second identifier code Opcode2 is used to indicate the data type of M pieces of the second data; the second identifier code Opcode2 is different from the first identifier code Opcode1.

[0100] In this embodiment of the disclosure, the processor can also generate multiple different identifier codes based on sequential data of different data types; that is, sequential data of the same data type generate a corresponding identifier code. For example, the processor can generate a first logical address group Ltulist1 based on N consecutive logical address data entries, and generate a first identifier code Opcode1 based on Ltulist1. Furthermore, the processor can generate a second logical address group Ltulist2 based on M consecutive logical address data entries, and generate a second identifier code Opcode2 based on Ltulist2. Here, the data types indicated by the first identifier code Opcode1 and the second identifier code Opcode2 are different.

[0101] It is understandable that, in addition to the first identifier Opcode1 and the second identifier Opcode2, the cache 312 can also store other identifiers. One identifier can be used to represent the data type of multiple data items with the same data type and consecutive logical addresses (an identifier can also represent the data type of a single random data item). The number of identifiers is not strictly limited here. In other words, the cache 312 can store multiple logical address groups, each configured with a corresponding identifier.

[0102] For example, the k data entries correspond to k consecutive logical addresses Ltu1, Ltu2, ..., Ltu1. k-1 Ltu k k>M+N and k is an integer, where the data types of the first to Nth data entries are the same and their logical addresses are Ltu1 to Ltu2. N Continuous (i.e., the first N data entries above), the data from the (N+1)th to the (N+M)th data entries have the same data type and logical address Ltu. N+1 To Ltu N+M Continuous (i.e., the M second data entries mentioned above), the data types of the N+M+1th to the kth data entries are the same and their logical address is Ltu. N+M+1 To Ltu kThe data types of the first, second, and fourth data are different. Thus, the processor can generate corresponding first, second, and fourth identifier codes respectively, and cache them in cache 312. It is worth noting that the data types of the first and fourth data can also be the same, but the processor will still generate first and fourth identifier codes (the storage location of the identifier codes in the cache or memory device can be adjacent to the corresponding logical address group, thus distinguishing them even when the data types are the same). In this way, multiple data entries and their corresponding L2P information and identifier codes can be flexibly stored, thereby compressing the storage space of identifier codes and logical addresses as much as possible, improving the storage space utilization of the cache and memory device, and enhancing the stability of the memory system.

[0103] In some embodiments, such as Figure 6 As shown, the buffer 312 is further configured to cache P third logical addresses, where P is an integer greater than 0; wherein the P third logical addresses are not consecutive.

[0104] The processor is further configured to generate P corresponding third identifier codes Opcode3 based on P of the third logical addresses, and cache the third identifier codes Opcode3 in the cache 312; wherein, the third identifier code Opcode3 is used to indicate the data type of the third data corresponding to the third logical address.

[0105] In this embodiment of the disclosure, the processor can further generate P corresponding third identifier codes Opcode3 based on P non-contiguous third data entries and the corresponding P non-contiguous third logical addresses, and cache the third identifier codes Opcode3 in the cache 312. It is understood that each third identifier code Opcode3 is used to indicate the data type of a third data entry; therefore, the data types indicated by any two third identifier codes Opcode3 can be the same or different.

[0106] It should be noted that the cache 312 may include one or more of the first identifier, the second identifier, and the third identifier. That is, for sequential data, the processor can determine whether the data types are the same, and then choose whether to compress the identifier and logical address group, thereby improving the storage space utilization of the cache and memory device; while for random data, the processor can use... Figure 4 The illustrated embodiment generates a corresponding identifier for each piece of data, thereby achieving compatibility with both sequential and random data.

[0107] In some embodiments, the memory controller 310 is configured to receive a plurality of logical addresses and data corresponding to the plurality of logical addresses; wherein the logical addresses include the first logical address and / or the third logical address;

[0108] The processor 311 is also configured to:

[0109] Determine whether the received multiple logical addresses are consecutive and whether the data corresponding to the multiple logical addresses are of the same data type, and generate a determination result;

[0110] When the judgment result indicates that multiple logical addresses are consecutive and the data corresponding to the multiple logical addresses are of the same data type, the first identifier code is generated based on the judgment result.

[0111] In some embodiments, the processor 311 is further configured to:

[0112] When the judgment result indicates that multiple logical addresses are not contiguous, multiple third identifier codes are generated based on the judgment result.

[0113] In this embodiment, the processor 311 can detect and judge the continuity of multiple logical addresses corresponding to multiple data items, as well as the data types of the multiple data items, and generate a judgment result. Then, based on the judgment result, it generates a first identifier (sequential data with the same data type) or multiple third identifiers (random data, or any two data items with adjacent logical addresses in the sequential data items have different data types). The processor 311 may include an arbitrator circuit to perform the above judgment operation and generate the judgment result. It should be noted that the order of judging whether the logical addresses of the multiple data items are consecutive and whether the data types of the multiple data items are the same is not strictly limited; the specific judgment order can be determined according to actual design requirements.

[0114] Exemplarily, the memory controller 310 receives k pieces of data and corresponding k logical addresses, where the first to the (i - 1)-th logical addresses are discontinuous, the i-th to the j-th logical addresses are continuous, the (j + 1)-th to the k-th logical addresses are discontinuous, i, j, and k are all positive integers, and i > 2, i < j, j + 1 < k; the data types of the i-th to the t-th pieces of data are the same, i < t and t + 2 < j, the data type of the (t + 1)-th piece of data is different from the data types of the i-th to the t-th pieces of data, the data types of the (t + 2)-th to the j-th pieces of data are the same, and the data types of the (t + 2)-th to the j-th pieces of data are different from the data type of the (t + 1)-th piece of data. Thus, the processor 311 can generate corresponding i - 1 identification codes based on the first to the (i - 1)-th pieces of data, generate corresponding 1 identification code based on the i-th to the t-th pieces of data, generate corresponding 1 identification code based on the (t + 1)-th piece of data, generate corresponding 1 identification code based on the (t + 2)-th to the j-th pieces of data, and generate corresponding k - j identification codes based on the (j + 1)-th to the k-th pieces of data.

[0115] In some embodiments, the processor 311 is further configured to:

[0116] Based on the sum of the first identification code and the capacities of N pieces of the first data reaching a preset capacity, store the first identification code and N pieces of the first data in the buffer 312 into the memory device 320;

[0117] Or,

[0118] Based on a power-off command from the host 400 and / or detecting an abnormal power-off, store the first identification code and N pieces of the first data in the buffer 312 into the memory device 320.

[0119] In the embodiments of the present disclosure, since the buffer 312 is generally a volatile memory with a small storage capacity, the logical address to physical address mapping information in the buffer 312, as well as multiple identification codes corresponding to multiple pieces of data, can be transferred to the memory device 320 under certain conditions. Exemplarily, when the sum of the storage identification codes, logical addresses, physical addresses, and data (or any combination of one or more of the four) in the buffer 312 reaches a preset capacity, the processor 311 can transfer the identification codes, logical addresses, physical addresses, and data in the buffer 312 to the memory device 320. Here, the preset capacity is less than or equal to the total capacity of the buffer 312, and the preset capacity can be determined according to the total capacity of the buffer 312 and the read / write performance requirements for the memory system 300.

[0120] Furthermore, the processor 311 can also transfer the identifier, logical address, physical address, and data from the cache 312 to the memory device 320 based on a power-down command from the host 400 and / or upon detecting an abnormal power failure. This significantly reduces the storage space occupied by the identifier and logical address, resulting in higher storage space utilization for the cache 312 and memory device 320. Moreover, due to the reduced storage space occupied by the identifier and logical address, when the processor 311 receives a power-down command from the host 400 (i.e., a normal power failure in the memory system), the transfer of the identifier and logical address from the cache 312 to the memory device 320 is faster, and the operation time required for a normal power failure is shorter, thereby improving the operating efficiency of the memory system 300. In the event of an abnormal power failure, the faster transfer of the identifier from the cache 312 to the memory device 320 reduces the likelihood of data errors and loss, thus improving the reliability of the memory system 300.

[0121] This disclosure provides a method for operating a memory controller, the memory controller including a cache and a processor coupled to the cache, the method comprising:

[0122] The cache caches a first logical address group; wherein the first logical address group is used to indicate N consecutive first logical addresses, where N is an integer greater than 1; the N first data corresponding to the N first logical addresses have the same data type;

[0123] The processor generates a first identifier code based on the first logical address group and caches the first identifier code in the cache; wherein, the first identifier code is used to indicate the data type of N pieces of the first data.

[0124] In some embodiments, the first logical address group includes a starting logical address and a logical address length; wherein, the starting logical address is the first or the Nth of a series of N consecutive first logical addresses; the operation method further includes:

[0125] The processor determines the starting logical address and the logical address length based on N consecutive first logical addresses.

[0126] In some embodiments, the operating method further includes:

[0127] The buffer caches a second logical address group; wherein the second logical address group is used to indicate M consecutive second logical addresses, where M is an integer greater than 1; the M second logical addresses correspond to M pieces of second data with the same data type; the data type of the second data is different from the data type of the first data;

[0128] The processor generates a second identifier code based on the second logical address group and caches the second identifier code in the cache; wherein, the second identifier code is used to indicate the data type of the M pieces of the second data; the second identifier code is different from the first identifier code.

[0129] In some embodiments, the operating method further includes:

[0130] The cache caches P third logical addresses, where P is an integer greater than 0; wherein the P third logical addresses are not consecutive.

[0131] The processor generates P corresponding third identifiers based on the P third logical addresses, and caches the third identifiers in the cache; wherein, the third identifier is used to indicate the data type of the third data corresponding to the third logical address.

[0132] In some embodiments, the operating method further includes:

[0133] Receive multiple logical addresses and data corresponding to the multiple logical addresses; wherein, the logical addresses include the first logical address and / or the third logical address;

[0134] The processor determines whether the received multiple logical addresses are consecutive and whether the data corresponding to the multiple logical addresses are of the same data type, and generates a determination result;

[0135] When the judgment result indicates that multiple logical addresses are consecutive and the data corresponding to the multiple logical addresses are of the same data type, the processor generates the first identifier code based on the judgment result.

[0136] In some embodiments, the operating method further includes:

[0137] When the judgment result indicates that multiple logical addresses are not contiguous, the processor generates multiple third identifier codes based on the judgment result.

[0138] In some embodiments, the operating method further includes:

[0139] The processor stores the first identifier and the N first data entries in the cache into a memory device based on the sum of the capacities of the first identifier and the N first data entries reaching a preset capacity.

[0140] or,

[0141] The processor, based on a power-down command from the host and / or the detection of an abnormal power outage, stores the first identifier and N records of the first data in the cache into a memory device.

[0142] This disclosure also provides a computer-readable storage medium storing executable instructions that, when executed, implement the method described in any of the above embodiments. Exemplarily, the executable instructions may be stored in a memory device 320 and executed by a processor 311. Specifically, the executable instructions may be instructions related to the Flash Translation Layer (FTL). The executable instructions may also be referred to as firmware.

[0143] like Figure 3 As shown, this disclosure provides a memory system 300, which includes a memory device 320 and a memory controller 310 coupled to the memory device 320; the memory controller 310 includes a cache 312 and a processor 311 coupled to the cache 312;

[0144] The buffer 312 is configured to cache a first logical address group; wherein, the first logical address group is used to indicate N consecutive first logical addresses, where N is an integer greater than 1; the data types of the N first data corresponding to the N first logical addresses are the same;

[0145] The processor 311 is configured to generate a first identifier code based on the first logical address group and cache the first identifier code in the cache 312; wherein, the first identifier code is used to indicate the data type of N pieces of the first data;

[0146] The processor 311 is also configured to store the first identifier and N records of the first data in the cache 312 to the memory device 320.

[0147] In this embodiment, the memory controller 310 can be configured to receive data and commands from the host 400 and operate the memory device 320, such as read, erase, and write operations. The processor 311 in the memory controller 310 can be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array, an application-specific integrated circuit), etc. The cache 312 can be a static random access memory (SRAM), a dynamic random access memory (DRAM), etc. The cache 312 can be used to cache multiple data entries and the logical address-to-physical address mapping information corresponding to each data entry, where each data entry corresponds to a logical address and a physical address. The logical addresses of the multiple data entries can be consecutive (i.e., sequential data) or non-consecutive (i.e., random data).

[0148] Processor 311 can generate a first identifier based on N logically consecutive first data entries of the same data type and a first logical address group, and cache the first identifier in cache 312. It can be understood that the N first data entries here are sequential data. For example, the data type represented by the first identifier may include, but is not limited to, trimmed data, host data, garbage collection data, or wear-leveling data.

[0149] Since the cache 312 is generally a volatile memory with a small storage capacity, the logical address to physical address mapping information in the cache 312, as well as the multiple identifiers corresponding to multiple data entries, can be transferred to the memory device 320 under certain conditions. For example, when the sum of the storage capacity of the first identifier, first logical address, physical address, and first data (or any combination of one or more of these) in the cache 312 reaches a preset capacity, the processor 311 can transfer the first identifier, first logical address, physical address, and first data from the cache 312 to the memory device 320. This preset capacity can be determined based on the total capacity of the cache 312 and the read / write performance requirements of the memory system 300. Furthermore, the processor 311 can also transfer the first identifier, first logical address, physical address, and first data from the cache 312 to the memory device 320 based on a power-down command from the host 400 and / or the detection of an abnormal power failure.

[0150] Thus, N pieces of initial data only need to be identified by a single initial identifier to mark their data type, compared to... Figure 4 The embodiment shown (where each piece of data requires an identifier to mark the data type) can greatly reduce the storage space occupied by the identifier, resulting in higher storage space utilization of the cache 312 and the memory device 320. In addition, when the processor 311 receives a power-off command from the host 400, the first identifier is transferred from the cache 312 to the memory device 320 quickly, thereby improving the working efficiency of the memory system 300. In the event of an abnormal power failure, because the first identifier is transferred from the cache 312 to the memory device 320 quickly, the possibility of data errors and data loss is low, thereby improving the reliability of the memory system 300.

[0151] It should be noted that the first logical address group stored in the cache 312 can also be generated by the processor 311. For details, please refer to the above embodiment, which will not be repeated here.

[0152] In some embodiments, the first logical address group includes a starting logical address and a logical address length; wherein, the starting logical address is the first or the Nth of a series of N consecutive first logical addresses; the processor is specifically configured to:

[0153] The starting logical address and the length of the logical address are determined based on N consecutive first logical addresses.

[0154] In some embodiments, the cache is further configured to cache P third logical addresses, where P is an integer greater than 0; wherein the P third logical addresses are not contiguous.

[0155] The processor is further configured to generate P corresponding third identifiers based on P of the third logical addresses, and cache the third identifiers in the corresponding caches; wherein the third identifiers are used to indicate the data type of the third data corresponding to the third logical address.

[0156] In some embodiments, the memory controller is configured to receive a plurality of logical addresses and data corresponding to the plurality of logical addresses; wherein the logical addresses include the first logical address and / or the third logical address;

[0157] The processor is also configured to:

[0158] Determine whether the received multiple logical addresses are consecutive and whether the data corresponding to the multiple logical addresses are of the same data type, and generate a determination result;

[0159] When the judgment result indicates that multiple logical addresses are consecutive and the data corresponding to the multiple logical addresses are of the same data type, the first identifier code is generated based on the judgment result.

[0160] In some embodiments, the processor is further configured to:

[0161] When the judgment result indicates that multiple logical addresses are not contiguous, multiple third identifier codes are generated based on the judgment result.

[0162] In some embodiments, the processor is further configured to:

[0163] When the sum of the capacity of the first identifier and the capacity of N first data entries reaches a preset capacity, the first identifier and the N first data entries in the cache are stored in the memory device.

[0164] or,

[0165] Based on a power-off command from the host and / or the detection of an abnormal power outage, the first identifier and N records of the first data in the buffer are stored in the memory device.

[0166] In some embodiments, the processor generates an identifier, a starting logical address, and a logical address length based on multiple logically consecutive data entries of the same data type. This significantly reduces the storage space occupied by the identifier and logical address. This operation can be implemented by the processor executing executable instructions. It is understood that by examining the source code, it can be found that the data structures of the identifier and logical address have changed in the optimized version of this disclosure.

[0167] Table 1

[0168]

[0169] In some embodiments, the memory system can be an enterprise-grade solid-state drive (SSD). Because the processor can compress the identifier and logical address of sequential data, the storage space occupied by the identifier and logical address in the cache and memory devices is smaller, thus improving the full-disk sequential write capability of the enterprise-grade SSD. For example, referring to Table 1, for writing 1024 sequential data entries of the same data type, if the processor does not compress the identifier and logical address, the storage space occupied by the identifier and logical address is 8K (each data entry's identifier and logical address occupy 8 bytes); if the processor compresses the identifier and logical address, that is, for 1024 sequential data entries of the same data type, only one identifier, one starting logical address, and one logical address length are generated, then the storage space occupied by the identifier and logical address is 8 bytes, only 1 / 1024 of the uncompressed case described above.

[0170] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0171] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A memory controller, characterized in that, The memory controller includes a cache and a processor coupled to the cache; The cache is configured to cache a first logical address group; wherein the first logical address group is used to indicate N consecutive first logical addresses, where N is an integer greater than 1; the N first data corresponding to the N first logical addresses have the same data type; The processor is configured to generate a first identifier code based on the first logical address group and cache the first identifier code in the cache; wherein the first identifier code is used to indicate the data type of N pieces of the first data.

2. The memory controller according to claim 1, characterized in that, The first logical address group includes a starting logical address and a logical address length; wherein, the starting logical address is the first or the Nth of a series of N consecutive first logical addresses; the processor is specifically configured as follows: The starting logical address and the length of the logical address are determined based on N consecutive first logical addresses.

3. The memory controller according to claim 1 or 2, characterized in that, The buffer is further configured to cache a second logical address group; wherein the second logical address group is used to indicate M consecutive second logical addresses, where M is an integer greater than 1; the M second data corresponding to the M second logical addresses have the same data type; the data type of the second data is different from the data type of the first data; The processor is further configured to generate a second identifier based on the second logical address group and cache the second identifier in the cache; wherein the second identifier is used to indicate the data type of the M pieces of the second data; the second identifier is different from the first identifier.

4. The memory controller according to claim 1, characterized in that, The buffer is also configured to cache P third logical addresses, where P is an integer greater than 0; wherein the P third logical addresses are not contiguous. The processor is further configured to generate P corresponding third identifiers based on P of the third logical addresses, and cache the third identifiers in the cache; wherein the third identifiers are used to indicate the data type of the third data corresponding to the third logical address.

5. The memory controller according to claim 4, characterized in that, The memory controller is configured to receive multiple logical addresses and data corresponding to the multiple logical addresses; The processor is also configured to: Determine whether the received multiple logical addresses are consecutive and whether the data corresponding to the multiple logical addresses are of the same data type, and generate a determination result; When the judgment result indicates that multiple logical addresses are consecutive first logical addresses and the data corresponding to the multiple logical addresses are of the same data type, the first identifier code is generated based on the judgment result.

6. The memory controller according to claim 5, characterized in that, The processor is also configured to: When the judgment result indicates that multiple logical addresses are non-contiguous third logical addresses, multiple third identifier codes are generated based on the judgment result.

7. The memory controller according to claim 1, characterized in that, The processor is also configured to: When the sum of the capacity of the first identifier and the capacity of N first data entries reaches a preset capacity, the first identifier and the N first data entries in the cache are stored in the memory device. or, Based on a power-off command from the host and / or the detection of an abnormal power outage, the first identifier and N records of the first data in the buffer are stored in the memory device.

8. A method for operating a memory controller, characterized in that, The memory controller includes a cache and a processor coupled to the cache, and the operation method includes: The cache caches a first logical address group; wherein the first logical address group is used to indicate N consecutive first logical addresses, where N is an integer greater than 1; the N first data corresponding to the N first logical addresses have the same data type; The processor generates a first identifier code based on the first logical address group and caches the first identifier code in the cache; wherein, the first identifier code is used to indicate the data type of N pieces of the first data.

9. The operating method according to claim 8, characterized in that, The first logical address group includes a starting logical address and a logical address length; wherein, the starting logical address is the first or the Nth of a series of N consecutive first logical addresses; the operation method further includes: The processor determines the starting logical address and the logical address length based on N consecutive first logical addresses.

10. The operating method according to claim 8 or 9, characterized in that, The operation method further includes: The buffer caches a second logical address group; wherein the second logical address group is used to indicate M consecutive second logical addresses, where M is an integer greater than 1; the M second logical addresses correspond to M pieces of second data with the same data type; the data type of the second data is different from the data type of the first data; The processor generates a second identifier code based on the second logical address group and caches the second identifier code in the cache; wherein, the second identifier code is used to indicate the data type of the M pieces of the second data; the second identifier code is different from the first identifier code.

11. The operating method according to claim 8, characterized in that, The operation method further includes: The cache caches P third logical addresses, where P is an integer greater than 0; wherein the P third logical addresses are not consecutive. The processor generates P corresponding third identifiers based on the P third logical addresses, and caches the third identifiers in the cache; wherein, the third identifier is used to indicate the data type of the third data corresponding to the third logical address.

12. The operating method according to claim 11, characterized in that, The operation method further includes: The processor receives multiple logical addresses and the data corresponding to those logical addresses; it determines whether the received multiple logical addresses are consecutive and whether the data corresponding to the multiple logical addresses are of the same type, and generates a determination result. When the judgment result indicates that multiple logical addresses are consecutive first logical addresses and the data corresponding to the multiple logical addresses are of the same data type, the processor generates the first identifier code based on the judgment result.

13. The operating method according to claim 12, characterized in that, The operation method further includes: When the judgment result indicates that multiple logical addresses are non-contiguous third logical addresses, the processor generates multiple third identifier codes based on the judgment result.

14. The operating method according to claim 8, characterized in that, The operation method further includes: The processor stores the first identifier and the N first data entries in the cache into a memory device based on the sum of the capacities of the first identifier and the N first data entries reaching a preset capacity. or, The processor, based on a power-down command from the host and / or the detection of an abnormal power outage, stores the first identifier and N records of the first data in the cache into a memory device.

15. A memory system, characterized in that, The memory system includes: a memory device and a memory controller coupled to the memory device; the memory controller includes a cache and a processor coupled to the cache; The cache is configured to cache a first logical address group; wherein the first logical address group is used to indicate N consecutive first logical addresses, where N is an integer greater than 1; the N first data corresponding to the N first logical addresses have the same data type; The processor is configured to generate a first identifier code based on the first logical address group and cache the first identifier code in the cache; wherein, the first identifier code is used to indicate the data type of N pieces of the first data; The processor is also configured to store the first identifier and N records of the first data in the cache to the memory device.

16. The memory system according to claim 15, characterized in that, The first logical address group includes a starting logical address and a logical address length; wherein, the starting logical address is the first or the Nth of a series of N consecutive first logical addresses; the processor is specifically configured as follows: The starting logical address and the length of the logical address are determined based on N consecutive first logical addresses.

17. The memory system according to claim 15, characterized in that, The buffer is also configured to cache P third logical addresses, where P is an integer greater than 0; wherein the P third logical addresses are not contiguous. The processor is further configured to generate P corresponding third identifiers based on P of the third logical addresses, and cache the third identifiers in the corresponding caches; wherein the third identifiers are used to indicate the data type of the third data corresponding to the third logical address.

18. The memory system according to claim 17, characterized in that, The memory controller is configured to receive multiple logical addresses and data corresponding to the multiple logical addresses; the processor is further configured to: Determine whether the received multiple logical addresses are consecutive and whether the data corresponding to the multiple logical addresses are of the same data type, and generate a determination result; When the judgment result indicates that multiple logical addresses are consecutive first logical addresses and the data corresponding to the multiple logical addresses are of the same data type, the first identifier code is generated based on the judgment result.

19. The memory system according to claim 18, characterized in that, The processor is also configured to: When the judgment result indicates that multiple logical addresses are non-contiguous third logical addresses, multiple third identifier codes are generated based on the judgment result.

20. The memory system according to claim 15, characterized in that, The processor is also configured to: When the sum of the capacity of the first identifier and the capacity of N first data entries reaches a preset capacity, the first identifier and the N first data entries in the cache are stored in the memory device. or, Based on a power-off command from the host and / or the detection of an abnormal power outage, the first identifier and N records of the first data in the buffer are stored in the memory device.

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