A method, device, equipment and medium for detecting timing anomalies of integrated circuits

Abstract

The present application provides a method, apparatus, device, and medium for detecting timing anomalies in an integrated circuit, including: using a sliding window to traverse the timing information of each circuit path in a target integrated circuit at a preset window interval; performing feature engineering processing on the timing information of each circuit path to extract the timing features of each circuit path; inputting the timing features of each circuit path into the multi-head self-attention network layer, normalization processing network layer, sparse transition network layer, and fully connected network layer of a timing anomaly detection model to perform timing anomaly detection processing, and outputting abnormal timing information of the integrated circuit; wherein the timing anomaly detection model is obtained by iteratively training the sparse transition network model. When there are a large number of circuit paths in the integrated circuit, the accuracy and efficiency of abnormal timing detection can be improved when the sparse transition network layer and other network layers in the timing anomaly detection model are used to detect timing anomalies in the integrated circuit.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit detection technology, and in particular to a method, device, equipment and medium for detecting timing anomalies of an integrated circuit. Background Art

[0002] In the field of electronic design automation (EDA), static timing analysis (STA) is a key technology used to ensure that digital circuits meet their performance requirements. STA tools use static analysis methods to evaluate and verify the timing behavior of integrated circuit (IC) designs. As IC designs continue to scale, the number of components in the circuits has increased dramatically, and the interconnect structures have become more complex. This complexity requires STA tools to process a large amount of data and paths when counting delays, increasing the difficulty and computational complexity of the analysis. As feature sizes shrink, the resistance and capacitance of interconnects have an increasingly significant impact on signal propagation. This leads to the so-called "interconnect dominance" phenomenon, in which interconnect delays exceed the delay of the transistors themselves. Accurately extracting parameters such as parasitic resistance and capacitance from the physical layout is a complex task, and inaccurate parasitic parameters can lead to skewed STA results. Therefore, how to quickly and accurately detect timing anomalies in ICs has become a critical technical challenge. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a method, device, equipment and medium for detecting timing anomalies in an integrated circuit. When there are a large number of circuit paths in the integrated circuit, the accuracy and efficiency of abnormal timing detection can be improved when timing anomaly detection is performed on the integrated circuit through other network layers such as the sparse transition network layer in the timing anomaly detection model.

[0004] An embodiment of the present application provides a method for detecting timing anomalies of an integrated circuit, the method comprising:

[0005] Traversing the timing information of each circuit path in the target integrated circuit at a preset window interval using a sliding window;

[0006] Performing feature engineering processing on the timing information of each circuit path to extract the timing features of each circuit path;

[0007] The timing features of each circuit path are input into the multi-head self-attention network layer, normalization processing network layer, sparse transition network layer and fully connected network layer of the timing anomaly detection model for timing anomaly detection processing, and the abnormal timing information of the integrated circuit is output; wherein, the timing anomaly detection model is obtained by iteratively training the sparse transition network model.

[0008] In a possible implementation, for each of the timing characteristics of the circuit path, timing anomaly detection is performed through the following steps:

[0009] Inputting the timing features of the circuit path into the multi-head self-attention network layer for attention mechanism processing and outputting attention features;

[0010] Inputting the attention feature into the normalization processing network layer for processing, and outputting the normalized attention feature;

[0011] Inputting the normalized attention features into multiple feedforward sub-network layers of the sparse transformation network layer for feedforward processing, and outputting target features;

[0012] The target feature is input into the fully connected network layer for linear processing, and whether the target feature is abnormal time series information is output.

[0013] In one possible implementation, the inputting the timing features of the circuit path into the multi-head self-attention network layer for attention mechanism processing and outputting the attention features includes:

[0014] Performing an attention mechanism on the timing features of the circuit path to determine a query tensor, a key tensor, and a value tensor corresponding to the timing features;

[0015] Calculating an attention score between the query tensor and the key tensor based on an activation function to determine a probability matrix of the time series feature;

[0016] The time series feature and the probability matrix are multiplied to output the attention feature.

[0017] In one possible implementation, inputting the normalized attention features into multiple feedforward sub-network layers of the sparse transformation network layer for feedforward processing and outputting target features includes:

[0018] Processing the normalized attention features based on the first linear transformation weight matrix corresponding to each of the feedforward sub-network layers to obtain a plurality of reference features;

[0019] Sparse processing is performed based on the weight values ​​of multiple reference features so that the reference feature with the largest weight value is used as the target feature.

[0020] In a possible implementation manner, whether the target feature is abnormal time series information is determined by:

[0021]

[0022] Among them, if the category of Y is 1, the target feature F is abnormal time series information, and if the category of Y is 0, the target feature F is normal time series information. is the second linear transformation matrix.

[0023] In a possible implementation, the time series anomaly detection model is determined by the following steps:

[0024] Inputting the sample timing features of the sample circuit path into the sparse switching network model to perform timing anomaly detection processing to determine a predicted label of the sample timing features;

[0025] The sparse transformation network model is iteratively trained based on the true label of the sample time series feature and the loss value between the predicted label to determine the time series anomaly detection model.

[0026] In a possible implementation, the iterative training of the sparse transformation network model based on the loss value between the real label and the predicted label of the sample time series feature to determine the time series anomaly detection model includes:

[0027] Detecting whether the loss value is greater than a preset threshold;

[0028] If so, the network parameters of the sparse transformation network model are updated, and the updated sparse transformation network model is continuously iteratively trained;

[0029] If not, the iterative training of the sparse transformation network model is stopped to determine the time series anomaly detection model.

[0030] The present application also provides a timing anomaly detection device for an integrated circuit, the timing anomaly detection device comprising:

[0031] A timing information extraction module is used to traverse the timing information of each circuit path in the target integrated circuit at a preset window interval using a sliding window;

[0032] a feature processing module, configured to perform feature engineering processing on the timing information of each circuit path to extract the timing features of each circuit path;

[0033] The detection module is used to input the timing features of each circuit path into the multi-head self-attention network layer, sparse transition network layer and fully connected network layer of the timing anomaly detection model for timing anomaly detection processing, and output abnormal timing information of the integrated circuit; wherein, the timing anomaly detection model is obtained by iteratively training the sparse transition network model.

[0034] An embodiment of the present application also provides an electronic device, comprising: a processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor and the memory communicate through the bus, and when the machine-readable instructions are executed by the processor, the steps of the timing anomaly detection method for an integrated circuit as described above are performed.

[0035] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the above-mentioned method for detecting timing anomalies of an integrated circuit are executed.

[0036] The embodiments of the present application provide a method, apparatus, device, and medium for detecting timing anomalies in an integrated circuit. The method comprises: traversing the timing information of each circuit path in a target integrated circuit at a preset window interval using a sliding window; performing feature engineering processing on the timing information of each circuit path to extract the timing features of each circuit path; inputting the timing features of each circuit path into the multi-head self-attention network layer, normalization processing network layer, sparse transition network layer, and fully connected network layer of a timing anomaly detection model to perform timing anomaly detection processing, and outputting abnormal timing information of the integrated circuit; wherein the timing anomaly detection model is obtained by iteratively training a sparse transition network model. When there are a large number of circuit paths in the integrated circuit, when timing anomaly detection is performed on the integrated circuit through other network layers such as the sparse transition network layer in the timing anomaly detection model, the accuracy and efficiency of abnormal timing detection can be improved.

[0037] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 A flowchart of a timing anomaly detection method for an integrated circuit provided in an embodiment of the present application;

[0040] Figure 2 A schematic diagram of the processing process of the time series anomaly detection model provided in an embodiment of the present application;

[0041] Figure 3This is a structural diagram of a timing anomaly detection device for an integrated circuit provided in an embodiment of the present application;

[0042] Figure 4 This is a second structural diagram of a timing anomaly detection device for an integrated circuit provided in an embodiment of the present application;

[0043] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application for which protection is claimed, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, each other embodiment obtained by those skilled in the art without making creative work falls within the scope of protection of the present application.

[0045] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0046] In order to enable those skilled in the art to use the contents of this application, the following implementation methods are provided in combination with the specific application scenario of "detecting timing anomalies in integrated circuits". For those skilled in the art, the general principles defined herein can be applied to other embodiments and application scenarios without departing from the spirit and scope of this application.

[0047] The following methods, devices, electronic devices, or computer-readable storage media of the embodiments of the present application can be applied to any scenario where timing anomalies of an integrated circuit need to be detected. The embodiments of the present application are not limited to specific application scenarios. Any scheme using the timing anomaly detection method, device, equipment, and medium of an integrated circuit provided by the embodiments of the present application is within the scope of protection of this application.

[0048] First, the application scenarios to which this application is applicable are introduced. This application can be applied in the field of integrated circuit detection technology.

[0049] Research has found that in the field of electronic design automation (EDA), static timing analysis (STA) is a key technology used to ensure that digital circuits meet their performance requirements. STA tools use static analysis methods to evaluate and verify the timing behavior of integrated circuit (IC) designs. As IC designs continue to scale, the number of components in the circuits has increased dramatically, and the interconnect structures have become more complex. This complexity requires STA tools to process a large amount of data and paths when counting delays, increasing the difficulty and computational complexity of the analysis. As feature sizes shrink, the resistance and capacitance of interconnects have an increasingly significant impact on signal propagation. This leads to the so-called "interconnect dominance" phenomenon, in which interconnect delays exceed the delay of the transistors themselves. Accurately extracting parameters such as parasitic resistance and capacitance from the physical layout is a complex task, and inaccurate parasitic parameters can lead to skewed STA results. Therefore, how to quickly and accurately detect timing anomalies in ICs has become a critical technical challenge.

[0050] Based on this, an embodiment of the present application provides a method for detecting timing anomalies in an integrated circuit. When there are a large number of circuit paths in the integrated circuit, the accuracy and efficiency of abnormal timing detection can be improved when timing anomaly detection is performed on the integrated circuit through other network layers such as the sparse transition network layer in the timing anomaly detection model.

[0051] See also Figure 1 , Figure 1 This is a flow chart of a timing anomaly detection method for an integrated circuit provided in an embodiment of the present application. Figure 1 As shown in , the timing anomaly detection method provided by the embodiment of the present application includes:

[0052] S101: Traversing the timing information of each circuit path in the target integrated circuit at a preset window interval using a sliding window.

[0053] In this step, the timing information of each circuit path in the target integrated circuit at a preset window interval is traversed according to the sliding window.

[0054] The timing information includes characteristic data information when the circuit path is working at each time point, and the characteristic data information includes resistance information, capacitance information, and pin information.

[0055] S102: Perform feature engineering processing on the timing information of each circuit path to extract the timing features of each circuit path.

[0056] In this step, feature engineering is performed on the timing information of each circuit path to extract the timing features of each path.

[0057] S103: Input the timing features of each circuit path into the multi-head self-attention network layer, normalization processing network layer, sparse transition network layer and fully connected network layer of the timing anomaly detection model for timing anomaly detection processing, and output the abnormal timing information of the integrated circuit; wherein, the timing anomaly detection model is obtained by iteratively training the sparse transition network model.

[0058] In this step, the timing features of each circuit path are input into the multi-head self-attention network layer, normalization processing network layer, sparse transformation network layer and fully connected network layer of the timing anomaly detection model for timing anomaly detection processing, and the abnormal timing information of the integrated circuit is output.

[0059] The time series anomaly detection model is obtained by iteratively training a sparse transition network model.

[0060] The Sparse Transformer model is designed to optimize the architectural computational complexity and memory consumption of traditional neural network models. It uses a sparse mechanism to reduce the computational complexity of the self-attention mechanism, making it more efficient when processing long sequences, thereby improving the efficiency of abnormal timing detection in integrated circuits.

[0061] Among them, the sparse transformation network layer includes multiple feedforward sub-network layers (FNN).

[0062] In a possible implementation, for each of the timing characteristics of the circuit path, timing anomaly detection is performed through the following steps:

[0063] A: Input the timing features of the circuit path into the multi-head self-attention network layer for attention mechanism processing and output the attention features.

[0064] Here, the timing features of the circuit path are input into the multi-head self-attention network layer for attention mechanism processing, and the attention features are output.

[0065] In one possible implementation, the inputting the timing features of the circuit path into the multi-head self-attention network layer for attention mechanism processing and outputting the attention features includes:

[0066] a: Perform attention mechanism processing on the timing features of the circuit path to determine the query tensor, key tensor, and value tensor corresponding to the timing features.

[0067] Here, through three transformation matrices Get the query tensor Q, key tensor V, and value tensor K:

[0068]

[0069] in, is the output of the previous self-attention network layer.

[0070] b: Calculate the attention score between the query tensor and the key tensor based on the activation function to determine the probability matrix of the time series feature.

[0071] Here, a matrix is ​​constructed for the query tensor and the key tensor, and the attention score between the query tensor and the key tensor in the matrix is ​​calculated according to the activation function to determine the probability matrix of the time series feature.

[0072] Among them, the formula of the softmax operator is as follows, for each element of the matrix Calculate the attention score:

[0073]

[0074] in, To query a tensor, j is the key tensor, k is the total number of features, For the To query a tensor, j is the attention score between the key tensors.

[0075] c: Normalize the temporal features and the attention weight vector, and output the attention features.

[0076] Here, the time series features and the probability matrix are multiplied to output the attention features.

[0077] B: Input the attention feature into the normalization processing network layer for processing, and output the normalized attention feature.

[0078] Here, the attention feature is input into the normalization processing network layer for processing, and the normalized attention feature is output.

[0079] C: Input the normalized attention features into multiple feedforward sub-network layers of the sparse transformation network layer for feedforward processing, and output the target features.

[0080] Here, the normalized attention features are input into multiple feedforward sub-network layers of the sparse transformation network layer for feedforward processing to output the target features.

[0081] In one possible implementation, inputting the normalized attention features into multiple feedforward sub-network layers of the sparse transformation network layer for feedforward processing and outputting target features includes:

[0082] (1): The normalized attention features are processed based on the first linear transformation weight matrix corresponding to each of the forward feedback sub-network layers to obtain multiple reference features.

[0083] Here, the normalized attention features are processed according to the first linear transformation weight matrix corresponding to each of the forward feedback sub-network layers to obtain multiple reference features and corresponding weight values.

[0084] The reference features are obtained in the following way:

[0085]

[0086] Among them, X is the normalized attention feature, For the i The first linear transformation weight matrix of the FFN, For the i Reference features of FFN.

[0087] (2) Sparse processing is performed based on the weight values ​​of multiple reference features so that the reference feature with the maximum weight value is used as the target feature.

[0088] Here, sparse processing is performed based on the weight values ​​of multiple reference features, and the reference feature with the largest weight value is used as the target feature.

[0089] Among them, for indivual , only one is taken through the sparse operation. The sparse function of this application is as follows:

[0090]

[0091] Here, F is the target feature.

[0092] D: Input the target feature into the fully connected network layer for linear processing, and output whether the target feature is abnormal time series information.

[0093] Here, the target feature is input into the fully connected network layer for linear processing, and the output is whether the target feature is abnormal time series information.

[0094] In a possible implementation manner, whether the target feature is abnormal time series information is determined by:

[0095]

[0096] Among them, if the category of Y is 1, the target feature F is abnormal time series information, and if the category of Y is 0, the target feature F is normal time series information. is the second linear transformation matrix.

[0097] For further information, see Figure 2 , Figure 2 This is a schematic diagram of the processing process of the time series anomaly detection model provided in the embodiment of the present application. Figure 2 As shown, the timing features X1 and X2 of the circuit path are input together into the multi-head self-attention network layer of the timing anomaly detection model for processing to obtain the attention features of the timing feature X1 and the attention features of the timing feature X2. The attention features of the timing feature X1 and the attention features of the timing feature X2 are input into the normalization processing network layer for processing to obtain the normalized attention features of the timing feature X1 and the normalized attention features of the timing feature X2. The normalized attention features are input into the multiple forward feedback sub-network layers FFN of the sparse transition network layer for forward feedback processing to obtain reference features and corresponding weight values. The reference feature corresponding to the maximum weight value is input into the fully connected network layer for linear processing, and the output is whether X1 and X2 are abnormal timing information.

[0098] In a possible implementation, the time series anomaly detection model is determined by the following steps:

[0099] I: Inputting the sample timing features of the sample circuit path into the sparse switching network model to perform timing anomaly detection processing and determine the predicted label of the sample timing features.

[0100] Here, the sample timing features of the sample circuit path are input into the sparse transition network model to perform timing anomaly detection processing to determine the predicted label of the sample timing features.

[0101] The process of determining the prediction label is consistent with the process of determining the abnormal time series information described above, and will not be described in detail in this section.

[0102] Here, we traverse all circuits and extract the features of each path as a sample set. This includes information about resistance, capacitance, and pins. Feature engineering is then used to determine the mean, variance, and other parameters. For each path, if the latency difference exceeds a certain threshold, the path is labeled 1, indicating an outlier. This data is then divided into a training set and a test set.

[0103] II: Iteratively training the sparse transformation network model based on the true labels of the sample time series features and the loss value between the predicted labels to determine the time series anomaly detection model.

[0104] Here, the sparse transformation network model is iteratively trained based on the true labels of the sample time series features and the loss value between the predicted labels to determine the time series anomaly detection model.

[0105] In a possible implementation, the iterative training of the sparse transformation network model based on the loss value between the real label and the predicted label of the sample time series feature to determine the time series anomaly detection model includes:

[0106] i: Detect whether the loss value is greater than a preset threshold.

[0107] Here, it is detected whether the loss value is greater than a preset threshold.

[0108] ii: If yes, the network parameters of the sparse transition network model are updated, and the updated sparse transition network model is continued to be iteratively trained; if no, the iterative training of the sparse transition network model is stopped, and the timing anomaly detection model is determined.

[0109] Here, if yes, the network parameters of the sparse transition network model are updated, and the updated sparse transition network model is continued to be iteratively trained; if no, the iterative training of the sparse transition network model is stopped, and the time series anomaly detection model is determined.

[0110] An embodiment of the present application provides a method for detecting timing anomalies in an integrated circuit. The method comprises: traversing the timing information of each circuit path in a target integrated circuit at a preset window interval using a sliding window; performing feature engineering processing on the timing information of each circuit path to extract the timing features of each circuit path; inputting the timing features of each circuit path into the multi-head self-attention network layer, normalization processing network layer, sparse transition network layer, and fully connected network layer of a timing anomaly detection model to perform timing anomaly detection processing, and outputting abnormal timing information of the integrated circuit; wherein the timing anomaly detection model is obtained by iteratively training a sparse transition network model. When there are a large number of circuit paths in the integrated circuit, when timing anomaly detection is performed on the integrated circuit through other network layers such as the sparse transition network layer in the timing anomaly detection model, the accuracy and efficiency of abnormal timing detection can be improved.

[0111] See also Figure 3 、 Figure 4 , Figure 3 This is a structural diagram of a timing anomaly detection device for an integrated circuit provided in an embodiment of the present application; Figure 4 This is a second structural diagram of a timing anomaly detection device for an integrated circuit provided in an embodiment of the present application. Figure 3As shown in FIG, the timing anomaly detection device 300 for an integrated circuit includes:

[0112] A timing information extraction module 310 is configured to traverse the timing information of each circuit path in the target integrated circuit at a preset window interval using a sliding window;

[0113] A feature processing module 320 is configured to perform feature engineering processing on the timing information of each circuit path to extract the timing features of each circuit path;

[0114] The detection module 330 is used to input the timing features of each circuit path into the multi-head self-attention network layer, normalization processing network layer, sparse transition network layer and fully connected network layer of the timing anomaly detection model for timing anomaly detection processing, and output the abnormal timing information of the integrated circuit; wherein, the timing anomaly detection model is obtained by iteratively training the sparse transition network model.

[0115] Furthermore, the detection module 330 is configured to perform timing anomaly detection processing on the timing characteristics of each circuit path through the following steps:

[0116] Inputting the timing features of the circuit path into the multi-head self-attention network layer for attention mechanism processing and outputting attention features;

[0117] Inputting the attention feature into the normalization processing network layer for processing, and outputting the normalized attention feature;

[0118] Inputting the normalized attention features into multiple feedforward sub-network layers of the sparse transformation network layer for feedforward processing, and outputting target features;

[0119] The target feature is input into the fully connected network layer for linear processing, and whether the target feature is abnormal time series information is output.

[0120] Furthermore, when the detection module 330 inputs the timing features of the circuit path into the multi-head self-attention network layer for attention mechanism processing and outputs the attention features, the detection module 330 is specifically used to:

[0121] Performing an attention mechanism on the timing features of the circuit path to determine a query tensor, a key tensor, and a value tensor corresponding to the timing features;

[0122] Calculating an attention score between the query tensor and the key tensor based on an activation function to determine a probability matrix of the time series feature;

[0123] The time series feature and the probability matrix are multiplied to output the attention feature.

[0124] Furthermore, the detection module 330 performs feedforward processing in the plurality of feedforward sub-network layers for inputting the normalized attention features into the sparse transformation network layer and outputting target features. The detection module 330 is specifically configured to:

[0125] Processing the normalized attention features based on the first linear transformation weight matrix corresponding to each of the feedforward sub-network layers to obtain a plurality of reference features;

[0126] Sparse processing is performed based on the weight values ​​of multiple reference features so that the reference feature with the largest weight value is used as the target feature.

[0127] Furthermore, the detection module 330 determines whether the target feature is abnormal time series information by:

[0128]

[0129] Among them, if the category of Y is 1, the target feature F is abnormal time series information, and if the category of Y is 0, the target feature F is normal time series information. is the second linear transformation matrix.

[0130] Further, such as Figure 4 As shown, the timing anomaly detection device 300 for an integrated circuit includes a model training module 340. The model training module 340 determines the timing anomaly detection model through the following steps:

[0131] Inputting the sample timing features of the sample circuit path into the sparse switching network model to perform timing anomaly detection processing to determine a predicted label of the sample timing features;

[0132] The sparse transformation network model is iteratively trained based on the true label of the sample time series feature and the loss value between the predicted label to determine the time series anomaly detection model.

[0133] Furthermore, when the model training module 340 is used to iteratively train the sparse transformation network model based on the loss value between the real label and the predicted label based on the sample time series feature to determine the time series anomaly detection model, the model training module 340 is specifically used to:

[0134] Detecting whether the loss value is greater than a preset threshold;

[0135] If so, the network parameters of the sparse transformation network model are updated, and the updated sparse transformation network model is continuously iteratively trained;

[0136] If not, the iterative training of the sparse transformation network model is stopped to determine the time series anomaly detection model.

[0137] An embodiment of the present application provides a timing anomaly detection device for an integrated circuit, the timing anomaly detection device comprising: a timing information extraction module for traversing the timing information of each circuit path in a target integrated circuit at a preset window interval using a sliding window; a feature processing module for performing feature engineering processing on the timing information of each circuit path to extract the timing features of each circuit path; a detection module for inputting the timing features of each circuit path into the multi-head self-attention network layer, normalization processing network layer, sparse transition network layer, and fully connected network layer of a timing anomaly detection model to perform timing anomaly detection processing and output abnormal timing information of the integrated circuit; wherein the timing anomaly detection model is obtained by iteratively training the sparse transition network model. When there are a large number of circuit paths in the integrated circuit, the accuracy and efficiency of abnormal timing detection can be improved when the integrated circuit is subjected to timing anomaly detection through other network layers such as the sparse transition network layer in the timing anomaly detection model.

[0138] See also Figure 5 , Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Figure 5 As shown in FIG, the electronic device 500 includes a processor 510, a memory 520 and a bus 530.

[0139] The memory 520 stores machine-readable instructions executable by the processor 510. When the electronic device 500 is running, the processor 510 communicates with the memory 520 via the bus 530. When the machine-readable instructions are executed by the processor 510, the above-mentioned Figure 1 as well as Figure 2 The steps of the method for detecting timing anomalies of an integrated circuit in the method embodiment shown are specifically implemented in accordance with the method embodiment, and will not be described in detail here.

[0140] The embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the computer program can execute the above-mentioned Figure 1 as well as Figure 2 The steps of the method for detecting timing anomalies of an integrated circuit in the method embodiment shown are specifically implemented in accordance with the method embodiment, and will not be described in detail here.

[0141] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0142] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. There may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed may be through some communication interface, indirect coupling or communication connection of devices or units, which may be electrical, mechanical or other forms.

[0143] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0144] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0145] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0146] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The scope of protection of the present application is not limited thereto. Although the present application has been described in detail with reference to the above-mentioned embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-mentioned embodiments within the technical scope disclosed in the present application, or perform equivalent replacements for some of the technical features thereof. These modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A method for detecting timing anomalies of an integrated circuit, characterized in that: The time series anomaly detection method includes: Traversing the timing information of each circuit path in the target integrated circuit at a preset window interval using a sliding window; Performing feature engineering processing on the timing information of each circuit path to extract the timing features of each circuit path; Inputting the timing features of each circuit path into the multi-head self-attention network layer, normalization processing network layer, sparse transition network layer, and fully connected network layer of the timing anomaly detection model for timing anomaly detection processing, and outputting abnormal timing information of the integrated circuit; wherein the timing anomaly detection model is obtained by iteratively training the sparse transition network model; For each of the timing characteristics of the circuit path, timing anomaly detection is performed through the following steps: Inputting the timing features of the circuit path into the multi-head self-attention network layer for attention mechanism processing and outputting attention features; Inputting the attention feature into the normalization processing network layer for processing, and outputting the normalized attention feature; Inputting the normalized attention features into multiple feedforward sub-network layers of the sparse transformation network layer for feedforward processing, and outputting target features; The normalized attention features are input into the multiple feedforward sub-network layers of the sparse transformation network layer for feedforward processing, and the target features are output, including: Processing the normalized attention features based on the first linear transformation weight matrix corresponding to each of the feedforward sub-network layers to obtain a plurality of reference features; The reference features are obtained in the following way: Among them, X is the normalized attention feature, For the i The first linear transformation weight matrix of the FFN, For the i Reference features of FFN; Performing sparse processing based on the weight values ​​of multiple reference features so that the reference feature with the maximum weight value is used as the target feature; Among them, for indivual , only one is taken through the sparse operation, and the sparse function is as follows: Among them, F is the target feature.

2. The time series anomaly detection method according to claim 1, wherein: The timing features of the circuit path are input into the multi-head self-attention network layer for attention mechanism processing, and the attention features are output, including: Performing an attention mechanism on the timing features of the circuit path to determine a query tensor, a key tensor, and a value tensor corresponding to the timing features; Calculating an attention score between the query tensor and the key tensor based on an activation function to determine a probability matrix of the time series feature; The time series feature and the probability matrix are multiplied to output the attention feature.

3. The time series anomaly detection method according to claim 1, wherein: Determine whether the target feature is abnormal time series information by: Among them, if the category of Y is 1, the target feature F is abnormal time series information, and if the category of Y is 0, the target feature F is normal time series information. is the second linear transformation matrix.

4. The time series anomaly detection method according to claim 1, wherein: The time series anomaly detection model is determined by the following steps: Inputting the sample timing features of the sample circuit path into the sparse switching network model to perform timing anomaly detection processing to determine a predicted label of the sample timing features; The sparse transformation network model is iteratively trained based on the true label of the sample time series feature and the loss value between the predicted label to determine the time series anomaly detection model.

5. The time series anomaly detection method according to claim 4, characterized in that: The iterative training of the sparse transformation network model based on the real label of the sample time series feature and the loss value between the predicted label to determine the time series anomaly detection model includes: Detecting whether the loss value is greater than a preset threshold; If so, the network parameters of the sparse transformation network model are updated, and the updated sparse transformation network model is continuously iteratively trained; If not, the iterative training of the sparse transformation network model is stopped to determine the time series anomaly detection model.

6. A timing anomaly detection device for an integrated circuit, characterized in that: The timing anomaly detection device comprises: A timing information extraction module is used to traverse the timing information of each circuit path in the target integrated circuit at a preset window interval using a sliding window; a feature processing module, configured to perform feature engineering processing on the timing information of each circuit path to extract the timing features of each circuit path; a detection module, configured to input the timing features of each circuit path into the multi-head self-attention network layer, the normalization processing network layer, the sparse transition network layer, and the fully connected network layer of the timing anomaly detection model for timing anomaly detection processing, and output abnormal timing information of the integrated circuit; wherein the timing anomaly detection model is obtained by iteratively training the sparse transition network model; The detection module performs timing anomaly detection and processing through the following steps: Inputting the timing features of the circuit path into the multi-head self-attention network layer for attention mechanism processing and outputting attention features; Inputting the attention feature into the normalization processing network layer for processing, and outputting the normalized attention feature; Inputting the normalized attention features into multiple feedforward sub-network layers of the sparse transformation network layer for feedforward processing, and outputting target features; The detection module is used to input the normalized attention features into the multiple feedforward sub-network layers of the sparse transformation network layer for feedforward processing. When outputting the target features, the detection module is specifically used to: Processing the normalized attention features based on the first linear transformation weight matrix corresponding to each of the feedforward sub-network layers to obtain a plurality of reference features; The reference features are obtained in the following way: Among them, X is the normalized attention feature, For the i The first linear transformation weight matrix of the FFN, For the i Reference features of FFN; Performing sparse processing based on the weight values ​​of multiple reference features so that the reference feature with the maximum weight value is used as the target feature; Among them, for indivual , only one is taken through the sparse operation, and the sparse function is as follows: Among them, F is the target feature.

7. An electronic device, characterized in that: include: A processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor and the memory communicate via the bus. When the processor is running, the machine-readable instructions execute the steps of the timing anomaly detection method for an integrated circuit as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the timing anomaly detection method for an integrated circuit according to any one of claims 1 to 5 are executed.

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