Data writing method and device of quasi-two-terminal SOT device

Abstract

The application provides a data writing method and device for a quasi-two-terminal SOT device, the method comprising: performing an erasing operation on a target device, so that all magnetic tunnel junctions of the target device become initial states; and performing multiple selective writing operations on the target device, so that a target magnetic tunnel junction of the target device changes state to realize writing of target data. The device is used to execute the above method. The data writing method and device for the quasi-two-terminal SOT device provided in the embodiments of the application balance the false writing rate of unselected magnetic tunnel junctions while reducing the writing error rate of selected magnetic tunnel junctions, and improve the gating property of the target device through multiple selective writing operations.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, specifically to a data writing method and apparatus for a quasi-two-ended spin-orbit torque (SOT) device. Background Technology

[0002] Spin orbital moment, as a writing scheme for third-generation magnetic random access memory (MRAM), has advantages such as high speed and high durability.

[0003] Integration density is another key issue limiting SOT-MRAM. A three-port structure implies two transistors for control, requiring additional area redundancy. Quasi-two-ended SOT devices are one important solution for optimizing the cell area of ​​SOT-MRAM. Quasi-two-ended SOT devices form quasi-two ends by sharing the SOT channel, significantly reducing the number of transistors. In a quasi-two-ended structure, multi-bit data writing is typically achieved through two steps: an erase operation and a selective write operation. The selective write operation requires reliable writing to selected cells while ensuring that data in unselected cells is not disturbed; that is, the selectivity of the quasi-two-ended SOT device must meet the requirements. However, the selectivity of current quasi-two-ended SOT devices falls far short of the application requirements of memory. Summary of the Invention

[0004] To address the problems in the prior art, embodiments of the present invention provide a data writing method and apparatus for a quasi-two-ended SOT device, which can at least partially solve the problems existing in the prior art.

[0005] In a first aspect, the present invention proposes a data writing method for a quasi-two-ended SOT device, comprising:

[0006] An erasure operation is performed on the target device to restore all magnetic tunnel junctions (MTJs) of the target device to their initial state;

[0007] Multiple selective write operations are performed on the target device to change the state of the target magnetic tunnel junction and realize the writing of target data.

[0008] Furthermore, the parameters for each selective write operation in the multiple selective write operations are the same.

[0009] Furthermore, the write voltages corresponding to the multiple selective write operations are the same.

[0010] Furthermore, the multiple selective write operations are two selective write operations.

[0011] Furthermore, the write voltage corresponding to the second selective write operation is different from the write voltage corresponding to the first selective write operation.

[0012] Furthermore, the data writing method for a quasi-two-ended SOT device provided in this embodiment of the invention further includes:

[0013] After the multiple selective write operations are completed, the stored data corresponding to the target device is read.

[0014] If it is determined that the stored data corresponding to the target device is inconsistent with the target data, then the inconsistent data is acquired;

[0015] Based on the inconsistent data, perform multiple selective write operations on the target device until the stored data corresponding to the target device is consistent with the target data or the number of repeated writes reaches the upper limit.

[0016] On the other hand, the present invention provides a data writing device for a quasi-two-ended SOT device, comprising:

[0017] The erasure module is used to erase the target device, so that all magnetic tunnel junctions of the target device are returned to their initial state;

[0018] The writing module performs multiple selective write operations on the target device to change the state of the target magnetic tunnel junction and write the target data.

[0019] Thirdly, the present invention provides a computer device including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the program to implement the data writing method for a quasi-two-terminal SOT device as described in any of the above embodiments.

[0020] Fourthly, the present invention provides a computer-readable storage medium storing a computer program / instructions that, when executed by a processor, implement the data writing method for a quasi-two-terminal SOT device as described in any of the above embodiments.

[0021] Fifthly, the present invention provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the data writing method for a quasi-two-terminal SOT device as described in any of the above embodiments.

[0022] The data writing method and apparatus for a quasi-two-ended SOT device provided in this invention can perform an erase operation on the target device, causing all magnetic tunnel junctions of the target device to return to their initial state; perform multiple selective write operations on the target device, causing the target magnetic tunnel junctions of the target device to change state and realize the writing of target data. While reducing the write error rate of the selected magnetic tunnel junctions, it balances the false write rate of the unselected magnetic tunnel junctions, and improves the selectivity of the target device through multiple selective write operations. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0024] Figure 1 This is a schematic diagram of the structure of the quasi-two-terminal SOT device provided in the first embodiment of the present invention.

[0025] Figure 2 This is a schematic diagram of the structure of a quasi-two-terminal SOT device provided in the second embodiment of the present invention.

[0026] Figure 3 This is a flowchart illustrating the data writing method for a quasi-two-terminal SOT device provided in the third embodiment of the present invention.

[0027] Figure 4 This is a schematic flowchart of the data writing method for a quasi-two-terminal SOT device provided in the fourth embodiment of the present invention.

[0028] Figure 5 This is a schematic diagram of the data writing device for a quasi-two-terminal SOT device provided in the fifth embodiment of the present invention.

[0029] Figure 6 This is a schematic diagram of the data writing device for a quasi-two-terminal SOT device provided in the sixth embodiment of the present invention.

[0030] Figure 7 This is a schematic diagram of the physical structure of the electronic device provided in the seventh embodiment of the present invention. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments and descriptions of the present invention are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. The acquisition, storage, use, and processing of data in the technical solutions of this application all comply with the relevant provisions of laws and regulations.

[0032] To facilitate understanding of the technical solution provided in this application, the relevant content of the technical solution in this application will be explained below.

[0033] Conventional SOT-MTJ devices have a three-terminal structure; an M-bit SOT-MTJ device requires M write transistors and M read transistors. In this embodiment of the invention, the quasi-two-terminal SOT device reduces the number of write transistors by sharing a write path. For the quasi-two-terminal SOT device, using... Figure 1 and Figure 2 Taking the structure as an example, an M-bit SOT-MTJ device requires 1 write transistor and M read transistors.

[0034] Figure 1 This is a schematic diagram of the quasi-two-ended SOT device provided in the first embodiment of the present invention, as shown below. Figure 1 As shown, the quasi-two-ended SOT device provided in this embodiment of the invention includes a write transistor 101, a plurality of read transistors 102, a spin-orbit coupling layer 103, and a plurality of magnetic tunnel junctions 104 disposed on the spin-orbit coupling layer 103, wherein:

[0035] Write transistor 101 is connected to spin-orbit coupling layer 103 for writing operations; each read transistor 102 is connected to a magnetic tunnel junction 104 for reading operations; each magnetic tunnel junction 104 includes a free layer A1, a barrier layer A2 and a fixed layer A3 arranged sequentially from bottom to top.

[0036] Figure 2 This is a schematic diagram of the structure of the quasi-two-ended SOT device provided in the second embodiment of the present invention, as shown below. Figure 2 As shown, the quasi-two-ended SOT device provided in this embodiment of the invention includes a write transistor 201 and a plurality of parallel memory cells, wherein:

[0037] Each memory cell includes a read transistor 202, a spin-orbit coupling layer 203, and a magnetic tunnel junction 204 disposed on the spin-orbit coupling layer 203; the magnetic tunnel junction 204 includes a free layer A1, a barrier layer A2, and a fixed layer A3 disposed sequentially from bottom to top.

[0038] Write transistor 101 is connected to each spin-orbit coupling layer 203 for writing operations; each read transistor 202 is connected to the corresponding magnetic tunnel junction 204 for reading operations.

[0039] The data writing method for quasi-two-ended SOT devices provided in this embodiment of the invention is applicable not only to the aforementioned 2-bit SOT-MTJ devices, but also to SOT-MTJ devices with more than 2 bits. The data writing method provided in this embodiment of the invention is suitable for other shared write channel structures; an M-bit SOT-MTJ device requires less than M write transistors and M read transistors. As another example, an M-bit SOT-MTJ device requires less than M write transistors and less than M read transistors.

[0040] To improve the selectivity of quasi-two-ended SOT devices, researchers in this field are exploring material systems with optimized voltage-controlled magnetic anisotropy (VCMA) coefficients through materials engineering to enhance selectivity. However, selectivity is insufficient with conventional material systems. Effective integration solutions for unconventional systems have not yet been developed. Furthermore, the decreasing trend of write error rate gradually slows down with increasing write voltage, worsening the threshold values ​​for both the write error rate of selected write cells and the interference rate of unselected write cells.

[0041] This invention utilizes a unique and innovative dedicated write strategy for quasi-two-ended SOT devices to reduce the write efficiency of selected MTJs while balancing the derivative of unselected MTJs, thereby optimizing selectivity by a significant margin. This solution eliminates the need to develop special material systems and new integration schemes, thus addressing the memory application challenges of existing quasi-two-ended SOT devices.

[0042] Figure 3 This is a flowchart illustrating the data writing method for a quasi-two-ended SOT device provided in the third embodiment of the present invention, as shown below. Figure 3 As shown, the data writing method for a quasi-two-ended SOT device provided in this embodiment of the invention includes:

[0043] S301. Perform an erasure operation on the target device to restore all magnetic tunnel junctions of the target device to their initial state;

[0044] Specifically, a state-of-the-art (SOT) current is applied to the magnetic tunnel junctions of the target device, brushing all the magnetic tunnel junctions of the target device to the same initial state. During the erasure operation, no voltage is applied to the top of the magnetic tunnel junctions. The target device can be a multi-bit SOT device, a quasi-two-terminal SOT device with a shared bottom electrode, etc.

[0045] S302. Perform multiple selective write operations on the target device to change the state of the target magnetic tunnel junction of the target device and realize the writing of target data.

[0046] Specifically, in each selective write operation of the target device, the magnetic tunnel junction (MTJ) to be written to, i.e., the target MTJ, is selected. A SOT current of opposite polarity is applied, along with a VCMA voltage to lower the potential barrier, thereby changing the initial state of the selected MTJ to facilitate data writing. For MTJs that do not require data writing, i.e., those maintaining their initial state, a protection operation can be performed by applying a VCMA voltage to increase the potential barrier to prevent changes in the initial state. Since a single write operation is unlikely to meet the selectivity requirements of the target device, multiple selective write operations are employed to ensure that the selected MTJs can be reliably written to, while the states of unselected MTJs remain unchanged, thus improving the selectivity of the target device. The specific number of selective write operations is selected according to actual needs, such as 2, 3, or 4 times, and is not limited in this embodiment of the invention.

[0047] The data writing method for a quasi-two-ended SOT device provided in this embodiment of the invention performs an erase operation on the target device to make all magnetic tunnel junctions of the target device return to their initial state; performs multiple selective write operations on the target device to change the state of the target magnetic tunnel junctions of the target device to realize the writing of target data. While reducing the WER of the selected MTJ, the DER of the unselected MTJ is balanced. The selectivity of the target device is improved through multiple selective write operations.

[0048] Based on the above embodiments, further, the parameters of each selective write operation in the multiple selective write operations are the same, that is, each selective write operation is the same.

[0049] Based on the above embodiments, the write voltage corresponding to the multiple selective write operations is the same, that is, the write voltage applied to the magnetic tunnel junction that needs to be written to in each selective write operation is the same, and the generated SOT currents of opposite polarity are the same.

[0050] Based on the above embodiments, the multiple selective write operations are further defined as two selective write operations: a first selective write operation and a second selective write operation.

[0051] The WER (Write Error Rate) curve reflects the write error rate of the selected magnetic tunnel junction. After two selective write operations, WER2 = WER1 x WER1, where WER2 represents the write error rate of the magnetic tunnel junction after two selective write operations, and WER1 represents the write error rate of the magnetic tunnel junction after one selective write operation. If WER1 = 10... -3 Therefore, theoretically WER2 = (WER1) 2 =10 -6This achieves a doubling of the order of magnitude. The DER (Disturb Error Rate) curve reflects the write error rate of unselected magnetic tunnel junctions; after two selective write operations, DER2 = DER1 + DER1 + (DER1) 2 DER2 represents the write error rate of the magnetic tunnel junction after two selective write operations, and DER1 represents the write error rate of the magnetic tunnel junction after one selective write operation. When DER1 is small, DER2 is approximately twice that of DER1. DER2 does not double in magnitude. Therefore, through two selective write operations, the gating performance will be significantly optimized. The final optimization result of gating performance is subject to actual testing, and the embodiments of this invention are not limited thereto.

[0052] Based on the above embodiments, the write voltage corresponding to the second selective write operation is different from the write voltage corresponding to the first selective write operation.

[0053] The write voltage can include the SOT voltage and the VCMA voltage. The write voltage corresponding to the second selective write operation is different from that corresponding to the first selective write operation. This can be because the SOT voltage included in the write voltage corresponding to the second selective write operation is different from that included in the first selective write operation, the VCMA voltage included in the write voltage corresponding to the second selective write operation is different from that included in the first selective write operation, or both the SOT voltage and the VCMA voltage included in the write voltage corresponding to the second selective write operation are different from those included in the first selective write operation.

[0054] The SOT voltage and VCMA voltage included in each selective write operation may be asynchronous in timing, and the amplitudes of the SOT voltage and VCMA voltage may be different. Other variations of the SOT voltage and VCMA voltage included in the write voltage for selective write operations are not specifically limited in this invention.

[0055] During the second selective write operation, increasing the amplitude of the VCMA voltage can reduce the WER and DER of the second selective write operation, thereby improving the data write success rate. Furthermore, based on the above embodiments, the write voltage corresponding to the second selective write operation is lower than the write voltage corresponding to the first selective write operation. When the selectivity of the target device meets the requirements, reducing the write voltage corresponding to the second selective write operation is beneficial for improving the lifespan of the target device.

[0056] Figure 4 This is a flowchart illustrating the data writing method for a quasi-two-ended SOT device provided in the fourth embodiment of the present invention, as shown below. Figure 4As shown, based on the above embodiments, the data writing method for a quasi-two-terminal SOT device provided in this embodiment of the invention further includes:

[0057] S401. After the multiple selective write operations are completed, read the storage data corresponding to the target device;

[0058] Specifically, after the multiple selective write operations are completed, the stored data corresponding to the target device can be read.

[0059] S402. If it is determined that the stored data corresponding to the target device is inconsistent with the target data, then the inconsistent data is acquired;

[0060] Specifically, the stored data corresponding to the target device is compared with the target data. If the stored data corresponding to the target device is inconsistent with the target data, it indicates that the data is incorrect. That is, there is a situation where the selected magnetic tunnel junction has not been written with data or the initial state of the unselected magnetic tunnel junction has changed. In this case, inconsistent data is obtained, that is, data in the stored data that is different from the target data.

[0061] S403. Based on the inconsistent data, perform multiple selective write operations on the target device until the stored data corresponding to the target device is consistent with the target data or the number of repeated writes reaches the upper limit.

[0062] Specifically, based on the inconsistent data, multiple selective write operations are performed on the target device to ensure that the stored data on the target device matches the target data. If the number of times the selective write operations on the target device are repeated reaches the upper limit, the repeated writing will stop. After the upper limit is reached, any remaining inconsistent data can be recorded and reported.

[0063] By verifying the stored data corresponding to the target device and rewriting inconsistent data, the reliability of data writing to the target device is further improved.

[0064] Based on the above embodiments, the data writing method for a quasi-two-terminal SOT device provided in this embodiment of the invention further includes:

[0065] The number of write operations is received, and the target device is selectively written based on the number of write operations.

[0066] Specifically, the requirements for glossability vary in different application scenarios. The number of write operations for selective write operations can be set according to the needs of the actual application scenario to meet the glossability requirements in different scenarios. Before writing data to the target device, the number of write operations for selective write operations can be set, and selective write operations can be performed on the target device based on the number of write operations.

[0067] For example, if the write count is set to 1, then 1 selective write operation will be performed on the target device. If the write count is set to 2, then 2 selective write operations will be performed on the target device. If the write count is set to 3, then 3 selective write operations will be performed on the target device. And so on.

[0068] Based on the above embodiments, the data writing method for a quasi-two-terminal SOT device provided in this embodiment of the invention further includes:

[0069] The duration of each selective write operation is obtained based on the total write operation time and the number of writes in the selective write operation.

[0070] When the number of write operations in a selective write operation is greater than or equal to 2, there is a delay between adjacent selective write operations. The duration of each selective write operation and the delay between adjacent selective write operations can be set according to actual needs, and this embodiment of the invention does not impose any limitations.

[0071] For example, if the total write operation time is 100ns, when the selective write operation count is set to 1, there is only one write pulse, and the duration of the selective write operation can be 100ns. When the selective write operation count is set to 2, each selective write operation corresponds to one write pulse, resulting in two write pulses, with a delay between the two selective write operations. For example, the first and second write pulses are 40ns each, and the delay between the two selective write operations is 20ns. When the write count is set to 3, there are 3 write pulses. For example, the first, second, and third write pulses are all 20ns each, with a 20ns delay between the first and second write pulses, and a 20ns delay between the second and third write pulses. Alternatively, the first, second, and third write pulses are all 25ns each, with a 15ns delay between the first and second write pulses, and a 10ns delay between the second and third write pulses.

[0072] Figure 5 This is a schematic diagram of the data writing device for a quasi-two-ended SOT device provided in the fifth embodiment of the present invention, as shown below. Figure 5As shown, the data writing device for a quasi-two-ended SOT device provided in this embodiment of the invention includes an erasure module 501 and a writing module 502, wherein:

[0073] The erase module 501 is used to perform an erase operation on the target device, so that all magnetic tunnel junctions of the target device become the initial state; the write module 502 performs multiple selective write operations on the target device, so that the target magnetic tunnel junctions of the target device change state to realize the writing of target data.

[0074] Specifically, the erase module 501 applies a SOT current to the magnetic tunnel junctions of the target device, which brushes all the magnetic tunnel junctions of the target device to the same initial state. During the erase operation, no voltage is applied to the top of the magnetic tunnel junctions. The target device can be a multi-bit SOT device, a quasi-two-terminal SOT device with a shared bottom electrode, etc.

[0075] In each selective write operation of the target device, the write module 502 selects the magnetic tunnel junction (MTJ) to be written to, i.e., the target MTJ, applies a SOT current of opposite polarity, and applies a VCMA voltage to lower the potential barrier, thereby changing the initial state of the selected MTJ to facilitate data writing. For MTJs that do not require data writing, i.e., those that maintain their initial state, a protection operation can be performed by applying a VCMA voltage to increase the potential barrier to prevent changes in the initial state. Since a single write operation is unlikely to meet the selectivity requirements of the target device, multiple selective write operations are used to ensure that the selected MTJs can be reliably written to, while the states of the unselected MTJs remain unchanged, thus improving the selectivity of the target device. The specific number of selective write operations is selected according to actual needs, such as 2, 3, or 4 times, etc., and is not limited in this embodiment of the invention.

[0076] The data writing device for a quasi-two-ended SOT device provided in this embodiment of the invention performs an erase operation on the target device, causing all magnetic tunnel junctions of the target device to return to their initial state; and performs multiple selective write operations on the target device, causing the target magnetic tunnel junctions of the target device to change state to achieve the writing of target data. The selectivity of the target device is improved by performing multiple selective write operations.

[0077] Based on the above embodiments, further, the parameters of each selective write operation in the multiple selective write operations are the same.

[0078] Based on the above embodiments, the write voltages corresponding to the multiple selective write operations are the same.

[0079] Based on the above embodiments, the multiple selective write operations are further defined as two selective write operations.

[0080] Based on the above embodiments, the write voltage corresponding to the second selective write operation is different from the write voltage corresponding to the first selective write operation.

[0081] Based on the above embodiments, the write voltage corresponding to the second selective write operation is lower than the write voltage corresponding to the first selective write operation.

[0082] Figure 6 This is a schematic diagram of the data writing device for a quasi-two-ended SOT device provided in the sixth embodiment of the present invention, as shown below. Figure 6 As shown, based on the above embodiments, the data writing device for a quasi-two-ended SOT device provided in this embodiment of the invention further includes a reading module 503, an acquisition module 504, and a rewriting module 505, wherein:

[0083] The read module 503 is used to read the storage data corresponding to the target device after the multiple selective write operations are completed; the get module 504 is used to get the inconsistent data if it is determined that the storage data corresponding to the target device is inconsistent with the target data; the rewrite module 505 is used to perform multiple selective write operations on the target device based on the inconsistent data until the storage data corresponding to the target device is consistent with the target data or the number of repeated writes reaches the upper limit.

[0084] The embodiments of the device provided in this invention can be used to execute the processing flow of the above-described method embodiments. Its functions will not be repeated here, but can be referred to the detailed description of the above-described method embodiments.

[0085] The data writing method for the quasi-two-ended SOT device provided in this embodiment of the invention has no limitation on the type of magnetic tunnel junction, such as perpendicular magnetic anisotropic devices, in-plane anisotropic devices, etc.

[0086] The selection of reading circuits for quasi-two-terminal SOT devices can cover solutions such as resistance comparators, current comparators, and voltage comparators; it can also include multiple input selectors.

[0087] In the write circuit of the storage function of a quasi-two-terminal SOT device, multiple sets of write square wave pulses with different amplitudes can be used, such as triangular waves, periodic pulses, irregular pulses, stepped pulses, etc.

[0088] Quasi-two-ended SOT devices may include additional circuit modules, such as ECC correction modules.

[0089] The bottom electrode of the quasi-two-ended SOT device can be a strip type, a cross type, or a Y-branch type, and can be a 6P or 8P electrode type. This invention does not make any specific limitations.

[0090] Quasi-two-ended SOT devices allow for different bottom electrode widths at different MTJ locations; allow different MTJs to have different sizes; allow different MTJs to have different spacing; and allow multiple MTJs to be placed on the same heavy metal.

[0091] Quasi-two-ended SOT devices allow for actual connections to be formed through bottom / top vias of the SOT channel.

[0092] Depending on the material of the underlying spin-orbit coupling layer, the sign of the spin Hall angle varies, resulting in different polarization directions of the generated spin current. Metals with negative spin Hall angles, such as W, are preferred; for metals like Pt, the spin Hall angle is positive. Different signs of the spin Hall angle mean opposite directions of the applied current.

[0093] In alternative implementations, the external magnetic field in the quasi-two-terminal SOT device can be achieved in several ways. Specifically, the external magnetic field can be formed by at least one of the following methods:

[0094] The quasi-two-terminal SOT device includes a magnetic field generating device that provides the applied magnetic field or is equivalent to the applied magnetic field;

[0095] The magnetic tunnel junction may include a fixed layer A3, a barrier layer A2, and a free layer A1 arranged sequentially from top to bottom. At least one of the fixed layer A3, the barrier layer A2, and the free layer A1 has a trapezoidal cross-section to provide the applied magnetic field.

[0096] The spin-orbit coupling layer is made of an antiferromagnetic material, and the spin-orbit coupling layer and the free layer A1 form an exchange bias field to provide the external magnetic field;

[0097] The magnetic tunnel junction includes a magnetic material layer (e.g., a Co layer) for providing the applied magnetic field;

[0098] The magnetic tunnel junction has a shape capable of forming an anisotropic field (non-uniform demagnetizing field) to provide the applied magnetic field. In some embodiments, the magnetic tunnel junction can take the shape of a rectangle, ellipse, or isosceles right angle. Taking an ellipse as an example, the demagnetizing field along the major axis is weaker than that along the minor axis, and this demagnetizing field can be equivalent to the applied magnetic field.

[0099] The free layer A1 possesses a gradient of perpendicular magnetic anisotropy, which serves to provide an equivalent magnetic field for the applied magnetic field. Specifically, during the fabrication of the magnetic tunnel junction, the concentration of the target material can be adjusted to give the free layer A1 a gradient of perpendicular magnetic anisotropy, further disrupting the symmetry of the magnetic moment distribution, thus enabling it to provide an equivalent applied magnetic field. In this case, the free layer A1 can still be affected by interfacial interactions such as the DMI effect and other applied magnetic fields.

[0100] It should be noted that magnetic field generating devices or equivalent devices capable of forming an external magnetic field are conventional techniques in this field, and those skilled in the art can flexibly configure them according to their needs, which will not be elaborated here. In addition, external magnetic fields can also be provided by making at least one of the fixed layer A3, barrier layer A2, and free layer A1 trapezoidal in cross-section, using an antiferromagnetic material to form an exchange bias field with the free layer A1, and providing a magnetic material layer. In practical applications, external magnetic fields can also be formed through other feasible methods, which are not limited by this invention.

[0101] In an optional implementation, the quasi-two-ended SOT device includes readout circuitry and peripheral conversion circuitry (encoder, MUX, decoder, etc.).

[0102] In an alternative implementation, the magnetic tunnel junction may include multiple free layers, barrier layers, insertion layers, etc.

[0103] In optional embodiments, the available shapes of the magnetic tunnel junction include, but are not limited to, ellipses, isosceles triangles, rectangles, rhombuses, etc. Besides ellipses, rectangles, triangles, etc., also have the same effect. Inclined semicircles, isosceles triangles, etc., which do not possess x / y-axis symmetry after tilting, are also within the scope of protection. Here, various symmetrical structures based on these shapes are within the scope of this patent protection.

[0104] The SOT channel can be located above the MTJ, meaning the sequence from top to bottom is: SOT channel, free layer, barrier layer, reference layer, and pinned layer. It can be configured with two MTJs located above and below the SOT channel.

[0105] For perpendicular magnetic anisotropic devices, or when the direction of the SOT current is parallel to the long axis of the in-plane magnetic anisotropic device, additional factors are required to cooperate with the SOT current, including but not limited to: ① an external magnetic field in the same direction as the SOT; ② the ferromagnetic layer or barrier layer of the magnetic tunnel junction is made into a trapezoidal structure; ③ when fabricating the magnetic tunnel junction, the concentration of the target material can be adjusted to make the free layer have a gradient of perpendicular magnetic anisotropy, further disrupting the symmetry of the magnetic moment distribution; ④ the equivalent effect of the external magnetic field can be achieved by using magnetic materials such as the built-in Co layer; ④ the strong spin coupling layer can use antiferromagnetic materials to form an exchange bias field, replacing the use of the external magnetic field, etc.

[0106] In a preferred embodiment, the magnetic tunnel junction includes a fixed layer A3, a barrier layer A2, and a free layer A1 arranged sequentially from top to bottom. The bottom surface of the free layer A1 is fixedly connected to the spin-orbit coupling layer. It is understood that the resistance of the magnetic tunnel junction depends on the magnetization directions of the fixed layer A3 and the free layer A1, which are determined by the magnetic moment directions. Specifically, when the magnetic moment directions of the fixed layer A3 and the free layer A1 are the same, the magnetic tunnel junction is in a low-resistance state; when the magnetic moment directions of the fixed layer A3 and the free layer A1 are opposite, the magnetic tunnel junction is in a high-resistance state. The high-resistance and low-resistance states of the magnetic tunnel junction can be pre-assigned to different data. For example, the high-resistance state can be pre-set to correspond to the data "1", and the low-resistance state to correspond to the data "0". Then, by inputting current or voltage to the magnetic tunnel junction through the reading circuit, the resistance state of the magnetic tunnel junction can be determined as either a high-resistance state or a low-resistance state based on the change in current or voltage. Based on the resistance state of the magnetic tunnel junction, the data stored in the magnetic tunnel junction can be determined as either "1" or "0". Determining the range of the high-resistance and low-resistance states is a common technique in the art, and those skilled in the art can determine the resistance range of the high-resistance and low-resistance states of the magnetic tunnel junction based on common knowledge. This invention will not elaborate further on this point.

[0107] The magnetic tunnel junction may also include at least one of the following layered structures: an insertion layer, a pinning layer, a seed layer, and a capping layer. The arrangement of each layer may be one or more layers depending on actual needs, and those skilled in the art can determine the top-to-bottom arrangement order of the layers in the magnetic tunnel junction according to requirements; this invention does not limit this.

[0108] Optionally, the shape of the magnetic tunnel junction on the spin-orbit coupling layer can be any of the following shapes: cube, cylinder, cubic, or elliptical cylinder. The bottom surface shape of at least one magnetic tunnel junction disposed on the spin-orbit coupling layer, i.e., the lower surface of the free layer A1, is coupled to the spin-orbit coupling layer.

[0109] Preferably, the spin-orbit coupling layer can be rectangular, such that the top surface area of ​​the spin-orbit coupling layer is larger than the area occupied by at least one magnetic tunnel junction disposed on the spin-orbit coupling layer, and at least one magnetic tunnel junction can be disposed on the spin-orbit coupling layer, with the outer edge of the at least one magnetic tunnel junction located inside the outer edge of the spin-orbit coupling layer. Preferably, the spin-orbit coupling layer can be a heavy metal strip film or an antiferromagnetic strip film.

[0110] It should be noted that there can be one or more magnetic tunnel junctions on the spin-orbit coupling layer. Preferably, multiple magnetic tunnel junctions can be placed on the same spin-orbit coupling layer, which can realize a one-time data writing operation on multiple magnetic tunnel junctions, reduce the number of control transistors that input the first current or the second current, thereby improving integration and reducing circuit power consumption.

[0111] In a preferred embodiment, when the magnetic random access memory (RAM) cell inputs current to the spin-orbit coupling layer and the magnetic tunnel junction, it can be done by setting electrodes on the spin-orbit coupling layer and the magnetic tunnel junction. For example, a top electrode can be set on the top of the magnetic tunnel junction, and input and output electrodes can be set on opposite sides of the spin-orbit coupling layer, respectively. Preferably, the electrode material can be any one of tantalum (Ta), aluminum (Al), gold (Au), or copper (Cu).

[0112] Preferably, the materials of the free layer A1 and the fixed layer A3 can be ferromagnetic metals, and the material of the barrier layer A2 can be an oxide. The magnetic tunnel junction exhibits perpendicular magnetic anisotropy, meaning that the magnetization directions of the free layer A1 and the fixed layer A3 forming the magnetic tunnel junction are perpendicular to the magnetic field. The ferromagnetic metal can be a mixed metal material formed from at least one of cobalt-iron (CoFe), cobalt-iron-boron (CoFeB), or nickel-iron (NiFe), and the proportions of the mixed metal materials can be the same or different. The oxide can be one of magnesium oxide (MgO) or aluminum oxide (Al2O3), used to generate the tunneling magnetoresistance effect. In practical applications, other feasible materials can also be used for the ferromagnetic metal and oxide, and this invention does not limit this.

[0113] The free layer A1 of the magnetic tunnel junction is fixed in contact with the spin-orbit coupling layer. The layers of the magnetic tunnel junction and the spin-orbit coupling layer can be deposited on the substrate in a bottom-up order by traditional methods such as ion beam epitaxy, atomic layer deposition or magnetron sputtering. Then, multiple magnetic tunnel junctions can be formed by traditional nano-device processing technology such as photolithography and etching.

[0114] In a preferred embodiment, the spin-orbit coupling layer is a spin-orbit coupling layer made of a heavy metal thin film, an antiferromagnetic thin film, or other materials. The heavy metal thin film or antiferromagnetic thin film can be made into a rectangle, and its top area is preferably larger than the bottom area of ​​the contour formed by all magnetic tunnel junctions, so as to be able to set one or more magnetic tunnel junctions, the bottom shape of which is completely embedded within the top shape of the heavy metal thin film or antiferromagnetic thin film. Preferably, the material of the spin-orbit coupling layer can be one of platinum (Pt), tantalum (Ta), or tungsten (W). In practical applications, the spin-orbit coupling layer can also be formed using other feasible materials, and the present invention is not limited thereto.

[0115] In this embodiment, the magnetic tunnel junction includes a top fixed layer A3, a free layer A1 in contact with the spin-orbit coupling layer, and a barrier layer A2 disposed between the fixed layer A3 and the free layer A1. The magnetic tunnel junction is a three-layer structure, including only one free layer A1. In other embodiments, there may be multiple free layers A1, i.e., two or more free layers A1. The magnetic tunnel junction then includes a top fixed layer A3, multiple free layers A1, and a barrier layer A2 disposed between each pair of adjacent layers, with the bottom free layer A1 in contact with the spin-orbit coupling layer. For example, in a specific example, when two free layers A1 are included, the magnetic storage cell structure may include a spin-orbit coupling layer, a first free layer A1, a barrier layer A2, a second free layer A1, a barrier layer A2, and a fixed layer A3 sequentially disposed on the spin-orbit coupling layer.

[0116] The apparatus, module, or unit described in the above embodiments may be implemented by a computer chip or entity, or by a product having a certain function. A typical implementation device is an electronic device, specifically, such as a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0117] In a typical example, the electronic device specifically includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the data writing method for the quasi-two-terminal SOT device described above.

[0118] The following is for reference. Figure 7 It shows a schematic diagram of the physical structure of an electronic device 600 suitable for implementing embodiments of the present application.

[0119] like Figure 7 As shown, the electronic device 600 includes a central processing unit (CPU) 601, which can perform various appropriate tasks and processes according to a program stored in a read-only memory (ROM) 602 or a program loaded from a storage section 608 into a random access memory (RAM) 603. The RAM 603 also stores various programs and data required for the operation of the electronic device 600. The CPU 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0120] The following components are connected to I / O interface 605: an input section 606 including a keyboard, mouse, etc.; an output section 607 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 608 including a hard disk, etc.; and a communication section 609 including a network interface card such as a LAN card, modem, etc. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to I / O interface 605 as needed. A removable medium 611, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on drive 610 as needed so that computer programs read from it can be installed in storage section 608 as needed.

[0121] In particular, according to embodiments of the present invention, the processes described above with reference to the flowchart can be implemented as computer software programs. For example, embodiments of the present invention provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the data writing method for the quasi-two-ended SOT device described above.

[0122] For example, an embodiment of the present invention provides a computer program product, the computer program product including a computer program stored on a non-transitory computer-readable storage medium, the computer program including program instructions, and when the program instructions are executed by a computer, the computer is able to perform the steps of the above-described data writing method for quasi-two-terminal SOT devices.

[0123] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 609, and / or installed from the removable medium 611.

[0124] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0125] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0126] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0127] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0128] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0129] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0130] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0131] This application can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0132] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0133] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A data write method of a quasi-two-terminal SOT device, characterized by, The quasi-two-terminal SOT devices share a write channel, including: An erasure operation is performed on the target device to restore all magnetic tunnel junctions of the target device to their initial state; Multiple selective write operations are performed on the target device to change the state of the target magnetic tunnel junction and realize the writing of target data. The selectivity of the target device is improved by utilizing the exponential decrease in the write error rate of the selected magnetic tunnel junction and the linear increase in the write error rate of the unselected magnetic tunnel junction. The magnetic tunnel junction for writing the target data is the selected magnetic tunnel junction. There is a delay time between adjacent selective write operations, which is on the order of nanoseconds.

2. The method according to claim 1, characterized in that, The parameters are the same for each of the multiple selective write operations.

3. The method according to claim 1, characterized in that, The write voltages corresponding to the multiple selective write operations are the same.

4. The method according to claim 1, characterized in that, The multiple selective write operations are two selective write operations.

5. The method according to claim 4, characterized in that, The write voltage for the second selective write operation is different from the write voltage for the first selective write operation.

6. The method according to any one of claims 1 to 5, characterized in that, Also includes: After the multiple selective write operations are completed, the stored data corresponding to the target device is read. If it is determined that the stored data corresponding to the target device is inconsistent with the target data, then the inconsistent data is acquired; Based on the inconsistent data, perform multiple selective write operations on the target device until the stored data corresponding to the target device is consistent with the target data or the number of repeated writes reaches the upper limit.

7. A data writing device for a quasi-two-ended SOT device, characterized in that, The quasi-two-terminal SOT devices share a write channel, including: The erasure module is used to erase the target device, so that all magnetic tunnel junctions of the target device are returned to their initial state; The write module performs multiple selective write operations on the target device to change the state of the target magnetic tunnel junction and realize the writing of target data. This improves the selectivity of the target device by utilizing the exponential decrease in the write error rate of the selected magnetic tunnel junction and the linear increase in the write error rate of the unselected magnetic tunnel junction. The magnetic tunnel junction used to write the target data is the selected magnetic tunnel junction. There is a delay time between adjacent selective write operations, which is on the order of nanoseconds.

8. A computer device, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program / instructions that, when executed by a processor, implement the steps of the method according to any one of claims 1 to 6.

10. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the method according to any one of claims 1 to 6.

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