Package heat dissipation structure for large-size and high-power artificial intelligence chips

Abstract

The present invention discloses a packaging and heat dissipation structure for large-size and high-power artificial intelligence chips, belonging to the technical field of chip heat dissipation. The packaging and heat dissipation structure of the chip includes: a substrate; a multi-chip structure completed with wafer-level packaging, located on one side of the substrate. The multi-chip structure completed with wafer-level packaging includes a plurality of chips and a cofferdam. The chip includes a functional surface and a back surface arranged opposite to each other. The cofferdam is arranged around the periphery of the chip, and the surface of the cofferdam close to the back surface of the chip is flush with the back surface of the chip; a metal heat dissipation cover, covering one side of the substrate and enclosing a receiving cavity with the substrate for receiving the multi-chip structure completed with wafer-level packaging. The metal heat dissipation cover is fixedly connected to the outermost cofferdam through an adhesive; a plurality of chips, the cofferdams between adjacent chips, the metal heat dissipation cover and the adhesive jointly enclose a liquid metal heat dissipation channel. The liquid metal heat dissipation channel is filled with liquid metal and the end is closed. The packaging and heat dissipation structure provided by the present invention has a high heat dissipation capacity.

Description

Technical Field

[0001] The present invention relates to the technical field of chip heat dissipation, and more specifically, to a packaging heat dissipation structure for large-size and high-power artificial intelligence chips. Background Art

[0002] With the rapid development of semiconductor integrated circuit technology, electronic devices are developing towards miniaturization and high power density. The power density of chips continues to increase, resulting in a sharp increase in heat per unit area. The overall structure needs to dissipate heat in a timely manner, otherwise it will cause the chips to fail in a high-temperature environment, and may even cause damage to individual devices, ultimately affecting the performance of the overall system and even causing system failure.

[0003] Chinese Patent Application No. CN118398574A discloses a chip packaging structure with double-sided heat dissipation, which transfers the heat of the chip to the ambient space through the substrate via a thermal conductive adhesive layer. However, with the rapid development of artificial intelligence, the demand for high-computing-power chips is gradually increasing, and the requirement for the heat dissipation ability of chips is also increasing accordingly. The traditional thermal conductive adhesive layer far cannot meet this demand, so there are deficiencies in the existing technology. Summary of the Invention

[0004] Aiming at the deficiencies of the existing technology, the purpose of the present invention is to provide a packaging heat dissipation structure for large-size and high-power artificial intelligence chips, which has high heat dissipation ability.

[0005] To achieve the above purpose, the present invention provides the following technical solutions:

[0006] The present invention provides a packaging heat dissipation structure for large-size and high-power artificial intelligence chips, and the packaging heat dissipation structure of the chip includes:

[0007] A substrate;

[0008] A completed wafer-level packaged multi-chip structure, located on one side of the substrate. The completed wafer-level packaged multi-chip structure includes a plurality of chips and a cofferdam. The chip includes a functional surface and a back surface arranged oppositely. The cofferdam is arranged around the periphery of the chip, and the surface of the cofferdam close to the back surface of the chip is flush with the back surface of the chip;

[0009] A metal heat dissipation cover, covering one side of the substrate and enclosing an accommodation cavity with the substrate for accommodating the completed wafer-level packaged multi-chip structure. The metal heat dissipation cover is fixedly connected to the outermost cofferdam through an adhesive;

[0010] The several chips, the dams between adjacent chips, the metal heat dissipation cover and the adhesive jointly enclose a liquid metal heat dissipation channel. Both ends of the liquid metal heat dissipation channel extend away from the chips and penetrate through the metal heat dissipation cover. The liquid metal heat dissipation channel is filled with liquid metal and its ends are closed.

[0011] As a further improvement of the present invention, the liquid metal heat dissipation channel includes a first channel in direct contact with the back surface of the chip and a second channel extending in a direction perpendicular to the surface of the chip and penetrating through the metal heat dissipation cover.

[0012] As a further improvement of the present invention, the thickness of the first channel in the direction perpendicular to the surface of the chip is the same as the thickness of the adhesive.

[0013] As a further improvement of the present invention, the thickness of the first channel in the direction perpendicular to the surface of the chip is 0.1 mm - 1 mm, the thickness of the second channel in the direction parallel to the surface of the chip is 0.5 mm - 1.5 mm, and the length of the second channel in the direction perpendicular to the surface of the chip is 2 mm - 9 mm.

[0014] As a further improvement of the present invention, the orthographic projection of the liquid metal heat dissipation channel on the chip covers the chip and the dams between adjacent chips.

[0015] As a further improvement of the present invention, the material of the dam is a plastic encapsulation material.

[0016] As a further improvement of the present invention, the interior of the metal heat dissipation cover further has a liquid cooling channel, which is arranged close to the back surface of the chip and is located within the space enclosed by the liquid metal heat dissipation channel.

[0017] As a further improvement of the present invention, the completed wafer-level packaged multi-chip structure further includes a redistribution layer, which is fixed on one side of the functional surface of the chip;

[0018] The completed wafer-level packaged multi-chip structure further includes micro-bumps, which are located between the chip and the redistribution layer;

[0019] The completed wafer-level packaged multi-chip structure further includes an interposer, which is fixed on the side of the redistribution layer away from the chip and the dam. The interposer has a vertical interconnection structure;

[0020] The completed wafer-level packaged multi-chip structure further includes a solder joint. One end of the solder joint is fixed on the side of the interposer away from the chip and the dam, and the solder joint is electrically connected to the redistribution layer through the vertical interconnection structure of the interposer. The other end of the solder joint is fixed on one side of the substrate;

[0021] The welding part is a nickel-palladium-gold pad, a nickel-gold pad, a titanium-copper pad or a BGA solder ball;

[0022] The periphery of the welding part is filled with underfill.

[0023] As a further improvement of the present invention, the substrate is a printed circuit board, a glass substrate, a silicon substrate or a ceramic substrate.

[0024] The present invention provides a manufacturing method for a packaging and heat dissipation structure of a large-size high-power artificial intelligence chip, which is applied to the manufacturing of the above-mentioned packaging and heat dissipation structure of a large-size high-power artificial intelligence chip, and includes the following steps:

[0025] Provide a completed wafer-level packaged multi-chip structure, the completed wafer-level packaged multi-chip structure includes a plurality of chips and a cofferdam, the chips include a functional surface and a back surface arranged opposite to each other, the cofferdam is arranged around the periphery of the chips, and the surface of the cofferdam close to the back surface of the chips is flush with the back surface of the chips;

[0026] Flip the completed wafer-level packaged multi-chip structure onto one side of the substrate;

[0027] Cover a metal heat sink on one side of the substrate, and enclose a receiving cavity for receiving the completed wafer-level packaged multi-chip structure with the substrate. The metal heat sink is fixedly connected to the outermost cofferdam through an adhesive to obtain the packaged heat dissipation structure of the chip. Among them, the plurality of chips, the cofferdams between adjacent chips, the metal heat sink and the adhesive jointly enclose a liquid metal heat dissipation channel. The two ends of the liquid metal heat dissipation channel extend away from the chips and penetrate through the metal heat sink. The liquid metal heat dissipation channel is filled with liquid metal and the ends are closed.

[0028] The manufacturing method of the chip packaging and heat dissipation structure of the technical solution of the present invention has a simple process. In the obtained chip packaging and heat dissipation structure, the liquid metal is in direct contact with the back surface of the chip and has strong heat conduction performance for the heat generated during the operation of the chip. The two ends of the liquid metal heat dissipation channel extend away from the chip and penetrate through the metal heat sink, which is beneficial to increasing the heat dissipation area. The ends of the liquid metal heat dissipation channel are closed, which can prevent the liquid metal from flowing and affecting the heat dissipation effect. The above can improve the heat dissipation ability, especially suitable for the packaging and heat dissipation of large-size high-power artificial intelligence chips. Description of the Drawings

[0029] Figure 1 It is a schematic diagram of the chip packaging and heat dissipation structure according to an embodiment of the present invention;

[0030] Figure 2 is Figure 1Partial enlarged schematic diagram at the dashed box;

[0031] Figure 3 Flowchart of the manufacturing method of the chip package heat dissipation structure according to an embodiment of the present invention;

[0032] Figure 4 Schematic diagram of a wafer after the chip and the interposer are assembled in the manufacturing method of the chip package heat dissipation structure according to an embodiment of the present invention;

[0033] Figure 5 Schematic diagram after the wafer is diced in the manufacturing method of the chip package heat dissipation structure according to an embodiment of the present invention;

[0034] Figure 6 Schematic diagram after the substrate is flip-chip welded and the underfill is filled in the manufacturing method of the chip package heat dissipation structure according to an embodiment of the present invention.

[0035] Reference numerals: 100, chip package heat dissipation structure; 110, substrate; 120, completed wafer-level packaged multi-chip structure; 121, chip; 1211, functional surface; 1212, back surface; 122, dam; 123, redistribution layer; 124, micro-bump; 125, interposer; 1251, vertical interconnection structure; 1252, vertical end; 1253, horizontal end; 126, welding part; 127, underfill; 130, metal heat sink cover; 131, liquid metal heat dissipation channel; 132, liquid metal; 133, first channel; 134, second channel; 135, liquid cooling channel; 136, input / output valve; 140, adhesive. Detailed Description of the Invention

[0036] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. The same components are denoted by the same reference numerals. It should be noted that the terms "front", "rear", "left", "right", "upper" and "lower" used in the following description refer to the directions in the drawings, and the terms "bottom surface" and "top surface", "inner" and "outer" refer to the directions towards or away from the geometric center of a specific component, respectively.

[0037] The term " / and" in the following text merely describes the association relationship of associated objects, indicating that there can be three relationships. For example, A / and B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " generally represents an "or" relationship between the associated objects before and after.

[0038] As Figure 1 and Figure 2 shown, the chip package heat dissipation structure 100 according to an embodiment of the present invention includes a substrate 110, a completed wafer-level packaged multi-chip structure 120, and a metal heat sink cover 130.

[0039] In this embodiment, the completed wafer-level packaged multi-chip structure 120 is located on one side of the substrate 110. The completed wafer-level packaged multi-chip structure 120 includes a plurality of chips 121 and a cofferdam 122. The chip 121 includes a functional surface 1211 and a back surface 1212 that are oppositely arranged. The cofferdam 122 is arranged around the periphery of the chip 121. The surface of the cofferdam 122 on the side close to the back surface 1212 of the chip 121 is flush with the back surface 1212 of the chip 121. Among them, the functional surface 1211 of the chip 121 has a functional area and pads. Among them, "a plurality" refers to an indefinite quantity, which can be one, two, or more than two. When the number of chips 121 is two or more, a cofferdam 122 is arranged around the periphery of each chip 121. Among them, the cofferdam 122 is located in the fan-out area of the wafer-level assembly process from the chip 121 to the interposer 125, and usually exists at the edges and between the chips of the multi-chip to interposer 125 package.

[0040] In this embodiment, the metal heat sink cover 130 is covered on one side of the substrate 110 and encloses a receiving cavity with the substrate 110 for receiving the completed wafer-level packaged multi-chip structure 120. The metal heat sink cover 130 and the outermost cofferdam 122 are fixedly connected by an adhesive 140. Among them, the metal heat sink cover 130 and one side of the substrate 110 can be connected in any way, such as by gluing.

[0041] In this embodiment, a plurality of chips 121, the cofferdams 122 between adjacent chips 121, the metal heat sink cover 130 and the adhesive 140 together enclose a liquid metal heat dissipation channel 131. Both ends of the liquid metal heat dissipation channel 131 extend away from the chip 121 and penetrate through the metal heat sink cover 130. The liquid metal heat dissipation channel 131 is filled with liquid metal 132 and the ends are closed. Among them, the liquid metal 132 is used to dissipate heat from the chip 121. In the chip package heat dissipation structure 100 of the present invention, the metal heat sink cover 130 can dissipate heat from a plurality of chips 121 simultaneously.

[0042] Among them, the liquid metal 132 is a low-melting-point alloy that is liquid at room temperature, or presents a solid sheet shape and becomes liquid when heated to the melting point. The components are, for example, gallium-based composite metal materials or other composite metal materials, such as gallium-indium-tin alloy, indium-bismuth-tin alloy or indium-bismuth-zinc alloy, etc. Its properties are stable and it has excellent thermal conductivity (the heat transfer coefficient can reach 20 W / m•K to 75 W / m•K). The liquid metal 132 can be filled into the above-mentioned liquid metal heat dissipation channel 131 by extrusion. When the chip 121 is working, the liquid metal 132 is in a liquid state, which is beneficial to achieving a better heat conduction effect.

[0043] In this embodiment, the liquid metal 132 is located inside the metal heat sink cover 130, and the injection port of the liquid metal 132 is finally closed, which can prevent the liquid metal 132 from overflowing, and can maintain the effective filling of the liquid metal 132 under long-term operation, realizing the long-term reliability of the overall packaging structure.

[0044] The overall structure of the chip packaging heat dissipation structure 100 of this embodiment is relatively simple. The liquid metal 132 is in direct contact with the back surface 1212 of the chip 121 and has strong heat conduction performance for the heat generated when the chip 121 works. Both ends of the liquid metal heat dissipation channel 131 extend away from the chip 121 and penetrate through the metal heat sink cover 130, which is beneficial to increasing the heat dissipation area. The end of the liquid metal heat dissipation channel 131 is closed, which can prevent the liquid metal 132 from flowing and affecting the heat dissipation effect. The above overall can improve the heat dissipation ability, and is particularly suitable for the packaging heat dissipation of large-size high-power artificial intelligence chips.

[0045] On the basis of the foregoing embodiment, the liquid metal heat dissipation channel 131 includes a first channel 133 in direct contact with the back surface 1212 of the chip 121 and a second channel 134 extending in a direction perpendicular to the surface of the chip 121 and penetrating through the metal heat sink cover 130. The heat generated when the chip 121 works is conducted into the liquid metal 132 in the horizontal first channel 133, and then the heat is conducted into the liquid metal 132 in the vertical second channel 134.

[0046] On the basis of the foregoing embodiment, the thickness of the first channel 133 in the direction perpendicular to the surface of the chip 121 is the same as the thickness of the adhesive 140, as Figure 1 shown.

[0047] On the basis of the foregoing embodiment, the thickness of the first channel 133 in the direction perpendicular to the surface of the chip 121 is 0.1 mm - 1 mm, the thickness of the second channel 134 in the direction parallel to the surface of the chip 121 is 0.5 mm - 1.5 mm, and the length of the second channel 134 in the direction perpendicular to the surface of the chip 121 is 2 mm - 9 mm. Further, the thickness of the first channel 133 in the direction perpendicular to the surface of the chip 121 can be, but is not limited to, 0.1 mm, 0.2 mm, 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm or 1 mm; the thickness of the second channel 134 in the direction parallel to the surface of the chip 121 can be, but is not limited to, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1 mm, 1.1 mm, 1.2 mm, 1.3 mm, 1.4 mm or 1.5 mm; the length of the second channel 134 in the direction perpendicular to the surface of the chip 121 can be, but is not limited to, 2 mm, 3 mm, 4 mm, 5 mm, 6 mm, 7 mm, 7.7 mm, 8 mm or 9 mm, and 7.7 mm is preferred.

[0048] On the basis of the foregoing embodiments, the orthographic projection of the liquid metal heat dissipation channel 131 on the chip 121 covers the chip 121 and the cofferdam 122 between adjacent chips 121. In this way, the back surface 1212 of the chip 121 is provided with liquid metal 132, which can sufficiently dissipate heat from the chip 121.

[0049] On the basis of the foregoing embodiments, the material of the cofferdam 122 is a plastic encapsulation material. For example, the cofferdam 122 can be an epoxy molding compound (EMC), specifically, the plastic encapsulation material used for epoxy wafer-level packaging.

[0050] On the basis of the foregoing embodiments, the interior of the metal heat dissipation cover 130 further has a liquid cooling channel 135, which is arranged close to the back surface 1212 of the chip 121 and is located within the space surrounded by the liquid metal heat dissipation channel 131. During use, the input-output valve 136 can be used to Figure 1 fill or discharge the coolant into or from the liquid cooling channel 135 along the direction of the arrow in the figure, so as to perform heat exchange with the liquid metal 132 in the liquid metal heat dissipation channel 131, thereby taking away the heat generated by the chip 121 and improving the heat dissipation performance. Among them, the coolant can be water or a high molecular organic liquid.

[0051] On the basis of the foregoing embodiments, the completed wafer-level packaged multi-chip structure 120 further includes a redistribution layer 123 (RDL), which is fixed to one side of the functional surface 1211 of the chip 121. Specifically, the redistribution layer 123 is fixed to the pads on the functional surface 1211 of the chip 121. The redistribution layer 123 is a metal layer added to the chip 121 to reallocate electrical connections.

[0052] On the basis of the foregoing embodiments, the completed wafer-level packaged multi-chip structure 120 further includes micro-bumps 124, which are located between the chip 121 and the redistribution layer 123. It should be noted that the micro-bumps 124 may not be provided in other embodiments.

[0053] On the basis of the foregoing embodiments, the completed wafer-level packaged multi-chip structure 120 further includes an interposer 125, which is fixed to the side of the redistribution layer 123 away from the chip 121 and the cofferdam 122. The interposer 125 has a vertical interconnection structure 1251. Among them, the vertical interconnection structure 1251 of the interposer 125 includes an interconnected vertical end 1252 and a horizontal end 1253. The vertical end 1252 penetrates through the interior of the body of the interposer 125 and is connected to the redistribution layer 123, and the horizontal end 1253 is located on the side of the body of the interposer 125 away from the redistribution layer 123.

[0054] Specifically, the adapter plate 125 is provided with a through hole for one end of the vertical interconnection structure 1251 to pass through, specifically for the vertical end 1252 of the vertical interconnection structure 1251 to pass through. Further, the adapter plate 125 can be a silicon adapter plate or a glass adapter plate. When the adapter plate 125 is a silicon adapter plate, it has a through silicon via structure (TSV); when the adapter plate 125 is a glass adapter plate, it has a through glass via structure (TGV).

[0055] On the basis of the above-mentioned embodiment, the wafer-level package multi-chip structure 120 further includes a welding portion 126. One end of the welding portion 126 is fixed to a side of the adapter plate 125 away from the chip 121 and the cofferdam 122, and the welding portion 126 is electrically connected to the rewiring layer 123 through the vertical interconnection structure 1251 of the adapter plate 125. Specifically, the welding portion 126 is electrically connected to the horizontal end 1253 of the vertical interconnection structure 1251 to achieve electrical connection with the rewiring layer 123. The other end of the welding portion 126 is fixed to one side of the substrate 110.

[0056] On the basis of the above-mentioned embodiment, the soldering portion 126 is a nickel-palladium-gold soldering pad, a nickel-gold soldering pad, a titanium-copper soldering pad or a BGA (Ball Grid Array) solder ball.

[0057] On the basis of the above-mentioned embodiment, the periphery of the welding part 126 is filled with an underfill 127. The underfill 127 may be an organic material, which supports the welding part 126 and prevents expansion and contraction.

[0058] Based on the above embodiments, the substrate 110 is a printed circuit board, a glass substrate, a silicon substrate or a ceramic substrate. Of course, the substrate 110 is not limited thereto, and can also be any substrate that can be used in the art.

[0059] In the chip packaging heat dissipation structure using the technical solution of the present invention, the liquid metal is in direct contact with the back of the chip, and has a strong thermal conductivity for the heat generated when the chip is working; the two ends of the liquid metal heat dissipation channel extend away from the chip and penetrate the metal heat dissipation cover, which is conducive to increasing the heat dissipation area; the end of the liquid metal heat dissipation channel is closed, which can prevent the liquid metal flow from affecting the heat dissipation effect. The above overall can improve the heat dissipation capacity, especially suitable for the packaging heat dissipation of large-size and high-power artificial intelligence chips.

[0060] like Figure 3 The method for manufacturing a chip packaging heat dissipation structure according to an embodiment of the present invention comprises the following steps:

[0061] S10. Provide a completed wafer-level packaged multi-chip structure, wherein the completed wafer-level packaged multi-chip structure includes a plurality of chips and a cofferdam, wherein the chip includes a functional surface and a back surface that are relatively arranged, and the cofferdam is arranged around the periphery of the chip, and the surface of the cofferdam close to the back surface of the chip is flush with the back surface of the chip.

[0062] Specifically in this embodiment, please also combine Figure 1 and Figures 4 - 6 , the manufacturing method of the chip package heat dissipation structure 100 of the above embodiment includes the following steps:

[0063] According to the CoWoS (Chip on Wafer on Substrate) process flow, after the CoW process is completed, a Figure 4 shown wafer assembled with components such as the chip 121 and the interposer 125 is obtained. The wafer includes a number of wafer-level packaged multi-chip structures 120. The wafer-level packaged multi-chip structure 120 includes multiple chips 121, a dam 122, a redistribution layer 123, micro-bumps 124, an interposer 125 with a vertical interconnection structure 1251, and a solder joint 126. Among them, the dam 122 is disposed around the periphery of the chip 121, and the surface of the dam 122 close to the back surface 1212 of the chip 121 is flush with the back surface 1212 of the chip 121; the redistribution layer 123 is fixed on one side of the functional surface 1211 of the chip 121; the micro-bumps 124 are located between the chip 121 and the redistribution layer 123; the interposer 125 is fixed on the side of the redistribution layer 123 away from the chip 121 and the dam 122; the solder joint 126 is fixed on the side of the interposer 125 away from the chip 121 and the dam 122, and the solder joint 126 is electrically connected to the redistribution layer 123 through the vertical interconnection structure 1251 of the interposer 125.

[0064] Cut the above assembled wafer along the Figure 4 dotted line in Figure 5 to obtain two wafer-level packaged multi-chip structures 120 as shown in Figure 5 . As shown in Figure 4 and Figure 5 , only partial schematic diagrams are shown. The present invention does not limit the number of components such as the chip 121, the dam 122, the redistribution layer 123, the micro-bumps 124, the interposer 125 with a vertical interconnection structure 1251, and the solder joint 126 in the wafer-level packaged multi-chip structure 120.

[0065] S20. Flip the wafer-level packaged multi-chip structure onto one side of the substrate.

[0066] Specifically, flip-chip solder the substrate 110 and fill the underfill 127 to obtain the Figure 6 shown structure.

[0067] S30. Place the metal heat sink cover on one side of the substrate, and enclose a receiving cavity with the substrate for accommodating the multi-chip structure after wafer-level packaging. The metal heat sink cover is fixedly connected to the outermost cofferdam through an adhesive to obtain a chip package heat dissipation structure. Among them, several chips, the cofferdams between adjacent chips, the metal heat sink cover, and the adhesive jointly enclose a liquid metal heat dissipation channel. The two ends of the liquid metal heat dissipation channel extend away from the chips and penetrate through the metal heat sink cover. The liquid metal heat dissipation channel is filled with liquid metal and the ends are closed.

[0068] Specifically, place the metal heat sink cover 130 on one side of the substrate 110, which can be fixedly connected by adhesive. At the same time, the metal heat sink cover 130 and the substrate 110 enclose a receiving cavity for accommodating the multi-chip structure 120 after wafer-level packaging. The metal heat sink cover 130 is fixedly connected to the outermost cofferdam 122 through the adhesive 140 to obtain Figure 1 the chip package heat dissipation structure 100 as shown. Among them, several chips 121, the cofferdams 122 between adjacent chips 121, the metal heat sink cover 130, and the adhesive 140 jointly enclose a liquid metal heat dissipation channel 131. The two ends of the liquid metal heat dissipation channel 131 extend away from the chips 121 and penetrate through the metal heat sink cover 130. The liquid metal heat dissipation channel 131 is filled with liquid metal 132 and the ends are closed.

[0069] The manufacturing method of the chip package heat dissipation structure of the technical solution of the present invention has a simple process. In the obtained chip package structure, the liquid metal is in direct contact with the back of the chip and has strong thermal conductivity for the heat generated when the chip works. The two ends of the liquid metal heat dissipation channel extend away from the chips and penetrate through the metal heat sink cover, which is beneficial to increasing the heat dissipation area. The ends of the liquid metal heat dissipation channel are closed, which can prevent the liquid metal from flowing and affecting the heat dissipation effect. The above can improve the heat dissipation ability, and is especially suitable for the packaging and heat dissipation of large-size high-power artificial intelligence chips.

[0070] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0071] The above is only the preferred embodiment of the present invention. The protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the idea of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and retouches should also be regarded as the protection scope of the present invention.

Claims

1. A packaging heat dissipation structure for large-size and high-power artificial intelligence chips, characterized in that, The chip package heat dissipation structure includes: A substrate; A completed wafer-level packaged multi-chip structure located on one side of the substrate. The completed wafer-level packaged multi-chip structure includes a plurality of chips and a cofferdam. The chips include a functional surface and a back surface disposed opposite to each other. The cofferdam is disposed around the periphery of the chips. The surface of the cofferdam close to the back surface of the chip is flush with the back surface of the chip; A metal heat dissipation cover covering one side of the substrate and enclosing a receiving cavity with the substrate for receiving the completed wafer-level packaged multi-chip structure. The metal heat dissipation cover is fixedly connected to the outermost cofferdam through an adhesive; The plurality of chips, the cofferdams between adjacent chips, the metal heat dissipation cover and the adhesive jointly enclose a liquid metal heat dissipation channel. The two ends of the liquid metal heat dissipation channel extend away from the chips and penetrate the metal heat dissipation cover. The liquid metal heat dissipation channel is filled with liquid metal and the ends are closed. The liquid metal heat dissipation channel includes a first channel in direct contact with the back surface of the chip and a second channel extending in a direction perpendicular to the surface of the chip and penetrating the metal heat dissipation cover. The thickness of the first channel in the direction perpendicular to the chip surface is the same as the thickness of the adhesive. The inside of the metal heat dissipation cover also has a liquid cooling channel. The liquid cooling channel is disposed close to the back surface of the chip and is located within the space enclosed by the liquid metal heat dissipation channel.

2. The encapsulation heat dissipation structure for a large-size high-power artificial intelligence chip according to claim 1, wherein The thickness of the first channel in the direction perpendicular to the chip surface is 0.1 mm - 1 mm. The thickness of the second channel in the direction parallel to the chip surface is 0.5 mm - 1.5 mm. The length of the second channel in the direction perpendicular to the chip surface is 2 mm - 9 mm.

3. The encapsulation heat dissipation structure for large-size and high-power artificial intelligence chips according to claim 1, wherein, The positive projection of the liquid metal heat dissipation channel on the chip covers the chips and the cofferdams between adjacent chips.

4. The encapsulation heat dissipation structure for large-size high-power artificial intelligence chips according to claim 1, characterized in that The material of the cofferdam is a plastic encapsulation material.

5. The encapsulation heat dissipation structure for large-size and high-power artificial intelligence chips according to claim 1, wherein The completed wafer-level packaged multi-chip structure further includes a redistribution layer fixed on the side of the functional surface of the chip; The completed wafer-level packaged multi-chip structure further includes micro-bumps located between the chips and the redistribution layer; The completed wafer-level packaged multi-chip structure further includes an interposer fixed on the side of the redistribution layer away from the chips and the cofferdam. The interposer has a vertical interconnection structure; The completed wafer-level packaged multi-chip structure further includes a solder joint. One end of the solder joint is fixed on the side of the interposer away from the chips and the cofferdam. And the solder joint is electrically connected to the redistribution layer through the vertical interconnection structure of the interposer. The other end of the solder joint is fixed on one side of the substrate; The solder joint is a nickel-palladium-gold pad, a nickel-gold pad, a titanium-copper pad or a BGA solder ball; The periphery of the solder joint is filled with underfill; 6. The encapsulation heat dissipation structure for large-size and high-power artificial intelligence chips according to claim 1, wherein The substrate is a printed circuit board, a glass substrate, a silicon substrate or a ceramic substrate.

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