Method for automatically optimizing decimal stray and integer boundary stray of frequency source

Abstract

The invention discloses a method for automatically optimizing fractional spurious and integer boundary spurious for a frequency source, belongs to the technical field of radar communication, and is used for solving the problem that the signal quality is influenced due to the fact that an existing frequency source outputs more spurious signals. According to the method, by setting a phase-locked loop phase discrimination frequency change range and phase discrimination frequency change stepping, an integer boundary spurious frequency and a decimal spurious frequency are associated with an out-of-band suppression point of a phase-locked loop loop filter through software configuration, the phase discrimination frequency is automatically optimized to integer boundary spurious suppression, the decimal spurious suppression meets an index, and the phase discrimination frequency is automatically optimized to the out-of-band suppression point. And automatic optimization of decimal stray and integer boundary stray is effectively realized.

Description

Technical Field

[0001] The invention belongs to the technical field of radar communication, and in particular relates to a method for automatically optimizing fractional spurious and integer boundary spurious of a frequency source. Background Art

[0002] The frequency source is the basic signal source of the electronic system. In modern electronic technology, the frequency source has become the core component of the electronic system and is widely used in radar, communication, measurement and control, countermeasures and navigation. With the development of modern electronic technology, the performance of electronic equipment has been continuously improved, and the functions have been continuously increased. At the same time, higher requirements have been put forward for the performance of frequency sources in all aspects. The indicators of frequency sources mainly include: miniaturization, small steps, high stability, ultra-wideband, low phase noise, low spurious, low power consumption, agile frequency change, fast start-up, etc. However, these indicators are mutually restrictive, and it is difficult to take them into account comprehensively. At the same time, the emphasis on the requirements of various indicators of frequency sources in different application fields is also different. Therefore, when designing frequency sources, it is often necessary to combine the actual application scenarios and make trade-offs and compromises on various indicators.

[0003] There are many ways to implement the existing frequency source, including phase-locked loop (PLL) frequency source, direct digital frequency synthesis (DDS) frequency source, DDS excitation PLL frequency source, PLL excitation PLL frequency source, etc. Phase-locked loop (PLL) cannot achieve fine-step frequency hopping; although DDS can achieve fine-step frequency hopping, it is limited by its working principle and cannot output relatively high-frequency and wide-band signals. In addition, due to the nonlinear characteristics of the DAC (digital-to-analog converter) inside the DDS, the output spurious is also very high, affecting the signal quality. DDS directly excites PLL, and the spurious and phase noise of the DDS output are greatly deteriorated, affecting the final output signal quality. PLL excites PLL frequency source, the circuit structure is simple, but when achieving fine steps, it is necessary to optimize integer boundary spurs and fractional spurs. Summary of the invention

[0004] The object of the present invention is to provide a method for automatically optimizing fractional spurs and integer boundary spurs by a frequency source, and to associate integer boundary spurious frequencies and fractional spurious frequencies with an out-of-band suppression point of a phase-locked loop filter, thereby realizing automatic optimization of fractional spurs and integer boundary spurs.

[0005] To achieve the above purpose, the technical solution adopted by the present invention is as follows: A method for automatically optimizing fractional spurious and integer boundary spurious of a frequency source comprises the following steps: S1, set the loop filter bandwidth of the phase-locked loop to f BW , the output frequency is set to f OUT , the phase detection frequency is set to f REFThe loop division ratio of the phase-locked loop is configured as Nx = f OUT / f REF ; S2, set the phase detection frequency range to f REF1 ~f REF2 , the phase detection frequency change step is set to X; S3, calculate the integer boundary spurs and fractional spurs of the phase-locked loop; S4, judging whether the integer boundary spurious and the fractional spurious of the phase-locked loop meet the condition that they both fall within the suppression band of the loop filter of the phase-locked loop; if they do, entering step S5, otherwise, adjusting the phase-locked frequency step by step according to the phase-locked frequency change, looping step S3 and step S4, until the integer boundary spurious and the fractional spurious of the phase-locked loop both fall within the suppression band of the loop filter of the phase-locked loop, then entering step S5; S5, outputs the final loop division ratio of the phase-locked loop.

[0006] Furthermore, in the present invention, the integer boundary spurious F1 calculation formula of the phase-locked loop is: F1=(Nx- INT(Nx))*f REF ; The calculation formula of fractional spurious F2 of the phase-locked loop is: F2=(INT(Nx)+1-Nx)*f REF ; The integer boundary spurious F1 and fractional spurious F2 of the phase-locked loop fall within the loop filter suppression band of the phase-locked loop, and the condition satisfied is F1 ≥ n*f BW And F2≥n*f BW ; Where n is the coefficient of the loop bandwidth multiplication; INT represents the rounding function.

[0007] Furthermore, in step S4, the specific steps of adjusting the phase-detection frequency stepwise according to the phase-detection frequency change are: S41, judge f REF1 ≤f REF +X≤f REF2 Is it established? If established, go to step S42; otherwise, go to step S43; S42, add the phase-lock frequency change step X to the last configured phase-lock frequency, and repeat steps S3 to S5 until F1 ≥ n*f BW And F2≥n*f BW Established, the final loop frequency division ratio is obtained; S43, subtract the difference f of the phase-lock frequency variation range from the last configured phase-lock frequency REF2 -f REF1 , repeat steps S3 to S5 until F1≥n*f BWAnd F2≥n*f BW Established, the final loop frequency division ratio is obtained.

[0008] Compared with the prior art, the present invention has the following beneficial effects: The frequency source of the present invention sets the phase-locked loop phase-comparison frequency variation range and the phase-comparison frequency variation step, associates the integer boundary spurious frequency and the fractional spurious frequency with the out-of-band suppression point of the phase-locked loop loop filter through software configuration, automatically optimizes the phase-comparison frequency until the integer boundary spurious suppression and fractional spurious suppression meet the index, and effectively realizes the algorithm of automatically optimizing the fractional spurious and the integer boundary spurious. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Schematic diagram of the structure of the frequency source in an embodiment of the present invention.

[0010] Figure 2 Flow chart of the method of the present invention. DETAILED DESCRIPTION

[0011] The present invention is further described below in conjunction with the accompanying drawings and embodiments. The embodiments of the present invention include but are not limited to the following embodiments.

[0012] The present invention discloses a method for automatically optimizing fractional spurious and integer boundary spurious of a frequency source, such as Figure 1 As shown, the frequency source in this embodiment includes a variable reference clock, a phase-locked loop and a control unit. Figure 2 As shown, the present invention designs the phase-locked loop bandwidth to be f through a hardware circuit. BW , the control unit sets the phase-locked loop output frequency to f OUT , the phase detection frequency range is set to f REF1 ~f REF2 , the phase detection frequency change step is set to X, and the phase detection frequency of the phase-locked loop is set to f REF , the loopback frequency ratio is configured as N=f OUT / f REF =Nx, then the integer boundary spurious F1 calculation formula of the phase-locked loop is: F1=(Nx- INT(Nx))*f REF ; The calculation formula for the fractional stray F2 of the phase-locked loop is: F2=(INT(Nx)+1-Nx)*f REF ; If F1 ≥ 100*f BW And F2 ≥ 100*f BW , then the integer boundary spurious F1 and fractional spurious F2 of the phase-locked loop fall within the loop filter suppression band of the phase-locked loop, and the integer boundary spurious suppression and fractional spurious suppression are better; where 100 is the coefficient multiplied by the loop bandwidth, which can be adjusted appropriately according to actual conditions. If F1<100*f BW or F2*fREF <100*f BW , the integer boundary spurious and fractional spurious of the phase-locked loop do not fall within the loop filter suppression band of the phase-locked loop, and the integer boundary spurious suppression and fractional spurious suppression are poor. Change the phase detection frequency. If f REF +X at the phase detection frequency f REF1 ~f REF2 If f REF鉴相 =f REF +X, if f REF鉴相 =f REF +X is not at the phase detection frequency f REF1 ~f REF2 If f REF鉴相 =f REF -(f REF2 -f REF1 ).

[0013] The following is an example of specific values: The loop filter bandwidth of the phase-locked loop is designed to be 0.1MHz, the phase-locked loop frequency range is set to 50MHz-80MHz, and the phase-locked loop frequency changes in steps of 10MHz.

[0014] The output frequency is 2005.8MHz, the phase-locked frequency is designed to be 50MHz, Nx=2005.8 / 50=40.116; (40.116-INT(40.116))*100=(40.116-40)*100=11.6MHz>0.1MHz*100; (INT(40.116)+1-40.116)*100=(40+1-40.116)*100=88.4MHz>0.1MHz*100, at this time the phase-locked frequency is 50MHz, Nx=2005.8 / 50=40.116.

[0015] Output frequency is 2000.1MHz, phase detection frequency is designed to be 50MHz, Nx=2000.1 / 50=40.002; (40.002-INT(40.002))*100=(40.002-40)*100=0.2MHz<0.1MHz*100; (INT(40.002)+1-40.002)*100=(40+1-40.002)*100=99.8MHz>0.1MHz*100 , at this time, the phase-locked frequency is 50MHz+10MHz=60MHz; Nx=2000.1 / 60=33.335, (33.335-INT(33.335))*100=(33.335-33)*100=33.5MHz>0.1MHz*100; (INT(33.335)+1-33.335)*100=(33+1-33.335)*100=66.5MHz>0.1MHz*100. At this time, the phase-locked frequency is 60MHz; Nx=2000.1 / 60=33.335.

[0016] The output frequency is 2080.4MHz, the phase-locked frequency is designed to be 80MHz, Nx=2080.4 / 80=26.005; (26.005-INT(26.005))*100=(26.005-26)*100=0.5MHz<0.1MHz*100; (INT(26.005)+1-26.005)*100=(26+1-26.005)*100=99.5MHz>0.1MHz*100, At this time, the phase-lock frequency is 80MHz-(80-50)=50MHz; Nx=2080.4 / 50=41.608, (41.608-INT(41.608))*100=(41.608-41)*100=60.8MHz>0.1MHz*100; (INT(41.608)+1-41.608)*100=(41+1-41.608)*100=39.2MHz>0.1MHz*100. At this time, the phase-lock frequency is 50MHz; Nx=2080.4 / 50=41.608.

[0017] The frequency source of the present invention sets the phase-locked loop phase-comparison frequency variation range and the phase-comparison frequency variation step, associates the integer boundary spurious frequency and the fractional spurious frequency with the out-of-band suppression point of the phase-locked loop loop filter through software configuration, automatically optimizes the phase-comparison frequency until the integer boundary spurious suppression and fractional spurious suppression meet the index, and effectively realizes the algorithm of automatically optimizing the fractional spurious and the integer boundary spurious.

[0018] The above embodiment is only one of the preferred implementation modes of the present invention and should not be used to limit the protection scope of the present invention. Any changes or modifications that are made to the main design concept and spirit of the present invention and have no substantive significance, and the technical problems they solve are still consistent with the present invention, should be included in the protection scope of the present invention.

Claims

1. A method for automatically optimizing fractional spurious and integer boundary spurious of a frequency source, characterized in that: The following steps are involved: S1, set the loop filter bandwidth of the phase-locked loop to f BW , the output frequency is set to f OUT , the phase detection frequency is set to f REF The loop division ratio of the phase-locked loop is configured as Nx = f OUT / f REF ; S2, set the phase detection frequency range to f REF1 ~f REF2 , the phase detection frequency change step is set to X; S3, calculate the integer boundary spurs and fractional spurs of the phase-locked loop; S4, judging whether the integer boundary spurious and the fractional spurious of the phase-locked loop meet the condition that they both fall within the suppression band of the loop filter of the phase-locked loop; if they do, entering step S5, otherwise, adjusting the phase-locked frequency step by step according to the phase-locked frequency change, looping step S3 and step S4, until the integer boundary spurious and the fractional spurious of the phase-locked loop both fall within the suppression band of the loop filter of the phase-locked loop, then entering step S5; S5, outputs the final loop division ratio of the phase-locked loop.

2. The method for automatically optimizing fractional spurious and integer boundary spurious of a frequency source according to claim 1, characterized in that: The calculation formula for the integer boundary spurious F1 of the phase-locked loop is: F1=(N.x- INT(N.x))*f REF ; The calculation formula of fractional spurious F2 of the phase-locked loop is: F2=(INT(N.x)+1-N.x)*f REF ; The integer boundary spurious F1 and fractional spurious F2 of the phase-locked loop fall within the loop filter suppression band of the phase-locked loop, and the condition satisfied is F1 ≥ n*f BW And F2≥n*f BW ; Where n is the coefficient of the loop bandwidth multiplication; INT represents the rounding function.

3. The method for automatically optimizing fractional spurious and integer boundary spurious of a frequency source according to claim 2, characterized in that: In step S4, the specific steps of adjusting the phase detection frequency step by step according to the phase detection frequency change are: S41, judge f REF1 ≤f REF +X≤f REF2 Is it established? If established, proceed to step S42; Otherwise, proceed to step S43; S42, add the phase-locking frequency change step X to the last configured phase-locking frequency, and repeat steps S3 to S5 until F1 ≥ n*f BW And F2≥n*f BW Established, the final loop frequency division ratio is obtained; S43, subtract the difference f of the phase-lock frequency variation range from the last configured phase-lock frequency REF2 -f REF1 , repeat steps S3 to S5 until F1≥n*f BW And F2≥n*f BW Established, the final loop frequency division ratio is obtained.

Images