A data synchronization optimization method for x86 instruction conversion in ARM multi-core

Abstract

The present invention discloses an x86 instruction conversion data synchronization optimization method for ARM many-cores. When executing a multi-threaded executable file in a dynamic instruction conversion mode, a data synchronization optimization module is constructed in the ARM many-core system, a program flow analysis unit inserts synchronization instructions according to the program flow analysis result, a data synchronization window manager inserts synchronization instructions for functions and related shared data instructions according to the execution time of data synchronization related functions, and a synchronization instruction combination optimization unit combines the inserted synchronization instructions, thereby realizing data synchronization and optimization of the converted ARM instruction sequence, improving the data synchronization performance and efficiency of the x86 program in the ARM many-core system, reducing the synchronization overhead, ensuring the correctness of program execution and data consistency, and providing an innovative solution for the efficient operation of cross-architecture programs.

Description

Technical Field

[0001] The invention belongs to the technical field of computer software development, and in particular relates to an ARM multi-core oriented x86 instruction conversion data synchronization optimization method. Background Art

[0002] As the demand for heterogeneous computing grows, using ARM many-core systems to execute traditional x86 programs has become an important way to expand computing capabilities. ARM many-core systems usually refer to systems with more than 64 computing cores. However, there are significant differences between x86 and ARM architectures in terms of data synchronization mechanisms. Existing technologies have many problems in handling data synchronization in cross-architecture conversions, especially when it comes to many-core architectures, such as high synchronization overhead and low performance. They cannot fully utilize the parallelism of ARM many-cores and are difficult to adapt to complex program structures and data dependencies. Therefore, maintaining data synchronization in the instruction conversion process when dynamically converting x86 programs and running them on ARM many-core systems faces certain challenges. Summary of the invention

[0003] In view of this, the present invention provides an x86 instruction conversion data synchronization optimization method for ARM many-core, and realizes the synchronous execution of x86 instructions in the ARM many-core system by constructing a data synchronization optimization module.

[0004] The present invention provides an ARM multi-core oriented x86 instruction conversion data synchronization optimization method, which specifically includes the following steps:

[0005] Step 1: When the ARM many-core system is initialized, the data synchronization optimization module is started. The data synchronization optimization module includes a program flow analysis unit, a data synchronization window manager, and a synchronization instruction combination optimization unit. The program flow analysis unit is used to perform program flow analysis on the executable file to insert synchronization instructions. The data synchronization window manager inserts synchronization instructions for the data synchronization related functions and related shared data instructions according to the execution time of the data synchronization related functions. The synchronization instruction combination optimization unit is used to combine the inserted synchronization instructions.

[0006] Step 2: Load the executable file in the ARM multi-core system through dynamic instruction conversion. If the executable file is a multi-threaded program, execute step 3; otherwise, complete the loading and execution of the executable file through dynamic instruction conversion and end this process;

[0007] Step 3, obtaining the current instruction to be converted, pre-fetching a set number of instructions from the current instruction to be converted as the first instruction set, and fetching a set number of instructions from the current instruction to be converted as the second instruction set, forming a third instruction set from the first instruction set, the current instruction to be converted and the second instruction set, and completing instruction conversion of the third instruction set to obtain the first ARM instruction set;

[0008] Step 4, the program flow analysis unit obtains the operands of each instruction in the first ARM instruction set to form a first ARM operand set; in the first ARM operand set, when there is an operand that is an operand of multiple instructions and is of memory type, and these instructions contain at least one write operation, the operand is saved in the operand list to be synchronized; when there is an operand that is of register type and uses the same global variable to store data, the operand is saved in the operand list to be synchronized; when there is an operand that is located in a branch structure and is an operand of a data transmission instruction, the operand and the branch instruction are saved in the operand list to be synchronized; when there is an operand that is located in a loop structure and is an operand of a data transmission instruction, the operand and the loop instruction are saved in the operand list to be synchronized;

[0009] Obtain the function entry position and function exit position of the function where each operand in the operand list to be synchronized is located, record the records in the operand list to be synchronized contained in the function as the sub-operand list to be synchronized, extract non-repeated function entry and exit position pairs, obtain the estimated execution time of the function, and save the function entry and exit position pairs, the corresponding sub-operand list to be synchronized and the estimated execution time in the function list to be synchronized;

[0010] Step 5, the data synchronization window manager traverses the function entry and exit position pairs in the function list to be synchronized, adds a data memory barrier instruction at the function entry position, and adds a data synchronization barrier instruction at the function exit position; pre-executes the function to obtain the execution time of the function, if the execution time is greater than the estimated execution time and the total number of shared data related instructions during the function execution process is greater than the threshold, then execute step 6; otherwise, move the data synchronization barrier instruction backward to after the last shared data related instruction in the function body to form a data synchronization post-instruction sequence, and then execute step 7;

[0011] Step 6, obtain the records in the sub-operand list to be synchronized. If the record contains only operands, convert the operand-related data loading instructions into instructions for exclusive loading, and convert the operand-related data storage instructions into instructions for exclusive storage; if the record contains branch instructions, add data memory barrier instructions before and after the branch structure starts; if the record contains loop instructions, add instructions for loading the operand in an exclusive manner before the operand-related instructions in the loop body, and add instructions for storing the operand in an exclusive manner after the instructions, thereby obtaining an instruction sequence after data synchronization;

[0012] Step 7, the synchronization instruction combination optimization unit obtains the data memory barrier instruction pairs adjacent to each other in the instruction sequence after data synchronization, and replaces the data memory barrier instruction pairs with a data synchronization barrier instruction, and the position of the data synchronization barrier instruction is the larger instruction address in the data memory barrier instruction pair;

[0013] Step 8, obtaining the influence of the operands in the sub-operand list to be synchronized on the execution performance of the function, and saving the operands with lower influence in the delayed synchronization list; obtaining the operands that will not be used later through branch prediction, and saving the operands in the delayed synchronization list; adding the storage instructions corresponding to the operands in the delayed synchronization list to the delayed synchronization buffer, and executing the corresponding storage instructions in the delayed synchronization buffer to complete the update operation only when other instructions need to use the operands;

[0014] Step 9: If the executable file has not been executed, execute step 3; otherwise, end this process.

[0015] Furthermore, the data synchronization optimization module in step 1 is added to the dynamic instruction conversion engine of the ARM many-core system.

[0016] Furthermore, the method for determining whether the executable file is a multi-threaded program in step 2 is as follows: if there is an import operation of creating a thread interface provided by the operating system when the executable file is loaded, then the executable file is determined to be a multi-threaded program.

[0017] Furthermore, the method for determining whether the executable file is a multi-threaded program in step 2 is as follows: during the execution of the executable file, if there is a call to create a thread interface provided by the operating system, the executable file is determined to be a multi-threaded program.

[0018] Furthermore, the method of obtaining the estimated execution time of the function in step 4 is: calculating it according to the execution time of each instruction.

[0019] Furthermore, the method of obtaining the estimated execution time of the function in step 4 is: measuring it when the function is dynamically executed.

[0020] Furthermore, if the record contains a loop instruction and a loop end instruction is obtained, a data memory barrier instruction is added at the end of the loop. Beneficial Effects

[0021] When executing a multi-threaded executable file in a dynamic instruction conversion manner, the present invention constructs a data synchronization optimization module in the ARM many-core system, a program flow analysis unit inserts synchronization instructions according to the program flow analysis results, a data synchronization window manager inserts synchronization instructions for functions and related shared data instructions according to the execution time of data synchronization-related functions, and a synchronization instruction combination optimization unit combines the inserted synchronization instructions, thereby realizing data synchronization and optimization of the converted ARM instruction sequence, improving the performance and efficiency of data synchronization of x86 programs in the ARM many-core system, reducing synchronization overhead, ensuring the correctness of program execution and data consistency, and providing an innovative solution for the efficient operation of cross-architecture programs. DETAILED DESCRIPTION

[0022] The present invention is described in detail with reference to the following embodiments.

[0023] The invention provides an x86 instruction conversion data synchronization optimization method for ARM many-cores, the core idea of ​​which is: when executing a multi-threaded executable file in a dynamic instruction conversion mode, by constructing a data synchronization optimization module in the ARM many-core system, a program flow analysis unit inserts synchronization instructions according to the program flow analysis results, a data synchronization window manager inserts synchronization instructions for functions and related shared data instructions according to the execution time of data synchronization related functions, and a synchronization instruction combination optimization unit combines the inserted synchronization instructions to achieve data synchronization and optimization of the converted ARM instruction sequence.

[0024] The present invention provides an ARM multi-core oriented x86 instruction conversion data synchronization optimization method, which specifically includes the following steps:

[0025] Step 1. When the ARM many-core system is initialized, the data synchronization optimization module is started. The data synchronization optimization module includes a program flow analysis unit, a data synchronization window manager and a synchronization instruction combination optimization unit. The program flow analysis unit is used to perform program flow analysis on the executable file to be converted, and insert synchronization instructions according to the program flow analysis results; the data synchronization window manager is used to obtain data synchronization related functions, and insert synchronization instructions for functions and related shared data instructions according to the function execution time; the synchronization instruction combination optimization unit is used to combine the inserted synchronization instructions to optimize the synchronization process.

[0026] Among them, the data synchronization optimization module is added to the dynamic instruction conversion engine of the ARM many-core system.

[0027] Step 2: Load the executable file in the ARM multi-core system through dynamic instruction conversion. If the executable file is a multi-threaded program, execute step 3; otherwise, complete the loading and execution of the executable file through dynamic instruction conversion to end this process.

[0028] Step 3, obtain the current instruction to be converted, pre-fetch a set number of instructions from the current instruction to be converted as the first instruction set, fetch a set number of instructions from the current instruction to be converted as the second instruction set, form an instruction set related to the current instruction to be converted by the first instruction set, the current instruction to be converted and the second instruction set, record it as the third instruction set, complete the instruction conversion of the third instruction set to obtain the first ARM instruction set.

[0029] Among them, the method of judging whether the executable file is a multi-threaded program is a static method, that is, judging whether there is an import of the thread creation interface provided by the operating system when the executable file is loaded. If so, the executable file is judged to be a multi-threaded program, otherwise it is not a multi-threaded program. In addition, a dynamic method can be used for judgment, that is, during the running of the executable file, dynamically judging whether there is a call to the thread creation interface provided by the operating system. If so, the executable file is judged to be a multi-threaded program, otherwise it is not a multi-threaded program.

[0030] Step 4, the program flow analysis unit analyzes the first ARM instruction set of the current instruction to be converted, obtains the operands of each instruction in the first ARM instruction set to form a first ARM operand set; in the first ARM operand set, when there are operands that are operands of multiple instructions and are of memory type, and these instructions contain at least one write operation, the operand is saved in the operand list to be synchronized; when there are operands of register type, and the same global variable is used to store the data of the operand in a multi-threaded environment, the operand is saved in the operand list to be synchronized; when there is an operand that is located in a branch structure and is an operand of a data transmission instruction, the operand and the branch instruction are saved in the operand list to be synchronized; when there is an operand that is located in a loop structure and is an operand of a data transmission instruction, the operand and the loop instruction are saved in the operand list to be synchronized;

[0031] Get the function entry position and function exit position of the function where each operand in the operand list to be synchronized is located, record the records in the operand list to be synchronized contained in the function as the sub-operand list to be synchronized, extract non-repeating function entry and exit position pairs, get the estimated execution time of the function, and save the function entry and exit position pairs, the corresponding sub-operand list to be synchronized and the estimated execution time in the function list to be synchronized.

[0032] Among them, data transfer instructions include data loading and data storage instructions. The estimated execution time of the function is obtained statically or dynamically. Static acquisition is calculated based on the execution time of each instruction, and dynamic acquisition is obtained through dynamic execution measurement.

[0033] Step 5, traverse the function entry and exit position pairs in the list of functions to be synchronized, the data synchronization window manager adds a data memory barrier instruction at the function entry position, and adds a data synchronization barrier instruction at the function exit position; pre-execute the function, record the execution time of the function, if the execution time is greater than the estimated execution time and the total number of shared data related instructions during the function execution process is greater than the threshold, then execute step 6; otherwise, if the execution time is not greater than the estimated execution time, and the total number of shared data related instructions is not greater than the threshold, then move the data synchronization barrier instruction backward to after the last shared data related instruction in the function body to form a post-data synchronization instruction sequence, and then execute step 7.

[0034] Step 6. Obtain the records in the sub-operand list to be synchronized. If the record contains only operands, convert the operand-related data loading instructions into instructions for exclusive loading, and convert the operand-related data storage instructions into instructions for exclusive storage; if the record contains branch instructions, add data memory barrier instructions before the start and after the end of the branch structure; if the record contains loop instructions, add instructions for exclusively loading the operand before the operand-related instructions in the loop body, and add instructions for exclusively storing the operand after the instructions, thereby obtaining an instruction sequence after data synchronization.

[0035] In order to further improve the execution efficiency of the executable file, the present invention optimizes the data synchronization of the loop structure. Specifically, if the record contains a loop instruction and the loop end instruction is obtained, a data memory barrier instruction is added only at the end of the loop. The loop end instruction is obtained by obtaining a set of instructions from the loop start instruction forward to detect the loop end instruction. By replacing the instructions for loading and storing operands in an exclusive manner added in the loop body with the data memory barrier instructions added at the end of the loop, the number of synchronization instructions used is significantly reduced, thereby effectively improving the execution efficiency of the executable file.

[0036] Step 7. The synchronization instruction combination optimization unit obtains data memory barrier instruction pairs adjacent to each other in the instruction sequence after data synchronization. A data memory barrier instruction pair means that there are no other data synchronization instructions between two data memory barrier instructions. The data memory barrier instruction pair is replaced with one data synchronization barrier instruction. The insertion position of the data synchronization barrier instruction is the larger instruction address in the data memory barrier instruction pair.

[0037] Step 8. Obtain the degree of influence of the operands in the sub-operand list to be synchronized on the execution performance of the function, and save the operands with lower influence in the delayed synchronization list; obtain the operands that may not be used later through branch prediction, and save the operands in the delayed synchronization list; add the storage instructions corresponding to the operands in the delayed synchronization list to the delayed synchronization buffer, and execute the corresponding storage instructions in the delayed synchronization buffer to complete the update operation only when other instructions need to use the operands.

[0038] Step 9: If the executable file has not been executed, execute step 3; otherwise, end this process. Example

[0039] In this embodiment, an x86 instruction conversion data synchronization optimization method for ARM many-core provided by the present invention is adopted to realize the synchronous execution of x86 instruction programs in the ARM many-core system, including the following steps:

[0040] S1. When starting to convert x86 instructions into ARM instructions, the program flow analysis unit analyzes the x86 program, determines possible synchronization points, and inserts initial synchronization instructions according to different program structures, including:

[0041] S1.1. Perform pre-insertion of synchronization instructions based on program flow analysis. In the process of converting x86 programs to ARM instructions, the LLVM compiler is used to deeply analyze the instruction flow of x86 programs. For code segments with potential data sharing and competition conditions, the positions where synchronization instructions may need to be inserted are determined in advance by analyzing the operands, register usage, and control flow structure of the instructions.

[0042] For simple instructions, as shown in the following code snippet:

[0043] MOV EAX, [shared variable address]

[0044] ADD EAX, 10

[0045] MOV [shared variable address], EAX

[0046] After conversion to ARM instructions:

[0047] LDR R0, = shared variable address

[0048] LDR R1, [R0]

[0049] ADD R1, #10

[0050] DMB / / Data memory barrier to ensure that subsequent storage operations will not be executed in advance to ensure data consistency

[0051] STR R1, [R0]

[0052] Determine whether x86 assembly instructions have potential data sharing and race conditions, including operand analysis:

[0053] Memory operands: If multiple x86 instructions operate on the same memory address, and at least one of them is a write operation, there may be a race. For example, consider the following x86 instruction sequence:

[0054] MOV eax, [address] / / Read the value of memory address address to the eax register

[0055] MOV [address], ebx / / Write the value of the ebx register to the memory address address

[0056] In this example, the first instruction reads the value at address and the second instruction writes the value to address. If these two instructions are executed concurrently in different threads of execution, a race condition may result because the second instruction may overwrite the value read by the first instruction, while the first instruction expects the original value to be unmodified.

[0057] Register operands: Although registers are usually private in each thread, there are some special cases that need to be paid attention to. For example, if multiple threads use the same global variable to store register information (which may occur in some low-level programming), or if information is passed through registers in a multi-threaded environment, contention may occur. For example:

[0058] MOV eax, [global_variable] / / Read value from global variable to eax

[0059] ADD eax, 1 / / add 1 to eax

[0060] MOV [global_variable], eax / / Write the updated value back to the global variable

[0061] Here, different threads may read, modify, and write back global_variable at the same time, resulting in data race.

[0062] Control flow structure analysis:

[0063] Branch structure [consider only the structure]: In a multi-threaded environment, if different threads perform branch operations on shared data, different results may occur. For example:

[0064] CMP eax, 0 / / Compare whether eax is 0

[0065] JNE label / / If eax is not 0, jump to label

[0066] MOV [address], 1 / / Otherwise, write 1 to address

[0067] If multiple threads execute this code, their modifications to eax will affect whether address is written, possibly leading to inconsistent results.

[0068] Loop structure: In a loop, if multiple threads access shared data and the operation of modifying the data is in the loop, it may cause contention. For example:

[0069] MOV ecx, 10

[0070] loop_start:

[0071] MOV eax, [address]

[0072] ADD eax, 1

[0073] MOV [address], eax

[0074] LOOP loop_start

[0075] When multiple threads execute this loop, they will concurrently read, modify, and write the value at address, causing contention.

[0076] S1.2. The steps to determine the location of inserting synchronization instructions when converting to ARM instructions are as follows:

[0077] The ARM architecture provides a variety of synchronization mechanisms, such as LDREX, STREX, and DMB.

[0078] Consider the following x86 instructions:

[0079] MOV eax, [address] / / Read the value of memory address address to the eax register

[0080] ADD eax, 1 / / add 1 to eax

[0081] MOV [address], eax / / Write the updated value back to the memory address address

[0082] Converted to ARM instructions as follows:

[0083] LDR R0, =address / / Load the address of address into the R0 register

[0084] LDREX R1, [R0] / / Read the value of the memory address pointed to by R0 to the R1 register in an exclusive manner

[0085] ADD R1, R1, #1 / / Add 1 to R1

[0086] STREX R2, R1, [R0] / / Try to store the value of R1 to the memory address pointed to by R0 in an exclusive manner. If successful, R2 is 0, otherwise it is 1

[0087] CMP R2, #0 / / Check if the storage is successful

[0088] BNE retry / / If storage is unsuccessful (R2 is not 0), retry

[0089] In this ARM code: The LDREX and STREX instructions are combined to implement exclusive access, ensuring safe updates to shared memory in a multiprocessor environment. LDREX marks a memory address as exclusive access. If other processors are accessing the address, STREX will fail, that is, R2 is not 0 and needs to be retried. CMP and BNE are used to check the result of STREX. If it fails, re-execute the operation starting from LDREX.

[0090] For more complex control flow structures such as branches and loops.

[0091] Branch structure: For codes with conditional branches and shared data, synchronization instructions need to be inserted before and after the shared data access. For example:

[0092] LDR R0, =address / / Load shared address

[0093] DMB / / Data memory barrier to ensure that the previous operation is completed

[0094] CMP R1, #0 / / Compare whether R1 is 0

[0095] BNE label / / If not 0, jump to label

[0096] LDR R2, [R0] / / Read the value of the shared address

[0097] ADD R2, R2, #1 / / Add 1 to the value

[0098] STR R2, [R0] / / Store updated value

[0099] DMB / / Data memory barrier to ensure storage operation completion

[0100] The DMB instruction is used here to ensure that operations on shared data before and after the conditional branch will not be reordered, ensuring data consistency.

[0101] Loop structure: In a loop, exclusive access or memory barriers need to be used in each iteration to ensure the consistency of shared data. For example:

[0102] MOV R3, #10 / / loop counter

[0103] loop_start:

[0104] LDR R0, =address / / Load shared address

[0105] LDREX R1, [R0] / / Read in exclusive mode

[0106] ADD R1, R1, #1 / / Add 1 to the value

[0107] STREX R2, R1, [R0] / / Try to store

[0108] CMP R2, #0 / / Check if the storage is successful

[0109] BNE loop_start / / If unsuccessful, retry

[0110] SUBS R3, R3, #1 / / Decrement counter

[0111] BNE loop_start / / Continue looping until the counter reaches 0

[0112] Data sharing and contention analysis focuses on the read and write operations on memory operands, especially memory addresses that may be accessed concurrently in a multi-threaded environment, taking into account register operations and control flow structures that may affect shared data, such as branches and loops; inserting synchronization instructions, using LDREX and STREX for exclusive access, ensuring that atomic operations on shared memory are accurate, and using memory barrier instructions such as DMB to ensure the execution order of instructions and prevent reordering of memory operations.

[0113] In addition, for shared data access in loop structures, the insertion of synchronization instructions is further optimized. For example, for the following x86 loop code:

[0114] LOOP_START:

[0115] MOV EAX, [shared variable address]

[0116] ADD EAX, 1

[0117] MOV [shared variable address], EAX

[0118] CMP EAX, 100

[0119] JNE LOOP_START

[0120] After conversion to ARM instructions:

[0121] LOOP_START_ARM:

[0122] LDR R0, = shared variable address

[0123] LDR R1, [R0]

[0124] ADD R1, #1

[0125] STR R1, [R0]

[0126] CMP R1, #100

[0127] BNE LOOP_START_ARM

[0128] DSB / / Data synchronization barrier, inserted at the end of the loop to ensure that data updates during the entire loop are visible to other cores

[0129] In this embodiment, instead of inserting a synchronization instruction after each storage operation, a stronger data synchronization barrier (DSB) is inserted at the end of the loop, which reduces the frequent insertion of synchronization instructions and improves the efficiency of program execution. At the same time, through the analysis of the loop structure, it is determined that the data update in the loop has a certain locality, and the overall update is only ensured to be visible to other cores at the end of the loop, avoiding unnecessary synchronization overhead.

[0130] S2. The synchronization instruction combination optimization unit optimizes and combines the inserted synchronization instructions according to the real-time information of program execution to improve performance. The synchronization instruction combination optimization unit combines and optimizes the inserted synchronization instructions and merges multiple adjacent synchronization instructions into more efficient synchronization primitives according to the context of program execution and data dependencies.

[0131] In an x86 program containing multiple independent synchronization points:

[0132] LOCK XADD [lock address 1], EAX

[0133] MOV EBX, [shared variable address 1]

[0134] LOCK XADD [lock address 2], ECX

[0135] MOV EDX, [shared variable address 2]

[0136] After conversion to ARM instructions:

[0137] LDREX R1, [lock address 1]

[0138] ADD R1, R0

[0139] STREX R2, R1, [lock address 1]

[0140] DMB / / Initial inserted data memory barrier

[0141] LDR R3, [shared variable address 1]

[0142] LDREX R4, [lock address 2]

[0143] ADD R4, R5

[0144] STREX R6, R4, [lock address 2]

[0145] DMB / / Second data memory barrier

[0146] LDR R3, [shared variable address 1]

[0147] LDR R7, [shared variable address 2]

[0148] After optimization, the two DMB instructions can be combined into a stronger DSB instruction, because the program context indicates that the two synchronization points are relatively independent, but ultimately both need to ensure overall data consistency. When multiple DMB instructions are added, optimization needs to be attempted.

[0149] LDREX R1, [lock address 1]

[0150] ADD R1, R0

[0151] STREX R2, [lock address 1]

[0152] LDREX R4, [lock address 2]

[0153] ADD R4, R5

[0154] STREX R6, [lock address 2]

[0155] DSB / / Combined synchronization instructions to ensure the update of lock operations and shared variable reading

[0156] LDR R3, [shared variable address 1]

[0157] LDR R7, [shared variable address 2]

[0158] The above operation merges multiple relatively independent but related synchronization operations according to the program's execution logic and data dependencies, avoiding the performance overhead caused by multiple synchronization instruction executions and improving the overall performance.

[0159] S3. During program execution, the data synchronization window manager creates and adjusts the data synchronization window according to the program entry and exit, and combines the delayed synchronization buffer to store and delay the execution of non-critical shared data update operations.

[0160] When the program execution enters a code segment that may have data sharing, a data synchronization window is created. The initial size of the data synchronization window is set according to the estimated execution time of the code segment. The estimation steps are as follows:

[0161] For a function, obtain the ARM code after the entire function code is converted, and obtain the ARM assembly instruction list of the entire function code. If each instruction has a certain execution time or execution cycle number according to the ARM processor manual, the initial window size is the sum of the execution time of the ARM assembly instructions of the entire function code; otherwise, it means that there are instructions with uncertain instruction execution cycle numbers in the function code, such as dynamic function calls, etc., then the window is set according to the time record of the function's previous execution.

[0162] For example, for a function call, at the function entry, its execution time and shared data volume are estimated based on the function's historical execution data or static analysis results when the program is loaded, and an initial data synchronization window is created. For the following x86 function:

[0163] FUNC:

[0164] MOV EAX, [shared variable address 1]

[0165] ADD EAX, 10

[0166] MOV [shared variable address 1], EAX

[0167] CALL SUB_FUNC

[0168] MOV EBX, [shared variable address 2]

[0169] ADD EBX, 5

[0170] MOV [shared variable address 2], EBX

[0171] RET

[0172] After conversion to ARM instructions:

[0173] FUNC_ARM:

[0174] DMB / / Create a data synchronization window at the function entry

[0175] LDR R0, = shared variable address 1

[0176] LDR R1, [R0]

[0177] ADD R1, #10

[0178] STR R1, [R0]

[0179] BL SUB_FUNC_ARM

[0180] LDR R2, = shared variable address 2

[0181] LDR R3, [R2]

[0182] ADD R3, #5

[0183] STR R3, [R2]

[0184] DSB / / Close the data synchronization window when the function ends

[0185] BX LR

[0186] Create and close data synchronization windows according to the boundaries of code segments, concentrate synchronization operations in one window, and reduce the fragmentation of synchronization operations.

[0187] The window is adjusted dynamically, that is, within the data synchronization window, the window size and synchronization strategy are adjusted dynamically according to the actual execution of the program. If the execution time within the window exceeds the expected time and more shared data operations are detected, the window is expanded and additional synchronization instructions are inserted, that is: in the above FUNC_ARM function, if more shared variable operations are found when executing the SUB_FUNC_ARM sub-function, according to the new shared variable address and the number of operands monitored, insert additional DMB or DSB instructions at the instructions for accessing shared data inside SUB_FUNC_ARM to ensure data consistency within the data synchronization window and extend the window closing time accordingly.

[0188] On the contrary, if the program executes faster than expected and the shared data operations are reduced, the data synchronization window can be closed in advance or the intensity of the synchronization instructions can be reduced. This can be achieved by monitoring factors such as instruction execution speed, data operation frequency, and shared data address access mode.

[0189] The data synchronization strategy is dynamically adjusted according to the real-time execution of the program, avoiding the inefficiency of fixed synchronization strategy in the execution of complex programs, realizing flexible synchronization control and improving system performance.

[0190] S4. Delayed synchronization and speculative execution.

[0191] The delayed synchronization strategy in this embodiment is: for shared data operations on non-critical paths, a delayed synchronization strategy is adopted. During program execution, the update operation of shared data is temporarily stored in a local delayed synchronization buffer instead of being immediately synchronized to other computing cores.

[0192] The above-mentioned method for determining the critical path is: using hardware performance counters, such as Intel's performance monitoring unit PMU, to collect performance data during program execution, including instruction cycle count, cache hit rate, branch prediction error rate, etc. For code segments that may involve shared data operations, by analyzing the data of the performance counter, it is possible to determine whether the instruction is on the instruction path that has a great impact on the overall performance of the program.

[0193] For the following x86 code:

[0194] MOV EAX, [shared variable address]

[0195] ADD EAX, 1

[0196] MOV [shared variable address], EAX

[0197] After conversion to ARM instructions:

[0198] LDR R0, = shared variable address

[0199] LDR R1, [R0]

[0200] ADD R1, #1

[0201] STR_LATER R1, [R0] / / Instead of performing the store operation immediately, store the store operation in a delayed synchronization buffer

[0202] Delaying some non-critical shared data update operations reduces the impact of synchronization operations on the critical path and improves the smoothness of program execution.

[0203] Predictive execution and synchronization decisions, that is, combining branch prediction technology to predict the execution path of the program and the necessity of shared data operations. When it is predicted that some shared data updates may not be used by other computing cores, the synchronization operation is delayed.

[0204] For the following x86 code with conditional branching:

[0205] CMP EAX, 10

[0206] JGE BRANCH1

[0207] MOV [shared variable address], EBX

[0208] BRANCH1:

[0209] After conversion to ARM instructions:

[0210] CMP R0, #10

[0211] BGE BRANCH1_ARM

[0212] STR_LATER R1, [shared variable address] / / Delay the store operation only if the branch is predicted not to be taken

[0213] BRANCH1_ARM:

[0214] If the branch prediction does not execute the branch of the storage operation, the storage operation is delayed. Only when the prediction is wrong or the subsequent instructions depend on the shared data, the delayed storage operation is synchronized from the buffer to the memory and other computing cores are updated. Combining data synchronization with predictive execution technology avoids unnecessary synchronization operations and improves program performance and efficiency.

[0215] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for optimizing x86 instruction conversion data synchronization for ARM multi-core, characterized in that: The specific steps include: Step 1: When the ARM multi-core system is initialized, the data synchronization optimization module including the program flow analysis unit, the data synchronization window manager and the synchronization instruction combination optimization unit is started; the executable file is loaded through dynamic instruction conversion, if it is a multi-threaded program, step 2 is executed, otherwise the loading and execution are completed and the process is ended; Step 2, obtain the current instruction to be converted, and complete the instruction conversion by pre-fetching a set number of instructions from the current instruction to be converted, fetching a set number of instructions and the current instruction to be converted, and obtaining an instruction set. The program flow analysis unit obtains operands in the instruction set to form a first ARM operand set; in the first ARM operand set, when there are operands of memory type and multiple instruction operands, and these instructions contain at least one write operation, they are saved in the list to be synchronized; when there are operands of register type and the same global variable is used to store data, they are saved in the list to be synchronized; when there are operands that are located in a branch structure and are data transmission instruction operands, they are saved together with the branch instruction in the list to be synchronized; when there are operands that are located in a loop structure and are data transmission instruction operands, they are saved together with the loop instruction in the list to be synchronized; Obtain the function entry and exit positions of the operands in the to-be-synchronized list, record the records in the to-be-synchronized list contained in the function as the to-be-synchronized sub-list, and save the non-repeated function entry and exit position pairs, the corresponding to-be-synchronized sub-list and the estimated execution time of the function in the first list; Step 3, the data synchronization window manager traverses the function entry and exit position pairs in the first list, adds a data memory barrier instruction at the entry position, and adds a data synchronization barrier instruction at the exit position; pre-executes the function to obtain the execution time, if the execution time is greater than the estimated execution time and the total number of shared data related instructions during the execution process is greater than the threshold, then execute step 4, otherwise, move the data synchronization barrier instruction to after the last shared data related instruction in the function body, form a first instruction sequence, and execute step 5; Step 4: If the sublist to be synchronized contains only operands, convert its related data loading instructions into instructions for exclusive loading, and convert its related data storage instructions into instructions for exclusive storage; if it contains branch instructions, add data memory barrier instructions before and after the branch structure; if it contains loop instructions, add instructions for exclusive loading before the operand-related instructions in the loop body, and add instructions for exclusive storage after them, to obtain a first instruction sequence; Step 5: The synchronization instruction combination optimization unit obtains adjacent data memory barrier instruction pairs in the first instruction sequence, and replaces them with data synchronization barrier instructions located at a larger instruction address; Step 6: Add the storage instructions corresponding to the operands in the sublist to be synchronized that have a lower impact on the function execution performance and are not used in the subsequent branch prediction to the first buffer. When other instructions need to use these operands, execute the instructions in the first buffer to complete the update; if not completed, execute step 2, otherwise end this process.

2. The x86 instruction conversion data synchronization optimization method according to claim 1, characterized in that: The data synchronization optimization module in step 1 is added to the dynamic instruction conversion engine of the ARM many-core system.

3. The x86 instruction conversion data synchronization optimization method according to claim 1, characterized in that: In step 1, whether the executable file is a multi-threaded program is determined as follows: if there is an import operation of creating a thread interface provided by the operating system when the executable file is loaded, then the executable file is determined to be a multi-threaded program.

4. The x86 instruction conversion data synchronization optimization method according to claim 1, characterized in that: In step 1, whether the executable file is a multi-threaded program is determined as follows: during the execution of the executable file, if there is a call to create a thread interface provided by the operating system, the executable file is determined to be a multi-threaded program.

5. The x86 instruction conversion data synchronization optimization method according to claim 1, characterized in that: The estimated execution time of the function in step 2 is obtained by calculating it according to the execution time of each instruction.

6. The x86 instruction conversion data synchronization optimization method according to claim 1, characterized in that: The estimated execution time of the function in step 2 is obtained by measuring it when the function is dynamically executed.

7. The x86 instruction conversion data synchronization optimization method according to claim 1, characterized in that: If the record contains a loop instruction and a loop end instruction is obtained, a data memory barrier instruction is added at the end of the loop.