An exception handling conversion optimization method for ARM many-core dynamic instruction conversion

Abstract

The present invention discloses an exception handling conversion optimization method for ARM many-core dynamic instruction conversion. The method establishes a mapping relationship between x86 exception types and ARM exception types by constructing an exception type mapping table, establishes a first ARM exception handling program and a second ARM exception handling program for each type of ARM exception type, adds an exception identifier to the converted ARM exception triggering instruction, and when an exception occurs in the ARM many-core system, determines to start the first ARM exception handling program or the second ARM exception handling program in a multi-core parallel or single thread manner according to the system load and the number of the same exception types, thereby realizing efficient and accurate exception handling, solving the exception handling problem caused by architecture differences, providing an innovative exception handling conversion solution for cross-architecture program conversion, and improving the efficiency and performance of exception handling, thereby ensuring the stability and reliability of the system under various circumstances.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer software development, and in particular relates to an exception handling conversion optimization method for ARM multi-core dynamic instruction conversion. Background Art

[0002] As the demand for heterogeneous computing grows, using ARM many-core systems to execute traditional x86 programs has become an important way to expand computing capabilities. ARM many-core systems usually refer to systems with more than 64 computing cores. Due to the significant differences between the x86 architecture and the ARM architecture in terms of exception handling mechanisms, including exception types, exception triggering conditions, exception handler calling and execution processes, and exception handler storage layout, the existing exception handling conversion methods cannot meet the complex cross-architecture program conversion requirements. Summary of the invention

[0003] In view of this, the present invention provides an exception handling conversion optimization method for ARM many-core dynamic instruction conversion, which realizes seamless exception handling transition from x86 architecture to ARM architecture and ensures that the converted program can still run normally under abnormal circumstances.

[0004] The present invention provides an exception handling conversion optimization method for ARM multi-core dynamic instruction conversion, which specifically includes the following steps:

[0005] Step 1, constructing an exception type mapping table for mapping x86 exception types to ARM exception types; according to the exception type mapping table, establishing a first ARM exception handler and a second ARM exception handler for the ARM exception type, wherein the execution overhead of the first ARM exception handler is less than the execution overhead of the second ARM exception handler;

[0006] Step 2: When the ARM many-core system is initialized, the ARM exception vector table is initialized, memory space is allocated for the exception type mapping table and the ARM exception vector table, and the first ARM exception handler and the second ARM exception handler corresponding to the ARM exception type are stored in the corresponding ARM exception vector table according to the exception type mapping table; the executable file is loaded and executed through dynamic instruction conversion;

[0007] Step 3, obtain the current instruction to be converted. If the current instruction to be converted is an exception triggering instruction under the x86 architecture, convert the current instruction to be converted into an ARM exception triggering instruction, create an exception identifier for the ARM exception triggering instruction to indicate the corresponding x86 exception type, and then execute step 4; otherwise, convert the current instruction to be converted into an ARM instruction and execute step 7;

[0008] Step 4: When the ARM many-core system captures an exception, obtain the exception identifier of the current ARM exception triggering instruction, determine the current ARM exception type corresponding to the exception identifier according to the exception type mapping table, add the current ARM exception triggering instruction, the computing core where it is located, and the current ARM exception type to the dynamic execution exception list, obtain the current load of the ARM many-core system, and execute step 5 if the load is not greater than the threshold, otherwise execute step 6;

[0009] Step 5: If the number of records of the current ARM exception type in the dynamic execution exception list is greater than the threshold, the computing core where the current ARM exception type in the dynamic execution exception list is located is used as the target computing core, and the first ARM exception handler is started on each target computing core to complete the exception processing, and step 7 is executed; if the number of records of the current ARM exception type in the dynamic execution exception list is not greater than the threshold, the first ARM exception handler is started in an independent thread mode to complete the exception processing, and step 7 is executed;

[0010] Step 6: Start the second ARM exception handling program in an independent thread mode, complete the exception handling, and execute step 7;

[0011] Step 7: If the executable file has not completed execution, execute step 3; otherwise, end this process.

[0012] Furthermore, the exception types in the exception type mapping table include hardware exceptions, software exceptions and system exceptions.

[0013] Furthermore, the first ARM exception handling program and the second ARM exception handling program are both preloaded into a high-speed storage area.

[0014] Furthermore, the high-speed storage area is a tightly coupled memory of an ARM processor.

[0015] Furthermore, the exception flag is stored using an unused bit of ARM or a custom instruction extension field.

[0016] Furthermore, the exception flag is stored in a fast-access special register.

[0017] Furthermore, the processing process of the first ARM exception handler is: using an ARM batch storage instruction to save the first state of the target computing core, then performing an exception handling operation, and then using an ARM batch load instruction to restore the first state to the current computing core, and finally performing an exception return operation.

[0018] Furthermore, the exception handling operation includes outputting an error log.

[0019] Furthermore, the first state includes the states of general registers and program status registers in the target computing core.

[0020] Furthermore, the second ARM exception handling program is obtained by performing instruction combination optimization on the first ARM exception handling program. Beneficial Effects

[0021] The present invention establishes a mapping relationship between x86 exception types and ARM exception types by constructing an exception type mapping table, establishes a first ARM exception handling program and a second ARM exception handling program for each type of ARM exception type, adds an exception identifier to the converted ARM exception trigger instruction, and when an exception occurs in the ARM many-core system, determines to start the first ARM exception handling program or the second ARM exception handling program in a multi-core parallel or single thread manner according to the system load and the number of similar exception types, thereby achieving efficient and accurate exception handling, solving the exception handling problem caused by architecture differences, providing an innovative exception handling conversion solution for cross-architecture program conversion, and at the same time improving the efficiency and performance of exception handling, ensuring the stability and reliability of the system under various circumstances. DETAILED DESCRIPTION

[0022] The present invention is described in detail with reference to the following embodiments.

[0023] The present invention provides an exception handling conversion optimization method for ARM many-core dynamic instruction conversion, the core idea of ​​which is: by constructing an exception type mapping table to establish a mapping relationship between x86 exception types and ARM exception types, a first ARM exception handler and a second ARM exception handler are established for each type of ARM exception type, an exception identifier is added to the converted ARM exception trigger instruction, and when an exception occurs in the ARM many-core system, the first ARM exception handler or the second ARM exception handler is started in a multi-core parallel or single thread manner according to the system load and the number of similar exception types to complete the exception handling.

[0024] The present invention provides an exception handling conversion optimization method for ARM multi-core dynamic instruction conversion, which specifically includes the following steps:

[0025] Step 1: construct an exception type mapping table for establishing a mapping relationship between x86 exception types and ARM exception types, including x86 exception types, ARM exception types and exception description information; according to the exception type mapping table, establish a first ARM exception handler and a second ARM exception handler for each ARM exception type, wherein the execution overhead of the first ARM exception handler is less than the execution overhead of the second ARM exception handler.

[0026] In the present invention, the first ARM exception handling program is suitable for handling exceptions in the ARM many-core system under low load, and the second ARM exception handling program is suitable for handling exceptions in the ARM many-core system under high load. The exception types in the exception type mapping table include hardware exceptions, software exceptions and system exceptions.

[0027] Step 2: When the ARM many-core system is initialized, the ARM exception vector table is initialized, memory space is allocated for the exception type mapping table, the ARM exception vector table and the exception state, and the first ARM exception handler and the second ARM exception handler corresponding to the exception type are stored in the corresponding exception vector table according to the exception type mapping table; the executable file is loaded and executed in the ARM many-core system through dynamic instruction conversion.

[0028] In order to further improve the execution efficiency of the ARM exception handling program, the present invention preloads both the first ARM exception handling program and the second ARM exception handling program into a high-speed storage area, such as a tightly coupled memory of an ARM processor.

[0029] Step 3, obtain the current instruction to be converted. If the current instruction to be converted is an exception triggering instruction under the x86 architecture, convert the current instruction to be converted into an ARM exception triggering instruction, create an exception identifier for the ARM exception triggering instruction, and the exception identifier is used to identify the x86 exception type corresponding to the ARM exception triggering instruction, and then execute step 4; otherwise, convert the current instruction to be converted into an ARM instruction and execute step 7.

[0030] The exception flag can be saved using unused bits of ARM or custom instruction extension fields. In addition, to further improve execution efficiency, the exception flag can also be stored in a fast-access dedicated register.

[0031] Step 4. When the ARM many-core system captures an exception, obtain the exception identifier of the current ARM exception trigger instruction, determine the current ARM exception type corresponding to the exception identifier according to the exception type mapping table, and add the current ARM exception trigger instruction, the computing core where it is located, and the current ARM exception type to the dynamic execution exception list, and obtain the current load of the ARM many-core system. If the load is not greater than the threshold, execute step 5, otherwise execute step 6.

[0032] Step 5. If the number of records of the current ARM exception type in the dynamic execution exception list is greater than the threshold, the computing core where the current ARM exception type in the dynamic execution exception list is located is used as the target computing core, and the first ARM exception handler is started on each target computing core to complete the exception processing, and step 7 is executed; if the number of records of the current ARM exception type in the dynamic execution exception list is not greater than the threshold, the first ARM exception handler is started as an independent thread to complete the exception processing, and step 7 is executed.

[0033] The processing process of the first ARM exception handler is: using the ARM batch storage instruction to save the first state of the target computing core, then performing the exception handling operation, and then using the ARM batch load instruction to restore the first state to the current computing core, and finally performing the exception return operation. The exception handling operation includes outputting an error log, etc. The first state of the target computing core includes the states of the general registers, program status registers, etc. in the target computing core.

[0034] Step 6: Start the second ARM exception handling program in an independent thread mode, complete the exception handling, and execute step 7.

[0035] The second ARM exception handling program is obtained by performing instruction combination optimization on the first ARM exception handling program. The instruction combination optimization includes merging repeated instructions and the like.

[0036] Step 7: If the executable file has not completed execution, execute step 3; otherwise, end this process. Example

[0037] In this embodiment, an exception handling conversion optimization method for ARM many-core dynamic instruction conversion provided by the present invention is adopted to realize efficient and accurate exception handling of x86 instruction programs in an ARM many-core system, including the following steps:

[0038] S1. During the system initialization phase, an exception type mapping table is constructed and stored in an accessible area of ​​the system. At the same time, memory space is allocated for the storage and state saving area of ​​the exception handler, and the ARM exception vector table is initialized. Frequently used exception handlers are preloaded into high-speed storage areas, such as tightly coupled memory.

[0039] S1.1. Build exception type mapping and identification. Build a detailed mapping of x86 exception types to ARM types, covering all types of exceptions in the x86 architecture, and accurately map them to the corresponding exceptions or exception handling mechanisms in the ARM architecture. An example of an exception type mapping is as follows:

[0040] | x86 exception type | ARM exception type | exception description |

[0041] | 0x00 (Divide Error) | 0x01 (Undefined Instruction) | The division error is mapped to the undefined instruction exception, which may require special handling in ARM because ARM has no direct corresponding division error exception |

[0042] | 0x05 (BOUND Range Exceeded) | 0x02 (Data Abort) | The x86 bounds check exception is converted to the ARM data abort exception, adjusted according to the operands and program state when the exception is triggered |

[0043] | 0x0C (Stack Fault) | 0x03 (Stacking Error) | Convert the x86 stack error exception to the ARM stack error exception, taking into account the different management methods of stack pointer operations and stack space |

[0044] | 0x0D (General Protection Fault) | 0x04 (Prefetch Abort) | Convert the x86 general protection fault exception to the ARM prefetch abort exception, and adjust the handling method according to different error scenarios, such as illegal memory access, etc. |

[0045] | 0x0E (Page Fault) | 0x05 (Data Abort) | The page fault exception also corresponds to the data abort exception in ARM, but it needs to be handled differently according to the differences in the page table structure and the memory management unit (MMU). For example, ARM's MMU may use different translation tables and access permission checking mechanisms. |

[0046] Compared with traditional simple mapping, this mapping table has enhanced depth and breadth, accurately matches the characteristics of similar exceptions in different architectures, takes into account the specific circumstances of exception triggering, and ensures the accuracy and completeness of exception type conversion. Through the detailed classification and mapping of different exception types, it provides a clear basis for subsequent exception handling and avoids confusion and incorrect handling caused by architectural differences.

[0047] S1.2, build exception identification extension and conversion, that is, when converting the exception triggering instructions of the x86 program into ARM instructions, add additional exception identification information to the ARM instructions. For each x86 instruction that may trigger an exception, use ARM's unused bits or custom instruction extension fields to carry the x86 exception information.

[0048] For example, for the x86 division instruction DIV EBX, a division error exception (0x00) may be triggered. When converted to an ARM instruction, an exception flag is added by using an unused bit of the ARM instruction or a custom instruction extension field through a custom instruction extension.

[0049] The x86 division instruction is:

[0050] DIV EBX

[0051] The converted ARM instructions are:

[0052] SDIV R0, R1, R2

[0053] MOV R3, #0x00 / / Store x86 exception type, i.e. division error

[0054] STRB R3, [R13, #-4] / / Store the exception flag in the stack, assuming that the stack pointer offset is used for storage

[0055] To improve performance, the exception flags can be stored in a dedicated register with fast access, as follows:

[0056] MOV R14, #0x00 / / stored in register R14, can be adjusted according to the register usage convention of ARM computing core

[0057] By adding exception identification information to the ARM instruction, we can ensure that the original x86 exception type can be accurately traced when the exception is triggered, providing a more accurate information source for subsequent exception processing. Using fast-access registers to store exception identification speeds up the acquisition of exception information, reduces the time overhead of finding information during exception processing, and improves the response speed of exception processing compared to traditional stack storage methods.

[0058] S1.3. Establish the conversion of exception handlers and preload the frequently used exception handlers into a high-speed storage area, such as the tightly coupled memory of the ARM processor. The specific steps are as follows:

[0059] Convert the structure of the exception handler, that is, for the x86 exception handler, convert its structure to the exception handler structure that conforms to the ARM architecture. The x86 exception handler usually jumps from the exception vector table to the corresponding handler, and performs operations such as register saving, error code processing, and state recovery. In ARM, it needs to be converted to a handler that uses the corresponding exception vector table entry and exception mode.

[0060] For example, for the x86 divide error exception handler:

[0061] divide_error_handler:

[0062] push eax / / save register

[0063] push ebx

[0064] … / / Exception handling logic, which may include error message printing, error code processing, etc.

[0065] mov eax, [esp + 8] / / Get error code

[0066] … / / More processing logic, such as error logging or recovery strategies

[0067] pop ebx / / restore register

[0068] pop eax

[0069] iret / / Interrupt return

[0070] Converted to ARM exception handler:

[0071] divide_error_handler_arm:

[0072] stmdb sp!, {r0 - r12, lr} / / Save registers according to ARM exception handling mode

[0073] … / / Exception handling logic, adjusted according to the storage and access methods of ARM exception handlers

[0074] ldr r0, [sp, #24] / / Get the error code and adjust it according to the ARM stack frame layout

[0075] ... / / Error logging, using ARM output instructions, such as outputting error information via UART

[0076] ldr r1, =error_message / / Assume error_message is the address where the error message is stored

[0077] bl uart_print / / Call custom UART print function

[0078] … / / More processing logic, such as possible recovery strategy adjustment, optimized according to the characteristics of ARM architecture

[0079] ldmia sp!, {r0 - r12, lr} / / Restore registers

[0080] subs pc, lr, #4 / / Exception return, according to ARM interrupt return mechanism

[0081] The structure of the x86 exception handler is redesigned according to the ARM exception handling mode and storage layout to ensure that the program processing flow after the exception occurs can be smoothly executed under the ARM architecture. At the same time, the operations in the exception handler are optimized, such as using more efficient output instructions to print error information, avoiding unnecessary operations and performance overhead, and improving the execution efficiency of the exception handler.

[0082] The storage layout of the exception handler is adjusted, and the storage location of the converted exception handler in the ARM many-core system is reorganized. On the ARM processor platform, the exception handler is usually stored in a specific exception vector table, and the converted exception handler is stored in the corresponding position according to the mapped exception type. In order to improve performance, the present invention adopts the method of dynamic allocation and preloading to store the most commonly used exception handler in a high-speed storage area closer to the processor core.

[0083] For example, for the above converted division error exception handler, it is stored in the storage location corresponding to the entry of the undefined instruction exception vector table of ARM, assuming it is 0x04 address:

[0084] word divide_error_handler_arm / / Stored at the entry of the undefined instruction exception vector table

[0085] LDR R0, =divide_error_handler_arm

[0086] STR R0, [TCM_START_ADDRESS] / / Assume that TCM_START_ADDRESS is the starting address of the tightly coupled memory

[0087] The converted exception handler is stored according to the ARM exception vector table layout to ensure that the correct handler can be called quickly when an exception occurs. At the same time, by preloading common exception handlers into the high-speed storage area, the program loading time is reduced, the response speed of exception handling and the overall performance of the system are improved, especially when handling high-frequency exceptions.

[0088] S2. Abnormal state preservation and recovery.

[0089] S2.1. Identification of exceptions. In the ARM many-core system architecture, many different types of exceptions may occur during instruction execution, such as data access exceptions, undefined instruction exceptions, etc. The exception identification extension built based on the previous steps can detect and identify these exceptions more accurately and quickly. When the instruction is executed, the system can quickly determine the type of exception that has occurred based on the pre-defined identifiers in the exception identification extension, and provide accurate information for subsequent processing procedures. For example, when many cores are executing instructions in parallel, a computing core generates an exception when executing a specific instruction. Through the exception identification extension, the system can immediately determine what type of exception it is, instead of performing complex troubleshooting, thereby improving the efficiency of exception detection.

[0090] S2.2. Ensure the integrity and accuracy of state saving, that is, when an exception is triggered, the x86 program state is accurately saved to the corresponding storage location of the ARM computing core. Not only general registers are saved, but also x86-specific state information, such as the flag register (FLAGS) and instruction pointer (EIP). To improve efficiency, batch save and restore operations are used, and ARM's multi-register storage and load instructions are used.

[0091] For example, when an exception occurs in an x86 program, the state of the x86 program when the exception is triggered is saved:

[0092] pushf / / Save flag register

[0093] push cs / / Save code snippet

[0094] push eip / / Save instruction pointer

[0095] When converting to ARM, the state is saved in ARM using the bulk store instruction:

[0096] stmdb sp!, {r0 - r12, lr, cpsr} / / Save multiple registers and the program status register (CPSR), including flag information

[0097] Ensure that the exception status of the x86 program is completely saved and accurately mapped to the storage location of the ARM computing core. At the same time, ARM's multi-register storage instructions are used to reduce the number of instructions for storage operations, increase the speed of state saving, and reduce the performance overhead during exception handling.

[0098] S2.3, ensure the accuracy and compatibility of state recovery, that is, after the exception handling program is executed, the stored state information is accurately restored to the ARM computing core to ensure that the program can continue to operate normally. The recovery process needs to consider the instruction execution order and register usage rules of the ARM architecture. The present invention adopts a batch recovery operation similar to state preservation to improve recovery efficiency.

[0099] For example, after the above exception handler completes, the ARM restores the state using a bulk load instruction:

[0100] ldmia sp!, {r0 - r12, lr, cpsr} / / Restore multiple registers and CPSR

[0101] By accurately restoring status information, the program can be smoothly restored from an abnormal state. At the same time, using batch loading instructions, the number of instructions required for state recovery is reduced, the recovery process is accelerated, and the recovery process is ensured to comply with the instruction execution and register operation characteristics of the ARM architecture, thereby improving system performance.

[0102] S3. Dynamic adjustment and optimization of exception handling.

[0103] S3.1. Dynamic adjustment based on runtime information, that is, when the program is running, according to the running status of the ARM many-core system and the program execution information, some aspects of the exception handler are dynamically adjusted. For example, the execution order and resource allocation of the exception handler are adjusted according to the system load, memory usage and exception frequency.

[0104] Assume that under high load, for frequently occurring exceptions, more resources are allocated to handle them first, mainly by increasing the execution priority of these exception handling functions, which can be achieved through the system call setpriority. When a large number of division error exceptions are detected, add dynamic adjustment logic to the exception handler:

[0105] divide_error_handler_arm:

[0106] stmdb sp!, {r0 - r12, lr}

[0107] ldr r0, =system_load / / Assume that system_load stores system load information

[0108] ldr r0, [r0]

[0109] cmp r0, #load_threshold / / Compare with load threshold

[0110] bgt high_load_handler / / If the threshold is exceeded, high load handling mode is adopted

[0111] bl optimized_error_handling / / Call the optimized error handling function

[0112] ldmia sp!, {r0 - r12, lr}

[0113] subs pc, lr, #4

[0114] high_load_handler:

[0115] stmdb sp!, {r13} / / Only save necessary status information, such as stack pointer

[0116] bl simplified_error_handling / / Call the simplified error handling function

[0117] ldmia sp!, {r13} / / Restore necessary status information

[0118] subs pc, lr, #4

[0119] Dynamically adjusting exception handling based on runtime information improves the adaptability and performance of the system under different loads and execution states, avoiding the performance bottleneck of static exception handling in complex situations. By using different processing logic and resource allocation under different load conditions, the flexibility and efficiency of exception handling are improved, ensuring that the system can still handle exceptions quickly under high load, while performing more detailed exception handling under low load.

[0120] S3.2, optimize the exception handling process, that is, optimize the converted exception handling program, reduce unnecessary instructions and operations, and improve the processing speed. Use ARM's conditional execution instructions and advanced instruction set features to optimize the exception handling program process.

[0121] Consider the following simple x86 exception handler:

[0122] simple_handler:

[0123] push eax

[0124] pop eax

[0125] iret

[0126] When converted and optimized to ARM:

[0127] simple_handler_arm:

[0128] cmp r0, #0 / / Assume r0 stores a condition flag

[0129] IT EQ / / Execute subsequent instructions only when r0 is 0

[0130] POPEQ {r0} / / Execute the pop operation only when the condition is met

[0131] subs pc, lr, #4

[0132] By optimizing the exception handler, the exception handling overhead is reduced and the overall system performance is improved. The conditional execution feature of ARM is used to avoid unnecessary register operations and instruction execution, improve the execution efficiency of the exception handler, and ensure the effectiveness of exception handling.

[0133] S4. Parallelization of exception handling and multi-core coordinated scheduling.

[0134] Parallel preparation for exception handling, in the ARM many-core system environment, for parallelizable exception handling tasks, identify and mark them. For example, for some exception information collection or error analysis tasks that can be processed in parallel, add a mark in the exception handler. In a many-core system, multiple computing cores execute the same code, for example, when multiple threads execute a function, the same type of exception occurs. It can be determined whether the same code is being executed by checking whether the address of the exception triggering instruction in the exception information is the same. If data access exceptions occur in multiple computing cores and the methods for handling these exceptions are the same, then the present invention parallelizes these exception processing.

[0135] Consider a complex exception handler:

[0136] complex_handler

[0137] … / / Save state

[0138] stmdb sp!, {r0 - r12, lr}

[0139] … / / Exception handling

[0140] bl analyze_error / / Assume this function can parallelize exception handling

[0141] … / / Restore state

[0142] ldmia sp!, {r0 - r12, lr}

[0143] subs pc, lr, #4

[0144] Converts to:

[0145] complex_handler_arm:

[0146] … / / Save the state scene

[0147] stmdb sp!, {r0 - r12, lr}

[0148] … / / Exception information collection part, add parallelization mark

[0149] MOV R1, #PARALLEL_FLAG_COLLECT / / Assume PARALLEL_FLAG_COLLECT is a custom parallelization flag

[0150] STR R1, [sp, #-4] / / Store flag on stack

[0151] Send the exception status to the exception handling thread for processing:

[0152] bl analyze_error_arm / / Call the converted parallelizable function

[0153] … / / Wait for the exception handling thread to complete processing and give up CPU time.

[0154] … / / Restore state

[0155] ldmia sp!, {r0 - r12, lr}

[0156] subs pc, lr, #4

[0157] By analyzing and marking the parallelism of exception handling tasks, a basis is provided for subsequent multi-core coordinated exception handling, and the parallel processing capabilities of the ARM many-core system are fully utilized to improve the efficiency of exception handling, especially for complex exception handling tasks, which can significantly reduce the processing time.

[0158] S5. When converting an x86 program to an ARM program, each instruction and exception handler that may trigger an exception is converted and stored according to the above-mentioned exception type mapping, program structure conversion, state saving and recovery, dynamic adjustment optimization, and multi-core coordination method.

[0159] S6. When an exception occurs during program execution, the corresponding exception handler is called according to the stored exception identifier and mapping table. When the exception handler is executed, the state is saved and restored. The processing method is dynamically adjusted according to the runtime information, and parallel tasks are assigned to different ARM computing cores for execution.

[0160] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An exception handling conversion optimization method for ARM multi-core dynamic instruction conversion, characterized in that: The specific steps include: Step 1, constructing an exception type mapping table for mapping x86 exception types to ARM exception types; according to the exception type mapping table, establishing a first ARM exception handler and a second ARM exception handler for the ARM exception type, wherein the execution overhead of the first ARM exception handler is less than the execution overhead of the second ARM exception handler; Step 2: When the ARM many-core system is initialized, the ARM exception vector table is initialized, memory space is allocated for the exception type mapping table and the ARM exception vector table, and the first ARM exception handler and the second ARM exception handler corresponding to the ARM exception type are stored in the corresponding ARM exception vector table according to the exception type mapping table; the executable file is loaded and executed through dynamic instruction conversion; Step 3, obtain the current instruction to be converted. If the current instruction to be converted is an exception triggering instruction under the x86 architecture, convert the current instruction to be converted into an ARM exception triggering instruction, create an exception identifier for the ARM exception triggering instruction to indicate the corresponding x86 exception type, and then execute step 4; otherwise, convert the current instruction to be converted into an ARM instruction and execute step 7; Step 4: When the ARM many-core system captures an exception, obtain the exception identifier of the current ARM exception triggering instruction, determine the current ARM exception type corresponding to the exception identifier according to the exception type mapping table, add the current ARM exception triggering instruction, the computing core where it is located, and the current ARM exception type to the dynamic execution exception list, obtain the current load of the ARM many-core system, and execute step 5 if the load is not greater than the threshold, otherwise execute step 6; Step 5: If the number of records of the current ARM exception type in the dynamic execution exception list is greater than the threshold, the computing core where the current ARM exception type in the dynamic execution exception list is located is used as the target computing core, and the first ARM exception handler is started on each target computing core to complete the exception processing, and step 7 is executed; if the number of records of the current ARM exception type in the dynamic execution exception list is not greater than the threshold, the first ARM exception handler is started in an independent thread mode to complete the exception processing, and step 7 is executed; Step 6: Start the second ARM exception handling program in an independent thread mode, complete the exception handling, and execute step 7; Step 7: If the executable file has not completed execution, execute step 3; otherwise, end this process.

2. The exception handling conversion optimization method according to claim 1, characterized in that: The exception types in the exception type mapping table include hardware exceptions, software exceptions and system exceptions.

3. The exception handling conversion optimization method according to claim 1, characterized in that: The first ARM exception handling program and the second ARM exception handling program are both preloaded into the high-speed storage area.

4. The exception handling conversion optimization method according to claim 3 is characterized in that: The high-speed storage area is a tightly coupled memory of the ARM processor.

5. The exception handling conversion optimization method according to claim 1, characterized in that: The exception flag is stored using an unused bit of ARM or a custom instruction extension field.

6. The exception handling conversion optimization method according to claim 1, characterized in that: The exception flags are stored in fast-access special registers.

7. The exception handling conversion optimization method according to claim 1, characterized in that: The processing process of the first ARM exception handler is: using ARM batch storage instructions to save the first state of the target computing core, then performing an exception handling operation, and then using ARM batch loading instructions to restore the first state to the current computing core, and finally performing an exception return operation.

8. The exception handling conversion optimization method according to claim 7, characterized in that: The exception handling operation includes outputting an error log.

9. The exception handling conversion optimization method according to claim 7, characterized in that: The first state includes the states of general registers and program status registers in the target computing core.

10. The exception handling conversion optimization method according to claim 1, characterized in that: The second ARM exception handling program is obtained by performing instruction combination optimization on the first ARM exception handling program.