Anti-jamming i2c slave module and communication system

Abstract

The application discloses an anti-interference I2C slave module and a communication system, and relates to the technical field of I2C communication.The module comprises a clock processing module, a reset processing module, a slave control module and a register read-write module, the clock processing module is used for generating a first clock signal and a first data signal according to a received serial clock signal and a serial data signal, and performing inversion on the serial clock signal and the serial data signal to generate a second clock signal and a second data signal; the reset processing module is electrically connected with the clock processing module, and the reset processing module is used for performing filtering processing on a reset signal to obtain an anti-interference reset signal; the slave control module is electrically connected with the clock processing module and the reset processing module; and the register read-write module is electrically connected with the clock processing module and the slave control module.The anti-interference I2C slave module according to the embodiment of the application can avoid the influence of online burrs on the system.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of I2C communication, and in particular to an anti-interference I2C slave module and a communication system. BACKGROUND

[0002] Information transmission of the I2C bus requires the host and the slave to reply to each other, and the interaction between the communication devices is strong, so that the on-line glitch can easily affect the transmission of the I2C. In the case of unstable power supply, the on-line glitch is easily formed, which is extremely unfavorable to the transmission of information. If the glitch on the line causes the generation of an error signal in the idle phase, incorrect data transmission may occur, and if the glitch occurs in the reset signal itself, it is more likely to completely reset the entire circuit. Moreover, the existing I2C bus does not perform certain processing on the reset signal inside the module, so that the glitch of the reset signal in the data transmission process may cause the entire circuit to be abnormally reset. SUMMARY

[0003] The present application aims to at least solve one of the technical problems existing in the prior art. To this end, the present application provides an anti-interference I2C slave module and a communication system, which can avoid the influence of the on-line glitch on the system.

[0004] In a first aspect, the anti-interference I2C slave module according to the embodiments of the present application comprises:

[0005] A clock processing module is configured to generate a first clock signal and a first data signal according to a received serial clock signal and a serial data signal, and to invert the serial clock signal and the serial data signal to generate a second clock signal and a second data signal;

[0006] A reset processing module is electrically connected to the clock processing module, and is configured to filter a reset signal according to the first clock signal, the first data signal and the second data signal to obtain an anti-interference reset signal;

[0007] A slave control module is electrically connected to the clock processing module and the reset processing module, and is configured to perform logic processing;

[0008] A register read-write module is electrically connected to the clock processing module and the slave control module, and is configured to perform read-write operation.

[0009] According to some embodiments of the present application, the clock processing module comprises a first inverter unit and a second inverter unit; the first inverter unit comprises a first branch and a second branch connected in parallel, the first branch is configured to generate the first clock signal according to the serial clock signal, and the second branch comprises a first inverter configured to invert the serial clock signal to generate the second clock signal; the second inverter unit comprises a third branch and a fourth branch connected in parallel, the third branch is configured to generate the first data signal according to the serial data signal, and the fourth branch comprises a second inverter configured to invert the serial data signal to generate the second data signal.

[0010] According to some embodiments of the present application, the reset processing module comprises:

[0011] a reset delay unit configured to perform delay filtering processing on the reset signal to generate a delayed reset signal;

[0012] a reset generation unit configured to generate an on-line start jump signal and an on-line stop jump signal according to the first clock signal, the first data signal and the second data signal, and generate the anti-interference reset signal and a jump indication signal according to the on-line start jump signal, the on-line stop jump signal and the delayed reset signal;

[0013] a restart generation unit configured to generate an on-line restart signal according to the first clock signal, the jump indication signal, the second data signal and the delayed reset signal.

[0014] According to some embodiments of the present application, the reset delay unit comprises a plurality of delay units connected in series and a plurality of first OR gates connected in series, each of the delay units corresponds to one of the first OR gates, the plurality of delay units are configured to delay the reset signal for multiple times, each of the delay units generates a corresponding delay signal, a first one of the first OR gates performs OR operation on the reset signal and the delay signal of a first one of the delay units to generate an OR operation signal, and each of the remaining first OR gates performs OR operation on the OR operation signal output by a previous one of the first OR gates and the delay signal of a corresponding one of the delay units to generate a corresponding OR operation signal, and the OR operation signal generated by a last one of the first OR gates is the delayed reset signal.

[0015] According to some embodiments of the present application, the reset delay unit comprises three delay units and three first OR gates connected in series, an input terminal of the first delay unit is electrically connected with the reset signal, an output terminal of the first delay unit outputs a first delay signal, an input terminal of the second delay unit is electrically connected with the output terminal of the first delay unit, an output terminal of the second delay unit outputs a second delay signal, an input terminal of the third delay unit is electrically connected with the output terminal of the second delay unit, an output terminal of the third delay unit outputs a third delay signal, a first input terminal of the first first OR gate is electrically connected with the reset signal, a second input terminal of the first first OR gate is electrically connected with the output terminal of the first delay unit, a first input terminal of the second first OR gate is electrically connected with the output terminal of the first first OR gate, a second input terminal of the second first OR gate is electrically connected with the output terminal of the second delay unit, a first input terminal of the third first OR gate is electrically connected with the output terminal of the second first OR gate, a second input terminal of the third first OR gate is electrically connected with the output terminal of the third delay unit, and an output terminal of the third first OR gate outputs the delay reset signal.

[0016] According to some embodiments of the present application, the reset generation unit comprises a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate, an XOR gate, a second OR gate, a third OR gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a first flip-flop and a second flip-flop.

[0017] An input terminal of the third inverter is electrically connected with the first clock signal, an output terminal of the third inverter is electrically connected with a first input terminal of the first AND gate, a second input terminal of the first AND gate is electrically connected with a first input terminal of the XOR gate, an output terminal of the first AND gate is electrically connected with a first input terminal of the second OR gate, a second input terminal of the XOR gate is electrically connected with an input terminal of the fourth inverter, an output terminal of the fourth inverter is electrically connected with a first input terminal of the second AND gate, a second input terminal of the second AND gate is electrically connected with the first clock signal, an output terminal of the second AND gate is electrically connected with a second input terminal of the second OR gate, an output terminal of the second OR gate is electrically connected with an input terminal of the first flip-flop, a reset terminal of the first flip-flop is electrically connected with the delayed reset signal, a trigger terminal of the first flip-flop is electrically connected with the second data signal, an output terminal of the first flip-flop is electrically connected with a first input terminal of the third AND gate, a second input terminal of the third AND gate is electrically connected with the first clock signal, an output terminal of the third AND gate is electrically connected with a first input terminal of the third OR gate; an input terminal of the fifth inverter is electrically connected with the first clock signal, an output terminal of the fifth inverter is electrically connected with a first input terminal of the fourth AND gate, a second input terminal of the fourth AND gate is electrically connected with a second input terminal of the XOR gate, an output terminal of the fourth AND gate is electrically connected with a second input terminal of the third OR gate, an output terminal of the third OR gate is electrically connected with an input terminal of the second flip-flop, a reset terminal of the second flip-flop is electrically connected with the delayed reset signal, a trigger terminal of the second flip-flop is electrically connected with the first data signal, an output terminal of the second flip-flop is electrically connected with a second input terminal of the XOR gate, an output terminal of the XOR gate is electrically connected with a first input terminal of the fifth AND gate, a second input terminal of the fifth AND gate is electrically connected with the delayed reset signal, an output terminal of the fifth AND gate outputs the anti-interference reset signal, and the output terminal of the XOR gate outputs the jump indication signal.

[0018] According to some embodiments of the present application, the restart generation unit comprises:

[0019] a sixth AND gate, a first input terminal of the sixth AND gate is electrically connected with the first clock signal, and a second input terminal of the sixth AND gate is electrically connected with the jump indication signal;

[0020] a third flip-flop, an input terminal of the third flip-flop is electrically connected with an output terminal of the sixth AND gate, a reset terminal of the third flip-flop is electrically connected with the delayed reset signal, a trigger terminal of the third flip-flop is electrically connected with the second data signal, and an output terminal of the third flip-flop outputs the on-line restart signal.

[0021] According to some embodiments of the present application, the slave control module comprises:

[0022] The slave state machine is electrically connected with the reset processing module;

[0023] The slave data channel selection module is electrically connected with the slave state machine and the register read-write module.

[0024] The slave address updating module is electrically connected with the slave data channel selection module.

[0025] According to some embodiments of the present application, the number of the register read-write modules is two, and the register read-write modules are used to write data into corresponding registers according to the received read command, and the register read-write modules are also used to send out the data of the corresponding registers according to the received write command.

[0026] In a second aspect, the anti-interference communication system according to the embodiments of the present application comprises the anti-interference I2C slave module according to the embodiments of the above aspect.

[0027] The anti-interference I2C slave module and the communication system according to the embodiments of the present application have at least the following beneficial effects: the reset signal is subjected to certain filtering processing by the reset processing module, the interference problem of the idle stage line error signal on the transmission is solved, and the interference problem of the glitch of the reset signal on the circuit is solved, so that the data transmission is more stable.

[0028] Additional aspects and advantages of the present application will be made apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0029] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description, taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 It is a structural schematic diagram of the anti-interference I2C slave module according to the embodiments of the present application.

[0031] Figure 2 It is a principle diagram of the clock processing module according to the embodiments of the present application.

[0032] Figure 3 It is a principle diagram of the reset delay unit according to the embodiments of the present application.

[0033] Figure 4 It is a timing diagram of the reset delay unit according to the embodiments of the present application.

[0034] Figure 5 It is a principle diagram of the reset generation unit according to the embodiments of the present application.

[0035] Figure 6 It is a timing diagram of the reset generation unit according to the embodiments of the present application.

[0036] Figure 7 A schematic diagram of a restart generation unit of an embodiment of the application;

[0037] Figure 8 A timing diagram of a restart generation unit of an embodiment of the application. DETAILED DESCRIPTION

[0038] Embodiments of the application are described in detail below with reference to the attached drawing figures, wherein the same or like reference numerals are used throughout the figures to refer to same or like elements or elements with same or similar function. The embodiments described below are merely exemplary for the purposes of explanation and are not intended to limit the application. For the purposes of the following embodiments, the numbering of steps is merely provided for ease of explanation and does not limit the order between the steps, and the order of execution of the steps in the embodiments can be adapted according to the understanding of those skilled in the art.

[0039] In the description of the present application, it is to be understood that the orientation description, such as the orientation or position relationship indicated by up, down, front, back, left, right, etc. is based on the orientation or position relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0040] The terms "first", "second", "third", and "fourth" and the like in the description and in the claims of the present application and the accompanying drawings are used to distinguish different objects, and are not intended to describe a particular sequential order. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to such processes, methods, products, or devices.

[0041] In the present application, the phrase "embodiment" means that the specific features, structures, or characteristics described in connection with the embodiment can be included in at least one embodiment of the present application. The appearance of this phrase at various places in the specification does not necessarily all refer to the same embodiment, nor is it mutually exclusive or alternative to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0042] I2C: Inter-Integrated Circuit, which is the abbreviation of internal integrated circuit, is a kind of synchronous, multi-master and slave architecture serial communication bus invented by Philips Semiconductor in 1982. It is mainly used to connect microcontrollers and their peripheral devices, and its essence is a kind of low-cost two-wire interface, including a serial clock line SCL for transmitting clock signals and a serial data line SDA for transmitting data between devices, through which message sending and receiving between devices can be realized.

[0043] The information transmission of the I2C bus needs the response of the host and the slave to each other, and the interaction between the communication devices is strong, so the on-line glitch can easily affect the transmission of the I2C. In the case of unstable power supply, the on-line glitch is easy to form, which is extremely unfavorable to the transmission of information. If the glitch on the line causes the generation of error signal in the idle stage, incorrect data transmission may occur, and if the glitch occurs in the reset signal itself, it is more likely to completely reset the entire circuit. Moreover, the existing I2C bus does not process the reset signal in the module, so the glitch of the reset signal in the data transmission process may cause the entire circuit to be abnormally reset.

[0044] Therefore, the embodiment of the present application provides an anti-interference I2C slave module and an anti-interference communication system, which solves the interference problem of the error signal on the line in the idle stage and the interference problem of the glitch of the reset signal to the circuit by filtering the reset signal through the reset processing module, so that the data transmission is more stable.

[0045] The anti-interference I2C slave module and the anti-interference communication system of the embodiment of the present application will be described in detail below with reference to the accompanying drawings. Figures 1-8 , the anti-interference I2C slave module and the anti-interference communication system of the embodiment of the present application will be described in detail below with reference to the accompanying drawings.

[0046] On the one hand, the embodiment of the present application provides an anti-interference I2C slave module, as shown in Figure 1As shown, it comprises a clock processing module 100, a reset processing module 200, a slave control module 300 and a register read-write module 400, wherein the clock processing module 100 is configured to generate a first clock signal (clk_scl) and a first data signal (clk_sda) according to a received serial clock signal (SCL_I) and a serial data signal (SDA_I), and to generate a second clock signal (clk_scl_b) and a second data signal (clk_sda_b) by inverting the serial clock signal (SCL_I) and the serial data signal (SDA_I); the reset processing module 200 is electrically connected to the clock processing module 100, and is configured to filter a reset signal (rst_n) according to the first clock signal (clk_scl), the first data signal (clk_sda) and the second data signal (clk_sda_b) to obtain an anti-interference reset signal (i2c_rst_n); the slave control module 300 is electrically connected to the clock processing module 100 and the reset processing module 200, and is configured to perform logical processing; and the register read-write module 400 is electrically connected to the clock processing module 100 and the slave control module 300, and is configured to perform read-write operations.

[0047] Specifically, the clock processing module 100 processes the SCL_I and SDA_I signals input to the I2C slave, generates corresponding signals clk_scl and clk_sda, and generates their inverted signals clk_scl_b and clk_sda_b. The reset processing module 200 generates an anti-interference reset signal (i2c_rst_n) according to the signals (clk_scl, clk_sda and clk_sda_b) output by the clock processing module 100. The generation of the anti-interference reset signal (i2c_rst_n) depends on the on-line stop jump signal (sto_st) and the on-line start jump signal (sta_st), which is equivalent to indicating the on-line busy state. The slave control module 300 performs logical processing related to the I2C protocol, including slave output data signal generation, slave address update, slave data channel selection, etc. The register read-write module 400 writes the received data into the corresponding register according to the received command code command when performing data reading, and outputs to the corresponding analog port, and sends the data of the corresponding register according to the received command code command when performing data writing.

[0048] Further, as shown in FIG. 2, the clock processing module 100 comprises a clock signal generation module 110 and an inverter module 120, wherein the clock signal generation module 110 is configured to generate the first clock signal (clk_scl) and the first data signal (clk_sda) according to the received serial clock signal (SCL_I) and the serial data signal (SDA_I), and the inverter module 120 is configured to generate the second clock signal (clk_scl_b) and the second data signal (clk_sda_b) by inverting the serial clock signal (SCL_I) and the serial data signal (SDA_I). Figure 2As shown, in some embodiments of the present application, the clock processing module 100 includes a first inverter unit and a second inverter unit; the first inverter unit includes a first branch and a second branch in parallel, the first branch is used to generate a first clock signal (clk_scl) according to a serial clock signal (SCL_I), and the second branch includes a first inverter A1 used to invert the serial clock signal (clk_scl_b) to generate a second clock signal (clk_scl_b); the second inverter unit includes a third branch and a fourth branch in parallel, the third branch is used to generate a first data signal (clk_sda) according to a serial data signal (SDA_I), and the fourth branch includes a second inverter A2 used to invert the serial data signal (SDA_I) to generate a second data signal (clk_sda_b). By inverting the serial clock signal and the serial data signal, it is convenient for the subsequent reset processing module 200 to process the reset signal.

[0049] Further, as Figure 1 As shown, in some embodiments of the present application, the reset processing module 200 includes a reset delay unit 210, a reset generation unit 220, and a restart generation unit 230, the reset delay unit 210 is used to perform delay filtering processing on the reset signal (rst_n) to generate a delay reset signal (dev_rst_n); the reset generation unit 220 is used to generate an on-line start jump signal (sta_st) and an on-line stop jump signal (sto_st) according to the first clock signal (clk_scl), the first data signal (clk_sda), and the second data signal (clk_sda_b), and generate an anti-interference reset signal (i2c_rst_n) according to the on-line start jump signal (sta_st), the on-line stop jump signal (sto_st), and the delay reset signal (dev_rst_n), and send it to the slave control module 300; the restart generation unit 230 is used to generate an on-line restart signal (i2c_sta) according to the first clock signal (clk_scl), the jump indication signal (sta_stb), the second data signal (clk_sda_b), and the delay reset signal (dev_rst_n), and send it to the slave control module 300.

[0050] Specifically, when the input reset signal (rst_n) is given to the I2C slave, the delay filtering processing is first performed by the reset delay unit 210 to generate a delay reset signal (dev_rst_n), and this filtering can only filter out the low-level glitches. By delaying the reset signal (rst_n) and then performing an or operation, the low-level glitches are filtered out. In this example, the circuit and timing of the reset delay unit 210 are as follows: Figure 3 and Figure 4As shown, this filtering process can prevent a very short reset pulse from appearing on the line, which could cause the entire circuit to reset.

[0051] Specifically, such as Figure 3 As shown, in this example, the reset delay unit 210 includes multiple delayers connected in series and multiple first OR gates connected in series. Each delayer corresponds to a first OR gate. The multiple delayers are used to delay the reset signal multiple times. Each delayer generates a corresponding delayed signal. The first first OR gate performs an OR operation on the reset signal (rst_n) and the delayed signal (rst_n_dly0) of the first delayer to generate an OR operation signal. Each of the remaining first OR gates performs an OR operation on the OR operation signal output by the previous first OR gate and the delayed signal of the corresponding delayer to generate a corresponding OR operation signal. The OR operation signal generated by the last first OR gate is the delayed reset signal (dev_rst_n).

[0052] Taking an example where both the delay unit and the first OR gate have three elements, such as... Figure 3 As shown, the three delay units are D1, D2, and D3, and the three first OR gates are U11, U12, and U13. The reset delay unit 210 includes three delay units (D1, D2, and D3) connected in series and three first OR gates (U11, U12, and U13) connected in series. The input of the first delay unit D1 is electrically connected to the reset signal (rst_n), and the output of the first delay unit D1 outputs the first delayed signal (rst_n_dly0). The input of the second delay unit D2 is electrically connected to the output of the first delay unit D1, and the output of the second delay unit D2 outputs the second delayed signal (rst_n_dly1). The input of the third delay unit D3 is electrically connected to the output of the second delay unit D2, and the output of the third delay unit D3 outputs the third delayed signal (rst_n_dly). 2) The first input of the first OR gate U11 is electrically connected to the reset signal (rst_n), and the second input of the first OR gate U11 is electrically connected to the output of the first delay unit D1. The first input of the second OR gate U12 is electrically connected to the output of the first OR gate U11, and the second input of the second OR gate U12 is electrically connected to the output of the second delay unit D2. The first input of the third OR gate U13 is electrically connected to the output of the second OR gate U12, and the second input of the third OR gate U13 is electrically connected to the output of the third delay unit D3. The output of the third OR gate U13 outputs the delayed reset signal (dev_rst_n). It should be noted that the specific number of delay units and OR gates can be adjusted according to actual needs and is not specifically limited here.

[0053] like Figure 4The timing diagram shown is the filtering process of the reset delay unit 210 on the reset signal (rst_n). It can be intuitively seen that the actual filtering process. The filtering is mainly through the delay plus or processing. The sum of the delay time (delay0, delay1, delay2) is the width of the glitch that can be filtered out, or the processing determines that it can only filter out the glitch in the low level direction. In practical application, if the reset signal is unstable due to unstable power supply, it is possible to reset the entire circuit. This filtering process can filter out glitches within a certain width, greatly avoiding this problem.

[0054] After the delay filtering process of the reset signal (rst_n) to generate the delay reset signal (dev_rst_n), the anti-interference reset signal (i2c_rst_n) needs to be generated through the reset generation unit 220, which is equivalent to the flag of the busy state online. The circuit and timing of the reset generation unit 220 are shown in Figure 5 and Figure 6 The anti-interference reset signal (i2c_rst_n) is mainly generated according to the online start jump signal (sta_st) and the online stop jump signal (sto_st) XOR, and the delay reset signal (dev_rst_n). The timing of the signal is shown in Figure 6 The signal is high between start and stop, and low between stop and start. Among them, the online start jump signal (sta_st) will change its level every time the online start is recognized, and the stop jump signal (sto_st) will change its level every time the online stop is recognized.

[0055] Specifically, as shown in Figure 5As shown, in the present example, the reset generation unit 220 comprises a first AND gate Q1, a second AND gate Q2, a third AND gate Q3, a fourth AND gate Q4, a fifth AND gate Q5, an XOR gate U2, a second OR gate U3, a third OR gate U4, a third inverter A3, a fourth inverter A4, a fifth inverter A5, a first flip-flop REG0 and a second flip-flop REG1; wherein the input terminal of the third inverter A3 is electrically connected with the first clock signal (clk_scl), the output terminal of the third inverter A3 is electrically connected with the first input terminal of the first AND gate Q1, the second input terminal of the first AND gate Q1 is electrically connected with the first input terminal of the XOR gate U2, the output terminal of the first AND gate Q1 is electrically connected with the first input terminal of the second OR gate U3, the second input terminal of the XOR gate U2 is electrically connected with the input terminal of the fourth inverter A4, the output terminal of the fourth inverter A4 is electrically connected with the first input terminal of the second AND gate Q2, the second input terminal of the second AND gate Q2 is electrically connected with the first clock signal (clk_scl), the output terminal of the second AND gate Q2 is electrically connected with the second input terminal of the second OR gate U3, the output terminal of the second OR gate U3 is electrically connected with the input terminal of the first flip-flop REG0, the reset terminal of the first flip-flop REG0 is electrically connected with the delayed reset signal (dev_rst_n), the trigger terminal of the first flip-flop REG0 is electrically connected with the first data signal (clk_sda_b), the output terminal of the first flip-flop REG0 is electrically connected with the first input terminal of the third AND gate Q3, the second input terminal of the third AND gate Q3 is electrically connected with the first clock signal (clk_scl), the output terminal of the third AND gate Q3 is electrically connected with the first input terminal of the third OR gate U4; the input terminal of the fifth inverter A5 is electrically connected with the first clock signal (clk_scl), the output terminal of the fifth inverter A5 is electrically connected with the first input terminal of the fourth AND gate Q4, the second input terminal of the fourth AND gate Q4 is electrically connected with the second input terminal of the XOR gate U2, the output terminal of the fourth AND gate Q4 is electrically connected with the second input terminal of the third OR gate U4, the output terminal of the third OR gate U4 is electrically connected with the input terminal of the second flip-flop REG1, the reset terminal of the second flip-flop REG1 is electrically connected with the delayed reset signal (dev_rst_n), the trigger terminal of the second flip-flop REG1 is electrically connected with the first data signal (clk_sda), the output terminal of the second flip-flop REG1 is electrically connected with the second input terminal of the XOR gate U2, the output terminal of the XOR gate U2 is electrically connected with the first input terminal of the fifth AND gate Q5, the second input terminal of the fifth AND gate Q5 is electrically connected with the delayed reset signal (dev_rst_n), the output terminal of the fifth AND gate Q5 outputs the anti-interference reset signal (i2c_rst_n), and the output terminal of the XOR gate U2 also outputs the jump indication signal (sta_stb).

[0056] As Figure 5As shown, regarding the generation of the online start jump signal (sta_st) and the online stop jump signal (sto_st), the present application provides a special design idea: for the generation of the online start jump signal (sta_st), the timing logic always block takes the rising edge of the inverse signal (clk_sda_b) of the data as the trigger condition, and when sta_st=1 and clk_scl=0 or sto_st=0 and clk_scl=1, sta_st is 1, otherwise it is 0; for the generation of the stop jump signal (sto_st), the timing logic always block takes the rising edge of the data signal (clk_sda) as the trigger condition, and when sta_st=1 and clk_scl=1 or sto_st=1 and clk_scl=0, sto_st is 1, otherwise it is 0. Reset processing is performed with a new anti-interference reset signal (i2c_rst_n) before each transmission is started, which can filter out the influence of all actions during the online idle stage on the transmission, and can greatly improve the anti-interference performance of the I2C slave.

[0057] At the same time, the reset processing module 200 also generates an online restart signal (i2c_sta) through the restart generation unit 230, and the circuit and timing of the restart generation unit 230 are as shown in Figure 7 and Figure 8 Specifically, the restart generation unit 230 includes a sixth AND gate Q6 and a third flip-flop REG2, the first input end of the sixth AND gate Q6 is electrically connected with the first clock signal (clk_scl), the second input end of the sixth AND gate Q6 is electrically connected with the jump indication signal (sta_stb), the input end of the third flip-flop REG2 is electrically connected with the output end of the sixth AND gate Q6, the reset end of the third flip-flop REG2 is electrically connected with the delay reset signal (dev_rst_n), the trigger end of the third flip-flop REG2 is electrically connected with the second data signal (clk_sda_b), and the output end of the third flip-flop REG2 outputs the online restart signal (i2c_sta). In the restart generation unit 230, the timing logic always block takes the rising edge of the inverse signal (clk_sda_b) of the data as the trigger condition to generate the online restart signal (i2c_sta).

[0058] Further, as shown in Figure 1 In some embodiments of the present application, the slave control module 300 includes:

[0059] The slave state machine 310 is electrically connected with the reset processing module 200;

[0060] The slave data channel selection module 320 is electrically connected with the slave state machine 310 and the register read-write module 400, respectively;

[0061] The slave address update module 330 is electrically connected to the slave data channel selection module 320.

[0062] The slave control module 300 is used to perform logic processing related to the I2C protocol, including generating slave output data signals through the slave state machine 310, updating the slave address through the slave address update module 330, and selecting the slave data channel through the slave data channel selection module 320.

[0063] Furthermore, such as Figure 1 As shown, in some embodiments of the present invention, there are two register read / write modules 400, namely register read / write module 0 and register read / write module 1. The register read / write module 400 is used to write data into the corresponding register according to the received read command and output it to the corresponding analog port. The register read / write module 400 is also used to send out the data of the corresponding register according to the received write command.

[0064] The anti-interference I2C slave module according to an embodiment of the present invention performs certain filtering processing on the reset signal through the reset processing module 200, solving the problem of interference from line error signals during idle phases and the interference from glitches in the reset signal, thus making data transmission more stable. Furthermore, the technical solution of this application does not require the use of a high-frequency clock, thereby reducing power consumption.

[0065] On the other hand, embodiments of the present invention also propose an anti-interference communication system, including the anti-interference I2C slave module described in the above-mentioned embodiments.

[0066] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. An anti-interference I2C slave module, characterized in that, The application relates to a clock processing module, a reset processing module, a slave control module, a register read-write module, a reset delay unit, a reset generation unit and a restart generation unit. The clock processing module is used for generating a first clock signal and a first data signal according to a received serial clock signal and a serial data signal, and inverting the serial clock signal and the serial data signal to generate a second clock signal and a second data signal. The reset processing module is electrically connected with the clock processing module, and is used for filtering a reset signal according to the first clock signal, the first data signal and the second data signal to obtain an anti-interference reset signal. The slave control module is electrically connected with the clock processing module and the reset processing module, and is used for logical processing. The register read-write module is electrically connected with the clock processing module and the slave control module, and is used for read-write operation. The reset processing module comprises a reset delay unit and a reset generation unit. The reset delay unit is used for delaying and filtering the reset signal to generate a delay reset signal. The reset generation unit is used for generating an on-line start jump signal and an on-line stop jump signal according to the first clock signal, the first data signal and the second data signal, and generating the anti-interference reset signal and a jump indication signal according to the on-line start jump signal, the on-line stop jump signal and the delay reset signal. The restart generation unit is used for generating an on-line restart signal according to the first clock signal, the jump indication signal, the second data signal and the delay reset signal.

2. The tamper-resistant I2C slave module of claim 1, wherein, The clock processing module comprises a first inverting unit and a second inverting unit.

3. The tamper-resistant I2C slave module of claim 1, wherein, The first inverting unit comprises a first branch and a second branch connected in parallel. The first branch is used for generating the first clock signal according to the serial clock signal. The second branch comprises a first inverter used for inverting the serial clock signal to generate the second clock signal. The second inverting unit comprises a third branch and a fourth branch connected in parallel. The third branch is used for generating the first data signal according to the serial data signal. The fourth branch comprises a second inverter used for inverting the serial data signal to generate the second data signal. The reset delay unit comprises a plurality of delay units and a plurality of first OR gates connected in series. Each delay unit generates a corresponding delay signal. The first OR gate generates an OR operation signal after performing OR operation on the reset signal and the delay signal of the first delay unit. The rest of the first OR gates are used for performing OR operation on the OR operation signal output by the previous first OR gate and the delay signal of the corresponding delay unit, and generating a corresponding OR operation signal. The OR operation signal generated by the last first OR gate is the delay reset signal.

4. The tamper-resistant I2C slave module of claim 3, wherein, The reset delay unit comprises three delay units connected in series and three first OR gates connected in series, an input terminal of the first delay unit is electrically connected with the reset signal, an output terminal of the first delay unit outputs a first delay signal, an input terminal of the second delay unit is electrically connected with the output terminal of the first delay unit, an output terminal of the second delay unit outputs a second delay signal, an input terminal of the third delay unit is electrically connected with the output terminal of the second delay unit, an output terminal of the third delay unit outputs a third delay signal, a first input terminal of the first first OR gate is electrically connected with the reset signal, a second input terminal of the first first OR gate is electrically connected with the output terminal of the first delay unit, a first input terminal of the second first OR gate is electrically connected with the output terminal of the first first OR gate, a second input terminal of the second first OR gate is electrically connected with the output terminal of the second delay unit, a first input terminal of the third first OR gate is electrically connected with the output terminal of the second first OR gate, a second input terminal of the third first OR gate is electrically connected with the output terminal of the third delay unit, and an output terminal of the third first OR gate outputs the delay reset signal.

5. The tamper-resistant I2C slave module of claim 1, wherein, The reset generation unit comprises a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate, an XOR gate, a second OR gate, a third OR gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a first flip-flop and a second flip-flop. An input terminal of the third inverter is electrically connected with the first clock signal, an output terminal of the third inverter is electrically connected with a first input terminal of the first AND gate, a second input terminal of the first AND gate is electrically connected with a first input terminal of the XOR gate, an output terminal of the first AND gate is electrically connected with a first input terminal of the second OR gate, a second input terminal of the XOR gate is electrically connected with an input terminal of the fourth inverter, an output terminal of the fourth inverter is electrically connected with a first input terminal of the second AND gate, a second input terminal of the second AND gate is electrically connected with the first clock signal, an output terminal of the second AND gate is electrically connected with a second input terminal of the second OR gate, an output terminal of the second OR gate is electrically connected with an input terminal of the first flip-flop, a reset terminal of the first flip-flop is electrically connected with the delayed reset signal, a trigger terminal of the first flip-flop is electrically connected with the first data signal, an output terminal of the first flip-flop is electrically connected with a first input terminal of the third AND gate, a second input terminal of the third AND gate is electrically connected with the first clock signal, an output terminal of the third AND gate is electrically connected with a first input terminal of the third OR gate; an input terminal of the fifth inverter is electrically connected with the first clock signal, an output terminal of the fifth inverter is electrically connected with a first input terminal of the fourth AND gate, a second input terminal of the fourth AND gate is electrically connected with a second input terminal of the XOR gate, an output terminal of the fourth AND gate is electrically connected with a second input terminal of the third OR gate, an output terminal of the third OR gate is electrically connected with an input terminal of the second flip-flop, a reset terminal of the second flip-flop is electrically connected with the delayed reset signal, a trigger terminal of the second flip-flop is electrically connected with the first data signal, an output terminal of the second flip-flop is electrically connected with a second input terminal of the XOR gate, an output terminal of the XOR gate is electrically connected with a first input terminal of the fifth AND gate, a second input terminal of the fifth AND gate is electrically connected with the delayed reset signal, an output terminal of the fifth AND gate outputs the anti-interference reset signal, and the output terminal of the XOR gate outputs the jump indication signal.

6. The tamper-resistant I2C slave module of claim 5, wherein, The restart generation unit comprises: a sixth AND gate, a first input terminal of the sixth AND gate is electrically connected with the first clock signal, and a second input terminal of the sixth AND gate is electrically connected with the jump indication signal; a third flip-flop, an input terminal of the third flip-flop is electrically connected with an output terminal of the sixth AND gate, a reset terminal of the third flip-flop is electrically connected with the delayed reset signal, a trigger terminal of the third flip-flop is electrically connected with the second data signal, and an output terminal of the third flip-flop outputs the on-line restart signal.

7. The tamper-resistant I2C slave module of claim 1, wherein, The slave control module comprises: a slave state machine, electrically connected with the reset processing module; a slave data channel selection module, respectively electrically connected with the slave state machine and the register read-write module; a slave address updating module, electrically connected with the slave data channel selection module.

8. The tamper-resistant I2C slave module of claim 1, wherein, The number of the register read-write modules is two, the register read-write module is used for writing data into the corresponding register according to the received read command, and the register read-write module is also used for issuing the data of the corresponding register according to the received write command.

9. An interference-resistant communication system, characterized by An anti-interference I2C slave module as claimed in any of claims 1-8.

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