Display substrate and display device

Abstract

The present invention provides a display substrate and a display device. The display substrate comprises: a base substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of first power lines, a plurality of pads, a first power bus, and a second power bus. The orthographic projection of the second power bus on the base substrate at least partially overlaps with the orthographic projection of the first power bus on the base substrate. The technical solution of the present invention helps improve display effects and the reliability of the display substrate.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] The OLED (Organic Light-Emitting Diode) display device itself requires an EL (Electroluminescent) device to emit light, and the required light-emitting current needs to be provided by a DTFT (Drive Thin Film Transistor). Therefore, in order to improve the uniformity of the product's light emission, it is necessary to ensure the consistency of the light-emitting characteristics of the light-emitting device. In the related art, the consistency of the light-emitting characteristics of the light-emitting device is usually ensured by external compensation. In order to achieve compensation for the light-emitting characteristics of the light-emitting device, the display device needs to be tested. When designing the detection signal, since some signals require a large amount of current, the test traces usually need to be wide enough to ensure current transmission. However, when such test traces are connected to the display substrate, they will occupy a large trace area, which may have an adverse effect on the product appearance of the display device. At the same time, the residual traces will leave water vapor channels, which may affect the long-term reliability of the product. Summary of the Invention

[0003] Embodiments of the present invention provide a display substrate and a display device to solve the problem that a test line of an existing display device may affect the appearance of the product and the long-term reliability of the product.

[0004] To solve the above problems, the present invention is achieved as follows:

[0005] In a first aspect, an embodiment of the present invention provides a display substrate, comprising:

[0006] A base substrate, comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a binding area;

[0007] a plurality of sub-pixels located on one side of the base substrate and in the display area, at least one of the plurality of sub-pixels comprising a light-emitting element, the light-emitting element comprising a first electrode, a light-emitting layer, and a second electrode sequentially located away from the base substrate;

[0008] a plurality of data lines located in the display area and extending to the binding area, the plurality of data lines being electrically connected to the plurality of sub-pixels and configured to transmit data signals to the plurality of sub-pixels;

[0009] a plurality of first power lines located in the display area and electrically connected to the plurality of sub-pixels, the plurality of first power lines being configured to transmit first voltage signals to the plurality of sub-pixels;

[0010] a plurality of groups of pads, located in the binding area and arranged sequentially along a first direction, each group of the plurality of pads comprising a plurality of pads arranged along the first direction, the plurality of data lines being electrically connected to the plurality of groups of pads;

[0011] a first power bus located in the binding area and extending along the first direction, the first power bus being electrically connected to the plurality of first power lines;

[0012] A second power bus is located in the binding area and extends along the first direction. The second power bus is electrically connected to the second electrode, and an orthographic projection of the second power bus on the base substrate at least partially overlaps with an orthographic projection of the first power bus on the base substrate.

[0013] In some embodiments, the orthographic projection of the second power bus on the substrate covers the orthographic projection of the first power bus on the substrate.

[0014] In some embodiments, the display substrate further includes at least one second power sub-line located in the binding area, the at least one second power sub-line is located on a side of the second power bus close to the base substrate, and the orthographic projection of the second power bus on the base substrate overlaps and is electrically connected to the orthographic projection of the at least one second power sub-line on the base substrate.

[0015] In some embodiments, the at least one second power sub-line includes a second power sub-line main body and two second power sub-line pin portions located on a side of the second power sub-line main body away from the display area, one end of each of the two second power sub-line pin portions is electrically connected to the second power sub-line main body, and the other end of each of the two second power sub-line pin portions is respectively connected to some of the pads in adjacent groups of pads among the multiple groups of pads.

[0016] In some embodiments, the display substrate further includes a third power bus located in the peripheral area and partially surrounding the display area, the third power bus including two third power bus pin portions located in the binding area, the two third power bus pin portions being respectively connected to some of the pads in two groups of pads among the multiple groups of pads close to the edge of the display substrate.

[0017] In some embodiments, the present invention further includes at least two first power sub-lines and at least two first power sub-line pin portions located in the binding area, one end of each of the at least two first power sub-lines is electrically connected to the first power bus, and the other end of each of the at least two first power sub-lines is respectively connected to some of the pads in the adjacent groups of pads in the multiple groups of pads, and the at least one second power sub-line is located between two adjacent first power sub-lines.

[0018] In some embodiments, a plurality of second power lines are further included, which are located in the display area and are electrically connected to the second power bus and a third power bus located in the peripheral area away from the binding area.

[0019] In a second aspect, the present application provides a display device comprising the display substrate described in any one of the first aspects.

[0020] In a third aspect, an embodiment of the present application provides a display substrate, comprising:

[0021] A base substrate, comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a binding area;

[0022] a plurality of sub-pixels located on one side of the substrate and in the display area, at least one of the plurality of sub-pixels comprising a light-emitting element, the light-emitting element comprising a first electrode, a light-emitting layer, and a second electrode sequentially disposed away from the substrate;

[0023] a plurality of first power lines, located in the display area and electrically connected to the plurality of sub-pixels;

[0024] at least one group of pads, located in the bonding area, including at least one first pad and at least one second pad;

[0025] a first power bus located in the binding area and between the display area and the at least one group of pads, the first power bus extending along a first direction and electrically connected to the plurality of first power lines;

[0026] at least one first power sub-line and at least one first power sub-line pin portion, wherein one end of the at least one first power sub-line is connected to the first power bus, the other end of the at least one first power sub-line is connected to the at least one first power sub-line pin portion, and the at least one first power sub-line pin portion is connected to the first pad;

[0027] at least one second power sub-line located in the binding area, the at least one second power sub-line comprising a second power sub-line main portion and at least one second power sub-line pin located on a side of the second power sub-line main portion away from the display area, one end of the at least one second power sub-line pin electrically connected to the second power sub-line main portion, the other end of the at least one second power sub-line pin electrically connected to the second pad, and the second power sub-line main portion electrically connected to the second electrode;

[0028] a plurality of test signal lines, located on a side of the at least one group of pads away from the display area;

[0029] a plurality of test circuit pads, located on a side of the plurality of test signal lines away from the display area, including a first test pad and a second test pad;

[0030] A plurality of test signal connection lines are connected to the plurality of test signal lines and the plurality of test circuit pads, wherein the first test pad and the second test pad meet at least one of the following conditions:

[0031] The first test pad is configured to transmit a first test voltage signal to the plurality of first power lines through the first pad;

[0032] The second test pad is configured to transmit a second test voltage signal to the second electrode through the second pad.

[0033] In some embodiments, the first test pad and the second test pad are configured to provide a first voltage signal and a second voltage signal to the plurality of sub-pixels through the first pad and the second pad, respectively, during a test phase, and the first voltage signal is greater than the second voltage signal.

[0034] In some embodiments, the device further comprises at least one adapter unit, wherein an orthographic projection of the adapter unit on the substrate overlaps with an orthographic projection of the plurality of test signal lines on the substrate, and the data line is electrically connected to the adapter unit;

[0035] The plurality of test circuit pads further include a third test pad for transmitting a gate driving signal, wherein the third test pad is configured to be connected to a gate driving circuit located in the peripheral area through a gate driving signal line.

[0036] In some embodiments, the plurality of test signal connection lines include a power test signal connection line, the power test signal connection line includes a first power test signal connection line, and the first power test signal connection line includes a first power test signal connection sub-line and a second power test signal connection sub-line connected in sequence;

[0037] A first end of the first power test signal connection sub-line is connected to the first test pad, a second end of the first power test signal connection sub-line is connected to the first end of the second power test signal connection sub-line, and a second end of the second power test signal connection sub-line is connected to the first pad;

[0038] The orthographic projection of the first power test signal connecting sub-line on the substrate does not overlap with the multiple test signal lines, and the orthographic projection of the second power test signal connecting sub-line on the substrate overlaps with the multiple test signal lines.

[0039] In some embodiments, the first power test signal connection sub-line is in the same layer and made of the same material as the first electrode layer, and the second power test signal connection sub-line is in the same layer and made of the same material as the data line.

[0040] In some embodiments, the binding area is also provided with a third pad, the third pad is electrically connected to the gate drive circuit of the display substrate, the multiple power test signal connection lines include a second power test signal connection line, the third test pad is electrically connected to the third pad through the second test signal line connection line, and the second test signal line connection line is in the same layer and the same material as the first electrode.

[0041] In the technical solution of this embodiment, by arranging the position of the first power bus to overlap with the second power bus, space at the bottom of the display substrate is saved, thereby reducing the width of the non-display area of ​​the display substrate, helping to reduce the border of the display substrate and improve the display effect. At the same time, the position of the first electrode can be controlled to shrink toward the display area, thereby helping to reduce the IR Drop of the second voltage signal, and also reducing the risk of scratching the display substrate, which helps to improve the reliability of the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in describing the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0043] Figure 1 yes Figure 2 Schematic diagram of the A-A' structure of a neutron pixel;

[0044] Figure 2 is a schematic structural diagram of a display substrate in one embodiment of the present invention;

[0045] Figure 3 is a schematic structural diagram of a display substrate in another embodiment of the present invention;

[0046] Figure 4 is a schematic structural diagram of a display substrate in another embodiment of the present invention;

[0047] Figure 5 is a schematic structural diagram of a display substrate in another embodiment of the present invention;

[0048] Figure 6 is a schematic structural diagram of a pixel driving circuit in one embodiment of the present invention;

[0049] Figure 7 is a schematic structural diagram of a longitudinal connecting line in one embodiment of the present invention;

[0050] Figure 8 is a schematic structural diagram of longitudinal connecting lines and vias in one embodiment of the present invention;

[0051] Figure 9 is a schematic structural diagram of a test signal line in one embodiment of the present invention;

[0052] Figure 10 is a schematic diagram of the stacking of vertical connection lines and test signal lines in one embodiment of the present invention;

[0053] Figure 11 is a schematic structural diagram of a first via hole in one embodiment of the present invention;

[0054] Figure 12 This is a schematic structural diagram showing a first via hole formed on a display substrate in one embodiment of the present invention;

[0055] Figure 13 is a schematic structural diagram of the first electrode layer in one embodiment of the present invention;

[0056] Figure 14 FIG. 1 is a schematic diagram of a stack of display substrates including a first electrode according to an embodiment of the present invention. DETAILED DESCRIPTION

[0057] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0058] The terms "first", "second" etc. in the embodiments of the present invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or equipment comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or that are inherent to these processes, methods, products or equipment. In addition, "and / or" is used in this application to represent at least one of the connected objects, for example A and / or B and / or C, which means comprising 7 situations including single A, single B, single C, and both A and B exist, both B and C exist, both A and C exist, and both A, B and C exist.

[0059] An embodiment of the present invention provides a display substrate.

[0060] like Figure 1 As shown, in one embodiment, the display substrate includes a base substrate 101 , a driving circuit layer 11 formed on the base substrate 101 , and a plurality of light emitting elements 12 formed on the driving circuit layer 11 away from the base substrate 101 .

[0061] See also Figure 1 , Figure 1 Figure 1 shows a partial structure of a light-emitting element 12 and a corresponding pixel driving circuit 13 for a sub-pixel. Generally speaking, the driving circuit layer 11 includes a light-shielding layer (SHL) 102, a first insulating layer 103, an ACT (active layer) 104, a gate insulating layer (GI) 105, a gate metal layer (Gate) 106, a dielectric layer (ILD) 107, a source / drain electrode layer (SD) 108, a passivation layer (PVX) 109, and a planarization layer 110, which are sequentially formed on a base substrate 101.

[0062] The display substrate also includes a pixel definition layer (PDL) 111 for defining the light-emitting area of ​​each sub-pixel. The light-emitting element 12 includes a first electrode 111, a light-emitting layer 112, and a second electrode 113. The first electrode 111 generally serves as the anode of the light-emitting element, and the second electrode 113 is generally a surface electrode, which generally serves as the cathode of the light-emitting element.

[0063] like Figure 2 and Figure 3As shown, in some embodiments, the base substrate 101 includes a display area 10 (AA area) and a peripheral area 20 surrounding the display area 10. The peripheral area 20 includes a bonding area 21. The bonding area 21 can be used to bind with other structures to achieve signal transmission. Exemplarily, the bonding area 21 can be used to bind with structures including but not limited to COF (Chip On Flex or Chip On Film) to achieve signal transmission. Exemplarily, bonding can be achieved through multiple groups of pads 205 in the bonding area 21 and a flexible circuit board.

[0064] Please continue reading Figures 2 to 5 In this embodiment, the display substrate includes a plurality of sub-pixels 201, which are located on one side of the base substrate 101 and in the display area 10. At least one of the plurality of sub-pixels 201 includes a driving circuit 13 and a light-emitting element 12. Figure 1 It can be understood as Figure 2 Cross-sectional view of the neutron pixel along the AA' direction, Figure 1 The film structure in the middle driving circuit layer 11 forms the pixel driving circuit 13 of the sub-pixel 201 , and the light emitting element 12 formed on the side of the driving circuit layer 11 away from the base substrate 101 serves as the light emitting element 12 of the sub-pixel 201 .

[0065] like Figure 6 As shown, in an exemplary embodiment, the light-emitting element 12 can be an OLED (organic light-emitting diode), and the pixel driving circuit 13 of the sub-pixel 201 can be, but is not limited to, 3T1C, that is, it includes three thin-film transistors and one storage capacitor. The pixel driving circuit 13 includes two switching transistors T2 and T3, a driving transistor T1, a storage capacitor Cst, and a light-emitting element OLED. The first electrode of the transistor T2 is connected to the data line Data, and the second electrode is connected to the gate of the transistor T1 and the first plate of the storage capacitor Cst. The gate of the transistor T2 is connected to the first scan signal line Scan1. The first electrode of the driving transistor T1 is connected to the first power line (VDD) 203, and the second electrode is connected to the second plate of the storage capacitor Cst, the anode of the light-emitting element, and the second electrode of the transistor T3. The first electrode of the driving transistor T3 is connected to the sense signal line 215, and the gate of the transistor T3 is connected to the second scan line Scan2.

[0066] The cathode of the light emitting element OLED is connected to the second power bus (VSS) 207. The voltage of the first power line 203 is higher than the voltage of the second power bus 207. For example, the voltage of the first power line 203 is a positive voltage, and the voltage of the second power bus 207 is a negative voltage.

[0067] like Figure 2 and Figure 3As shown, the display substrate further includes a plurality of data lines 202 , a plurality of first power lines 203 , a plurality of pads 205 , a first power bus 206 and a second power bus 207 .

[0068] A plurality of data lines 202 of the display substrate are located in the display area 10 and extend to the binding area 21 . The plurality of data lines 202 are electrically connected to the plurality of sub-pixels 201 and are configured to transmit data signals to the plurality of sub-pixels 201 .

[0069] The first power line 203 is located in the display area 10 and extends to the binding area 21 to be connected to the first power bus 206. The first power line 203 is electrically connected to the multiple sub-pixels 201. The first power line 203 is configured to transmit a first voltage signal to the multiple sub-pixels 201. In some embodiments, the first voltage signal can be a VDD signal, for example, a positive voltage signal.

[0070] The plurality of pads 205 are arranged in the binding area 21 in sequence along the first direction. In this embodiment, the first direction refers to Figures 2 to 5 In the transverse direction shown, that is, the X direction in the figure, each group of pads 205 in the plurality of pad groups 205 includes a plurality of pads arranged along a first direction, and the plurality of data lines 202 are electrically connected to the plurality of pad groups 205 .

[0071] like Figure 2 As shown, the first power bus 206 is located in the binding area 21 and extends along a first direction. The first power bus 206 is electrically connected to the plurality of first power lines 203 to provide a first voltage signal to each first power line 203 .

[0072] The second power bus 207 is located in the binding area 21 and extends along the first direction. The second power bus 207 is electrically connected to the second electrode (cathode). The second power bus 207 is used to provide a second voltage signal to the second electrode. In some embodiments, the second voltage signal can be a VSS signal, such as a negative voltage signal.

[0073] like Figure 2 As shown, the orthographic projection of the second power bus 207 on the base substrate 101 at least partially overlaps with the orthographic projection of the first power bus 206 on the base substrate 101 .

[0074] In the technical solution of this embodiment, by arranging the position of the first power bus 206 to overlap with the second power bus 207, the space at the bottom of the display substrate is saved, thereby reducing the width of the display substrate binding area 21, helping to reduce the border of the display substrate and improve the display effect. At the same time, the position of the first electrode can be controlled to shrink toward the display area 10, thereby helping to reduce the IR Drop of the second voltage signal, and also reducing the risk of scratching the display substrate, which helps to improve the reliability of the display substrate.

[0075] In some of these instances, such as Figure 2 As shown, the orthographic projection of the second power bus 207 on the base substrate 101 covers the orthographic projection of the first power bus 206 on the substrate. In this way, the width of the peripheral area 20 (binding area 21) at the bottom of the display area 10 can be further saved, the space of the display substrate can be fully utilized, and the IR Drop of the second voltage signal can be further reduced, which helps to improve the reliability of the display substrate.

[0076] like Figure 2 and Figure 3 As shown, in some embodiments, the display substrate further includes at least one second power sub-line 209 located in the binding area 21, the second power sub-line 209 is used to provide a second voltage signal to the second power bus 207, and the at least one second power sub-line 209 is located on a side of the second power bus 207 close to the base substrate 101, and the orthographic projection of the second power bus 207 on the base substrate 101 overlaps and is electrically connected to the orthographic projection of the at least one second power sub-line 209 on the base substrate 101.

[0077] In some embodiments, at least one second power sub-line 209 includes a second power sub-line main body 2091 and two second power sub-line pin portions 2092 located on the side of the second power sub-line main body 2091 away from the display area 10, one end of each of the two second power sub-line pin portions 2092 is electrically connected to the second power sub-line main body 2091, and the other end of each of the two second power sub-line pin portions 2092 is respectively connected to some of the pads in adjacent groups of pads in the multiple groups of pads 205.

[0078] Please continue reading Figure 2 and Figure 3 In some embodiments, the display substrate further includes a third power bus 210 located in the peripheral area 20 and partially surrounding the display area 10. The third power bus 210 includes two third power bus pins 2101 located in the bonding area 21. The two third power bus pins 2101 are respectively connected to third power bus pads 2053 in two groups of pads 205 near the edge of the display substrate among the multiple groups of pads 205. The third power bus 210 is used to transmit a second voltage signal.

[0079] like Figure 2 and Figure 3As shown, in some embodiments, at least two first power sub-lines 208 and at least two first power sub-line pin portions 2081 are further included in the binding area 21, one end of each of the at least two first power sub-lines 208 is electrically connected to the first power bus 206, and the other end of each of the at least two first power sub-lines 208 is respectively connected to part of the pads in adjacent groups of pads 205 in the multiple groups of pads 205, and at least one second power sub-line 209 is located between two adjacent first power sub-lines 208.

[0080] In some embodiments, a plurality of second power lines 204 are further included, located in the display area 10 and extending to the peripheral area 20 , and the second power lines 204 are electrically connected to the second power bus 207 and a third power bus located in the peripheral area 20 away from the binding area 21 .

[0081] The present application also provides a display device, comprising the display substrate according to any one of the first aspects.

[0082] Since the display device of this embodiment includes all the technical solutions of the above-mentioned display substrate embodiment, it can at least achieve all the above-mentioned technical effects, which will not be described in detail here.

[0083] An embodiment of the present application provides a display substrate.

[0084] like Figure 4 and Figure 5 As shown, in one embodiment, the display substrate includes:

[0085] The base substrate 101 includes a display area 10 and a peripheral area 20 surrounding the display area 10 . The peripheral area 20 includes a binding area 21 .

[0086] Multiple sub-pixels 201 are located on one side of the base substrate 101 and in the display area 10. At least one sub-pixel 201 among the multiple sub-pixels 201 includes a light-emitting element, which includes a first electrode, a light-emitting layer and a second electrode arranged in sequence away from the side of the substrate.

[0087] A plurality of first power lines 203 are located in the display area 10 and electrically connected to the plurality of sub-pixels 201 .

[0088] At least one group of pads 205 is located in the bonding area 21 and includes at least one first pad 2051 and at least one second pad 2052 .

[0089] The first power bus 206 is located in the binding area 21 and between the display area 10 and at least one group of pads. The first power bus 206 extends along a first direction and is electrically connected to the plurality of first power lines 203 .

[0090] At least one first power sub-line 208 and at least one first power sub-line pin portion 2081, one end of at least one first power sub-line 208 is connected to the first power bus 206, the other end of at least one first power sub-line 208 is connected to at least one first power sub-line pin portion 2081, and at least one first power sub-line pin portion 2081 is connected to the first solder pad 2051.

[0091] At least one second power sub-line 209 is located in the binding area 21. At least one second power sub-line 209 includes a second power sub-line main body 2091 and at least one second power sub-line pin portion 2092 located on the side of the second power sub-line main body 2091 away from the display area 10. One end of the at least one second power sub-line pin portion 2092 is electrically connected to the second power sub-line main body 2091, and the other end of the at least one second power sub-line pin portion 2092 is connected to the second solder pad 2052. The main body of the second power sub-line 209 is electrically connected to the second power bus 207, and the second power bus 207 and the third power bus 210 are electrically connected to the second electrode (cathode).

[0092] It should be understood that the orthographic projection of the first solder pad 2051 on the base substrate 101 and the orthographic projection of the first power sub-line pin portion 2081 on the base substrate 101 overlap, and the orthographic projection of the second solder pad 2052 on the base substrate 101 and the orthographic projection of the second power sub-line pin portion 2092 on the base substrate 101 overlap.

[0093] The plurality of test signal lines 211 are located on a side of at least one group of pads 205 away from the display area 10 .

[0094] The test signal line 211 is used to provide a test signal to the display substrate during a test process after the display substrate is manufactured.

[0095] It should be understood that after the display substrate is manufactured, for example, after the sub-pixels are manufactured, an external test signal is required to test whether the sub-pixels of the display substrate can work normally, for example, whether the sub-pixels can light up, or whether there is a short circuit or open circuit in the display substrate. Figure 4 and Figure 5 The display substrate shown is the display substrate that needs to be tested after it is manufactured. After the test is completed, the test circuit part needs to be cut off, that is, the test circuit part needs to be cut off. Figure 4 and Figure 5 The portion below the binding area 21 in the state shown, thus, is obtained Figure 2 and Figure 3 The embodiment shown can be normally applied to a display substrate on a display device.

[0096] The plurality of test circuit pads 212 are located on a side of the plurality of test signal lines 211 away from the display area 10 , and include a first test pad 2121 and a second test pad 2122 .

[0097] The plurality of test signal connection lines 213 connect the plurality of test signal lines 211 and the plurality of test circuit pads 212 , wherein the first test pad 2121 and the second test pad 2122 meet at least one of the following conditions:

[0098] The first test pad 2121 is configured to transmit a first test voltage signal to the plurality of first power lines 203 through the first pad 2051 ;

[0099] The second test pad 2122 is configured to transmit a second test voltage signal to the second electrode through the second pad 2052 .

[0100] In some embodiments, the first test pad 2121 and the second test pad 2122 are configured to provide a first voltage signal and a second voltage signal to the plurality of sub-pixels 201 through the first pad 2051 and the second pad 2052 respectively during the test phase, and the first voltage signal is greater than the second voltage signal.

[0101] Some embodiments further include at least one adapter unit 214 , the orthographic projection of the adapter unit 214 on the base substrate 101 overlaps with the orthographic projections of the plurality of test signal lines 211 on the base substrate 101 , and the data line 202 is electrically connected to the adapter unit 214 .

[0102] Please also see Figure 1 and Figure 7 The transfer unit 214 includes a plurality of longitudinal connection lines 2141 of the same layer and material as the gate metal layer 106 of the display substrate. The longitudinal connection lines 2141 are used to connect the data lines 202 and the sense signal lines 215 of the display area 10. Figure 8 As shown, after the longitudinal connecting lines 2141 are manufactured, the dielectric layer 107 needs to be manufactured, and a first via hole 2142 is opened in the corresponding connecting portion 21411 .

[0103] Please also see Figure 4 、 Figure 5 、 Figure 9 and Figure 10Next, test signal lines 211 are fabricated. In one embodiment, the test signal lines 211 include a first test signal line 2111 for transmitting a data signal for a white sub-pixel (W), a second test signal line 2112 for transmitting a data signal for a red sub-pixel (R), a third test signal line 2113 for transmitting a detection signal (Sense), a fourth test signal line 2114 for transmitting a data signal for a blue sub-pixel (B), and a fifth test signal line 2115 for transmitting a data signal for a green sub-pixel (G). Please also refer to Figure 1 The test signal line 211 is in the same layer and made of the same material as the source / drain electrode layer 108 of the display substrate.

[0104] like Figure 11 As shown, after the test signal line 211 is made, a passivation layer 109 is further made as an insulating layer. After the passivation layer 109 is made, a second via hole 2143 is further opened on the passivation layer 109. After the second via hole 2143 is opened, please refer to Figure 1 、 Figure 12 and Figure 13 Next, the first electrode layer 2144 of the display substrate is manufactured. The first electrode layer 2144 is used to form the first electrode 111 of the light-emitting unit 12. In this way, the manufacturing of the adapter unit 214 is completed at the same time as the display substrate is manufactured.

[0105] The test circuit pads 212 also include a third test pad 2123 for transmitting a gate drive signal. The third test pad 2123 is configured to be connected to the gate drive circuit GOA located in the peripheral area via a gate drive signal line. Exemplarily, the third test pad 2123 can be used to connect to a clock signal line of the GOA, so that when testing whether the display substrate has a short circuit or a short circuit fault, an external device can be connected to the circuit pad 212 through a probe test to provide a test signal to the third test pad 2123.

[0106] In some embodiments, the pads in each group of pads 205 are electrically connected to corresponding test pads via corresponding test signal lines 211 and test signal connection lines 213 .

[0107] In some embodiments, the test signal connection line 213 further includes a power test signal connection line, the power test signal connection line includes a first power test signal connection line, and the first power test signal connection line includes a first power test signal connection sub-line 21311 and a second power test signal connection sub-line 21312 connected in sequence;

[0108] The first end of the first power test signal connection sub-line 21311 is connected to the first test pad 2121, the second end of the first power test signal connection sub-line 21311 is connected to the first end of the second power test signal connection sub-line 21312, and the second end of the second power test signal connection sub-line 21312 is connected to the first pad 2051.

[0109] The orthographic projection of the first power test signal connecting sub-line 21311 on the base substrate 101 does not overlap with the test signal line 211 , and the orthographic projection of the second power test signal connecting sub-line 21312 on the base substrate 101 overlaps with the test signal line 211 .

[0110] In some of these embodiments, please also refer to Figure 1 The first power test signal connection sub-line 21311 is in the same layer and material as the first electrode layer 2144 , that is, in the same layer and material as the first electrode 111 of the light-emitting unit 12 , and the second power test signal connection sub-line 21312 is in the same layer and material as the data line 202 .

[0111] In this way, by providing the first power supply test signal connection sub-line 21311 and the second power supply test signal connection sub-line 21312 , it is possible to implement the first power supply test signal connection line being connected across the test signal line 211 .

[0112] In some embodiments, the binding area is also provided with a third pad 2054, the third pad 2054 is electrically connected to the gate drive circuit GOA of the display substrate, the power test signal connection line includes a second power test signal connection line 21231, the test circuit pad 212 includes a third test pad 2123, the third test pad 2123 is used to provide a GOA test signal, the third test pad 2123 is electrically connected to the third pad 2054 through the second test signal line connection line 21231, and the second test signal line connection line 21231 is in the same layer and the same material as the first electrode 111.

[0113] The above is a preferred implementation of the embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A display substrate, comprising: A base substrate, comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a binding area; a plurality of sub-pixels located on one side of the base substrate and in the display area, at least one of the plurality of sub-pixels comprising a light-emitting element, the light-emitting element comprising a first electrode, a light-emitting layer, and a second electrode sequentially located away from the base substrate; a plurality of data lines located in the display area and extending to the binding area, the plurality of data lines being electrically connected to the plurality of sub-pixels and configured to transmit data signals to the plurality of sub-pixels; a plurality of first power lines located in the display area and electrically connected to the plurality of sub-pixels, the plurality of first power lines being configured to transmit a first voltage signal to the plurality of sub-pixels; a plurality of groups of pads, located in the binding area and arranged sequentially along a first direction, each group of the plurality of pads comprising a plurality of pads arranged along the first direction, the plurality of data lines being electrically connected to the plurality of groups of pads; a first power bus located in the binding area and extending along the first direction, the first power bus being electrically connected to the plurality of first power lines; A second power bus is located in the binding area and extends along the first direction. The second power bus is electrically connected to the second electrode, and an orthographic projection of the second power bus on the base substrate at least partially overlaps with an orthographic projection of the first power bus on the base substrate.

2. The display substrate according to claim 1, wherein The orthographic projection of the second power bus on the substrate covers the orthographic projection of the first power bus on the substrate.

3. The display substrate according to claim 1, wherein The display substrate also includes at least one second power sub-line located in the binding area, the at least one second power sub-line is located on a side of the second power bus close to the base substrate, and the orthographic projection of the second power bus on the base substrate overlaps and is electrically connected to the orthographic projection of the at least one second power sub-line on the base substrate.

4. The display substrate according to claim 3, wherein: The at least one second power sub-line includes a second power sub-line main body and two second power sub-line pin portions located on a side of the second power sub-line main body away from the display area, one end of each of the two second power sub-line pin portions is electrically connected to the second power sub-line main body, and the other end of each of the two second power sub-line pin portions is respectively connected to some of the pads in adjacent groups of pads among the multiple groups of pads.

5. The display substrate according to any one of claims 1 to 4, wherein: The display substrate also includes a third power bus located in the peripheral area and partially surrounding the display area, the third power bus includes two third power bus pin portions located in the binding area, and the two third power bus pin portions are respectively connected to some of the pads in two groups of pads in the multiple groups of pads close to the edge of the display substrate.

6. The display substrate according to claim 5, wherein: It also includes at least two first power sub-lines and at least two first power sub-line pin portions located in the binding area, one end of each of the at least two first power sub-lines is electrically connected to the first power bus, and the other end of each of the at least two first power sub-lines is respectively connected to some of the pads in adjacent groups of pads in the multiple groups of pads, and the at least one second power sub-line is located between two adjacent first power sub-lines.

7. The display substrate according to claim 5, wherein: The device further comprises a plurality of second power lines, which are located in the display area and are electrically connected to the second power bus and a third power bus located in the peripheral area away from the binding area.

8. A display device, characterized in that: A display substrate comprising the display substrate according to any one of claims 1 to 7.

9. A display substrate, comprising: A base substrate, comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a binding area; a plurality of sub-pixels located on one side of the substrate and in the display area, at least one of the plurality of sub-pixels comprising a light-emitting element, the light-emitting element comprising a first electrode, a light-emitting layer, and a second electrode sequentially disposed away from the substrate; a plurality of first power lines, located in the display area and electrically connected to the plurality of sub-pixels; at least one group of pads, located in the bonding area, including at least one first pad and at least one second pad; a first power bus located in the binding area and between the display area and the at least one group of pads, the first power bus extending along a first direction and electrically connected to the plurality of first power lines; at least one first power sub-line and at least one first power sub-line pin portion, wherein one end of the at least one first power sub-line is connected to the first power bus, the other end of the at least one first power sub-line is connected to the at least one first power sub-line pin portion, and the at least one first power sub-line pin portion is connected to the first pad; at least one second power sub-line located in the binding area, the at least one second power sub-line comprising a second power sub-line main portion and at least one second power sub-line pin located on a side of the second power sub-line main portion away from the display area, one end of the at least one second power sub-line pin electrically connected to the second power sub-line main portion, the other end of the at least one second power sub-line pin electrically connected to the second pad, and the second power sub-line main portion electrically connected to the second electrode; a plurality of test signal lines, located on a side of the at least one group of pads away from the display area; a plurality of test circuit pads, located on a side of the plurality of test signal lines away from the display area, including a first test pad and a second test pad; A plurality of test signal connection lines are connected to the plurality of test signal lines and the plurality of test circuit pads, wherein the first test pad and the second test pad meet at least one of the following conditions: The first test pad is configured to transmit a first test voltage signal to the plurality of first power lines through the first pad; The second test pad is configured to transmit a second test voltage signal to the second electrode through the second pad.

10. The display substrate according to claim 9, wherein The first test pad and the second test pad are configured to provide a first voltage signal and a second voltage signal to the plurality of sub-pixels through the first pad and the second pad, respectively, during a test phase, and the first voltage signal is greater than the second voltage signal.

11. The display substrate according to claim 9, wherein The device further comprises at least one adapter unit, wherein the orthographic projection of the adapter unit on the base substrate overlaps with the orthographic projections of the plurality of test signal lines on the base substrate, and the data line is electrically connected to the adapter unit; The plurality of test circuit pads further include a third test pad for transmitting a gate driving signal, wherein the third test pad is configured to be connected to a gate driving circuit located in the peripheral area through a gate driving signal line.

12. The display substrate according to any one of claims 9 to 11, wherein: The plurality of test signal connection lines include a power test signal connection line, wherein the power test signal connection line includes a first power test signal connection line, and the first power test signal connection line includes a first power test signal connection sub-line and a second power test signal connection sub-line connected in sequence; A first end of the first power test signal connection sub-line is connected to the first test pad, a second end of the first power test signal connection sub-line is connected to the first end of the second power test signal connection sub-line, and a second end of the second power test signal connection sub-line is connected to the first pad; The orthographic projection of the first power test signal connecting sub-line on the substrate does not overlap with the multiple test signal lines, and the orthographic projection of the second power test signal connecting sub-line on the substrate overlaps with the multiple test signal lines.

13. The display substrate according to claim 12, wherein: The first power test signal connection sub-line is in the same layer and made of the same material as the first electrode layer, and the second power test signal connection sub-line is in the same layer and made of the same material as the data line.

14. The display substrate according to claim 12, wherein: The binding area is also provided with a third pad, the third pad is electrically connected to the gate drive circuit of the display substrate, the power test signal connection line includes a second power test signal connection line, the third test pad is electrically connected to the third pad through the second test signal line connection line, and the second test signal line connection line is in the same layer and made of the same material as the first electrode.

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