A high-speed low-power comparator for SAR ADCs

Abstract

The application discloses a high-speed low-power comparator of a SAR ADC, and relates to the technical field of analog or digital-analog hybrid integrated circuits.The comparator comprises a pre-amplification stage and a latch stage, the enable signal cp end of the pre-amplification stage is connected with an enable signal Ki, the positive input end is connected with a differential input positive end signal vp, the negative input end is connected with a differential input negative end signal vn, the positive output end vop is connected with the positive input end of the latch stage through a switch K1, the negative output end von is connected with the positive input end of the latch stage through a switch K2, the switches K1 and K2 are controlled by the enable signal Ki, the differential input positive end signal vp is connected with the positive input end of the latch stage through a switch K3, the differential input negative end signal vn is connected with the positive input end of the latch stage through a switch K4, and the switches K3 and K4 are controlled by the inverted signal Kim of the enable signal Ki.The scheme improves the gain and bandwidth of the pre-amplification stage, thereby improving the speed and precision of the pre-amplification stage simultaneously.

Description

Technical Field

[0001] This application relates to the field of analog or mixed-signal integrated circuit technology, and in particular to a high-speed, low-power comparator for a SAR ADC. Background Technology

[0002] In recent years, with the further improvement of analog-to-digital converter (ADC) performance, especially with the continuous development of integrated circuit technology, research on high-speed, low-power SAR ADCs has become increasingly in-depth. As integrated circuit manufacturing processes continue to evolve, the requirements for comparator power consumption and speed are becoming increasingly stringent. Therefore, high-speed, low-power SAR ADC technology has become a research hotspot in the current ADC field.

[0003] The following section introduces the basic working principle of a traditional SAR ADC structure and existing comparator technologies. A schematic diagram of a SAR ADC structure is shown below. Figure 1 As shown, the SAR ADC mainly consists of a sampling switch S, a comparator, a capacitor array, and SAR logic. When the SAR ADC is in the sampling phase, switch S is turned on, and the positive and negative input terminals of the comparator are connected to the differential signal sources VIP and VIN, respectively, sampling the differential input positive signals vp and vn onto the plates of the capacitor array. After sampling, the sampling switch S is turned off, and the SAR ADC enters the successive approximation phase. At this time, the comparator performs successive comparisons on the differential input positive signals vp and vn, and the comparison results are used by the SAR logic to switch the capacitor array, generating a new residual voltage sum, thus completing one successive approximation process. After the SAR ADC performs n successive approximations according to the above process, it generates an n-bit digital code, finally completing the process of converting the analog signal into a digital signal. n is a natural number greater than 0, representing the number of successive approximations.

[0004] As the primary analog component in the aforementioned structure, the comparator's performance directly impacts the overall performance of the SAR ADC. A schematic diagram of a traditional comparator structure in a SAR ADC is shown below. Figure 2 As shown, it includes a pre-amplification stage and a latching stage. The differential input positive terminals, vp and vn, are input to the pre-amplification stage, and Ki is the enable signal for the pre-amplification stage. The output of the pre-amplification stage then enters the latching stage for further amplification and latching. Finally, the output of the latching stage controls the SAR logic. A traditional pre-amplification stage schematic is shown below. Figure 3As shown, IB is the tail current source, and the differential input transistors are NMOS transistors M1 and M2. The sources of NMOS transistors M1 and M2 are connected to one end of the current source IB, and the other end of the current source IB is grounded. The gates of NMOS transistors M1 and M2 are connected to the positive terminal signals vp and vn of the differential input, respectively. The drains of NMOS transistors M1 and M2 are connected to the drains of PMOS transistors M3 and M4, respectively. PMOS transistors M3 and M4 are load transistors, and the drains of PMOS transistors M3 and M4 are connected to their own gates. The sources of PMOS transistors M3 and M4 are both connected to the power supply vdd.

[0005] Assuming the above pre-amplification stage is perfectly symmetrical, the absolute value of the gain A of the above pre-amplification stage can be expressed as:

[0006]

[0007] Among them, g m1 and g m3 They are respectively Figure 3 The transconductance of NMOS transistor M1 and PMOS transistor M3 can be determined from equation (1) because g m1 and g m3 Within the same order of magnitude, the absolute gain of a traditional pre-amplifier stage is relatively small, resulting in poor accuracy. Increasing the amplification factor can be achieved by increasing the output impedance of the pre-amplifier stage, but this rapidly reduces the bandwidth, significantly impacting the overall comparator speed. Furthermore, traditional comparators operate in a fixed mode; the pre-amplifier stage remains active throughout the successive approximation process, preventing the comparator from reaching optimal speed. Additionally, the presence of quiescent current in the pre-amplifier stage ensures that the comparator also experiences static power consumption.

[0008] In view of this, there is an urgent need for a high-speed, low-power comparator for SAR ADC. Summary of the Invention

[0009] In view of the shortcomings of the prior art described above, this application proposes a high-speed, low-power comparator for SAR ADC, which solves the problem of static power consumption in the pre-amplification stage throughout the entire successive approximation process in the prior art; on the other hand, it solves the problem of the contradiction between the gain and bandwidth of the pre-amplification stage in the prior art.

[0010] To achieve the above objectives, this application specifically adopts the following technical solution:

[0011] A high-speed, low-power comparator for a SAR ADC, the comparator comprising a pre-amplification stage and a latching stage,

[0012] The enable signal cp terminal of the pre-amplification stage is connected to the enable signal Ki, the positive input terminal is connected to the differential input positive terminal signal vp, the negative input terminal is connected to the differential input negative terminal signal vn, the positive output terminal vop is connected to the positive input terminal of the latch stage through switch K1, and the negative output terminal von is connected to the positive input terminal of the latch stage through switch K2. Both switches K1 and K2 are controlled by the enable signal Ki.

[0013] Meanwhile, the differential input positive terminal signal vp is connected to the positive input terminal of the latch stage through switch K3, and the differential input negative terminal signal vn is connected to the positive input terminal of the latch stage through switch K4. Both switches K3 and K4 are controlled by the inverted signal Kim of the enable signal Ki.

[0014] As an optional technical solution, the enable signal Ki contains i = 1, 2, ..., n-1, n; n is a natural number greater than 0. When i takes the value n, it means that in the design of an n-bit SAR ADC, the latch stage uses n flip-flops (DFFs).

[0015] As an optional technical solution, the signal input terminal D of the first flip-flop DFF is connected to the power supply Vdd, the enable signal terminal CP is connected to the clock signal clk, and the reset terminal R is connected to the sampling control signal S.

[0016] When the sampling control signal S is high, the output terminal Q of the flip-flop DFF is forcibly reset to 0. When the sampling control signal S is low, the flip-flop DFF exits the reset state. The output terminal Q of the flip-flop DFF follows the clock signal clk and outputs the value of the output terminal Q as the enable signal K1, which is then passed to the input terminal D of the next flip-flop.

[0017] Until the last of the aforementioned triggers, DFF, outputs the enable signal Kn.

[0018] As an optional technical solution, the output terminal Q of the flip-flop DFF is forcibly reset to 0, specifically:

[0019] When the SAR ADC is in the sampling phase, S=1, and the output enable signal Ki of the n D flip-flops (DFFs) is reset to 0.

[0020] As an optional technical solution, when the sampling control signal S is low, the flip-flop DFF exits the reset state, specifically as follows:

[0021] When the SAR ADC is in the successive approximation phase, S=0, and the output enable signals Ki of the n D flip-flops (DFFs) are successively pulled high from 0 to 1 along with the rising edge of the clock signal clk.

[0022] As an optional technical solution, the pre-amplification stage includes a tail current source IB, which is controlled by an enable signal Ki.

[0023] When the enable signal Ki is 0, the tail current source IB is not enabled, and the pre-amplification stage has no static power consumption.

[0024] When the enable signal Ki is 1, the tail current source IB is enabled. One end of the tail current source IB is grounded, and the other end is connected to the source of the differential input NMOS transistors M1 and M2 of the pre-amplification stage.

[0025] The gates of NMOS transistors M1 and M2 are connected to the differential input positive terminals vp and vn, respectively. The drains of NMOS transistors M1 and M2 are connected to the drains of PMOS transistors M3 and M4, respectively. The drains of PMOS transistors M3 and M4 are connected to their own gates, respectively. The sources of PMOS transistors M3 and M4 are both connected to the power supply vdd.

[0026] As an optional technical solution, it also includes NMOS transistors M5 and M6, whose drains are both connected to the power supply vdd. The source of NMOS transistor M5 is simultaneously connected to the drain of NMOS transistor M1 and the drain of PMOS transistor M3. The gate of NMOS transistor M5 is connected to the negative terminal signal vn of the differential input. The source of NMOS transistor M6 is simultaneously connected to the drain of NMOS transistor M2 and the drain of PMOS transistor M4. The gate of NMOS transistor M6 is connected to the positive terminal signal vp of the differential input.

[0027] As an optional technical solution, the PMOS transistors M3 and M4 are load transistors.

[0028] As an optional technical solution, the enable signal cp of the latch stage is connected to the clock signal clk.

[0029] The beneficial effects of this application include:

[0030] Compared to the traditional method of always cascading the preamplifier stage and latch stage in the successive approximation process, a flexible configuration method for the preamplifier stage and latch stage is proposed. During the first few cycles of successive approximation, the comparator's operating mode is set so that the input signal is directly connected to the latch stage, allowing the latch stage to directly compare the comparator's input signal, and the preamplifier stage is disabled, reducing the comparator's static power consumption. During the later cycles of successive approximation, the comparator's operating mode is set so that the input signal is amplified by the preamplifier stage before entering the latch stage. This configuration optimizes the comparator's speed and power consumption.

[0031] Compared with the traditional method of increasing the output impedance of the preamplifier stage to improve its gain, this paper proposes a method that increases the equivalent impedance of the preamplifier stage, thereby simultaneously improving the gain and bandwidth of the preamplifier stage, and thus improving the speed and accuracy of the preamplifier stage.

[0032] Other beneficial effects or advantages of this application will be described in detail in conjunction with the specific structure in the specific embodiments. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In addition, it should be understood that the proportional relationship of each component in the drawings of this specification does not represent the proportional relationship in the actual material selection and design, but is only a schematic diagram of the structure or position, wherein:

[0034] Figure 1 Schematic diagram of SAR ADC structure

[0035] Figure 2 A schematic diagram of a traditional comparator structure in a SAR ADC.

[0036] Figure 3 Traditional pre-amplification stage structure

[0037] Figure 4 A schematic diagram showing the variation of the preamplification stage and latching stage with the input signal amplitude comparison speed.

[0038] Figure 5 Schematic diagram of successive approximation at the input of a SAR ADC comparator

[0039] Figure 6 The schematic diagram (a) of the pre-amplification stage and the half-side small-signal equivalent circuit (b) proposed in this invention are shown.

[0040] Figure 7 The configurable low-power amplifier structure proposed in this invention

[0041] Figure 8 Comparator control signal generation circuit Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0043] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0044] In the description of this application, it should be noted that the terms used, such as "top" and "bottom," refer to the portion closer to the top and the portion closer to the bottom in the application's usage state; the terms used, such as "first" and "second," are only for distinguishing descriptions and do not indicate or imply a difference in importance or order; the terms used, such as "inner" and "outer," refer to the inner and outer parts of a specific outline. The use of the above terms is only for the purpose of clearly and simply describing the technical solution of this application and should not be construed as limiting this application.

[0045] Example 1:

[0046] This invention discloses a high-speed, low-power comparator for a SAR ADC. The comparator includes a pre-amplifier stage and a latch stage. The enable signal cp of the pre-amplifier stage is connected to an enable signal Ki, the positive input is connected to the positive differential input signal vp, and the negative input is connected to the negative differential input signal vn. The positive output vop is connected to the positive input of the latch stage via switch K1, and the negative output von is connected to the positive input of the latch stage via switch K2. Both switches K1 and K2 are controlled by the enable signal Ki. Simultaneously, the positive differential input signal vp is connected to the positive input of the latch stage via switch K3, and the negative differential input signal vn is connected to the positive input of the latch stage via switch K4. Both switches K3 and K4 are controlled by the inverted signal Kim of the enable signal Ki.

[0047] To facilitate understanding of the improvements in this solution, the existing technology will be briefly described first:

[0048] The diagram illustrates the variation of the preamplifier stage and latch stage amplitude comparison speed with the input signal, as shown below. Figure 4 As shown, by Figure 4 It can be seen that when the input signal amplitude is relatively small, the comparison speed of the pre-amplifier stage is faster; when the input signal amplitude is relatively large, the comparison speed of the latch stage is faster. A schematic diagram of the successive approximation at the input of the SAR ADC comparator is shown below. Figure 5 As shown, by Figure 5 It can be seen that in the first few cycles of successive approximation, the differential input signals vp and vn of the comparator differ significantly. In the later cycles of successive approximation, the positive differential input signal vp and the negative differential input signal vn of the comparator gradually approach each other and become less different.

[0049] Based on the above principles, different comparator operating modes can be selected according to different successive approximation time periods, thereby achieving rapid comparison of the comparator input signals with minimal power consumption. Simultaneously, unnecessary operating modules are shut down in different modes to reduce the comparator's static power consumption.

[0050] Therefore, this invention proposes a high-speed, low-power comparator for SAR ADCs, such as... Figure 7 As shown:

[0051] In the enable signal Ki, i = 1, 2, ..., n-1, n; n is a natural number greater than 0. When i takes the value n, it means that in the design of an n-bit SAR ADC, the latch stage uses n flip-flops (DFFs).

[0052] The first flip-flop DFF has its signal input terminal D connected to the power supply Vdd, its enable signal terminal CP connected to the clock signal clk, and its reset terminal R connected to the sampling control signal S.

[0053] When the sampling control signal S is high, the output terminal Q of the flip-flop DFF is forcibly reset to 0. When the sampling control signal S is low, the flip-flop DFF exits the reset state. The output terminal Q of the flip-flop DFF follows the clock signal clk and outputs the value of the output terminal Q as the enable signal K1, which is then passed to the input terminal D of the next flip-flop.

[0054] Until the last of the aforementioned triggers, DFF, outputs the enable signal Kn.

[0055] The output terminal Q of the trigger DFF is forcibly reset to 0. Specifically, when the SAR ADC is in the sampling phase, S=1, and the output enable signal Ki of the n D triggers DFF is reset to 0.

[0056] When the sampling control signal S is low, the DFF flip-flops exit the reset state. Specifically, when the SAR ADC is in the successive approximation phase, S = 0, and the output enable signals Ki of the n D flip-flops are sequentially pulled high from 0 to 1 along with the rising edge of the clock signal clk.

[0057] Based on actual needs, a signal from Ki (i = 1, 2, ..., n-1, n) and its inverse signal Kim (i = 1, 2, ..., n-1, n) can be selected to control... Figure 7 Four switches between the preamplifier stage and the latch stage.

[0058] Furthermore, its working principle is as follows:

[0059] When the SAR ADC is in the first few successive approximation cycles, the difference between the positive differential input signal vp and the negative differential input signal vn of the comparator is relatively large. Figure 4 It can be seen that the comparison speed of the latch stage is faster than that of the preamplifier stage. Therefore, the positive differential input signal vp and the negative differential input signal vn of the comparator can be directly used as the input signals of the latch stage. At this point, the selection... Figure 8 The corresponding enable signal Ki (i = 1, 2, ..., n-1, n) is 0, so that it controls Figure 7 The switch in the middle is off;

[0060] At the same time, the enable signal Kim (i = 1, 2, ..., n-1, n) is set to 1, so that the controlled... Figure 7 When the switch is turned on, the differential input signal of the comparator is directly input to the latch stage.

[0061] By enabling the signal Ki (i = 1, 2, ..., n-1, n), Figure 6 In (a), the tail current source IB of the preamplifier stage is disabled, resulting in no static power consumption in the preamplifier stage and reducing the static power consumption of the entire comparator. As the successive approximation process continues, the difference between the positive signal vp at the differential input of the comparator and the negative signal vn at the differential input gradually decreases, and the comparison speed of the latch stage on the small-signal differential voltage gradually slows down compared to the preamplifier stage.

[0062] at this time, Figure 8 The corresponding enable signal Ki (i = 1, 2, ..., n-1, n) changes from 0 to 1, thus controlling... Figure 7 The switch in the circuit is turned on, enabling the preamplifier stage. The inverting signal Kim (i = 1, 2, ..., n-1, n) changes from 1 to 0, causing the circuit it controls to... Figure 7 When the switch is turned off, the differential input signal of the comparator is first input to the pre-amplifier stage, amplified by the pre-amplifier stage, and then input to the latch stage.

[0063] As an optional technical solution, the pre-amplification stage includes a tail current source IB, which is controlled by an enable signal Ki. When the enable signal Ki is 0, the tail current source IB is disabled, and the pre-amplification stage has no static power consumption. When the enable signal Ki is 1, the tail current source IB is enabled. One end of the tail current source IB is grounded, and the other end is connected to the source of the differential input NMOS transistors M1 and M2 of the pre-amplification stage. The gates of the NMOS transistors M1 and M2 are respectively connected to the differential input positive terminal signals vp and vn. The drains of the NMOS transistors M1 and M2 are respectively connected to the drains of the PMOS transistors M3 and M4. The drains of the PMOS transistors M3 and M4 are respectively connected to their own gates. The sources of the PMOS transistors M3 and M4 are both connected to the power supply vdd.

[0064] It also includes NMOS transistors M5 and M6, whose drains are both connected to the power supply Vdd. The source of NMOS transistor M5 is simultaneously connected to the drain of NMOS transistor M1 and the drain of PMOS transistor M3. The gate of NMOS transistor M5 is connected to the negative terminal signal Vn of the differential input. The source of NMOS transistor M6 is simultaneously connected to the drain of NMOS transistor M2 and the drain of PMOS transistor M4. The gate of NMOS transistor M6 is connected to the positive terminal signal Vp of the differential input. PMOS transistors M3 and M4 are load transistors.

[0065] Furthermore, the half-small-signal equivalent circuit of the preamplifier stage is as follows: Figure 6 As shown in (b), the working principle of the pre-amplification stage is as follows:

[0066] Assuming all MOSFETs are operating in the saturation region, o1 r o3 and r o6 These are the small-signal output impedances of MOSFETs M1, M3, and M6 operating in the saturation region, respectively. m1 and g m3 The transconductances of NMOS transistor M1 and PMOS transistor M3 are respectively, g m6 V is the transconductance of the PMOS transistor, and vp and vn are the positive and negative input signals of the pre-amplifier stage, respectively. xp and v xn for Figure 6 (b) Small signal voltage of the corresponding node.

[0067] Since MOSFETs M1, M3, and M6 are operating in the saturation region, their small-signal impedance r o1 r o3 and r o6 The flow is very large, therefore, the flow through the preamplifier stage output node v xn The current at that location is mainly composed of Figure 6 (b) consists of three voltage-controlled current sources. Therefore, ignoring the current flowing through r... o1 r o3 and r o6 Under the condition of a small signal current, according to Kirchhoff's current law, in this half of the equivalent circuit, the output node v xn The nodal current equation at point can be expressed as:

[0068] g m1 vp-g m3 v xn =g m6 (vp-v xn (2)

[0069] Similarly, if we consider the other half of the equivalent circuit, v xn The corresponding node is named v xpFurthermore, assuming the circuit is perfectly symmetrical, in the equivalent circuit of the other half, the output node v xp The nodal current equation at point can be expressed as:

[0070] g m1 vn-g m3 v xp =g m6 (vn-v xp (3)

[0071] Solving equations (2) and (3) together, the absolute value of the gain A of the preamplifier stage can be expressed as:

[0072]

[0073] As shown in equation (4), the pre-amplification stage structure proposed in this invention has a significantly smaller denominator and a significantly larger numerator compared to the traditional pre-amplification stage structure, resulting in a significant improvement in gain. Furthermore, the gain improvement is not achieved by increasing the output impedance of the pre-amplification stage, but rather by increasing the equivalent bandwidth of the pre-amplification stage. This means that the pre-amplification stage structure proposed in this invention simultaneously improves both the gain and bandwidth of the pre-amplification stage, significantly enhancing its accuracy and speed.

[0074] Finally, it should be understood that the embodiments described in this specification are merely illustrative of the principles of the embodiments described herein. Other variations may also fall within the scope of this specification. Therefore, alternative configurations of the embodiments described herein are intended to be illustrative rather than limiting, and should be considered consistent with the teachings of this specification. Accordingly, the embodiments described herein are not limited to those explicitly introduced and described herein.

Claims

1. A high-speed, low-power comparator for a SARADC, comprising a pre-amplification stage and a latching stage, characterized in that: The enable signal cp terminal of the pre-amplification stage is connected to the enable signal Ki, the positive input terminal is connected to the differential input positive terminal signal vp, the negative input terminal is connected to the differential input negative terminal signal vn, the positive output terminal vop is connected to the positive input terminal of the latch stage through switch K1, and the negative output terminal von is connected to the positive input terminal of the latch stage through switch K2. Both switches K1 and K2 are controlled by the enable signal Ki. Meanwhile, the differential input positive terminal signal vp is connected to the positive input terminal of the latch stage through switch K3, and the differential input negative terminal signal vn is connected to the positive input terminal of the latch stage through switch K4. Both switches K3 and K4 are controlled by the inverted signal Kim of the enable signal Ki. The pre-amplification stage includes a tail current source IB, differential input NMOS transistors M1 and M2, PMOS load transistors M3 and M4, and NMOS transistors M5 and M6; the tail current source IB is controlled by an enable signal Ki, one end of the tail current source IB is grounded, and the other end is connected to the source of NMOS transistors M1 and M2. When the enable signal Ki is 0, the tail current source IB is not enabled, and the pre-amplification stage has no static power consumption. When the enable signal Ki is 1, the tail current source IB is enabled. One end of the tail current source IB is grounded, and the other end is connected to the source of the differential input NMOS transistors M1 and M2 of the pre-amplification stage. The gates of NMOS transistors M1 and M2 are connected to the positive differential input signal vp and the negative differential input signal vn, respectively. The drain of NMOS transistor M1 is connected to the drain of PMOS transistor M3 and the source of NMOS transistor M5. The drain of NMOS transistor M2 is connected to the drain of PMOS transistor M4 and the source of NMOS transistor M6. The gates of PMOS transistors M3 and M4 are connected to their respective drains, and the sources of PMOS transistors M3 and M4 are both connected to the power supply Vdd. The drains of NMOS transistors M5 and M6 are both connected to the power supply Vdd. The gate of NMOS transistor M5 is connected to the negative terminal signal vn of the differential input; The gate of NMOS transistor M6 is connected to the positive terminal signal vp of the differential input; The positive output terminal vop and the negative output terminal von of the pre-amplification stage are led out from the drains of NMOS transistors M1 and M2, respectively, and connected to the input terminal of the latch stage.

2. The high-speed, low-power comparator for a SARADC as described in claim 1, characterized in that, In the enable signal Ki, i = 1, 2, ..., n-1, n; n is a natural number greater than 0. When i takes the value n, it means that in the design of an n-bit SARADC, the latch stage uses n flip-flops (DFFs).

3. A high-speed, low-power comparator for a SARADC as described in claim 2, characterized in that, The first flip-flop DFF has its signal input terminal D connected to the power supply Vdd, its enable signal terminal CP connected to the clock signal clk, and its reset terminal R connected to the sampling control signal S. When the sampling control signal S is high, the output terminal Q of the flip-flop DFF is forcibly reset to 0. When the sampling control signal S is low, the flip-flop DFF exits the reset state. The output terminal Q of the flip-flop DFF follows the clock signal clk and outputs the value of the output terminal Q as the enable signal K1, which is then passed to the input terminal D of the next flip-flop. This continues until the last flip-flop DFF outputs the enable signal Kn.

4. A high-speed, low-power comparator for a SARADC as described in claim 3, characterized in that, The output Q of the flip-flop DFF is forcibly reset to 0, specifically: When the SARADC is in the sampling phase, S=1, and the output enable signal Ki of the n D flip-flops (DFF) is reset to 0.

5. A high-speed, low-power comparator for a SARADC as described in claim 3, characterized in that, When the sampling control signal S is low, the flip-flop DFF exits the reset state, specifically as follows: When the SARADC is in the successive approximation phase, S=0, and the output enable signals Ki of the n D flip-flops are successively pulled high from 0 to 1 along with the rising edge of the clock signal clk.

6. A high-speed, low-power comparator for a SARADC as described in any one of claims 1-5, characterized in that, The latch stage also includes an enable signal cp terminal, which is connected to a clock signal clk.

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