An external bias pixel structure for a light receiving circuit in a dynamic vision sensor pixel

Abstract

The present invention discloses an external bias pixel structure of a light receiving stage circuit in a dynamic vision sensor pixel. The external bias pixel structure comprises a photodiode, a logarithmic tube, an amplifier tube, a switch tube, and a bias tube. The bias tube, the switch tube, and the amplifier tube are sequentially connected in series, wherein the source of the bias tube is connected to a power supply, the drain of the bias tube is connected to the drain of the switch tube, the source of the switch tube is connected to the drain of the amplifier tube, and the source of the amplifier tube is grounded. The gate of the bias tube is connected to V bias Signal connection, the gate of the switch tube is connected to V cpr Signal connection, the source of the switching tube and the drain of the amplifier tube are also connected to the gate of the logarithmic tube, the drain of the logarithmic tube is connected to the power supply, the source of the logarithmic tube is connected to the negative electrode of the photodiode, the positive electrode of the photodiode is grounded, and the source of the logarithmic tube and the negative electrode of the photodiode are also connected to the gate of the amplifier tube.

Description

Technical Field

[0001] The present invention relates to the field of dynamic vision sensors, and in particular to an external bias pixel structure of a light receiving stage circuit in a dynamic vision sensor pixel. Background Art

[0002] With the continuous development of image sensing technology, image sensors have been widely used in various fields. Image sensors are instruments that use optical components and imaging devices to obtain image information of the external environment. Existing image sensors generally include active pixel sensors (APS) and dynamic vision sensors (DVS).

[0003] DVS differs from traditional image sensors. Traditional image sensors convert absolute light intensity information into frame images, while DVS converts changes in light intensity into event information. Compared to traditional image sensors, DVS offers low latency, low data volume, and low power consumption. Currently, DVS can be divided into two readout methods: synchronous readout and asynchronous readout. For large arrays of DVS pixels, when the event rate is high, synchronous readout offers lower readout latency and more precise temporal resolution. Periodic synchronous readout causes DVS pixels to read changes in light intensity only at the readout moment, while continuously detecting external light intensity information during non-readout moments. Summary of the Invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art and provide an external bias pixel structure of the light receiving stage circuit in the dynamic vision sensor pixel, which only works at the pixel readout time and can further reduce the pixel size based on the traditional dynamic vision sensor pixel structure.

[0005] The purpose of the present invention is achieved through the following technical solutions:

[0006] An externally biased pixel structure for a light receiving stage circuit in a dynamic vision sensor pixel includes a light receiving stage circuit, a buffer stage circuit, a sample-and-hold circuit, and an event generation circuit, which are sequentially arranged. The light receiving stage circuit converts changes in external light intensity into logarithmic voltage changes; the buffer stage circuit electrically isolates the light receiving stage circuit from the sample-and-hold circuit; the sample-and-hold circuit samples and stores the voltage generated by the current light intensity; the event generation circuit compares the voltage difference between the previous moment and the current moment with a set threshold to determine whether an event has occurred; the externally biased pixel structure includes a photodiode, a logarithmic tube, an amplifier tube, a switch tube, and a bias tube.

[0007] The bias tube, switch tube and amplifier tube are connected in series in sequence, where the source of the bias tube is connected to the power supply, the drain of the bias tube is connected to the drain of the switch tube, the source of the switch tube is connected to the drain of the amplifier tube, and the source of the amplifier tube is grounded; the gate of the bias tube is connected to V bias Signal connection, V bias The signal is generated by the bias circuit outside the dynamic vision sensor pixel array, and the gate of the switch tube is connected to V cpr Signal connection, V cpr The signal is generated by a controller outside the pixel array of the dynamic vision sensor. The source of the switching tube and the drain of the amplifier tube are also connected to the gate of the logarithmic tube. The drain of the logarithmic tube is connected to the power supply. The source of the logarithmic tube is connected to the negative electrode of the photodiode. The positive electrode of the photodiode is grounded. The source of the logarithmic tube and the negative electrode of the photodiode are also connected to the gate of the amplifier tube.

[0008] Furthermore, in the dynamic vision sensor pixel array within the dynamic vision sensor, each column of pixels shares x bias tubes, where x is determined by the setup time from off to on of the light receiving stage circuit and the readout row period; V cpr The signal passes through each row of the pixel array and is connected to the control circuit, which controls the on and off of the switch tubes in the light receiving stage circuit of each row of pixels to control the working conditions of the entire row of pixels.

[0009] The present invention also provides an imaging method of a dynamic vision sensor, comprising:

[0010] S1. Taking the pixels in the nth and n+1th rows as an example, when the pixels in the nth row are within the t1 time, the switch tube is turned off, the light receiving stage circuit is closed, and no longer senses external light intensity information;

[0011] S2. When the pixels in the nth row are between t2 and t3, the switch is turned on. The light receiving stage circuit is in operation between t2 and t3. The time t2 is set according to the setup time of the light receiving stage circuit.

[0012] S3. During time t2, the light receiving stage circuit begins to build. The photodiode within the dynamic vision sensor pixel converts the light signal into photocurrent. The logarithmic tube converts the current signal into the current voltage signal and outputs it to the buffer stage circuit.

[0013] S4. The current voltage signal is output to the sample-and-hold circuit through the buffer stage circuit;

[0014] S5. The current voltage signal passes through the sample-and-hold circuit and is subtracted from the previous voltage within t3 to obtain the voltage difference between the two moments due to the change in light intensity. This is then amplified and input to the event generation circuit.

[0015] S6. The event generation circuit compares the amplified voltage difference signal at the two moments with the set threshold to determine whether an event has occurred. If an event has occurred, it is output to the column bus.

[0016] At S7.t4, the reading of the n+1th row begins, and steps S5 to S6 are repeated.

[0017] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0018] 1. Reduced pixel area: Traditional DVS pixels require a separate PMOS bias transistor, which must be placed in the N-well, increasing the layout area. This invention moves the PMOS bias transistor outside the pixel array and shares it across each column of pixels, enabling circuit reuse. This reduces the internal pixel layout area and improves the space utilization of the pixel array.

[0019] 2. Reduced manufacturing costs: Reducing the pixel layout area allows more pixels to be accommodated within a unit chip area, improving the pixel integration density and helping to achieve higher resolution within the same chip area, thereby reducing the manufacturing cost per pixel.

[0020] 3. Power consumption optimization: By designing a switch to control the operating state of the light receiving stage circuit, each row of pixels is powered on only during the setup time before readout and during readout, and is disabled at all other times, avoiding unnecessary energy consumption. Compared to traditional DVS architectures, this invention further optimizes overall power consumption while maintaining response speed.

[0021] 4. Improved dynamic response efficiency: This invention adopts a synchronous readout method, which can quickly respond to changes in light intensity through switch control, reduce the delay of event information, and help improve the response accuracy and time resolution of image sensors in fast-motion scenes. It is especially suitable for dynamic scenes with high event rates.

[0022] 5. Improved application adaptability: Since the pixel area is reduced or more layout resources are reserved under the same area, the present invention can provide more layout flexibility for subsequent circuit design and adapt to a wider range of dynamic visual application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Schematic diagram of a typical DVS pixel structure with synchronous readout;

[0024] Figure 2 This is a schematic diagram of the traditional DVS optical receiving stage circuit structure;

[0025] Figure 3 Schematic diagram of the external bias pixel structure of the light receiving stage circuit in the present invention;

[0026] Figure 4 Schematic diagram of the connection relationship of the external bias pixel array of the light receiving stage (x=1);

[0027] Figure 5 This is a timing diagram of the external bias pixel at the light receiving stage. DETAILED DESCRIPTION

[0028] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0029] In this embodiment, the bias transistor in the light receiving stage circuit of the DVS pixel is placed outside the pixel array, which can further reduce the pixel size under the same DVS pixel structure, or reserve more layout resources for use under the same pixel size.

[0030] The schematic diagram of the structure of a typical DVS pixel with synchronous readout is as follows: Figure 1 As shown in the figure, a DVS pixel consists of a light receiving stage, a buffer stage, a sample-and-hold circuit, and an event generation circuit. The light receiving stage converts changes in external light intensity into logarithmic voltage changes; the buffer stage electrically isolates the light receiving stage from the sample-and-hold circuit; the sample-and-hold circuit samples and stores the voltage generated by the current light intensity; and the event generation circuit compares the voltage difference between the previous and current moments with a set threshold to determine whether an event has occurred.

[0031] Traditional optical receiving circuits such as Figure 2 As shown, it includes a photodiode (PD), a logarithmic tube M1, an amplifier tube M2, and a bias tube M3. The PD senses the external light intensity and moves the photogenerated electrons in a directional manner in the circuit path, generating a photocurrent that is proportional to the current light intensity. The logarithmic tube M1 operates in the subthreshold region, converting the photocurrent change generated by the PD into a logarithmic voltage change, thereby increasing the dynamic range of the pixel. The gate of the amplifier tube M2 is connected to the negative electrode of the PD to clamp the voltage across the PD. The bias tube M3 is a PMOS transistor, which is connected to the reference voltage V bias To regulate the current flowing through M2 and M3.

[0032] Since the light receiving circuit part of each pixel of DVS requires a PMOS bias tube, the PMOS bias tube needs to be placed in the N-well, which requires more layout area in the pixel.

[0033] The external bias pixel structure of the light receiving stage circuit proposed in this embodiment is as follows Figure 3 shown. Figure 3Taking a single pixel in DVS as an example, the light receiving stage circuit includes a photodiode PD, a logarithmic tube M1, an amplifier tube M2, a switch tube M3, and a bias tube M4.

[0034] The bias tube M4, the switch tube M3 and the amplifier tube M2 are connected in series in sequence, wherein the source of the bias tube M4 is connected to the power supply, the drain of the bias tube M4 is connected to the drain of the switch tube M3, the source of the switch tube M3 is connected to the drain of the amplifier tube M2, and the source of the amplifier tube M2 is grounded; the gate of the bias tube M4 is connected to V bias Signal connection, the gate of switch tube M3 is connected to V cpr Signal connection, the source of the switch tube M3 and the drain of the amplifier tube M2 are also connected to the gate of the logarithmic tube M1, the drain of the logarithmic tube M1 is connected to the power supply, the source of the logarithmic tube M1 is connected to the cathode of the photodiode PD, the anode of the photodiode PD is grounded, and the source of the logarithmic tube M1 and the cathode of the photodiode PD are also connected to the gate of the amplifier tube M2.

[0035] The external bias pixel structure of the light receiving stage circuit introduces an additional switch tube M3, which is generated by the controller. cpr The signal controls the on / off switching of switch M3. If switch M3 is on, current flows from power supply VDD through bias transistor M4, switch M3, and amplifier M2, allowing the light receiving stage circuit to operate normally. If switch M3 is off, no current flows through bias transistor M4, switch M3, and amplifier M2, shutting down the light receiving stage circuit. By moving bias transistor M4 outside the pixel array, the PMOS bias transistor in the original pixel layout can be replaced with the NMOS switch M3. This eliminates the need to place the NMOS transistor in the N-well, saving layout area.

[0036] Preferably, in the external bias pixel structure of the light receiving stage circuit proposed in this embodiment, in the DVS pixel array, each column of pixels shares x PMOS bias tubes, where x can be determined based on the setup time from off to on of the DVS light receiving stage and the row cycle of the readout. In this embodiment, x=1 is taken as an example, i.e., each column of DVS pixels shares one PMOS bias tube. The connection relationship of the DVS pixel array with a×b resolution is as follows: Figure 4 As shown, V cpr The signal passes through each row of the pixel array and is connected to the control circuit, which controls the on and off of the switch tube M3 in the light receiving stage of each row of pixels to control the working conditions of the entire row of pixels. Figure 4 Only the connection relationship between the switch tube M3 and the bias tube M4 in the pixel is schematically represented. The buffer stage, sample and hold circuit, and event generation circuit in the DVS pixel are represented by other circuits, and other signals are not drawn.

[0037] Specifically, the imaging process of the dynamic vision sensor based on the above external bias pixel structure is as follows:

[0038] S1. Taking the pixels in the nth and n+1th rows as an example, the timing diagram is as follows Figure 5 As shown, when the pixels in the nth row are in the time t1, the switch tube M3 is turned off, the light receiving stage is closed, and the external light intensity information is no longer sensed.

[0039] S2. When the pixels in the nth row are in the time period t2 to t3, the switch tube M3 is turned on. At this time, the light receiving stage is in the working state in the time period t2 to t3. The time t2 needs to be set according to the setup time of the light receiving stage.

[0040] S3. Within t2, the light receiving stage begins to be established, and the photodiode in the pixel converts the light signal into photocurrent. The logarithmic tube M1 converts the current signal into the voltage signal at the current moment and outputs it to the buffer stage.

[0041] S4. The current voltage signal is output to the sample-and-hold circuit through the buffer stage.

[0042] S5. The voltage signal at the current moment passes through the sample-and-hold circuit and is subtracted from the voltage at the previous moment within t3 to obtain the voltage difference caused by the change in light intensity between the two moments. This is then amplified and input to the event generation circuit.

[0043] S6. The event generation circuit compares the voltage difference signal amplified at two moments with a set threshold value to determine whether an event has occurred. If an event has occurred, the circuit outputs the result to the column bus.

[0044] At S7.t4, the reading of the n+1th row begins, and steps 5 to 6 are repeated.

[0045] The present invention is not limited to the embodiments described above. The above description of the specific embodiments is intended to describe and illustrate the technical solutions of the present invention. The above specific embodiments are merely illustrative and not restrictive. Without departing from the scope of the present invention and the scope of protection of the claims, those skilled in the art may make various specific modifications based on the teachings of the present invention, all of which fall within the scope of protection of the present invention.

Claims

1. An external bias pixel structure for a light receiving stage circuit in a dynamic vision sensor pixel, wherein the dynamic vision sensor pixel includes a light receiving stage circuit, a buffer stage circuit, a sample and hold circuit, and an event generation circuit arranged in sequence. The light receiving stage circuit converts external light intensity changes into logarithmic voltage changes; the buffer stage circuit electrically isolates the light receiving stage circuit from the sample and hold circuit; the sample and hold circuit samples and stores the voltage generated by the light intensity at the current moment; and the event generation circuit compares the voltage difference between the previous moment and the current moment with a set threshold to determine whether an event has occurred. The invention is characterized in that: The external bias pixel structure includes a photodiode PD, a logarithmic tube M1, an amplifier tube M2, a switch tube M3, and a bias tube M4. The bias tube M4 is moved outside the pixel array, and the bias tube is shared between each column of pixels, thereby achieving circuit reuse. The bias tube M4, the switch tube M3 and the amplifier tube M2 are connected in series in sequence, wherein the source of the bias tube M4 is connected to the power supply, the drain of the bias tube M4 is connected to the drain of the switch tube M3, the source of the switch tube M3 is connected to the drain of the amplifier tube M2, and the source of the amplifier tube M2 is grounded; the gate of the bias tube M4 is connected to V bias Signal connection, the gate of the switch tube M3 and the V generated by the controller cpr Signal connection, through V cpr The signal controls the on and off of the switch tube M3. The source of the switch tube M3 and the drain of the amplifier tube M2 are also connected to the gate of the logarithmic tube M1. The drain of the logarithmic tube M1 is connected to the power supply. The source of the logarithmic tube M1 is connected to the cathode of the photodiode PD. The anode of the photodiode PD is grounded. The source of the logarithmic tube M1 and the cathode of the photodiode PD are also connected to the gate of the amplifier tube M2.

2. The external bias pixel structure of the light receiving stage circuit in a dynamic vision sensor pixel according to claim 1, characterized in that: In the dynamic vision sensor pixel array in the dynamic vision sensor, each column of pixels shares x bias tubes M4, where x is determined by the setup time from off to on of the light receiving stage circuit and the readout row cycle; V cpr The signal passes through each row of the pixel array and is connected to the control circuit, which controls the on and off of the switch tube M3 in the light receiving stage circuit of each row of pixels to control the working conditions of the entire row of pixels.

3. An imaging method for a dynamic vision sensor, based on the external bias pixel structure of the light receiving stage circuit in the dynamic vision sensor pixel according to any one of claims 1-2, characterized in that: include: S1. Taking the pixels in the nth and n+1th rows as an example, when the pixels in the nth row are within the time t1, the switch tube M3 is turned off, the light receiving stage circuit is closed, and no longer senses external light intensity information; S2. When the pixels in the nth row are between t2 and t3, the switch M3 is turned on. The light receiving stage circuit is in operation between t2 and t3. The time t2 is set according to the setup time of the light receiving stage circuit. S3. During time t2, the light receiving stage circuit begins to establish itself. The photodiode within the dynamic vision sensor pixel converts the light signal into photocurrent. Logarithmic transistor M1 converts the current signal into the current voltage signal and outputs it to the buffer stage circuit. S4. The current voltage signal is output to the sample-and-hold circuit through the buffer stage circuit; S5. The current voltage signal passes through the sample-and-hold circuit and is subtracted from the previous voltage within t3 to obtain the voltage difference between the two moments due to the change in light intensity. This is then amplified and input to the event generation circuit. S6. The event generation circuit compares the amplified voltage difference signal at the two moments with the set threshold to determine whether an event has occurred. If an event has occurred, it is output to the column bus. At S7.t4, the reading of the n+1th row begins, and steps S5 to S6 are repeated.

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