Formation of current electrodes using sacrificial materials

Abstract

A process for fabricating a transistor includes removing a sacrificial material under a base layer including dopants for an intrinsic base of the transistor. After the sacrificial layer is removed to form a cavity directly below the base layer, a semiconductor material is formed in the cavity. The semiconductor layer includes a dopant for a current electrode of the transistor located directly below the intrinsic base of the transistor.

Description

Technical Field

[0001] The present invention relates generally to transistors, and more particularly to utilizing sacrificial materials to form current electrodes of transistors. Background Art

[0002] Some transistors, such as bipolar transistors, include current electrodes, for example, for receiving and providing a current to be controlled by the transistor. Summary of the invention

[0003] According to a first aspect of the present invention, there is provided a method for forming a transistor, the method comprising:

[0004] removing sacrificial material directly below a first semiconductor layer in a first region to form a cavity, wherein the first semiconductor layer includes a conductive dopant having a first conductivity type, wherein the conductive dopant of the first semiconductor layer in the first region provides a conductive dopant for an intrinsic base of a transistor in the first region, wherein at least a portion of the intrinsic base of the transistor is located in the first semiconductor layer in the first region;

[0005] After removing the sacrificial material, a second semiconductor material is formed in the cavity, the second semiconductor material including a conductive dopant having a second conductivity type opposite to the first conductivity type, wherein the conductive dopant having the second semiconductor type of the second semiconductor material formed in the cavity provides a dopant for a first current electrode of the transistor, wherein at least a portion of the first current electrode is located in the second semiconductor material formed in the cavity directly below the intrinsic base.

[0006] In one or more embodiments, the method further includes forming the second semiconductor material directly above the first semiconductor layer after removing the sacrificial material, wherein the second semiconductor material formed directly above the first semiconductor layer includes a conductive dopant having the second conductivity type, wherein the conductive dopant having the second semiconductor type of the second semiconductor material formed directly above the first semiconductor layer provides a dopant for a second current electrode of the transistor, wherein at least a portion of the second current electrode is located in the second semiconductor material formed directly above the intrinsic base.

[0007] In one or more embodiments, the forming of the second semiconductor material in the cavity and the forming of the second semiconductor material directly above the first semiconductor layer are performed during the same semiconductor formation process.

[0008] In one or more embodiments, the same semiconductor formation process is characterized as an epitaxial process.

[0009] In one or more embodiments, after performing the same semiconductor process, the second semiconductor material formed in the cavity directly below the first semiconductor layer in the first region and the second semiconductor material formed directly above the first semiconductor layer in the first region are adjacent to each other, and the method further includes physically separating the second semiconductor material formed in the cavity directly below the first semiconductor layer in the first region and the second semiconductor material formed directly above the first semiconductor layer in the first region into non-adjacent portions.

[0010] In one or more embodiments, the physical separation includes a wafer planarization process to remove portions of the second semiconductor material that are physically bonded to the second semiconductor material formed in the cavity directly below the first semiconductor layer in the first region and the second semiconductor material formed directly above the first semiconductor layer in the first region.

[0011] In one or more embodiments, after the physical separation, a portion of the second semiconductor material adjacent to the second semiconductor material formed in the cavity directly below the first semiconductor layer in the first region is silicided, and a portion of the second semiconductor material adjacent to the second semiconductor material formed directly above the first semiconductor layer in the first region is silicided.

[0012] In one or more embodiments, the first current electrode is characterized as a collector and the second current electrode is characterized as an emitter.

[0013] In one or more embodiments, the first current electrode is characterized as an emitter and the second current electrode is characterized as a collector.

[0014] In one or more embodiments, a base semiconductor layer is located directly above the first semiconductor layer, and the method includes forming a first opening in the base semiconductor layer directly above the first region, wherein the second semiconductor material directly above the first semiconductor layer formed in the first region is formed in the opening, wherein the method includes forming a second opening in the base semiconductor simultaneously with forming the first opening, wherein the sacrificial material is removed by performing isotropic etching of the sacrificial material through the first opening.

[0015] In one or more embodiments, the first semiconductor layer includes silicon germanium, and the second semiconductor material includes silicon.

[0016] In one or more embodiments, the removing the sacrificial material comprises removing the sacrificial material directly below the first semiconductor layer in the second region, wherein the conductive dopant of the first semiconductor layer in the second region provides a conductive dopant for an intrinsic base of a second transistor in the second region, wherein at least a portion of the intrinsic base of the second transistor is located in the first semiconductor layer in the second region;

[0017] The conductive dopant of the second semiconductor material having the second semiconductor type formed in the cavity provides a dopant for a first current electrode of the second transistor, wherein at least a portion of the first current electrode of the second transistor is located in the second semiconductor material formed in the cavity directly below the intrinsic base of the second transistor.

[0018] In one or more embodiments, after singulating the wafer into a plurality of semiconductor dies, the second semiconductor material formed in the cavity directly below the first semiconductor layer in the first region is adjacent to the second semiconductor material formed in the cavity directly below the first semiconductor layer in the second region.

[0019] In one or more embodiments, the first current electrode of the first transistor is characterized as a collector, and the first current electrode of the second transistor is characterized as an emitter.

[0020] In one or more embodiments, the method further comprises:

[0021] forming a second semiconductor material directly over the first semiconductor layer after said removing the sacrificial material, wherein the second semiconductor material formed directly over the first semiconductor layer includes a conductive dopant having the second conductivity type, wherein the conductive dopant having the second semiconductor type of the second semiconductor material formed directly over the first semiconductor layer provides a dopant for a second current electrode of the transistor, wherein at least a portion of the second current electrode is located in the second semiconductor material formed directly over the intrinsic base;

[0022] wherein forming the second semiconductor material directly above the first semiconductor layer includes forming the second semiconductor material directly above the first semiconductor layer in the second region, wherein the conductive dopant having the second semiconductor type in the second semiconductor material formed directly above the first semiconductor layer in the second region provides a dopant for a second current electrode of the second transistor, wherein at least a portion of the second current electrode of the second transistor is located in the second semiconductor material formed directly above the intrinsic base of the second transistor.

[0023] In one or more embodiments, the method further comprises:

[0024] forming an opening in the first semiconductor layer, wherein the sacrificial layer is removed by performing an isotropic etch of the sacrificial material through the opening;

[0025] A contact is formed for the first current electrode of the first transistor, wherein the portion of the second semiconductor material located in the opening in the first semiconductor layer electrically couples the first current electrode of the first transistor to the contact.

[0026] In one or more embodiments, the sacrificial material is characterized as an oxide of a buried oxide layer.

[0027] According to a second aspect of the present invention, there is provided a method for forming a transistor, the method comprising:

[0028] removing sacrificial material directly beneath a first semiconductor layer of the wafer in a first region to form a cavity, the first semiconductor layer comprising a conductive dopant having a first conductivity type, wherein the conductive dopant of the first semiconductor layer in the first region provides a conductive dopant for an intrinsic base of a transistor, wherein at least a portion of the intrinsic base of the transistor is located in the first semiconductor layer in the first region;

[0029] After removing the sacrificial material, forming a second semiconductor material in the cavity directly below the first region of the first semiconductor layer and directly above the first region of the first semiconductor layer, the second semiconductor material including a conductive dopant having a second conductivity type opposite to the first conductivity type, wherein:

[0030] the conductive dopant of the second semiconductor material formed in the cavity having the second semiconductor type provides a dopant for a first current electrode of the transistor, wherein at least a portion of the first current electrode is located in the second semiconductor material formed in the cavity directly below the intrinsic base;

[0031] The conductive dopant of the second semiconductor type of the second semiconductor material formed directly above the first region of the first semiconductor layer provides dopant for a second current electrode of the transistor, wherein at least a portion of the second current electrode is located in the second semiconductor material formed directly above the intrinsic base.

[0032] In one or more embodiments, as a result of the forming of the second semiconductor material, the second semiconductor material formed in the cavity directly below the first region of the first semiconductor layer and the second semiconductor material formed directly above the first region of the first semiconductor layer are adjacent to each other, and the method further includes physically separating the second semiconductor material formed in the cavity directly below the first region of the first semiconductor layer and the second semiconductor material formed directly above the first region of the first semiconductor layer into non-adjacent portions by planarizing the wafer.

[0033] In one or more embodiments, the first transistor is characterized as a heterojunction bipolar transistor.

[0034] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0036] Figure 1-8 is a partial cross-sectional side view of a wafer during various stages of fabricating a semiconductor device in accordance with one embodiment of the present invention.

[0037] Fig. 9 is a partial cross-sectional side view of a wafer during a stage in the fabrication of a semiconductor device according to another embodiment of the present invention.

[0038] Fig.10 The doping configuration of the layers of a transistor after formation according to one embodiment of the present invention is shown.

[0039] Fig.11 The doping configuration of a layer of a transistor after activation of dopants according to one embodiment of the present invention is shown.

[0040] Unless otherwise indicated, the same reference numerals are used in different drawings to indicate the same items. The drawings are not necessarily drawn to scale. DETAILED DESCRIPTION

[0041] The following is a detailed description of at least one mode for carrying out the invention. This description is intended to illustrate the invention and should not be considered limiting.

[0042] Disclosed herein is a process for manufacturing a transistor, the process comprising removing a sacrificial material below a base layer comprising a dopant for an intrinsic base of the transistor. After removing the sacrificial layer to form a cavity directly below the base layer, a semiconductor material is formed in the cavity. The semiconductor layer comprises a dopant for a current electrode of the transistor located directly below the intrinsic base of the transistor. In some embodiments, the semiconductor material is also formed above the intrinsic base during the same process as that used to form the semiconductor material in the cavity. The dopant of the semiconductor material formed above the intrinsic base comprises a dopant for a second current electrode.

[0043] Some types of bipolar transistors, such as heterojunction bipolar transistors (HBTs), can be used for high-speed switching applications. HBTs typically implement different semiconductor material types for the emitter and base regions, forming a heterojunction. Some HBTs can handle very high frequency signals up to hundreds of GHz. HBTs can be used in radio frequency (RF) systems and applications that require high power efficiency, such as in RF power amplifiers for cellular phones.

[0044] Some HBTs and other high performance transistors may require a steeper dopant transition profile toward the intrinsic base to obtain the shortest switching time during operation. However, exposure to high temperatures (e.g., >850°C) during wafer processing may cause dopant diffusion in the current electrode region, thereby reducing the steepness of the current electrode dopant transition profile.

[0045] In some embodiments, removing the sacrificial layer to form a cavity below the base region and then forming a semiconductor material with a current electrode dopant located in the cavity can achieve a method in which the current electrode dopant is not subjected to high processing temperatures that may cause the dopant to diffuse undesirably. Therefore, this process can improve transistor performance. In addition, providing a current electrode with a steeper dopant transition configuration can enable the use of a thinner current electrode region. Providing a thinner current electrode region can shorten carrier transport time, increase transistor switching speed, and reduce the probability of current avalanche and voltage breakdown. Moreover, this process can also reduce the number of selective ion implantation operations.

[0046] Figure 1 1 is a partial cross-sectional side view of a wafer 101 according to one embodiment of the present invention. Wafer 101 includes a substrate 103. Substrate 103 includes a substrate layer 105, which in one embodiment is made of single crystal silicon, but may have other types of semiconductor materials such as SiGe, gallium nitride, or other III-V semiconductor materials.

[0047] The substrate 103 includes a buried oxide layer 113 surrounded by shallow trench isolation structures (STI) 107. In one embodiment, the buried oxide layer 113 has a thickness of less than 100 nm, but may be thicker in other embodiments.

[0048] In the illustrated embodiment, layer 113 is characterized as a local buried oxide (LOBOX) that does not extend across wafer 101. In one embodiment, layer 113 is formed by removing a sacrificial buried SiGe layer (not shown) in substrate 103 to form a cavity, which is then filled with an oxide of layer 113. However, in other embodiments, layer 113 may be formed by other LOBOX processes. In other embodiments, wafer 101 may be a semiconductor-on-insulator (SOI) wafer, in which oxide layer 113 extends across wafer 101. In other embodiments, layer 113 may be made of other types of sacrificial materials.

[0049] Layer 115 is located above layer 113. In one embodiment, layer 115 is made of single crystal silicon and has a thickness of less than 50 nm. However, in other embodiments, layer 115 can have other thicknesses and / or be made of other materials (e.g., SiGe, GaN, other III-V semiconductor materials). In some embodiments, layer 115 is etched to reduce its thickness before forming subsequent layers.

[0050] Layer 111 is formed on layer 115 and STI 107. In one embodiment, layer 111 is formed by an epitaxial process, wherein the portion of layer 111 formed on single crystal silicon layer 115 is single crystal, and the portion formed on STI 107 is polycrystalline or amorphous.

[0051] During the epitaxial process for forming layer 111, precursor materials are adjusted to first form silicon layer 121, silicon germanium layer 122, followed by cap silicon layer 123. In one embodiment, layers 121, 122, and 123 each have a thickness of 10 nm, but may have other thicknesses in other embodiments.

[0052] In one embodiment, layers 122 and 123 are doped with a base dopant (e.g., boron for an NPN bipolar transistor), and layer 122 is doped with carbon. For another discussion of the doping configuration of layer 111 according to one embodiment, see below with respect to Fig.10 In other embodiments, layer 111 may have other configurations, be formed of other materials, include other dopants, and / or be formed by other processes.

[0053] A thin oxide layer (not shown) is formed over layer 111 and patterned to form emitter window etch stops 125 and 127 at the locations of two subsequently formed transistors. Subsequently, a silicon layer 131 is formed over wafer 101 (e.g., by an epitaxial growth process), followed by a nitride layer 133. Layer 131 will be used to form a connecting base structure for subsequently formed transistors. In one embodiment, layers 131 and 133 each have a thickness of 100 nm, but may have other thicknesses in other embodiments.

[0054] Figure 2 1 is a partial cross-sectional side view of wafer 101 after emitter window openings 201 and 205 are formed in layers 133 and 131 to expose etch stops 125 and 127 and collector contact opening 203 is formed in layers 133, 131, 111, and 115 to expose layer 113. In one embodiment, these openings are formed by forming a photolithographic etch mask (not shown) and etching the layers with an appropriate etch chemistry. In other embodiments, openings 201 and 205 may be formed at a separate time from opening 203.

[0055] Figure 3 1 is a partial cross-sectional side view of wafer 101 after sidewall spacers 301, 303, and 305 are formed on the sidewalls of openings 201, 203, and 205, respectively. In the illustrated embodiment, sidewall spacers 301, 303, and 305 are formed by depositing an oxide layer, a nitride layer, and then a subsequent oxide layer (not shown) over wafer 101, wherein the three layers are anisotropically etched to remove portions of the three layers on horizontal surfaces. However, in other embodiments, the sidewall spacers may be formed by different processes and / or from different materials.

[0056] Figure 41 is a partial cross-sectional side view of wafer 101 after etch stops 125 and 127 have been removed to form cavities 401 and 403, respectively, and a portion of oxide layer 113 has been removed to form cavity 401. Cavity 401 extends directly below openings 201 and 205. In one embodiment, the oxide of etch stops 125 and 127 and the oxide of layer 113 are removed by a timed isotropic oxide etch with an etch chemistry that is selective to nitride and silicon. During the removal of etch stops 125 and 127 and layer 113, the outer oxide layer of spacers 301, 303, and 305 is removed, leaving these spacers with only oxide and nitride layers. In one embodiment, the oxide is etched by wet etching. In another embodiment, the oxide is etched by vapor phase HF etching. Because an isotropic etch is used, cavity 401 is symmetrical around opening 203. In other embodiments, etch stops 125 and 127 may be removed at a different time than oxide layer 113. Although in the illustrated embodiment, cavity 401 extends under both emitter openings 201 and 205 , in other embodiments cavity 401 may extend under only one emitter opening or under more than two emitter openings.

[0057] Figure 5 1 is a partial cross-sectional side view of wafer 101 after wafer 101 is subjected to a hydrogen sealing process to fill cavities 401 and 403 with silicon portions 501 and 503, respectively. In one embodiment of the hydrogen sealing process, silicon portions 501 and 503 are formed by subjecting wafer 101 to a low temperature anneal in a hydrogen environment, which promotes mobility of silicon atoms from silicon layer 131 to fill cavities 401 and 403 with silicon. Spacers 301, 303, and 305 prevent silicon from migrating from other portions of the sidewalls of layer 131.

[0058] Figure 6 1 is a partial cross-sectional side view of wafer 101 after a silicon layer 601 is formed by an epitaxial process to cover wafer 101 and fill cavity 401 and partially fill openings 201, 203, and 205. As part of the epitaxial growth process, the portion of layer 601 formed on the semiconductor material (on the top of layer 105, on the bottom side of layer 115, and on the top of layer 111) will be single crystalline. The portion formed on the dielectric (on the sidewalls 301, 303, and 305, and on the nitride layer 133) will be amorphous or polycrystalline.

[0059] Layer 601 is formed in situ for the subsequently formed bipolar transistor ( Figure 8The emitter and collector regions of the transistors 831 and 833 are doped with conductive dopants. In one embodiment where the transistor subsequently formed is an NPN bipolar transistor, the layer 601 is formed with an N-type dopant (e.g., phosphorus, arsenic) to provide conductive dopants for the emitter and collector. In one embodiment, the doping concentration of the N-type dopant is about 1e 20 cm -3 , but may have other concentrations in other embodiments. In other embodiments, openings 201, 203, and 205 may be completely filled with silicon. In other embodiments, layer 601 may be formed of other types of semiconductor materials. In one embodiment, the epitaxial process is a chemical vapor deposition process, but may have other types of epitaxial processes in other embodiments. In one embodiment, the thickness of oxide layer 113 is slightly less than twice the horizontal thickness of layer 601.

[0060] Figure 7 1 is a partial cross-sectional side view of wafer 101 after wafer 101 has been planarized (e.g., by a CMP process) to remove portions of layer 601 on top of nitride layer 133 so as to separate layer 601 into emitter structures 703 and 707 and collector structure 705. In some embodiments, prior to the planarization process, wafer 101 is covered with a blanket oxide layer (not shown) so as to fill the remaining portions of openings 201, 203, and 205. After planarization, the oxide is removed. Separating the emitter structure and the collector structure by planarization provides a simplified process for forming the emitter structure and the collector structure with the same semiconductor growth process.

[0061] Figure 8 1 is a partial cross-sectional side view of wafer 101 after forming silicide and contacts for transistor electrodes. Figure 7 After the nitride layer 133 is patterned to form openings for base contacts (812 and 814) in layer 133. The openings are formed by an anisotropic etch of layer 133 that stops on top of silicon base coupling structures 715 and 717 of silicon layer 131.

[0062] After forming openings to expose the base coupling structures 715 and 717, a silicidation process is performed to form emitter silicide 803, base silicide 821, collector silicide 805, base silicide 823, and emitter silicide 807. In one embodiment of the silicidation process, a metal (e.g., cobalt, nickel, titanium) is deposited over the wafer 101 and then heated (e.g., to 850° C.), where the metal reacts with the exposed portion of silicon to form silicide. The unreacted metal is then removed from the wafer 101.

[0063] After the silicide is formed, a dielectric layer 801 is formed over the wafer 101, for example, by a TEOS process. The layer 801 is then patterned to form openings to expose the silicides 803, 821, 805, 823, and 807. Subsequently, a contact material is formed over the wafer 101 and planarized to form contacts 811-815 in the openings of the layer 801 that contact the silicides 803, 821, 805, 823, and 807, respectively. In one embodiment, the contacts 811-815 are made of tungsten with a titanium liner formed prior to depositing the tungsten. However, in other embodiments, the contacts 811-815 may be made of other materials and / or formed by other processes.

[0064] Prior to silicidation, the wafer 101 is annealed to activate the dopants in the base layer 111, the emitter structures 703 and 705, and the collector structure 705. In one embodiment, the annealing process involves heating the wafer to a high temperature (e.g., 1050° C.) for a short period of time, where the dopants move to substitutional lattice sites in the semiconductor material. During activation, the dopants may diffuse to different layers. For diffusion of dopants after the annealing process, see Fig.11 and the accompanying text below.

[0065] Fig.10 Shows when the layer is formed Figure 8 The doping configuration of the structure. Fig.10 In the configuration of FIG. 1 , the horizontal axis represents the vertical distance of the structures of the wafer 101 (from the bottom portion of the emitter structure 703, the silicon cap layer 123, the SiGe layer 122, the silicon layer 121, and the SOI layer 115 to the top portion of the collector structure 705), and the vertical axis represents the concentration of different elements at the position along the horizontal axis according to one embodiment. Fig.10 As shown in FIG. 1 , because structures 703 and 705 are formed of the same material, they have the same doping concentration of N-type dopant arsenic (As) (eg, 2e 20 cm -3 In addition to having a relatively high concentration of germanium (Ge), the SiGe layer 122 is also doped with carbon (eg, at a concentration of (1e 20 cm -3 )). In addition, the middle portion of the SiGe layer 122 is formed with a high concentration (1e 20 cm -3 ) of the P-type dopant boron. The boron concentration at the upper portion of SiGe layer 122 and in layer 123 is a lower concentration (1e 18 cm -3 ).

[0066] Fig.11 Shows the Fig.10The doping configuration of the same structure shown in FIG. after the annealing process. Fig.10 The doping configuration transition is not vertical, indicating that the dopant has diffused into different layers due to the high temperature annealing. Fig.11 As shown in FIG. 1 , some carbon and germanium diffuse out of layer 123. Boron also diffuses into adjacent layers.

[0067] like Fig.11 As shown in FIG. 1 , arsenic from structure 703 diffuses into layer 123 and slightly into SiGe layer 122. However, for effective transistor performance, the slope of arsenic transition topography portion 1101 relative to structure 703 is still relatively steep. Because structure 705 is formed during the same process and has the same materials as structure 703, the slope of arsenic transition topography portion 1102 relative to structure 705 has the same magnitude as portion 1101.

[0068] If the collector structure 705 is formed before the base layer 111 (layers 121-123), the structure 705 will be subjected to additional high temperature processes, which will cause the arsenic in the structure 705 to diffuse further, so that the arsenic transition profile of the structure 705 will have a shallower slope (as shown by the dashed line 1103). Accordingly, forming the structure 705 after the base layers 121-123 are formed and after other processes (e.g., oxide, spacer, polysilicon and nitride formation and rapid thermal annealing process) can allow the collector structure to have a steeper dopant transition profile to improve transistor performance. For example, the oxide liner oxidation process during the formation of the STI 107 may require a process temperature of about 1100°C.

[0069] In other embodiments, the transistor structure may have other doping configurations and / or other layer configurations. For example, in some embodiments, the doping configuration may be symmetrical across the intrinsic base from structure 703 to structure 705. In this embodiment, layer 121 may be removed, and layer 115 may be thinned so that the distance from structure 703 to SiGe layer 122 is the same as the distance from structure 705 to SiGe layer 122.

[0070] Return to view Figure 8 , the above about Figure 1-8The described process produces two NPN HBT bipolar transistors 831 and 833. Transistor 831 includes a boron-doped intrinsic base 835 in layer 111, an arsenic-doped emitter in emitter structure 703, and an arsenic-doped collector in collector structure 705 directly below the intrinsic base 835. Transistor 833 includes a boron-doped intrinsic base 837 in layer 111, an arsenic-doped emitter in emitter structure 707, and an arsenic-doped collector in collector structure 705 directly below the intrinsic base 837. The collectors of transistors 831 and 833 are electrically connected together through collector structure 705.

[0071] exist Figure 8 After the manufacturing stage shown, subsequent processing can be performed on wafer 101. For example, an upper interconnect layer (not shown) can be formed on top of layer 801 and include conductive structures that are electrically coupled to the substrate for use. Figure 8 The wafer 101 is then singulated into a plurality of semiconductor dies, each having a plurality of semiconductor dies ... Figure 8 The die is then protected in a semiconductor package that can be implemented in an electronic system such as an RF communication device, a motor controller, an automotive electronic system, or a cellular phone. In one example, the transistor is used as a power amplifier to amplify a received RF signal or to amplify an RF signal to be transmitted, such as used in a cellular phone.

[0072] Transistors having other configurations may be formed by the processes described above. Figure 8 In one embodiment, base contacts 812 and 814 may be located outside emitter contacts 811 and 815, rather than between emitter contacts 811 and 815 and collector contact 813. In another embodiment, each transistor may include base contacts on both sides of the emitter contact. In yet another embodiment, emitter structures 703 and 707 may be contiguous, where they laterally surround collector structure 705, such that Figure 8One transistor is shown. In this embodiment, the base contact will wrap around the collector structure 705, or around both the collector structure and the emitter structure. In other embodiments, each transistor will include its own collector structure, which will be physically separated from the other collector structure. In still other embodiments, a deep isolation trench filled with dielectric will be formed through the middle of structure 705, extending as deep as STI 107 to divide collector structure 705 into two collector structures, one for each transistor. In still other embodiments, the opening (203) to expose oxide layer 113 will be located around the emitter opening so that the collector structure will be formed to wrap around the emitter structure. In other embodiments, more than two emitter structures will be formed for each collector structure.

[0073] In one embodiment, Figure 8 The structure can be configured as a Darlington transistor, where the base contact of one transistor (e.g., 812) is electrically connected to the emitter contact of another transistor (e.g., 815). In one embodiment, the electrical connection is made in an interconnect layer above layer 801. In another embodiment, the base contact of one transistor (e.g., 812) is electrically connected to the emitter contact of another transistor (e.g., 815). Figure 8 In other embodiments, Figure 8 The transistor may be configured as other types of devices having a transistor having a collector connected.

[0074] Fig. 9 is a partial cross-sectional side view of wafer 901 according to one embodiment of the present invention. Fig. 9 in Figure 8 Like reference numerals in the drawings indicate similar structures formed by similar methods.

[0075] exist Fig. 9 In the embodiment of FIG. 704 , the emitter of transistor 907 is located in structure 703 and the collector of transistor 907 is located in structure 705. In contrast, the emitter of transistor 909 is located in structure 705 and the collector of transistor 909 is located in structure 707. Structure 705 also serves as an interconnect between the collector of transistor 907 and the emitter of transistor 909. Fig. 9 In the embodiment, there are no contacts to interconnect the structure 705. However, Fig. 9 Other embodiments of the configuration may include contacts for structure 705 .

[0076] As shown in circuit diagram 911, transistors 907 and 909 may be implemented in a cascode configuration, where the collector of one transistor (907) is electrically connected to the emitter of the other transistor (909), for example using a cascode amplifier in Figure 911. In the embodiment of the amplifier of Figure 911, emitter contact 811 is connected to ground, base contact 812 is connected to receive an RF signal (RFIN) to be amplified, base contact 814 is connected to a bias source (VBIAS) for setting the gain of the amplifier, and collector contact 815 is connected to the output (RFOUT) and resistor 915. Structure 705 acts as an inter-stage electrical connector between transistors 907 and 909.

[0077] Accordingly, because the materials of structures 703, 705, and 707 are formed during the same process and from the same semiconductor material, the doping configurations of the current electrode structures located above the intrinsic base (e.g., structures 703 and 707) and the electrode structures located below the intrinsic base (e.g., structure 705) can be similar, so that either type of structure can be configured as an emitter or collector without performance loss due to increased base-emitter capacitance. For some of these embodiments, the processes formed herein can be used to form a cascode device, such as that shown in FIG. 911, which is closer due to reduced contacts for the two current electrodes.

[0078] As described above, forming a current electrode structure having a current electrode dopant located directly below the base layer after the base layer is formed reduces the exposure of the current electrode structure to high temperature processes, which may cause the current electrode dopant to diffuse undesirably, thereby causing the steepness of the current electrode dopant transition configuration to decrease. By reducing undesirable diffusion, transistor switching times can be improved. Also, the probability of avalanche current or voltage breakdown can be reduced.

[0079] Furthermore, forming the current electrodes with the same semiconductor material during the same process can achieve a more uniform transistor device, where the two structures operate at similar efficiencies. Thus, there will be no mismatch in dopant transition configurations, which can reduce transistor efficiency based on the current electrode structure with lower dopant transition configuration steepness. Furthermore, forming the current electrodes with the same semiconductor material during the same process can achieve the ability to interchange the functionality of the current electrodes, thereby allowing one structure to act as a collector or emitter depending on the circuit configuration. The flexibility provided by this capability can achieve more efficient circuit layouts.

[0080] The transistors described herein may have other configurations, have other structures, be made of other materials, and / or may be made by other processes. Figure 8 and 9Each shows an NPN bipolar transistor. However, other types of transistors can be made by the processes described herein. For example, a PNP transistor can be formed in which the collector and emitter have a net P-type conductive doping and the base has a net N-type conductive doping.

[0081] As disclosed herein, a first structure is "directly above" a second structure if the first structure is positioned above the second structure on a line oriented perpendicular to the generally planar major side of a wafer or substrate. Figure 8 , contact 812 is directly above layer 111. Contact 813 is not directly above layer 111. As disclosed herein, a first structure is “directly below” or “directly below” a second structure if the first structure is positioned below the second structure on a line oriented perpendicular to the major side of the generally planar surface of the wafer or substrate. For example, in Figure 8 In FIG. 1 , STI 107 is directly below nitride layer 133. STI 107 is not directly below contact 814. If two other structures are on opposite sides of a structure on a line, then the structure is "directly in the middle" of the two structures on the line. For example, in Figure 8 In the embodiment, the contact 813 is Figure 8 Layer 111 is not directly between contacts 811 and 814. A first structure is "directly transverse to" a second structure if the first structure and the second structure are located on a line parallel to the major side of the general plane of the wafer or substrate. For example, emitter contact 811 and base contact 812 are directly transverse to each other. A structure is "directly between" two structures if two other structures are located on opposite sides of the structure on a line parallel to the major side of the general plane of the wafer or substrate. For example, in Figure 8 , contact 813 is laterally located centered between base contact 812 and emitter contact 815. A surface is at a "higher elevation" than another surface if it is located closer to the top of the active side of the wafer or die on a line oriented perpendicular to the generally planar major side of the wafer or die. Figure 1-9 In the view of FIG. 1 , the active side of the wafer is the top side of the figure. For example, the contact 812 is at a higher elevation than the layer 115.

[0082] The intrinsic base is a region of a bipolar transistor having a net oppositely conductive doping of the emitter and collector, where carriers flow between the emitter and collector in response to carrier flow into the intrinsic base. The collector and emitter are the current electrodes of the bipolar transistor.

[0083] Features specifically shown or described with respect to one embodiment set forth herein may be implemented in other embodiments set forth herein. For example, a particular sealing process disclosed with respect to one embodiment may be implemented in another embodiment.

[0084] One embodiment includes a method for forming a transistor. The method includes removing a sacrificial material directly below a first semiconductor layer in a first region to form a cavity. The first semiconductor layer includes a conductive dopant having a first conductivity type. The conductive dopant of the first semiconductor layer in the first region provides a conductive dopant for an intrinsic base of the transistor in the first region. At least a portion of the intrinsic base of the transistor is located in the first semiconductor layer in the first region. The method includes forming a second semiconductor material in the cavity after removing the sacrificial material. The second semiconductor material includes a conductive dopant having a second conductivity type opposite to the first conductivity type. The conductive dopant of the second semiconductor material formed in the cavity with the second semiconductor type provides a dopant for a first current electrode of the transistor. At least a portion of the first current electrode is located in the second semiconductor material formed in the cavity directly below the intrinsic base.

[0085] Another embodiment includes a method for forming a transistor. The method includes removing a sacrificial material directly below a first semiconductor layer of a wafer located in a first region to form a cavity. The first semiconductor layer includes a conductive dopant having a first conductivity type. The conductive dopant of the first semiconductor layer in the first region provides a conductive dopant for an intrinsic base of the transistor. At least a portion of the intrinsic base of the transistor is located in the first semiconductor layer in the first region. The method includes, after removing the sacrificial material, forming a second semiconductor material in the cavity directly below a first region of the first semiconductor layer and directly above the first region of the first semiconductor layer. The second semiconductor material includes a conductive dopant having a second conductivity type opposite to the first conductivity type. The conductive dopant of the second semiconductor material formed in the cavity with the second semiconductor type provides a dopant for a first current electrode of the transistor. At least a portion of the first current electrode is located in the second semiconductor material formed in the cavity directly below the intrinsic base. The conductive dopant of the second semiconductor material formed directly above the first region of the first semiconductor layer with the second semiconductor type provides a dopant for a second current electrode of the transistor. At least a portion of the second current electrode is located in the second semiconductor material formed directly above the intrinsic base.

[0086] While particular embodiments of the present invention have been shown and described, those skilled in the art will recognize, based on the teachings herein, that further changes and modifications may be made without departing from the present invention and its broader aspects, and therefore, the appended claims are intended to cover within their scope all such changes and modifications that are within the true spirit and scope of the present invention.

Claims

1. A method for forming a transistor, characterized in that The method comprises: removing sacrificial material directly below a first semiconductor layer in a first region to form a cavity, wherein the first semiconductor layer includes a conductive dopant having a first conductivity type, wherein the conductive dopant of the first semiconductor layer in the first region provides a conductive dopant for an intrinsic base of a transistor in the first region, wherein at least a portion of the intrinsic base of the transistor is located in the first semiconductor layer in the first region; After removing the sacrificial material, a second semiconductor material is formed in the cavity, the second semiconductor material including a conductive dopant having a second conductivity type opposite to the first conductivity type, wherein the conductive dopant having the second semiconductor type of the second semiconductor material formed in the cavity provides a dopant for a first current electrode of the transistor, wherein at least a portion of the first current electrode is located in the second semiconductor material formed in the cavity directly below the intrinsic base.

2. The method according to claim 1, characterized in that Also included is forming the second semiconductor material directly above the first semiconductor layer after removing the sacrificial material, wherein the second semiconductor material formed directly above the first semiconductor layer includes a conductive dopant having the second conductivity type, wherein the conductive dopant having the second semiconductor type in the second semiconductor material formed directly above the first semiconductor layer provides a dopant for a second current electrode of the transistor, wherein at least a portion of the second current electrode is located in the second semiconductor material formed directly above the intrinsic base.

3. The method according to claim 2, characterized in that The forming of the second semiconductor material in the cavity and the forming of the second semiconductor material directly above the first semiconductor layer are performed during the same semiconductor formation process.

4. The method according to claim 3, characterized in that The same semiconductor formation process is characterized as an epitaxial process.

5. The method according to claim 3, characterized in that: After performing the same semiconductor process, the second semiconductor material formed in the cavity directly below the first semiconductor layer in the first region and the second semiconductor material formed directly above the first semiconductor layer in the first region are adjacent to each other, and the method further includes physically separating the second semiconductor material formed in the cavity directly below the first semiconductor layer in the first region and the second semiconductor material formed directly above the first semiconductor layer in the first region into non-adjacent parts.

6. The method according to claim 5, characterized in that The physically separating includes a wafer planarization process to remove a portion of the second semiconductor material that physically joins the second semiconductor material formed in the cavity directly below the first semiconductor layer in the first region and the second semiconductor material formed directly above the first semiconductor layer in the first region.

7. The method according to claim 5, characterized in that After the physical separation, a portion of the second semiconductor material adjacent to the second semiconductor material formed in the cavity directly below the first semiconductor layer in the first region is silicided, and a portion of the second semiconductor material adjacent to the second semiconductor material formed directly above the first semiconductor layer in the first region is silicided.

8. The method according to claim 1, characterized in that: The removing of the sacrificial material comprises removing the sacrificial material directly below the first semiconductor layer in the second region, wherein the conductive dopant of the first semiconductor layer in the second region provides a conductive dopant for an intrinsic base of a second transistor in the second region, wherein at least a portion of the intrinsic base of the second transistor is located in the first semiconductor layer in the second region; The conductive dopant of the second semiconductor material having the second semiconductor type formed in the cavity provides a dopant for a first current electrode of the second transistor, wherein at least a portion of the first current electrode of the second transistor is located in the second semiconductor material formed in the cavity directly below the intrinsic base of the second transistor.

9. The method according to claim 1, characterized in that: Also includes: forming an opening in the first semiconductor layer, wherein the sacrificial layer is removed by performing an isotropic etch of the sacrificial material through the opening; A contact is formed for the first current electrode of the first transistor, wherein the portion of the second semiconductor material located in the opening in the first semiconductor layer electrically couples the first current electrode of the first transistor to the contact.

10. A method for forming a transistor, characterized in that The method comprises: removing sacrificial material directly beneath a first semiconductor layer of the wafer in a first region to form a cavity, the first semiconductor layer comprising a conductive dopant having a first conductivity type, wherein the conductive dopant of the first semiconductor layer in the first region provides a conductive dopant for an intrinsic base of a transistor, wherein at least a portion of the intrinsic base of the transistor is located in the first semiconductor layer in the first region; After removing the sacrificial material, forming a second semiconductor material in the cavity directly below the first region of the first semiconductor layer and directly above the first region of the first semiconductor layer, the second semiconductor material including a conductive dopant having a second conductivity type opposite to the first conductivity type, wherein: the conductive dopant of the second semiconductor material formed in the cavity having the second semiconductor type provides a dopant for a first current electrode of the transistor, wherein at least a portion of the first current electrode is located in the second semiconductor material formed in the cavity directly below the intrinsic base; The conductive dopant of the second semiconductor type of the second semiconductor material formed directly above the first region of the first semiconductor layer provides dopant for a second current electrode of the transistor, wherein at least a portion of the second current electrode is located in the second semiconductor material formed directly above the intrinsic base.

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