Si / SiC MOS device with heterojunction and manufacturing method

Abstract

The present invention relates to the field of semiconductor technology, and in particular to a Si / SiC MOS device with a heterojunction and a manufacturing method, the device comprising: a silicon substrate, a silicon region, a silicon carbide region and a gate region; the silicon region is located on the silicon substrate and is used to achieve a high channel mobility of the device; the silicon carbide region is located on the silicon region and is used to make the device have a high breakdown voltage, and also have a low breakdown voltage state under zero gate voltage; the gate region runs through the silicon carbide region in the vertical direction, and the bottom of the gate region is located in the silicon region. The device adopts the structure of Si-SiC heterojunction, and has the advantages of high breakdown voltage of SiC and high channel mobility of Si at the same time, and has the advantages of increasing breakdown voltage, reducing on-resistance and low power consumption, and also has three different states of forward conduction, gate 0V low-voltage breakdown and gate negative voltage being high voltage, and increases the use function under low-voltage conditions, and enhances the use stability of the device under low-voltage conditions.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a Si / SiC MOS device with a heterojunction and a manufacturing method thereof. Background Art

[0002] As a third-generation wide bandgap semiconductor material, silicon carbide (SiC) has excellent properties such as high critical breakdown electric field strength, high electron saturation drift rate and high thermal conductivity, making it an ideal material for making high-power, high-temperature, high-frequency and radiation-resistant devices. Silicon carbide power devices such as SiC MOS (MOSFET, metal oxide semiconductor field effect transistor) devices have performance advantages such as low on-resistance, fast switching speed and high thermal conductivity, which can greatly reduce energy loss and improve system efficiency during power conversion. Therefore, silicon carbide power devices have been widely used in industrial automation, 5G communications, electric vehicles and renewable energy generation.

[0003] Among them, the low on-resistance and high current handling capability of the device are the most critical in practical applications, directly affecting power conversion, as well as the efficiency, size, cost and reliability of the transmission system. Low on-resistance means that the current flowing through the device in the on state encounters less resistance, which will significantly reduce power consumption and heat generation, and improve the energy efficiency of the entire system. In applications such as electric vehicles, solar inverters, and industrial motor drives, the improvement of device and system energy efficiency directly translates into longer battery life, higher energy output ratio or lower operating costs.

[0004] However, the SiC in existing SiC MOS devices has the disadvantage of low channel mobility, which prevents the on-resistance of the device from being further reduced, and the breakdown voltage of SiC fluctuates greatly, resulting in poor stability of low-voltage devices formed by SiC. Summary of the invention

[0005] The embodiments of the present application provide a Si / SiC MOS device with a heterojunction and a manufacturing method, thereby solving the disadvantage of low channel mobility of SiC in the SiC MOS device in the prior art, which makes it impossible to further reduce the on-resistance of the device, and the breakdown voltage of SiC fluctuates greatly, resulting in poor stability of the low-voltage device formed by SiC. The present application adopts a Si-SiC heterojunction structure to achieve the advantages of both high breakdown voltage of SiC and high channel mobility of Si, and has the advantages of increasing breakdown voltage, reducing on-resistance and low power consumption. It also has three different states of forward conduction, gate 0V low-voltage breakdown and gate negative voltage being high voltage, and can be used as a traditional SiC MOS device, and increases the use function under low-voltage conditions, and enhances the technical effects of the stability of the device under low-voltage conditions.

[0006] In a first aspect, an embodiment of the present invention provides a Si / SiC MOS device with a heterojunction, comprising: a silicon substrate, a silicon region, a silicon carbide region, and a gate region;

[0007] The silicon region is located on the silicon substrate and is used to achieve high channel mobility of the device;

[0008] The silicon carbide region is located above the silicon region and is used to enable the device to have a high breakdown voltage and a low breakdown voltage under zero gate voltage;

[0009] The gate region penetrates the silicon carbide region in a vertical direction, and the bottom of the gate region is located in the silicon region.

[0010] Preferably, the silicon region comprises: a silicon epitaxial layer, a P-type base region and an N+ type active region;

[0011] The silicon epitaxial layer is located on the silicon substrate;

[0012] The P-type base region and the N+-type active region are both located in the silicon epitaxial layer, and the upper surface of the P-type base region, the upper surface of the N+-type active region and the upper surface of the silicon epitaxial layer are located in the same horizontal plane;

[0013] The P-type base regions are distributed at intervals;

[0014] The P-type base region and the N+-type active region are arranged in one-to-one correspondence, and the N+-type active region is located in the P-type base region.

[0015] Preferably, the spacing distance between the P-type base regions ranges from 0.6 to 3 um.

[0016] Preferably, the silicon carbide region includes: a P region, a P-type well region and an N-type active region;

[0017] The N-type active region and the N+ type active region are arranged in one-to-one correspondence, and the N-type active region is located on the N+ type active region; the N-type active region is located around the gate region, and the N-type active region is in contact with the gate region;

[0018] The P region is arranged in one-to-one correspondence with the P-type base region, and the P region is located on the P-type base region; the P region is located on a side of the N-type active region away from the gate region, and the P region is in contact with the N-type active region;

[0019] The P-type well region is located in the P region and the N-type active region, and there is a fitting distance between the P-type well region and the gate region in a horizontal direction.

[0020] Preferably, the fitting distance ranges from 50nm to 150nm.

[0021] Preferably, the gate region comprises: a gate trench, a gate oxide layer and gate polysilicon;

[0022] The gate trench penetrates the silicon carbide region in a vertical direction, and the bottom of the gate trench is located in the silicon region;

[0023] The gate oxide layer is located on the bottom wall and the side wall in the gate trench, and is also located above the opening of the gate trench;

[0024] The gate polysilicon is located in a space formed by the gate oxide layer in the gate trench.

[0025] Preferably, it further comprises: a source metal layer; the source metal layer is located on the silicon carbide region, and the source metal layer covers the silicon carbide region and the gate region.

[0026] Preferably, the doping concentration of the N+ type active region is 1e18 / cm 3 -1e19 / cm 3 The doping concentration of the N-type active region is 1e17 / cm 3 -1e18 / cm 3 .

[0027] Preferably, the conductivity type of the silicon substrate and the silicon epitaxial layer is N-type.

[0028] Based on the same inventive concept, in a second aspect, the present invention further provides a method for manufacturing a Si / SiC MOS device with a heterojunction, which is used to manufacture the Si / SiC MOS device with a heterojunction as described in the first aspect, and the manufacturing method comprises:

[0029] forming a silicon region on a silicon substrate, wherein the silicon region is used to achieve high channel mobility of the device;

[0030] forming a silicon carbide region on the silicon region, wherein the silicon carbide region is used to enable the device to have a high breakdown voltage and a low breakdown voltage under zero gate voltage;

[0031] A gate region is formed in the silicon region and the silicon carbide region, the gate region vertically penetrates the silicon carbide region, and a bottom of the gate region is located in the silicon region.

[0032] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0033] The structure of the Si / SiC MOS device of the embodiment of the present invention is a heterojunction structure in which the lower half is a silicon Si region formed by silicon Si material and the upper half is a silicon carbide SiC region formed by silicon carbide SiC material. Among them, the gate region runs through the silicon carbide region in the vertical direction, and the bottom of the gate region is located in the silicon region. The silicon region is a traditional planar gate MOS structure, and the silicon carbide region is a trench-type superjunction structure. Therefore, the conductive channel of the silicon region is Si material, which makes the channel mobility very high, thereby reducing the on-resistance of the device. The silicon carbide region uses SiC material to stabilize the charge balance and improve the breakdown voltage of the device. In addition, through this heterojunction structure, the device has three different states of switching characteristics: positive gate bias conduction (i.e., forward conduction switching characteristics), gate 0V low-voltage breakdown (i.e., at zero gate voltage, low breakdown voltage state) and gate negative voltage (i.e., negative gate bias high-voltage shutdown), and can be used as a traditional SiC MOS device. Furthermore, although the device of the embodiment of the present invention is a high-voltage device, the device also has a low breakdown voltage state, which can be used to discharge the current in the loop and clamp the abnormal overvoltage at a lower level. The low breakdown voltage will not cause damage to the device of the embodiment of the present invention. In this way, through the device structure of the embodiment of the present invention, the use function under low-voltage conditions is increased, and the use stability of the device under low-voltage conditions is enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Also, throughout the accompanying drawings, the same reference figures are used to represent the same components. In the drawings:

[0035] Figure 1 A schematic structural diagram of a Si / SiC MOS device with a heterojunction in an embodiment of the present invention is shown;

[0036] Figure 2 A schematic diagram of the structure of forming a silicon epitaxial layer on a silicon substrate and forming a P-type base region on the silicon epitaxial layer in an embodiment of the present invention is shown;

[0037] Figure 3 A schematic diagram of a structure for forming an N+ type active region on a silicon epitaxial layer in an embodiment of the present invention is shown;

[0038] Figure 4 A schematic diagram of the structure of growing a SiC N-type epitaxial layer in an embodiment of the present invention is shown;

[0039] Figure 5 A schematic diagram of the structure of the etching area for forming the P region and the N-type active region in the embodiment of the present invention is shown;

[0040] Figure 6A schematic diagram showing a structure of forming a P region in an embodiment of the present invention is shown;

[0041] Figure 7 A schematic diagram of the structure of forming a P-type well region in an embodiment of the present invention is shown;

[0042] Figure 8 A schematic structural diagram of a trench region for forming a gate trench in an embodiment of the present invention is shown;

[0043] Fig. 9 A schematic diagram of a structure for forming a gate trench in an embodiment of the present invention is shown;

[0044] Fig.10 A schematic diagram of the structure of growing a gate oxide layer on the sidewalls and bottom wall in a gate trench in an embodiment of the present invention is shown;

[0045] Fig.11 A schematic diagram of the structure of forming gate polysilicon in an embodiment of the present invention is shown;

[0046] Fig.12 A schematic flow chart of the steps of a method for manufacturing a Si / SiC MOS device with a heterojunction in an embodiment of the present invention is shown.

[0047] In the drawings, 100, silicon substrate; 200, silicon region; 300, silicon carbide region; 400, gate region; 500, source metal layer;

[0048] 201, silicon epitaxial layer; 202, P-type base region; 203, N+-type active region;

[0049] 301, P region; 302, P-type well region; 303, N-type active region;

[0050] 401, gate trench; 402, gate oxide layer; 403, gate polysilicon. DETAILED DESCRIPTION

[0051] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0052] Embodiment 1

[0053] The first embodiment of the present invention provides a Si / SiC MOS device with a heterojunction, such as Figure 1 As shown, it includes: a silicon substrate 100, a silicon region 200, a silicon carbide region 300 and a gate region 400;

[0054] The silicon region 200 is located on the silicon substrate 100 and is used to achieve high channel mobility of the device;

[0055] The silicon carbide region 300 is located on the silicon region 200 and is used to make the device have a high breakdown voltage and a low breakdown voltage under zero gate voltage;

[0056] The gate region 400 penetrates the silicon carbide region 300 in a vertical direction, and the bottom of the gate region 400 is located in the silicon region 200 .

[0057] It should be noted that the material of the substrate is generally silicon, and the silicon substrate 100 can be regarded as a part of the silicon region 200 . Figure 1 The silicon substrate 100 is represented by Si N+ sub. The silicon substrate 100 is a heavily N-type doped substrate. The silicon substrate 100 has high stability and reliability.

[0058] The structure of the Si / SiC MOS device of this embodiment is a heterojunction structure of a silicon Si region 200 formed of a silicon Si material in the lower half and a silicon carbide SiC region formed of a silicon carbide SiC material in the upper half. Among them, the gate region 400 penetrates the silicon carbide region 300 in the vertical direction, and the bottom of the gate region 400 is located in the silicon region 200. The silicon region 200 is a traditional planar gate MOS structure, and the silicon carbide region 300 is a trench-type superjunction structure. Therefore, the conductive channel of the silicon region 200 is Si material, which makes the channel mobility very high, thereby reducing the on-resistance of the device. The silicon carbide region 300 has a high breakdown electric field due to the high breakdown electric field of the silicon carbide material, and at the same time, a charge balance is formed through the N-type active region 303, the P region 301 and the oxide layer, which can improve the breakdown voltage of the device. In addition, through this heterojunction structure, the device has three different switching characteristics: positive gate bias conduction (i.e., forward conduction switching characteristics), gate 0V low-voltage breakdown (i.e., low breakdown voltage state under zero gate voltage), and gate negative voltage (i.e., negative gate bias high-voltage shutdown), and can be used as a traditional SiC MOS device. Moreover, although the device of this embodiment is a high-voltage device, the device also has a low breakdown voltage state, which can be used to discharge the current in the loop and clamp the abnormal overvoltage at a lower level. The current discharge power under low breakdown voltage is low, which belongs to soft breakdown and will not cause damage to the device of this embodiment. In this way, through the device structure of this embodiment, the use function under low voltage conditions is increased, and the use stability of the device under low voltage conditions is enhanced.

[0059] Next, combine Figure 1 The structure of the Si / SiC MOS device with heterojunction of this embodiment is described in detail:

[0060] The silicon region 200 includes: a silicon epitaxial layer 201, a P-type base region 202 and an N+ type active region 203. The silicon epitaxial layer 201 is located on the silicon substrate 100. The P-type base region 202 and the N+ type active region 203 are both located in the silicon epitaxial layer 201, and the upper surface of the P-type base region 202, the upper surface of the N+ type active region 203 and the upper surface of the silicon epitaxial layer 201 are located in the same horizontal plane. The P-type base regions 202 are distributed at intervals. The P-type base regions 202 and the N+ type active regions 203 are arranged one by one, and the N+ type active region 203 is located in the P-type base region 202.

[0061] Specifically, Figure 1 As shown, the silicon region 200 includes: a silicon epitaxial layer 201, two P-type base regions 202 and two N+ type active regions 203. The silicon epitaxial layer 201 is located on the silicon substrate 100. The conductivity type of the silicon substrate 100 and the silicon epitaxial layer 201 is N-type. In the accompanying drawings, the silicon epitaxial layer 201 is represented by Si N- epi, the P-type base region 202 is represented by P base, and the N+ type active region 203 is represented by N+. The doping concentration of the silicon epitaxial layer 201 is lower than the doping concentration of the silicon substrate 100. The two P-type base regions 202 and the two N+ type active regions 203 are all located in the silicon epitaxial layer 201, and the upper surface of the P-type base region 202, the upper surface of the N+ type active region 203 and the upper surface of the silicon epitaxial layer 201 are located at the same horizontal plane. The two P-type base regions 202 are spaced apart and distributed in the silicon epitaxial layer 201. Two P-type base regions 202 and two N+-type active regions 203 are arranged in one-to-one correspondence, and each N+-type active region 203 is located in one P-type base region 202, that is, the N+-type active region 203 on the left is located in the P-type base region 202 on the left, and the N+-type active region 203 on the right is located in the P-type base region 202 on the right. The doping concentration range of the N+-type active region 203 is 1e18 / cm 3 -1e19 / cm 3 .

[0062] Among them, the spacing distance between the two P-type base regions 202 ranges from 0.6 to 3 um, and the spacing distance can be selected as 1 um. If the spacing distance range between the P-type base regions 202 is too small, the resistance of the active area of ​​the device will be very large, affecting the forward conductivity of the device. If the spacing distance range between the P-type base regions 202 is too large, when the device is subjected to reverse breakdown, the electric field of the gate oxide will be very large, which will have a negative impact on the gate oxide. Therefore, by setting the spacing distance range between the P-type base regions 202, the contact area between the gate trench 401 of the device and the silicon epitaxial layer 201 is small, thereby reducing the gate-drain capacitance of the device. This enables the device to have excellent switching characteristics.

[0063] The silicon region 200 of this embodiment is a traditional planar gate MOS structure, and the conductive channel of the silicon region 200 is made of Si material, so that the channel mobility is very high, thereby reducing the on-resistance of the device. First, the epitaxial layer is a silicon epitaxial layer 201, and using Si as a substrate is more conducive to the growth of the epitaxial layer. Secondly, the price of the silicon substrate 100 is relatively low, and the resistivity is low, which can reduce production costs and improve product efficiency.

[0064] The silicon carbide region 300 includes: a P region 301, a P-type well region 302, and an N-type active region 303. The N-type active region 303 is arranged in a one-to-one correspondence with the N+-type active region 203, and the N-type active region 303 is located above the N+-type active region 203. The N-type active region 303 is located around the gate region 400, and the N-type active region 303 is in contact with the gate region 400. The P region 301 is arranged in a one-to-one correspondence with the P-type base region 202, and the P region 301 is located above the P-type base region 202. The P region 301 is located on a side of the N-type active region 303 away from the gate region 400, and the P region 301 is in contact with the N-type active region 303. The P-type well region 302 is located in the P-type well region 302 and the N-type active region 303, and there is a fitting distance between the P-type well region 302 and the gate region 400 in the horizontal direction.

[0065] Specifically, Figure 1 As shown, the silicon carbide region 300 includes: two P regions 301, two P-type well regions 302 and two N-type active regions 303. In the figure, the P region 301 is represented by P, the P-type well region 302 is represented by P well, and the N-type active region 303 is represented by N. The two N-type active regions 303 are arranged in a one-to-one correspondence with the two N+ type active regions 203, and each N-type active region 303 is located on an N+ type active region 203. The doping concentration of the N-type active region 303 is 1e17 / cm 3 -1e18 / cm 3 The width of the N-type active region 303 may be 1 um, and the width of the P region 301 may be 0.5 um. In terms of space, the N-type active region 303 is located around the gate region 400, and the N-type active region 303 is in contact with the gate region 400. Specifically, the N-type active region 303 is located around the gate trench 401 of the gate region 400, and the N-type active region 303 is in contact with the gate trench 401 of the gate region 400. Figure 1 In the cross-sectional structure diagram shown, the two N-type active regions 303 are respectively located on both sides of the gate region 400 (specifically, the gate trench 401 of the gate region 400 ), and one side of each N-type active region 303 close to the gate region 400 (specifically, the gate trench 401 of the gate region 400 ) is in contact with the gate region 400 .

[0066] The two P regions 301 are arranged in one-to-one correspondence with the two P-type base regions 202, and each P region 301 is located on a P-type base region 202. In terms of space, the P region 301 surrounds the N-type active region 303, and the P region 301 is in contact with the N-type active region 303. Figure 1 In the cross-sectional structure diagram shown, the P region 301 on the left is located on the left side of the N-type active region 303 on the left, and the P region 301 on the left is in contact with the side of the N-type active region 303 on the left that is away from the gate region 400. The P region 301 on the right is located on the right side of the N-type active region 303 on the right, and the P region 301 on the right is in contact with the side of the N-type active region 303 on the right that is away from the gate region 400.

[0067] Each P-type well region 302 is located in the P region 301 and the N-type active region 303. Figure 1 As shown, the P-type well region 302 on the left is located in the P region 301 on the left and the N-type active region 303 on the left, and the P-type well region 302 on the right is located in the P region 301 on the right and the N-type active region 303 on the right. Each P-type well region 302 is a whole, located in the P region 301 and the N-type active region 303. There is a fitting distance between the P-type well region 302 and the gate region 400 in the horizontal direction. The fitting distance is specifically the distance between the P-type well region 302 and the gate oxide layer 402 on the inner wall of the gate region 400 in the horizontal direction.

[0068] Among them, the range of the fitting distance is 50nm-150nm. The small fitting distance indicates that the gate oxide layer 402 on the inner wall of the P-type well region 302 and the gate region 400 is not completely fitted or tightly fitted. In this way, the P-type well region 302 is a normally open conductive channel, and there is no need to consider the channel mobility, so that the device has a positive gate biased conduction state. When the device is in the on state, the gate will not prevent the current from passing when the gate is zero biased, but will be blocked by the P-type base region 202P base in the silicon region 200 below, and the breakdown voltage of silicon Si is low. Therefore, the device will have a low breakdown voltage state, so that the device of this embodiment is also suitable for low-voltage applications.

[0069] If the fitting distance is too small, it means that the P-type well region 302 is too close to the gate oxide layer 402 on the inner wall of the gate region 400, then the P-type well region 302 is in a zero gate normally closed state, and does not have a zero gate bias low voltage shutdown effect, and if the doping concentration of the P-type well region 302 is too high, a positive gate voltage normally closed state will also appear, and it does not have a conduction function. If the fitting distance is too large, it means that the P-type well region 302 is too far from the gate oxide layer 402 on the inner wall of the gate region 400, and the device does not have a negative gate voltage shutdown characteristic. Among them, when the device is in a negative gate voltage state, the P-type well region 302 that was not originally bonded to the gate oxide layer 402 will diffuse to the gate oxide layer 402 area due to the negative pressure, so that the P-type well region 302 can be closed. The device can use the SiC barrier layer (i.e., SiC region) to withstand pressure, and the pressure resistance is greatly improved. In addition, the distance between the P-type well region 302 and the gate oxide layer 402 on the opening of the gate trench 401 is in the range of 0.5-1 um.

[0070] The silicon carbide region 300 of this embodiment is a trench-type superjunction structure, which improves the breakdown voltage of the device. Through the heterojunction structure formed by the silicon carbide region 300 and the silicon region 200, the device has three different switching characteristics of positive gate bias conduction (i.e., forward conduction switching characteristics), gate 0V low-voltage breakdown (i.e., under zero gate voltage, low breakdown voltage state) and gate negative voltage (i.e., negative gate bias high-voltage turn-off characteristics), and can be used as a traditional SiC MOS device. In addition, although the device of this embodiment is a high-voltage device, the device also has a low breakdown voltage state, which can be used to discharge the current in the loop and clamp the abnormal overvoltage at a lower level. The low breakdown voltage will not cause damage to the device of this embodiment. In this way, through the device structure of this embodiment, the use function under low-voltage conditions is increased, and the use stability of the device under low-voltage conditions is enhanced.

[0071] The gate region 400 includes: a gate trench 401, a gate oxide layer 402 and a gate polysilicon 403. The gate trench 401 vertically penetrates the silicon carbide region 300, and the bottom of the gate trench 401 is located in the silicon region 200. The gate oxide layer 402 is located on the bottom wall and side walls in the gate trench 401, and is also located above the opening of the gate trench 401. The gate polysilicon 403 is located in the space formed by the gate oxide layer 402 in the gate trench 401. Among them, the material of the gate oxide layer 402 is silicon dioxide, and the material of the gate polysilicon 403 is polysilicon.

[0072] The device of this embodiment further includes: a source metal layer 500. The source metal layer 500 is located on the silicon carbide region 300, and the source metal layer 500 covers the silicon carbide region 300 and the gate region 400. Figure 1 As shown, the source metal layer 500 covers the N-type active region 303 , the P region 301 , the gate trench 401 , the gate oxide layer 402 on the opening of the gate trench 401 , and the like.

[0073] The following is an explanation of the manufacturing process of the device of this embodiment:

[0074] like Figure 2 As shown, a suitable silicon epitaxial layer 201 is grown on the silicon substrate 100. The doping concentration and thickness of the silicon epitaxial layer 201 can be set according to actual needs. For example, the thickness of the silicon epitaxial layer 201 can be in the range of 4-5um, and the doping concentration of the silicon epitaxial layer 201 is 5e16 / cm 3 A barrier layer is grown on the silicon epitaxial layer 201, and the barrier layer is etched by photoresist to form an implantation region of the P-type base region 202. Aluminum Al+ ions are then implanted into the implantation region to form the P-type base region 202Pbase.

[0075] like Figure 3 As shown, a self-aligned sidewall is grown on the silicon epitaxial layer 201, and N-type ions are implanted in the self-aligned sidewall to obtain an N+ type active region 203. Next, the barrier layer and the sidewall are removed.

[0076] like Figure 4 As shown, a SiC N-type epitaxial layer is grown on the silicon epitaxial layer 201. The thickness of the SiC N-type epitaxial layer is in the range of 10-15 um. Figure 5 As shown, a barrier layer (i.e. Figure 5 The green layer material above the SiC N-type epitaxial layer in the middle), and the barrier layer is etched by photoresist to the surface of the silicon epitaxial layer 201 to form the etched area of ​​the P region 301 and the N-type active region 303. Figure 6 As shown, the etched area of ​​the P region 301 is filled until the surface of the SiC N-type epitaxial layer is filled to obtain the P region 301. In essence, the SiC N-type epitaxial layer is an N-type active region 303.

[0077] like Figure 7 As shown, a barrier layer is grown on the N-type active area 303, and the barrier layer is etched by photoresist to form an implantation area of ​​P well, and high-energy ion implantation is performed on the implantation area to form a P-type well area 302P well. Then the barrier layer is removed. The thickness range of P well is 2-3um, and the doping concentration range of P well is 1e18 / cm 3 -5e18 / cm 3 .

[0078] like Figure 8 As shown, a barrier layer is grown on the N-type active region 303, and the barrier layer is etched by photoresist to form a trench region of the gate trench 401. Fig. 9As shown in FIG. 4 , the trench region is etched to form a gate trench 401. Fig.10 As shown, an oxide layer is grown on the sidewalls and bottom wall of the gate trench 401 to obtain a gate oxide layer 402. Fig.11 As shown, polysilicon is filled in the space formed by the gate oxide layer 402 in the gate trench 401 to form gate polysilicon 403. Then, the gate oxide layer 402 is filled on the opening of the gate trench 401. The thickness of the gate oxide layer 402 on the opening of the gate trench 401 is in the range of 1-2 um. Figure 1 As shown, a source metal is filled on the silicon carbide region 300 to form a source metal layer 500 .

[0079] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0080] The structure of the Si / SiC MOS device of this embodiment is a heterojunction structure in which the lower half is a silicon Si region formed by silicon Si material and the upper half is a silicon carbide SiC region formed by silicon carbide SiC material. Among them, the gate region runs through the silicon carbide region in the vertical direction, and the bottom of the gate region is located in the silicon region. The silicon region is a traditional planar gate MOS structure, and the silicon carbide region is a trench-type superjunction structure. Therefore, the conductive channel of the silicon region is Si material, which makes the channel mobility very high, thereby reducing the on-resistance of the device. The silicon carbide region uses SiC material to stabilize the charge balance and improve the breakdown voltage of the device. In addition, through this heterojunction structure, the device has three different states of switching characteristics: positive gate bias conduction (i.e., forward conduction switching characteristics), gate 0V low-voltage breakdown (i.e., at zero gate voltage, low breakdown voltage state) and gate negative voltage (i.e., negative gate bias high-voltage shutdown), and can be used as a traditional SiCMOS device. Furthermore, although the device of this embodiment is a high-voltage device, the device also has a low breakdown voltage state, which can be used to discharge the current in the loop and clamp the abnormal overvoltage at a lower level. The low breakdown voltage will not cause damage to the device of this embodiment. In this way, through the device structure of this embodiment, the use function under low voltage conditions is increased, and the use stability of the device under low voltage conditions is enhanced.

[0081] Embodiment 2

[0082] Based on the same inventive concept, the second embodiment of the present invention further provides a method for manufacturing a Si / SiC MOS device with a heterojunction, such as Fig.12 As shown, for manufacturing a Si / SiC MOS device with a heterojunction as shown in the first embodiment, the manufacturing method includes:

[0083] S201, forming a silicon region on a silicon substrate, wherein the silicon region is used to achieve high channel mobility of the device;

[0084] S202, forming a silicon carbide region on the silicon region, wherein the silicon carbide region is used to enable the device to have a high breakdown voltage and a low breakdown voltage under zero gate voltage;

[0085] S203 , forming a gate region in the silicon region and the silicon carbide region, wherein the gate region vertically penetrates the silicon carbide region, and a bottom of the gate region is located in the silicon region.

[0086] Since the method for manufacturing the Si / SiC MOS device with a heterojunction introduced in this embodiment is the method for manufacturing the Si / SiC MOS device with a heterojunction in the first embodiment of the present application, based on the Si / SiC MOS device with a heterojunction introduced in the first embodiment of the present application, the technicians in this field can understand the specific implementation method and various variations of the method for manufacturing the Si / SiC MOS device with a heterojunction in this embodiment, so how the method for manufacturing the Si / SiC MOS device with a heterojunction implements the Si / SiC MOS device with a heterojunction in the first embodiment of the present application is not described in detail here. As long as the technicians in this field implement the method for manufacturing the Si / SiC MOS device with a heterojunction in the first embodiment of the present application, it belongs to the scope of protection of the present application.

[0087] Those skilled in the art will appreciate that, although the preferred embodiments of the present invention have been described, those skilled in the art, once informed of the basic creative concept, may make additional changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0088] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A Si / SiC MOS device with a heterojunction, characterized in that: include: Silicon substrate, silicon region, silicon carbide region and gate region; The silicon region is located on the silicon substrate and is used to achieve high channel mobility of the device; The silicon carbide region is located above the silicon region and is used to enable the device to have a high breakdown voltage and a low breakdown voltage under zero gate voltage; The gate region penetrates the silicon carbide region in a vertical direction, and the bottom of the gate region is located in the silicon region; The silicon region includes: a silicon epitaxial layer, a P-type base region and an N+ type active region; The silicon epitaxial layer is located on the silicon substrate; The P-type base region and the N+-type active region are both located in the silicon epitaxial layer, and the upper surface of the P-type base region, the upper surface of the N+-type active region and the upper surface of the silicon epitaxial layer are located in the same horizontal plane; The P-type base regions are distributed at intervals; The P-type base region and the N+-type active region are arranged in one-to-one correspondence, and the N+-type active region is located in the P-type base region; The silicon carbide region includes: a P region, a P-type well region and an N-type active region; The N-type active region and the N+ type active region are arranged in one-to-one correspondence, and the N-type active region is located on the N+ type active region; the N-type active region is located around the gate region, and the N-type active region is in contact with the gate region; The P region is arranged in one-to-one correspondence with the P-type base region, and the P region is located on the P-type base region; the P region is located on a side of the N-type active region away from the gate region, and the P region is in contact with the N-type active region; The P-type well region is located in the P region and the N-type active region, and there is a fitting distance between the P-type well region and the gate region in a horizontal direction; The device is used to form a heterojunction structure through a silicon carbide region and a silicon region, so that the device has switching characteristics in three different states: positive gate bias conduction, gate 0V low voltage breakdown and gate negative voltage, and discharges the current in the circuit in the low breakdown voltage state.

2. The device according to claim 1, characterized in that The spacing distance of the P-type base regions ranges from 0.6 to 3 um.

3. The device according to claim 1, characterized in that The range of the bonding distance is 50nm-150nm.

4. The device according to claim 1, characterized in that The gate region includes: a gate trench, a gate oxide layer and a gate polysilicon; The gate trench penetrates the silicon carbide region in a vertical direction, and the bottom of the gate trench is located in the silicon region; The gate oxide layer is located on the bottom wall and the side wall in the gate trench, and is also located above the opening of the gate trench; The gate polysilicon is located in a space formed by the gate oxide layer in the gate trench.

5. The device according to claim 1, characterized in that Also includes: source metal layer; The source metal layer is located on the silicon carbide region, and the source metal layer covers the silicon carbide region and the gate region.

6. The device according to claim 1, characterized in that The doping concentration of the N+ type active region is 1e18 / cm 3 -1e19 / cm 3 The doping concentration of the N-type active region is 1e17 / cm 3 -1e18 / cm 3 .

7. The device according to claim 1, characterized in that The conductivity type of the silicon substrate and the silicon epitaxial layer is N type.

8. A method for manufacturing a Si / SiC MOS device having a heterojunction, characterized in that: A method for manufacturing a Si / SiC MOS device having a heterojunction as claimed in any one of claims 1 to 7, the method comprising: forming a silicon region on a silicon substrate, wherein the silicon region is used to achieve high channel mobility of the device; forming a silicon carbide region on the silicon region, wherein the silicon carbide region is used to enable the device to have a high breakdown voltage and a low breakdown voltage under zero gate voltage; A gate region is formed in the silicon region and the silicon carbide region, the gate region vertically penetrates the silicon carbide region, and a bottom of the gate region is located in the silicon region.

Images