Array substrate and display panel

Abstract

The present application belongs to the field of display technology, specifically to an array substrate and a display panel. The array substrate includes a base substrate, a pixel electrode block, a common electrode block, a scan line, a touch signal line, a switching structure, and a signal shielding line. The orthographic projection of each common electrode block on the base substrate covers the orthographic projection of at least one pixel electrode block on the base substrate. The signal shielding line and the touch signal line are arranged at intervals in the vertical direction. The switching structure includes a connecting block, a first via structure, and a second via structure. One end of the connecting block is connected to the touch signal line through the first via structure, and the other end of the connecting block is connected to the signal shielding line through the second via structure. The present application solution can reduce or eliminate the light leakage problem of the scan line, ensure the pixel aperture ratio, and improve the display effect.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and specifically relates to an array substrate and a display panel. Background Art

[0002] With the development of the times and the advancement of technology, people are not only demanding on the functionality of electronic products, but also increasingly demanding on their appearance. This has promoted the continuous development of electronic products towards being lighter, thinner, narrower and more energy-efficient.

[0003] Emerging from the times, in-cell touch displays incorporate touch electrodes within the pixel structure. These electrodes are connected via wires to a circuit that detects changes in capacitance across the electrodes to determine whether a corresponding location on the touch display has been touched. In-cell designs, light leakage from the scan lines is a common problem. Summary of the Invention

[0004] The purpose of the present application is to provide an array substrate and a display panel that can reduce or eliminate the light leakage problem of the scanning line and ensure the pixel aperture ratio.

[0005] According to a first aspect of the present application, an array substrate is provided, comprising a base substrate and pixel electrode blocks, common electrode blocks, scan lines, and touch signal lines provided on the base substrate, wherein the touch signal lines, the pixel electrode blocks, and the common electrode blocks are all formed on a side of the scan lines away from the base substrate, a plurality of the pixel electrode blocks and the common electrode blocks are provided, and are arranged in an array at intervals along row and column directions, the pixel electrode blocks and the common electrode blocks are arranged at intervals in a thickness direction of the base substrate, and the orthographic projection of each common electrode block on the base substrate covers the orthographic projection of at least one pixel electrode block on the base substrate;

[0006] The scanning line extends in the row direction and is located between two adjacent rows of pixel electrode blocks;

[0007] The touch signal lines are provided in plurality and arranged at intervals from each other, and each of the touch signal lines is connected to a common electrode block, and the touch signal lines transmit common signals to the common electrode blocks when no touch is performed;

[0008] The array substrate further includes a transfer structure and a signal shielding line, wherein the signal shielding line and the touch signal line are arranged at intervals in the thickness direction of the base substrate, and the transfer structure includes a connecting block, a first via structure, and a second via structure, wherein one end of the connecting block is connected to the touch signal line through the first via structure, and the other end of the connecting block is connected to the signal shielding line through the second via structure;

[0009] In which, the discontinuity formed between two adjacent common electrode blocks in the row direction is defined as a row discontinuity, the orthographic projection of the row discontinuity on the substrate overlaps with the orthographic projection of the scanning line on the substrate, and the orthographic projection of the row discontinuity on the substrate is covered by the orthographic projection of the signal shielding line on the substrate.

[0010] In an exemplary embodiment of the present application, the connection block and the pixel electrode block are arranged in the same layer and are spaced apart from each other.

[0011] In an exemplary embodiment of the present application, the pixel electrode block is provided on a side of the common electrode block away from the base substrate, the pixel electrode block is a slit electrode including a plurality of electrode strips arranged at intervals, and the common electrode block is a planar electrode.

[0012] In an exemplary embodiment of the present application, the signal shielding line is provided on a side of the common electrode block away from the base substrate, and forms an insulating layer with the common electrode block.

[0013] In an exemplary embodiment of the present application, the array substrate further includes a first insulating layer, the first insulating layer covers the signal shielding line, the second via structure is provided on the first insulating layer, and the pixel electrode block is provided on a side of the first insulating layer away from the base substrate.

[0014] In an exemplary embodiment of the present application, the signal shielding line is provided with a covering area on a side away from the second via structure, and the orthographic projection of the covering area on the base substrate covers the orthographic projection of the active layer on the base substrate.

[0015] In an exemplary embodiment of the present application, the orthographic projection of the common electrode block on the base substrate covers the orthographic projections of at least two pixel electrode blocks on the base substrate.

[0016] In an exemplary embodiment of the present application, the array substrate further includes a plurality of data lines, the data lines extending in the column direction, and the plurality of data lines being arranged in a spaced relationship with each other in the row direction.

[0017] The touch signal line and the data line are in the same layer and spaced apart from each other. The touch signal line is insulated from the common electrode block and is connected to the common electrode block through a third via structure.

[0018] In an exemplary embodiment of the present application, the array substrate includes a plurality of pixel units arranged in an array along row and column directions, each of the pixel units includes a plurality of pixel electrode blocks arranged at intervals in the column direction, the color resistance colors corresponding to any adjacent pixel electrode blocks in the column direction are different, and each pixel electrode block in the same pixel unit is connected to the data line in the same column and is respectively connected to the scanning line of the corresponding row.

[0019] In a second aspect of the present application, a display panel includes:

[0020] a counter substrate;

[0021] a liquid crystal layer; and

[0022] In any of the above array substrates, the counter substrate and the array substrate are arranged in a cell-type arrangement, and the liquid crystal layer is arranged between the counter substrate and the array substrate.

[0023] The array substrate and display panel of the present application have at least the following beneficial effects:

[0024] The array substrate includes a base substrate and scan lines, pixel electrode blocks, common electrode blocks, touch signal lines, a switching structure, and a signal shielding line disposed on the base substrate. The orthographic projection of the common electrode block on the base substrate overlaps the orthographic projection of at least one pixel electrode block on the base substrate. There is a row discontinuity between two adjacent common electrode blocks in the row direction. The orthographic projection of the row discontinuity on the base substrate overlaps the orthographic projection of the scan line on the base substrate. The orthographic projection of the signal shielding line on the base substrate overlaps the orthographic projection of the row discontinuity on the base substrate. The switching structure includes a connecting block and a first via structure and a second via structure. One end of the connecting block is connected to the touch signal line via the first via structure, and the other end is connected to the signal shielding line via the second via structure. The signal in the touch signal line is transmitted to the signal shielding line through the connecting block. The signal in the signal shielding line can weaken or shield the high-level signal generated by the scan line, thereby eliminating the signal generated by the scan line that interferes with liquid crystal deflection, ensuring normal liquid crystal deflection, reducing or eliminating light leakage caused by the scan line, and improving the display effect of the display panel. In addition, the signal shielding line is used to block the light leakage problem generated by the scanning line, and the size of the black matrix does not need to be increased to block the light leakage generated by the scanning line, thereby ensuring the pixel aperture ratio.

[0025] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by practice of the present application.

[0026] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0028] Figure 1 It shows a schematic diagram of the structure in which the signal shielding lines provided in the first to fifth embodiments of the present application are arranged at row discontinuities;

[0029] Figure 2 It shows a schematic structural diagram of a common electrode block corresponding to two or more pixel electrode blocks provided in Embodiments 1 to 5 of the present application;

[0030] Figure 3 It shows a schematic structural diagram of the connection between the touch signal line and the common electrode block provided by the first to fifth embodiments of the present application;

[0031] Figure 4 Schematic diagrams showing the arrangement structures of red sub-pixels, green sub-pixels, and blue sub-pixels provided in Examples 1 to 5 of the present application are shown;

[0032] Figure 5 It shows a schematic structural diagram of the row discontinuity between adjacent common electrode blocks provided by the first to fifth embodiments of the present application located on a scan line;

[0033] Figure 6 It shows a schematic structural diagram of the common electrode block provided in Embodiments 1 to 5 of the present application using a full-surface design;

[0034] Figure 7 Shown Figure 6 Schematic diagram of the cross-sectional structure along the C-C' line;

[0035] Figure 8 Shown Figure 1 Schematic diagram of the cross-sectional structure along the middle line B-B';

[0036] Figure 9 Shown Figure 1 Schematic diagram of the cross-sectional structure along the middle line A-A';

[0037] Figure 10 It shows a structural schematic diagram of a main shielding wire provided in the second or fifth embodiment of the present application, in which a first extension wire is provided at one end thereof;

[0038] Figure 11 A schematic structural diagram showing a common electrode block corresponding to two or more pixel electrode blocks provided in the second or fifth embodiment of the present application;

[0039] Figure 12 Shown Figure 10 Schematic diagram of the cross-sectional structure along the middle line D-D';

[0040] Figure 13 A schematic structural diagram showing the support pillars and the array substrate provided in the first or fifth embodiment of the present application are arranged opposite to each other at a first extension line;

[0041] Figure 14 It shows a structural schematic diagram of a second extension line provided at one end of the main shielding line provided in the third or fifth embodiment of the present application;

[0042] Figure 15 A schematic structural diagram showing a common electrode block corresponding to two or more pixel electrode blocks provided in the third or fifth embodiment of the present application;

[0043] Figure 16 Shown Figure 14 Schematic diagram of the cross-sectional structure along the E-E' line;

[0044] Figure 17 A schematic diagram of the structure in which the support pillars and the array substrate provided in the third or fifth embodiment of the present application are arranged opposite each other where the shielding area is provided;

[0045] Figure 18 A schematic diagram showing a structure in which the signal shielding wire provided in the fourth or fifth embodiment of the present application is connected to the common electrode block through a conductive via;

[0046] Figure 19 A schematic structural diagram showing a common electrode block corresponding to two or more pixel electrode blocks provided in the fourth or fifth embodiment of the present application;

[0047] Figure 20 A schematic structural diagram of a display panel provided in Example 3 of the present application is shown.

[0048] Description of reference numerals:

[0049] 10. Display panel; 100. Array substrate; 110. Base substrate; 120. Scan line; 130. Data line; 140. Touch signal line; 150. Subpixel; 150a. Red subpixel; 150b. Green subpixel; 150c. Blue subpixel; 151. Transistor; 1510. Gate; 1511. Active layer; 1512. First electrode; 1513. Second electrode; 152. Pixel electrode block; 1520. First electrode strip; 1521. First edge electrode strip; 1522. Second edge electrode strip; 1523. Connector; 160. Common electrode block; 170 , signal shielding line; 171, first extension line; 172, second extension line; 1720, covering area; 180, gate insulation layer; 190, row interruption; 1100, transfer structure; 1101, connecting block; 1102, first via structure; 1103, second via structure; 1110, first insulating layer; 1120, flat layer; 1130, second insulating layer; 1140, third insulating layer; 200, opposing substrate; 210, base; 220, supporting column; 300, liquid crystal layer; M, third via structure; N1, first overlapping area; N2, second overlapping area; P, conductive via. DETAILED DESCRIPTION

[0050] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0051] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically specified.

[0052] In this application, unless otherwise specified or limited, terms such as "assembly" and "connection" should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0053] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0054] Example 1

[0055] Embodiment 1 of the present application provides an array substrate 100, which is applied to an in-cell touch display panel 10. The display panel 10 may employ Fringe Field Switching (FFS) technology. The display panel 10 employing FFS technology has the advantages of fast response time, high light transmittance, and wide viewing angle.

[0056] See also Figures 1 to 3 As shown, the array substrate 100 may include a base substrate 110 and scan lines 120, data lines 130, touch signal lines 140, sub-pixels 150, common electrode blocks 160 and signal shielding lines 170 arranged on the base substrate 110. The data lines 130, touch signal lines 140, common electrode blocks 160 and signal shielding lines 170 are all formed on the side of the scan lines 120 away from the base substrate 110.

[0057] The base substrate 110 may be a glass substrate, but is not limited thereto, and may also be a substrate made of other materials, such as PI material.

[0058] A plurality of pixel units are disposed on the base substrate 110 . The plurality of pixel units may be arranged in an array along a row direction X and a column direction Y on the base substrate 110 .

[0059] Among them, see Figure 4 As shown, each pixel unit includes a plurality of sub-pixels 150 arranged at intervals in the column direction Y. The color resist colors corresponding to any two adjacent sub-pixels 150 in the column direction Y are different, that is, adjacent sub-pixels 150 in the same pixel unit correspond to different colors. Furthermore, the sub-pixels 150 in the same pixel unit are all connected to the same column data line 130, and the sub-pixels 150 in the same pixel unit are respectively connected to the corresponding row scan lines 120.

[0060] For example, see Figure 4As shown, a pixel unit may include a red sub-pixel 150a, a green sub-pixel 150b, and a blue sub-pixel 150c. The red sub-pixel 150a, the green sub-pixel 150b, and the blue sub-pixel 150c are arranged sequentially in the column direction Y. The red sub-pixel 150a, the green sub-pixel 150b, and the blue sub-pixel 150c correspond to different color resists, namely, red, green, and blue resists, respectively. The red sub-pixel 150a, the green sub-pixel 150b, and the blue sub-pixel 150c within the same pixel unit share the same data line 130. The red sub-pixel 150a, the green sub-pixel 150b, and the blue sub-pixel 150c within the same pixel unit are respectively connected to three different scan lines 120. That is, by using a three-gate 1510 transistor 151, the number of scan lines 120 is tripled compared to the solution in which three sub-pixels 150 are spaced apart in the row direction X within the pixel unit. The number of scan lines 120 increases, and the number of source driver chips is reduced by 2 / 3, thereby achieving the purpose of cost saving.

[0061] It should be noted that each pixel unit may include not only the three sub-pixels 150 mentioned above, but also four or more sub-pixels 150 . The specific design may be based on different embodiments and is not specifically limited here.

[0062] See Figure 1 As shown, each sub-pixel 150 may include a transistor 151, and the transistor 151 may include a gate 1510, an active layer 1511, and a first electrode 1512 and a second electrode 1513 arranged on the same layer. A gate insulating layer 180 may be provided between the gate 1510 and the active layer 1511 to insulate the gate 1510 and the active layer 1511 from each other; and the first electrode 1512 and the second electrode 1513 may be overlapped with the source and drain doping regions of the active layer 1511, respectively. Specifically, the corresponding connection relationship between the first electrode 1512 and the second electrode 1513 and the source and drain doping regions of the active layer 1511 can be determined according to whether the transistor 151 is N-type or P-type, that is, one of the first electrode 1512 and the second electrode 1513 is the source and the other is the drain.

[0063] For example, the transistor 151 of the embodiment of the present application may be a bottom-gate type, that is, the gate 1510 may be first formed on the substrate 110; then, a gate insulating layer 180 is formed on the substrate 110, and the gate insulating layer 180 covers the gate 1510; then, an active layer 1511 is formed on the side of the gate insulating layer 180 away from the substrate 110, that is, the active layer 1511 is located on the side of the gate 1510 away from the substrate 110, and the active layer 1511 and the gate 1510 are on the substrate substrate. There is overlap in the orthographic projections on the plate 110. For example, the orthographic projection of the active layer 1511 on the base substrate 110 may be located within the orthographic projection of the gate 1510 on the base substrate 110; the first pole 1512 and the second pole 1513 may be formed after the active layer 1511 is formed, and at least a portion of the first pole 1512 may overlap on one doped region of the source and drain doped regions of the active layer 1511; at least a portion of the second pole 1513 may overlap on another doped region of the source and drain doped regions of the active layer 1511.

[0064] It should be noted that the transistor 151 in the embodiment of the present application is not limited to the bottom-gate type mentioned above, but can also be a top-gate type.

[0065] The scan line 120 may extend in the row direction X, wherein the scan line 120 may be connected to the gate 1510 of the transistor 151 to control the on / off state of the transistor 151. Alternatively, the scan line 120 may be provided in the same layer as the gate 1510 of the transistor 151 and may be integrally connected.

[0066] In this application, "same-layer arrangement" refers to the use of the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through a single patterning process. That is, one patterning process corresponds to one mask (also called a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses. This simplifies the manufacturing process, saves manufacturing costs, and improves production efficiency.

[0067] For example, the scanning line 120 may be made of metal or alloy materials, such as molybdenum, aluminum, and titanium, to ensure good electrical conductivity, but is not limited thereto and may also be made of other materials with good electrical conductivity.

[0068] See Figure 1 and Figure 2As shown, the data line 130 may extend in the column direction Y, wherein the data line 130 may be connected to the second electrode 1513 of the transistor 151 to write a data signal to the second end of the transistor 151. Alternatively, the data line 130 may be provided in the same layer as the second electrode 1513 of the transistor 151 and integrally connected.

[0069] The data line 130 may be made of metal or alloy materials, such as molybdenum, aluminum, and titanium, to ensure good electrical conductivity, but is not limited thereto and may also be made of other materials with good electrical conductivity.

[0070] See Figure 1 and Figure 4 As shown, each sub-pixel 150 further includes a pixel electrode block 152, and within the same pixel unit, the color resist corresponding to any two adjacent pixel electrode blocks 152 is different in color. The pixel electrode block 152 can be connected to the first electrode 1512 of the transistor 151. When the transistor 151 is turned on in response to the scan signal provided by the scan line 120, the data signal provided by the data line 130 can flow into the first electrode 1512 of the transistor 151 through the second electrode 1513, thereby being written to the pixel electrode block 152, thereby forming a voltage difference with the common voltage on the opposite substrate 200 side of the display panel 10, thereby causing the liquid crystal molecules between the opposite substrate 200 and the array substrate 100 to deflect, thereby achieving the display function.

[0071] The pixel electrode block 152 of the embodiment of the present application may be a transparent electrode. For example, it may be made of ITO (indium tin oxide) material to improve light transmittance, but is not limited thereto and may also be made of other transparent conductive materials.

[0072] For example, the pixel electrode block 152 can be formed after the first electrode 1512 and the second electrode 1513 of the transistor 151 are formed, and an insulating layer can be provided between the pixel electrode block 152 and the metal layer where the first electrode 1512 and the second electrode 1513 of the transistor 151 are located, and the pixel electrode block 152 can be connected to the first electrode 1512 of the transistor 151 through a via passing through this insulating layer.

[0073] In the column direction Y, see Figure 5 As shown, the above-mentioned scan line 120 is provided between two adjacent rows of pixel electrode blocks 152 , that is, the scan line 120 is located between two adjacent pixel electrode blocks 152 in the column direction Y.

[0074] See also Figure 3 and Figure 5As shown, the common electrode blocks 160 are multiplexed as touch electrode blocks. Multiple common electrode blocks 160 are arranged in an array in the row direction X and the column direction Y. The common electrode blocks 160 and the pixel electrode blocks 152 are arranged alternately in the vertical direction. The common electrode blocks 160 can be arranged above the pixel electrode blocks 152, or the pixel electrode blocks 152 can be arranged above the common electrode blocks 160.

[0075] In the examples of this application, see Figure 7 As shown, the common electrode block 160 is disposed below the pixel electrode block 152, and an insulating layer is provided between the common electrode block 160 and the pixel electrode block 152. In this embodiment, the pixel electrode block 152 is a slit electrode comprising a plurality of spaced electrode strips, i.e., slits are provided at positions corresponding to the opening areas.

[0076] For example, see Figure 1 As shown, this pixel electrode block 152 includes a first electrode strip 1520, a first edge electrode strip 1521, a second edge electrode strip 1522 and a connecting portion 1523. The multiple first electrode strips 1520 are arranged at intervals in the column direction Y, and slits are formed between adjacent first electrode strips 1520; the first edge electrode strip 1521 is provided at one end of the multiple first electrode strips 1520 and is connected to the ends of the multiple first electrode strips 1520; the second edge electrode strip 1522 is provided at the other end of the multiple first electrode strips 1520 and is connected to the ends of the multiple first electrode strips 1520; the connecting portion 1523 is connected to the side of the second edge electrode strip 1522 away from the first electrode strip 1520, and this connecting portion 1523 is connected to the first pole 1512 through a via.

[0077] It is worth mentioning that see Figure 6 and Figure 7 As shown, the common electrode block 160 can be a planar electrode. The orthographic projection of the common electrode block 160 on the base substrate 110 at least covers the orthographic projection of one pixel electrode block 152 on the base substrate 110 , that is, the common electrode block 160 corresponds to at least one pixel electrode block 152 .

[0078] An optional embodiment, see Figure 1 As shown, the orthographic projection of a common electrode block 160 on the base substrate 110 covers the orthographic projection of a pixel electrode block 152 on the base substrate 110 , that is, the common electrode block 160 corresponds to the pixel electrode block 152 one-to-one.

[0079] Another optional embodiment, see Figure 2 、 Figure 6 and Figure 7As shown, the orthographic projection of a common electrode block 160 on the base substrate 110 covers the orthographic projections of two or more pixel electrode blocks 152 on the base substrate 110 , that is, one common electrode block 160 corresponds to two or more pixel electrode blocks 152 .

[0080] See Figure 3 As shown, in order to achieve touch control, a plurality of touch signal lines 140 are provided on the array substrate 100. The plurality of touch signal lines 140 are arranged in sequence and spaced apart in the row direction X. The touch signal lines 140 are connected to the common electrode blocks 160 in a one-to-one correspondence to transmit touch signals to the common electrode blocks 160.

[0081] It is worth mentioning that the touch signal line 140 and the common electrode block 160 are arranged in the thickness direction of the base substrate 110, that is, the touch signal line 140 and the common electrode block 160 are arranged in the vertical direction. An insulating layer is provided between the common electrode block 160 and the touch signal line 140. The touch signal line 140 is connected to the common electrode block 160 through the second via structure 1103 penetrating the insulating layer to transmit the touch signal. Figure 3 shown.

[0082] The touch signal line 140 and the first electrode 1512 may be provided in the same layer, and the two may be spaced apart from each other to avoid interference between the touch signal line 140 and the first electrode 1512 , thereby ensuring touch and display effects.

[0083] The touch signal line 140 can be made of the same material as the data line 130 , and can be made of metal or alloy materials, such as molybdenum, aluminum, and titanium, to ensure good conductivity, but is not limited thereto, and can also be made of other materials with good conductivity.

[0084] It is understandable that disposing the touch signal line 140 and the first electrode 1512 in the same layer can reduce the film layer designed for the touch signal line 140 , reduce the thickness of the array substrate 100 , and further reduce the thickness of the display panel 10 .

[0085] See also Figure 5 As shown, in order to avoid short circuits between adjacent common electrode blocks 160, adjacent common electrode blocks 160 are discontinuously formed 190, and the discontinuity formed between two adjacent common electrode blocks 160 in the row direction X is defined as a row discontinuity 190. That is, there is a row discontinuity 190 between two adjacent common electrode blocks 160 in the column direction Y.

[0086] See also Figure 5As shown, in order to increase the aperture ratio, the line break 190 is disposed on the scan line 120 , that is, the orthographic projection of the line break 190 on the base substrate 110 overlaps with the orthographic projection of the scan line 120 on the base substrate 110 . In other words, a portion of the scan line 120 is exposed at the line break 190 .

[0087] The signal inputted by the scan line 120 is a high-level signal, which may interfere with the voltage signal of the pixel electrode block 152 , thereby affecting the deflection angle of the liquid crystal, thereby causing light leakage.

[0088] See also Figure 1 and Figure 8 As shown, in order to eliminate or reduce the light leakage problem generated by the scan line 120 , the present application utilizes a signal shielding line 170 to shield the high-level signal of the scan line 120 .

[0089] In addition, see Figure 9 As shown, the array substrate 100 also includes a transfer structure 1100, which includes a connecting block 1101, a first via structure 1102 and a second via structure 1103. One end of the connecting block 1101 is electrically connected to the touch signal line 140 through the first via structure 1102, and the other end of the connecting block 1101 is connected to the signal shielding line 170 through the second via structure 1103.

[0090] See also Figure 8 As shown, the orthographic projection of the signal shield line 170 on the base substrate 110 overlaps the orthographic projection of the line break 190 on the base substrate 110. Furthermore, the signal shield line 170 is connected to the adjacent touch signal line 140 via a connecting block 1101. The touch signal line 140 typically carries a common signal. Therefore, the signal shield line 170 receives the common signal transmitted by the touch signal line 140 and uses the signal shield line 170, which receives the common signal, to shield the scan signal of the scan line 120. Specifically, the signal shield line 170 covers the line break 190 and transmits the common signal transmitted by the touch signal line 140 to the signal shield line 170. This weakens or shields the high-level signal of the scan line 120, reducing or eliminating the impact of the high-level signal on the liquid crystal molecules in the scan line 120, preventing the high-level signal from causing deflection of the liquid crystal molecules, and thereby reducing or eliminating light leakage from the scan line 120.

[0091] It is worth mentioning that the orthographic projection of this signal shielding line 170 on the base substrate 110 may or may not overlap with the orthographic projections of the two adjacent common electrode blocks 160 on the base substrate 110. The signal shielding line 170 can completely cover the line break 190 so as to shield the scanning line 120 exposed by the line break 190.

[0092] In addition, the touch signal line 140 can transmit a common signal to the common electrode block 160 when no touch is performed, so as to transmit the common signal to the signal shielding line 170 .

[0093] In some embodiments of the present application, the orthographic projection of the signal shielding line 170 on the base substrate 110 overlaps with the orthographic projections of two adjacent common electrode blocks 160 on the base substrate 110, and the width of the overlapping region in the column direction may be the same or different. By having an overlapping region between the signal shielding line 170 and the two adjacent common electrode blocks 160, the high-level signal of the scan line 120 can be better shielded, preventing the scan line 120 from directly affecting the pixel electrode block 152, and reducing or eliminating light leakage from the scan line 120.

[0094] In the embodiment of the present application, the connection block 1101 and the pixel electrode block 152 are in the same layer and spaced apart, that is, the connection block 1101 and the pixel electrode block 152 are spaced apart from each other and formed on the base substrate 110 using the same film forming process. The connection block 1101 and the pixel electrode block 152 are made of the same material.

[0095] It is understandable that the connection block 1101 may also be made of other materials and not be disposed on the same layer as the pixel electrode block 152. Alternatively, the connection block 1101 may be made of other materials and be disposed on the same layer as the pixel electrode block 152.

[0096] It is worth mentioning that see Figure 1 and Figure 2 As shown, in the row direction X: the edge of the signal shielding line 170 close to the transistor 151 exceeds the edge of the second edge electrode strip 1522 to reduce the light leakage problem of the scan line 120 at the edge of the adjacent common electrode block 160, thereby ensuring the shielding effect of the scan line 120.

[0097] In the examples of this application, see Figure 8 and Figure 9 As shown, the array substrate 100 also includes a first insulating layer 1110, a flat layer 1120, a second insulating layer 1130 and a third insulating layer 1140. The first insulating layer 1110 is formed between the signal shielding line 170 and the pixel electrode block 152, the second insulating layer 1130 is formed between the signal shielding line 170 and the common electrode block 160, and the flat layer 1120 and the third insulating layer 1140 are formed between the common electrode block 160 and the touch signal line 140. The third insulating layer 1140 is arranged on the side of the flat layer 1120 close to the base substrate 110, that is, the flat layer 1120 is arranged above the third insulating layer 1140.

[0098] In an embodiment of the present application, the first insulating layer 1110 adopts a composite, single-layer or stacked-layer structure of silicon nitride (SiOx) and silicon oxide (SiNx), and can reduce the capacitance between the gate 1510 and the pixel electrode block 152, thereby improving the quality of the display panel 10; the flattening layer 1120 adopts an organic acrylic material, which can play a flat and insulating role, so that the common electrode block 160 has a flattened design on the entire surface.

[0099] Understandably, see Figure 8 As shown, this flat layer 1120 is arranged between the third insulating layer 1140 and the common electrode block 160, which can enhance the shielding effect of the signal shielding line 170 on the scanning line 120, and further weaken the deflection of the liquid crystal molecules by the high-level signal of the scanning line 120, so as to reduce the light leakage problem caused by the scanning line 120 and improve the display effect of the display panel 10.

[0100] The third insulating layer 1140 covers the touch signal line 140 and the data line 130 . To ensure that the touch signal line 140 is connected to the common electrode, a third via structure M is opened on the flat layer 1120 and the third insulating layer 1140 to ensure that the common electrode block 160 is connected to the touch signal line 140 .

[0101] The second insulating layer 1130 covers the common electrode block 160 . The signal shielding line 170 is disposed on a side of the second insulating layer 1130 away from the base substrate 110 .

[0102] The second insulating layer 1130 and the third insulating layer 1140 can both be made of silicon nitride (SiOx) or silicon oxide (SiNx).

[0103] The signal shielding line 170 in the present application solution connects the signal shielding line 170 and the touch signal line 140 through the connecting block 1101, and transmits the common signal in the touch signal line 140 to the signal shielding line 170. The signal shielding line 170 is used to shield the scanning line 120 exposed by the upper discontinuity 190 of the adjacent common electrode block 160, thereby reducing or eliminating the influence of the high-level signal of the scanning line 120 on the pixel electrode block 152, thereby reducing or eliminating the light leakage problem caused by the scanning line 120; moreover, by using the signal shielding line 170 to shield the scanning line 120, it is not necessary to widen the size of the black matrix (BM), and the size of the pixel electrode block 152 can be designed to be larger, thereby improving the pixel aperture ratio.

[0104] Example 2

[0105] See also Figures 10 to 13As shown, the difference between the second embodiment of the present application and the first embodiment is that the signal shielding line 170 extends a first extension line 171 at one end close to the touch signal line 140 connected thereto, and the first extension line 171 extends in the row direction X and is the same as the extension direction of the scan line 120.

[0106] The counter substrate 200 disposed opposite to the array substrate 100 includes a base 210 and support columns 220 disposed on the base 210 . The support columns 220 extend vertically toward the base substrate 110 to support the cell gap between the array substrate 100 and the counter substrate 200 .

[0107] Among them, see Figure 12 and Figure 13 As shown, the height of the array substrate 100 at the location where the first extension line 171 is provided is greater than the height of the array substrate 100 at the location where the first extension line 171 is not provided. The support column 220 abuts the area corresponding to the first extension line 171 of the array substrate 100, that is, the support column 220 and the area corresponding to the first extension line 171 are aligned. This prevents the support column 220 from directly contacting the alignment film in the opening area, ensuring normal alignment of the liquid crystal molecules in the opening area. Furthermore, because the height of the array substrate 100 at the location where the first extension line 171 is provided is greater than the height of the array substrate 100 at the location where the first extension line 171 is not provided, even if the support column 220 slides off the area corresponding to the first extension line 171, the liquid crystal is still supported, preventing scratches on the alignment film of the array substrate 100, avoiding the problem of starry sky, and improving the quality of the display panel 10.

[0108] It is understandable that the height of the overlapping region between the touch signal line 140 and the first extension line 171 is higher than the height of the first extension line 171 not located in the overlapping region of the touch signal line 140 .

[0109] In the embodiment of the present application, the support column 220 abuts the overlapping area of ​​the first extension line 171 and the touch signal line 140. The array substrate 100 aligns the support column 220 at the overlapping area of ​​the first extension line 171 and the touch signal line 140. The support column 220 does not directly contact the alignment film in the opening area, thereby preventing scratches on the alignment film in the opening area and avoiding the problem of star-shaped spots. In this way, the signal shielding line 170 and the first extension line 171 can prevent light leakage from the scan line 120 while also preventing scratches on the alignment film on the array substrate 100, thereby improving the quality of the display panel 10.

[0110] Example 3

[0111] See also Figure 14 and Figure 17As shown, the difference between the third embodiment of the present application and the second embodiment is that the signal shielding line 170 is further provided with a second extension line 172 at one end away from the touch signal line 140 connected thereto, and the extension direction of the second extension line 172 is the same as the extension direction of the scanning line 120, and a covering area 1720 is provided on the second extension line 172, and the orthographic projection of the covering area 1720 on the base substrate 110 covers the orthographic projection of the active layer 1511 on the base substrate 110.

[0112] This covering area 1720 can completely cover and protect the channel area of ​​the transistor 151, thereby preventing the etching solution from penetrating into the active layer 1511 due to cracks or loose films in the flat layer 1120, the second insulating layer 1130 and the third insulating layer 1140 when preparing the common electrode block 160 and the pixel electrode block 152, thereby affecting the characteristics of the transistor 151.

[0113] In addition, the height of the area with the covering area 1720 is greater than the height of the area without the covering area 1720. The covering area 1720 can correspond to the support pillars 220 on the opposing substrate 200. The support pillars 220 can be aligned with the area where the covering area 1720 is provided on the array substrate 100. In this way, even if the support pillars 220 slide down from the area corresponding to the covering area 1720, the liquid crystal is still supported, and the alignment film of the array substrate 100 will not be scratched, thus avoiding the problem of starry sky, and improving the quality of the display panel 10.

[0114] The present application solution can shield the scanning signal of the scanning line 120 through the signal shielding line 170 and the covering area 1720, while also aligning the support column 220 to prevent the support column 220 from scratching the alignment film in the opening area, thereby ensuring the alignment stability of the liquid crystal molecules. It can also avoid the etching solution from damaging the active layer 1511 when preparing the common electrode block 160 and the pixel electrode block 152, thereby improving the characteristics of the transistor 151.

[0115] Example 4

[0116] See also Figures 18 and 19 As shown, the difference between the fourth embodiment of the present application and the first embodiment is that the signal shielding line 170 is used to connect to the common electrode block 160 instead of the touch signal line 140. This can reduce the size of the touch signal line 140 as much as possible and increase the area of ​​the pixel opening area.

[0117] In the embodiment of the present application, part of the common electrode block 160 is connected to the signal shielding line 170 through a conductive via P. Since the orthographic projection of the signal shielding line 170 on the base substrate 110 is located within the orthographic projection of the scanning line 120 on the base substrate 110, the conductive via P can be set within the orthographic projection of the scanning line 120 on the base substrate 110. In this way, it is possible to avoid opening the conductive via P on the touch signal line 140. The size of the main touch line can be designed to be smaller, thereby reducing the excessive space occupied by the touch signal line 140 and ensuring the pixel aperture ratio.

[0118] For example, the signal shielding line 170 is disposed on a side of the common electrode block 160 away from the base substrate 110. A second insulating layer 1130 is disposed between the signal shielding line 170 and the common electrode block 160. A conductive via P is formed in the second insulating layer 1130, exposing a portion of the common electrode block 160. The signal shielding line 170 is connected to the common electrode block 160 via the conductive via P. In the column direction Y, a first of two adjacent common electrode blocks 160 and an orthographic projection of the signal shielding line 170 on the base substrate 110 have a first overlapping region N1, and are connected at the first overlapping region N1 via the conductive via P penetrating the second insulating layer 1130. Furthermore, in the column direction Y, a second of the two adjacent common electrode blocks 160 and the signal shielding line 170 have a second overlapping region N2, and the width of the second overlapping region N2 in the column direction is smaller than the width of the first overlapping region N1 in the column direction. Specifically, the orthographic projection of the signal shielding line 170 on the base substrate 110 and the orthographic projection of the common electrode block 160 to which it is connected on the base substrate 110 have a first overlapping region N1, and the conductive via P is located within the first overlapping region N1. The signal shielding line 170 utilizes this first overlapping region N1 to both shield the scan line 120 and connect to the common electrode block 160.

[0119] It is understandable that arranging the conductive via P at the overlapping area between the signal shielding line 170 and the common electrode block 160 can reduce the size of the main touch line, thereby reducing the space occupied by the touch signal line 140 on the base substrate 110 and ensuring the pixel aperture ratio.

[0120] In the embodiment of the present application, the touch signal line 140 is electrically connected to the driver chip to receive touch signals transmitted by the driver chip. The common electrode block 160 near the driver chip is defined as the end common electrode block 160, and the touch signal line 140 correspondingly connected to the end common electrode block 160 is defined as the end touch signal line 140. The end touch signal line 140 is connected to the end common electrode block 160. That is, in the column direction Y, the common electrode block 160 near the driver chip is connected to the touch signal line 140, and the signal shielding line 170 is not used to connect to the common electrode block 160. This ensures the connection with the common electrode block 160, reduces the use of the signal shielding line 170, ensures the touch effect, and reduces production costs.

[0121] Example 5

[0122] See also Figure 20 As shown, the fifth embodiment of the present application provides a display panel 10, which may be a liquid crystal display panel 10. The display panel 10 may include the array substrate 100 described in the first embodiment, which will not be repeated here. Figure 20 As shown, in addition, the display panel 10 further includes an opposite substrate 200 arranged in a cell with the array substrate 100 and a liquid crystal layer 300 located between the array substrate 100 and the opposite substrate 200 .

[0123] The counter substrate 200 may include a glass substrate and a color resist layer, a BM layer, a common electrode plate, an alignment film, a support column 220, etc. formed on the glass substrate, which will not be described in detail here. The support column 220 corresponds to the signal shielding line 170, which can prevent the support column 220 from directly contacting the alignment film in the opening area of ​​the array substrate 100, thereby avoiding scratching the alignment film in the pixel opening area, ensuring the alignment of the liquid crystal molecules, and avoiding the problem of starry sky, such as Figure 13 or Figure 17 shown.

[0124] Among them, this support column 220 can be aligned with one of the first extension line 171 in Example 2 or the second extension line 172 in Example 3 to avoid scratching the alignment film on the side of the array substrate 100, ensure the alignment effect on the liquid crystal molecules, and improve the display quality of the display panel 10.

[0125] In some embodiments, the first extension line 171 and the second extension line 172 on the array substrate 100 side correspond to different support pillars 220 , and the first extension line 171 and the second extension line 172 correspond to different support pillars 220 and abut against them.

[0126] It is worth mentioning that the color resist layer on the opposite substrate 200 side may also be provided on the array substrate 100 , depending on the specific situation.

[0127] The BM layer shields the scan lines 120 , the data lines 130 , the touch signal lines 140 and the signal shielding lines 170 to avoid affecting the image display.

[0128] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0129] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent application.

Claims

1. An array substrate comprising a base substrate and pixel electrode blocks, common electrode blocks, scan lines, and touch signal lines disposed on the base substrate, wherein the touch signal lines, the pixel electrode blocks, and the common electrode blocks are all formed on a side of the scan lines away from the base substrate, characterized in that: A plurality of pixel electrode blocks and common electrode blocks are provided, and are arranged in an array at intervals along the row direction and the column direction. The pixel electrode blocks and the common electrode blocks are arranged at intervals in the thickness direction of the base substrate, and the orthographic projection of each common electrode block on the base substrate covers at least the orthographic projection of one pixel electrode block on the base substrate. The scanning line extends in the row direction and is located between two adjacent rows of pixel electrode blocks; The touch signal lines are provided in plurality and arranged at intervals from each other, and each of the touch signal lines is connected to a common electrode block, and the touch signal lines transmit common signals to the common electrode blocks when no touch is performed; The array substrate further includes a transfer structure and a signal shielding line, wherein the signal shielding line and the touch signal line are arranged at intervals in the thickness direction of the base substrate, and the transfer structure includes a connecting block, a first via structure, and a second via structure, wherein one end of the connecting block is connected to the touch signal line through the first via structure, and the other end of the connecting block is connected to the signal shielding line through the second via structure; In which, the discontinuity formed between two adjacent common electrode blocks in the row direction is defined as a row discontinuity, the orthographic projection of the row discontinuity on the substrate overlaps with the orthographic projection of the scanning line on the substrate, and the orthographic projection of the row discontinuity on the substrate is covered by the orthographic projection of the signal shielding line on the substrate.

2. The array substrate according to claim 1, wherein: The connection block and the pixel electrode block are arranged in the same layer and are spaced apart from each other.

3. The array substrate according to claim 1 or 2, wherein: The pixel electrode block is arranged on a side of the common electrode block away from the base substrate. The pixel electrode block is a slit electrode including a plurality of electrode strips arranged at intervals, and the common electrode block is a planar electrode.

4. The array substrate according to claim 3, wherein: The signal shielding line is arranged on a side of the common electrode block away from the base substrate, and a second insulating layer is formed between the signal shielding line and the common electrode block.

5. The array substrate according to claim 4, wherein: The array substrate further includes a first insulating layer, the first insulating layer covers the signal shielding line, the second via structure is provided on the first insulating layer, and the pixel electrode block is provided on a side of the first insulating layer away from the base substrate.

6. The array substrate according to claim 1, wherein: The signal shielding line is provided with a second extension line at one end away from the touch signal line connected thereto. The second extension line is provided with a covering area. The orthographic projection of the covering area on the base substrate covers the orthographic projection of the active layer on the base substrate.

7. The array substrate according to claim 1, wherein: The orthographic projection of the common electrode block on the base substrate covers the orthographic projections of at least two pixel electrode blocks on the base substrate.

8. The array substrate according to claim 1, wherein: The array substrate further includes a plurality of data lines, the data lines extending in the column direction, and the plurality of data lines being arranged at intervals with each other in the row direction; The touch signal line and the data line are in the same layer and spaced apart from each other. The touch signal line is insulated from the common electrode block and is connected to the common electrode block through a third via structure.

9. The array substrate according to claim 8, wherein: The array substrate includes a plurality of pixel units arranged in an array along row and column directions, each of the pixel units includes a plurality of pixel electrode blocks arranged at intervals in the column direction, the color resistance colors corresponding to any adjacent pixel electrode blocks in the column direction are different, and each pixel electrode block in the same pixel unit is connected to the data line in the same column and is respectively connected to the scan line in the corresponding row.

10. A display panel, characterized in that: include: a counter substrate; liquid crystal layer; as well as According to the array substrate according to any one of claims 1 to 9, the counter substrate and the array substrate are arranged in a box, and the liquid crystal layer is arranged between the counter substrate and the array substrate.

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