Correction method for pre-estimating program execution time

Abstract

The invention discloses a correction method for pre-estimating program execution time. The correction method comprises the following steps: S1, acquiring a frequency vector BBV and an execution clock cycle of each interval of a program; s2, dimensionality reduction is carried out on the BBV, and then clustering is carried out on vectors after dimensionality reduction by adopting Kmeans; s3, training a machine learning fitting model; s4, for the new architecture, re-collecting the number of execution clock cycles of the clustering center; and performing model estimation to obtain delta cyclei of each interval, and adding the delta cyclei with the number of execution clock cycles of the clustering center to obtain an estimated value of the number of execution clock cycles of the interval under the new architecture. According to the method, the correlation between the program execution behavior and the time interval is fully utilized, the accuracy of program performance prediction after the processor architecture is changed can be effectively improved, meanwhile, the calculation overhead of re-simulation is reduced, and the high precision of the pre-estimated execution time is ensured.

Description

Technical Field

[0001] The present invention belongs to the field of computer system architecture, and in particular relates to a correction method for estimating program execution time. Background Art

[0002] With the rapid development of computer technology, the complexity of processors continues to increase, and the number of transistors on a single-chip processor has reached 10 billion. Building such a complex computer system is not only technically challenging, but also very time- and economically expensive. The design and manufacture of processors involve multiple stages, each of which may need to be repeated, resulting in a whole cycle of several years and huge costs. The traditional development model relies on manufacturing samples for testing, and redesign and production are required after defects are found, further increasing the burden of time and cost. In order to solve this problem, in the design and manufacture of modern processor chips, software is usually used to simulate the functions and performance characteristics of processor hardware at the system structure level, and then evaluate and verify the processor chip, thereby reducing R&D costs and shortening the iteration cycle.

[0003] At present, the main difficulties in using architecture software simulation technology for performance evaluation are as follows:

[0004] 1. Simulation speed. The simulator needs to gradually simulate the behavior of the hardware in the software. When evaluating new design solutions, it takes a lot of time to simulate the operation of the processor. This long simulation limits the possibility of fast iteration and real-time feedback to a certain extent. For development teams that need to frequently modify and evaluate designs, this is undoubtedly a significant bottleneck.

[0005] 2. Simulation accuracy. Software simulation usually involves abstraction and simplification of hardware behavior. This abstraction inevitably introduces a certain degree of error, resulting in deviations between simulation results and real hardware in certain performance indicators. Although simulation technology can provide a preliminary evaluation of design solutions, in actual applications, these deviations may affect the accuracy of design decisions.

[0006] The research and development of architecture software simulation technology has a long history, and simulator research is very active both at home and abroad. In China, NEMU is a high-performance RISC-V instruction set interpreter that has attracted much attention. Its speed can reach 1GIPS (Xu Y, Yu Z, Tang D, et al. Towards Developing High Performance RISC-V Processors Using Agile Methodology [C]. 2022 55th IEEE / ACM International Symposium on Microarchitecture (MICRO), 2022, 1178-1199.); abroad, GEM5 is a widely used architecture-level simulator for computer system structure research and system software development. Its accuracy can be accurate to the clock cycle level (Binkert N, Beckmann B, Black G, et al. The gem5 simulator [J]. SIGARCH Comput. Archit. News, 2011, 39 (2): 1-7., Lowe-Power J, Ahmad AM, Akram A, et al. The gem5 simulator: Version 20.0+ [J]. arXiv preprint arXiv:2007.03152, 2020.).

[0007] The simulator needs to have the characteristics of fast running speed, high simulation accuracy, and flexible configuration modification, but these requirements are contradictory and difficult to achieve at the same time. In order to make a better compromise between simulation speed and accuracy, a variety of simulation acceleration technologies have been developed, among which the most representative technology is sampling simulation technology. Sampling simulation technology intercepts a small part of the program for simulation and uses it as an approximation of the simulation result of the entire program. If the sampled program fragment can represent the entire program, higher accuracy can be obtained. Common sampling methods include random sampling, SMARTS and SimPoint, among which SMARTS is a periodic sampling of the entire program (REWunderlich, TFWenisch, B.Falsafi and JCHoe,

[0008] "SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling," 30th Annual International Symposium on Computer Architecture, 2003.), SimPoint first finds the phase of program execution, where the phase represents the repeated behavior of the program during execution, and then samples and simulates the part representing each phase. This sampling method greatly reduces the simulation time (Sherwood T, Perelman E, Hamerly G, et al. Automatically characterizing large scale program behavior[J]. SIGARCH Comput. Archit. News, 2002, 30(5): 45-57.).

[0009] SimPoint is a technology that simplifies processor performance simulation and is currently widely used in performance evaluation of new processor architectures. It significantly speeds up simulation by reducing the number of workloads that need to be simulated. The basic principle of SimPoint is based on the similarity in program execution. Usually, the execution behavior of a program in different time periods is similar. This similarity means that the performance of the entire program can be estimated by selecting certain representative fragments without simulating the entire execution process. The core concept of SimPoint is to divide the program execution into multiple similar fragments, and then select representative fragments for detailed simulation. SimPoint usually divides the program into multiple fragments according to the number of instruction executions, and then classifies all fragments through a clustering algorithm, and then selects the most representative fragment from each class, called SimPoint.

[0010] The main steps of SimPoint are as follows:

[0011] (1) Collect BBV (Basic Block Vectors). A basic block in a program consists of a series of continuous instructions that do not contain jump instructions. SimPoint cuts the program into segments (intervals) with the same number of executed instructions. When the simulator executes the program, it counts the number of instructions executed in each basic block in each interval. All these values ​​form a vector, namely the Basic Block Vector. Assuming that the number of basic blocks in the program is n, the dynamic execution information of each interval is represented as an n-dimensional vector. Assuming that the program is divided into m intervals, the dynamic execution information of the entire program can be represented as the matrix A. m×n .

[0012] (2) Clustering. The basic block vector corresponding to each row in BBV represents the statistical value of the number of instructions executed by each basic block in an interval. If the value of each element in two basic block vectors is exactly the same, then executing the instruction stream of these two intervals and executing the instruction stream of one of the intervals twice are exactly the same in statistical terms. When clustering, Manhattan distance is used to measure the similarity between two basic block vectors, and the kmeans algorithm is used to cluster the m basic block vectors of the program. Assuming that k clusters are obtained, record the interval id of the center of each cluster and the weight w of the k clusters. k×1 .

[0013] (3) Execute representative intervals. Select the most representative BBV fragment from each cluster in (2) as the "SimPoint". This fragment is usually the BBV closest to the cluster center because it best represents the overall behavior of the category. Perform a detailed performance simulation on the selected k SimPoint fragments to obtain the execution clock cycle number of the k representative intervals. k×1 .

[0014] The common practice at present is to collect the Basic Block Vector information of the program through a high-performance simulator. When the representative interval is clustered, the high-performance simulator is used to fully execute the program to generate a checkpoint at the corresponding interval id. Then, a high-precision architecture simulator is used to execute the interval fragment in detail to obtain the number of clock cycles.

[0015] In traditional estimation, it is assumed that the number of clock cycles of each cluster center interval is the same as the average number of clock cycles of all intervals in the cluster, so:

[0016]

[0017] where cycle k×1 is the number of execution clock cycles of the k cluster center intervals, w k×1 is the weight of k clusters,

[0018] In fact, it is the weighted average clock cycle number of the cluster center interval, which is the average clock cycle number of all intervals of the program.

[0019]

[0020] where cycle total Represents the total number of clock cycles of all intervals in the entire program.

[0021] The high-precision architecture simulator is aligned with the architecture of the actual chip, so that by executing only the fragments of the cluster center, the number of clock cycles required for the high-precision architecture simulator to execute the complete program can be estimated. total Combined with the specific clock frequency of the chip, it is possible to estimate the time required for the chip to execute the entire program, thereby evaluating the performance of the chip.

[0022] However, there is a significant problem in traditional estimation: directly using the execution time of the cluster center interval to represent the average execution time of all intervals in the cluster may lead to errors. Summary of the invention

[0023] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a correction method for estimating program execution time. The present invention makes full use of the correlation between program execution behavior and time interval, which can effectively improve the accuracy of program performance prediction after the processor architecture is changed, while reducing the computational overhead of re-simulation, thereby ensuring the high accuracy of the estimated execution time.

[0024] The object of the present invention is achieved through the following technical solution: A correction method for estimating program execution time comprises the following steps:

[0025] S1, collect the frequency vector BBV of each interval of the program and the number of execution clock cycles of each interval;

[0026] S2. The collected BBV is reduced in dimension using the deep learning model AutoEncoder, and the BBV of each interval is reduced to 15 dimensions. Then Kmeans is used to cluster the vectors after dimensionality reduction to obtain the cluster center.

[0027] S3. Calculate the difference Δbbv between the BBV of each interval and the BBV of its corresponding cluster center i , and the difference between the execution clock cycles of each interval and its cluster center Δcycle i ; Set the Δbbv of all intervals i and Δcycle i As the sample set, k-fold cross validation is used to divide the samples, multiple machine learning fitting models are selected from the Python library and the machine learning fitting models are trained using the training set, and the model with the best performance on the test set is selected as the model most suitable for the corresponding benchmark test program;

[0028] S4. When predicting for a new architecture, re-collect the number of execution clock cycles of the cluster center interval; convert the Δbbv of each interval i Input into the model selected in S3 to estimate the Δcycle of each interval i , added to the execution clock cycle number of the re-collected cluster center is the estimated execution clock cycle number of this interval under the new architecture; adding the estimated execution clock cycle number of all intervals is the estimated execution clock cycle number of the program under the new architecture.

[0029] The beneficial effects of the present invention are as follows: the method of the present invention first extracts the basic block vector differences between each time interval and the cluster center time interval in the program, as well as the corresponding execution cycle number differences, and uses this to train a regression model suitable for the program. When the processor architecture changes and the program needs to be rerun, it is only necessary to provide the basic block vector differences between each time interval of the program and the cluster center time interval, and the difference in the number of execution cycles can be estimated through the regression model. Combined with the high-precision simulation of the cluster center time interval, the estimated number of execution cycles for each time interval can be obtained, and the accumulated number is the estimated number of execution cycles for the entire program under the new architecture. This method makes full use of the correlation between program execution behavior and time intervals, and can effectively improve the accuracy of program performance prediction after the processor architecture is changed, while reducing the computational overhead of re-simulation and ensuring the high accuracy of the estimated execution time. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1A schematic diagram of a flow chart of a method for correcting program execution time estimation according to the present invention;

[0031] Figure 2 It is a schematic diagram of reducing the dimension of Basic Block Vector by using the deep learning method AutoEncoder in the present invention;

[0032] Figure 3 A schematic diagram of calculating the difference between each interval and the Basic Block Vector of its cluster center interval in the present invention;

[0033] Figure 4 This is a schematic diagram of k-fold cross validation;

[0034] Figure 5 Schematic diagram for selecting the appropriate model for each procedure in the present invention. DETAILED DESCRIPTION

[0035] The method for estimating program execution time correction of the present invention first collects the number of cycles and basic block vectors of each interval of the program based on the old processor architecture, and then reduces the dimension of the basic block vector through the autoencoder, and then clusters the basic block vectors of all intervals of the program, and then calculates the error between each interval and its cluster center interval's basic block vector and the number of execution cycles, and uses this data as a training set to fit the model, and selects the model with the minimum error and the most suitable for the program based on the model's estimated execution cycle percentage error. When estimating the number of execution clock cycles for the new architecture later, it is only necessary to collect the number of clock cycles of the cluster center interval, and estimate the number of execution clock cycles of each interval based on the fitting model, so as to obtain the overall clock cycle estimate of the entire program on the new architecture. The specific flow chart is as follows: Figure 1 As shown, the specific description is given below.

[0036] A correction method for estimating program execution time comprises the following steps:

[0037] S1. The frequency vector BBV (Basic Block Vector) of each interval of the program is collected through the high-performance simulator NEMU, and the execution clock cycle number cycle of each interval of the program is collected through the high-precision simulator GEM5;

[0038] S2, the collected BBV is processed by deep learning model AutoEncoder to reduce the BBV of each interval to 15 dimensions; Figure 2 As shown, the input layer is the vector of the original dimension of BBV, denoted as X, the bottleneck layer is the vector of BBV reduced to 15 dimensions, and the hidden layer is the vector of other dimensions in the process of dimensionality reduction. Taking the actual application as an example, when reducing the dimension of BBV, there are 5 hidden layers in total. The complete dimensionality reduction process is input_dim→6400 dimensions→3200 dimensionsv1600 dimensions→800 dimensions→100 dimensions→15 dimensions, and the output vector output layer is obtained, denoted as X'. Then Kmeans is used to cluster the vectors after dimensionality reduction to obtain the cluster center;

[0039] S3. Calculate the difference Δbbv between the BBV of each interval and the BBV of its corresponding cluster center i , and the difference between the execution clock cycles of each interval and its cluster center Δcycle i ; When clustering in S2, each interval will be labeled with a label to indicate which category the interval belongs to; the difference Δbbv between the BBV of the i-th interval and the BBV of its corresponding cluster center is calculated i When , the BBV of the i-th interval is subtracted from the BBV of its corresponding cluster center, such as Figure 3 As shown; the difference between the i-th interval and the cycle of its corresponding cluster center is Δcycle i , that is, the cycle of the i-th interval is subtracted from the cycle of the interval of its corresponding cluster center;

[0040] The Δbbv of all intervals i and Δcycle i As the sample set, k-fold cross validation is used to divide the samples, such as Figure 4 As shown. Select multiple machine learning fitting models from the Python library and use the training set to train the machine learning fitting model. The model is used to calculate the difference between BBVs based on Δbbv. i Predicted Δcycle i The model that performs best on the test set is selected as the model best suited for the corresponding benchmark.

[0041] When selecting a model, use the trained model to perform a Δcycle on each interval in the test set. iThe prediction is made by adding each prediction result to the execution clock cycle number of the cluster center to get the estimated execution clock cycle number of interval, and the estimated execution clock cycle number of interval is accumulated to get the estimated execution clock cycle number of the entire program. The percentage error is calculated between the estimated execution clock cycle number of the entire program and the actual execution clock cycle number of the program. The model with the smallest percentage error is the most suitable model for the program, such as Figure 5 shown.

[0042] S4. When predicting for a new architecture, the BBV, dimensionality reduction, and clustering information collected in the previous steps can be reused; under the old processor architecture, run the simulator to collect data to train the model, and then use the model to test the performance of the new processor. When targeting a new architecture, only the execution clock cycles of the cluster center interval are collected again based on the high-precision architecture simulator; the Δbbv of each interval is converted into i Input into the model selected in S3 to estimate the Δcycle of each interval i , added to the execution clock cycle number of the re-collected cluster center is the estimated execution clock cycle number of this interval under the new architecture; adding the estimated execution clock cycle number of all intervals is the estimated execution clock cycle number of the program under the new architecture.

[0043] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific variations and combinations that do not deviate from the essence of the present invention based on the technical revelations disclosed by the present invention, and these variations and combinations are still within the protection scope of the present invention.

Claims

1. A method for estimating program execution time, characterized in that: The following steps are involved: S1, collect the frequency vector BBV of each interval of the program and the number of execution clock cycles of each interval; S2. The collected BBV is reduced in dimension using the deep learning model AutoEncoder, reducing the BBV of each interval to 15 dimensions. Kmeans is then used to cluster the reduced-dimensional vectors to obtain the cluster centers. S3. Calculate the difference Δbbv between the BBV of each interval and the BBV of its corresponding cluster center i , and the difference between the execution clock cycles of each interval and its cluster center Δcycle i ; Set the Δbbv of all intervals i and Δcycle i As the sample set, k-fold cross validation is used to divide the samples, multiple machine learning fitting models are selected from the Python library and the machine learning fitting models are trained using the training set, and the model with the best performance on the test set is selected as the model most suitable for the corresponding benchmark test program; S4. When predicting for a new architecture, re-collect the number of execution clock cycles of the cluster center interval; convert the Δbbv of each interval i Input into the model selected in S3 to estimate the Δcycle of each interval i , added to the execution clock cycle number of the re-collected cluster center is the estimated execution clock cycle number of this interval under the new architecture; adding the estimated execution clock cycle number of all intervals is the estimated execution clock cycle number of the program under the new architecture.

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