Verification method and verification device for chip design scheme, and electronic equipment

Abstract

The invention discloses a verification method and a verification device for a chip design scheme, and electronic equipment. The method comprises the following steps: converting C code test excitation for chip design scheme verification into a binary file; writing an instruction in the binary file into the virtual memory interval, and writing a reset vector in the binary file into the virtual PC after the reset signal of the virtual PC is reset; reading a to-be-executed instruction in the virtual memory interval according to an address pointed by a reset vector in the virtual PC in each clock signal, executing a preset verification process on a DUT of a chip design scheme based on the to-be-executed instruction, and storing data returned from the DUT in a virtual register; and after all the instructions in the virtual memory interval are read, determining a verification result of the chip design scheme according to the data in the virtual register. According to the invention, the time for developing the test excitation can be reduced.

Description

Technical Field

[0001] The present application relates to the field of chip verification technology, for example, to a verification method and verification device and electronic equipment for a chip design scheme. Background Art

[0002] In the process of designing a chip, the chip design needs to be verified. At present, the verification of chip design is usually divided into different verification levels, such as module level (IP Level), subsystem level (Subsystem Level) and system level verification (Chip Level). In subsystem level or system level verification, C code test stimulus built based on C language is usually used to perform simulation test on real processor. However, this method requires the processor to execute more logic, and the simulation takes a long time.

[0003] In the related art, in order to solve the above problems, a virtual processor is pre-built and mounted on a bus that communicates with the real processor. The C code test stimulus is input to the virtual processor. The virtual processor converts the C code test stimulus into a SystemVerilog test stimulus and then sends it to the bus for operation, thereby realizing subsystem-level or system-level verification of the chip design solution.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] In the related technology, the SystemVerilog side needs to provide a dpi-c interface, and the C code test stimulus calls the SystemVerilog side through the dpi-c interface to realize the conversion of the C code test stimulus to the SystemVerilog test stimulus. Although this method can reduce the amount of logic executed by the processor, it requires the function name and parameter type of the dpi-c interface to be defined in advance on the SystemVerilog side, which increases the time required for testers to develop test stimuli and is not conducive to the rapid update and iteration of chip design solutions.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a verification method, a verification device, and an electronic device for a chip design scheme, which can reduce the time spent by testers on developing test stimuli, improve the verification efficiency of the chip design scheme, and increase the update iteration rate of the chip design scheme.

[0009] In some embodiments, a verification method for a chip design scheme includes: converting a C code test stimulus for verifying the chip design scheme into a binary file, and constructing a virtual processor including a virtual memory, a virtual register, and a virtual PC structure; writing instructions in the binary file into a virtual memory interval, and after the reset signal of the virtual PC is reset, writing a reset vector in the binary file to the virtual PC; at each clock signal, reading an instruction to be executed in the virtual memory interval according to the address pointed to by the reset vector in the virtual PC, and executing a preset verification process on the DUT of the chip design scheme based on the instruction to be executed, wherein the data returned from the DUT of the chip design scheme is stored in a virtual register; after all instructions in the virtual memory interval are read, determining the verification result of the chip design scheme according to the data in the virtual register.

[0010] Optionally, a preset verification process is executed on the DUT of the chip design scheme based on the instructions to be executed, including: parsing the instructions to be executed, and determining the operation information of the instructions to be executed; wherein the operation information of the instructions to be executed includes the operation mode, operation source address, operation destination address and operation data of the instructions to be executed; judging whether the operation source address and the operation destination address of the instructions to be executed contain addresses in the DUT of the chip design scheme; if the addresses in the DUT do not exist, reading data from the virtual register or writing data to the virtual register according to the operation mode of the instructions to be executed; if the addresses in the DUT exist, converting the operation information of the instructions to be executed into SystemVerilog test stimuli, and sending the SystemVerilog test stimuli to the DUT of the chip design scheme for execution.

[0011] Optionally, the SystemVerilog test stimulus is sent to the DUT of the chip design scheme for execution, including: when the SystemVerilog test stimulus is a read operation, data is read from the DUT of the chip design scheme, and the read data is stored in a virtual register; when the SystemVerilog test stimulus is a write operation, the corresponding operation data is written to a corresponding address in the DUT of the chip design scheme.

[0012] Optionally, in the process of sending the SystemVerilog test stimulus to the DUT of the chip design scheme for execution, the verification method also includes: detecting whether the bus returns a bus exception error; wherein the virtual processor is communicated with the DUT of the chip design scheme through the bus; and executing a preset interrupt response program when a bus exception error returned by the bus is received.

[0013] Optionally, before executing a preset verification process on the DUT of the chip design scheme based on the instruction to be executed, the verification method also includes: detecting whether the instruction to be executed is an illegal instruction or there is a division by zero exception; if the instruction to be executed is an illegal instruction or there is a division by zero exception, executing a preset interrupt response program; if the instruction to be executed is not an illegal instruction or there is no division by zero exception, determining the step of executing a preset verification process on the DUT of the chip design scheme based on the instruction to be executed.

[0014] Optionally, in the process of executing a preset verification process on the DUT of the chip design scheme based on the instructions to be executed, the verification method also includes: detecting interrupt exception reporting information of the DUT of the chip design scheme; and executing a preset interrupt response program when the DUT reports an interrupt exception.

[0015] Optionally, executing a preset interrupt response procedure includes: saving the current address of the virtual PC, reading the vector table information in the virtual memory; searching the target vector corresponding to the current address from the vector table information, and pointing the PC address of the next virtual PC to the target vector.

[0016] In some embodiments, a verification device for a chip design scheme includes: a conversion module, configured to convert a C code test stimulus for verifying the chip design scheme into a binary file, and construct a virtual processor including a virtual memory, a virtual register and a virtual PC structure; a processing module, configured to write instructions in the binary file into a virtual memory interval, and write a reset vector in the binary file to the virtual PC after the reset signal of the virtual PC is reset; a parsing module, configured to read a to-be-executed instruction in the virtual memory interval according to the address pointed to by the reset vector in the virtual PC at each clock signal, and execute a preset verification process on the DUT of the chip design scheme based on the to-be-executed instruction, wherein the data returned from the DUT of the chip design scheme is stored in the virtual register; and a verification module, configured to determine the verification result of the chip design scheme according to the data in the virtual register after all instructions in the virtual memory interval have been read.

[0017] In some embodiments, a verification device for a chip design solution includes a processor and a memory storing program instructions, and the processor is configured to execute the verification method for the chip design solution as described above when running the program instructions.

[0018] In some embodiments, an electronic device includes: a device body; and a verification device for a chip design scheme as described above, which is disposed in the device body.

[0019] The verification method, verification device, and electronic device for chip design scheme provided by the embodiments of the present disclosure can achieve the following technical effects:

[0020] In the disclosed embodiment, when the chip design scheme is verified at the system level or subsystem level, the C code test stimulus is first converted into a binary file in a binary format. Then, the instructions in the binary file are processed by a virtual processor including virtual memory, virtual registers and virtual PC structures, and the chip design scheme is verified by interacting with the DUT of the chip design scheme. In this way, there is no need to define the function name and parameter type of the dpi-c interface on the SystemVerilog side to convert the C code test stimulus into a SystemVerilog test stimulus, so that the C code test stimulus can be written and modified more flexibly. Therefore, the disclosed embodiment can reduce the time spent by testers in developing test stimuli, improve the verification efficiency of the chip design scheme, and improve the update iteration rate of the chip design scheme.

[0021] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0023] Figure 1 is a schematic diagram of an electronic device provided by an embodiment of the present disclosure;

[0024] Figure 2 is a schematic diagram of a verification method for a chip design scheme provided by an embodiment of the present disclosure;

[0025] Figure 3 is a schematic diagram of another verification method for a chip design solution provided by an embodiment of the present disclosure;

[0026] Figure 4 is a schematic diagram of another verification method for a chip design solution provided by an embodiment of the present disclosure;

[0027] Figure 5 is a schematic diagram of a verification device for a chip design scheme provided by an embodiment of the present disclosure;

[0028] Figure 6 It is a schematic diagram of another verification device for a chip design scheme provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0030] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0031] Unless otherwise stated, the term "plurality" of a feature means two or more.

[0032] In the embodiment of the present disclosure, the character " / " feature indicates that the preceding and following objects are in an "or" relationship. For example, the A / B feature indicates: A or B.

[0033] The term "and / or" is a description of the association relationship between objects, and the characteristic indicates that there can be three relationships. For example, A and / or B, the characteristic indicates: A or B, or, A and B.

[0034] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0035] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0036] like Figure 1 As shown, the electronic device 100 provided by the embodiment of the present disclosure includes a device body 110 and a verification device 500 (600) for a chip design solution.

[0037] Specifically, the verification device 500 ( 600 ) for the chip design solution is disposed in the device body 110 .

[0038] Specifically, a virtual processor and a DUT of a chip design are deployed in the electronic device 100, and the virtual processor is connected to the bus signal, interrupt signal, clock signal and reset signal of the DUT of the chip design through a communication interface. It should be noted that the DUT (Device Under Test) of the chip design refers to an RTL simulation file constructed based on the chip design. The DUT of the chip design can receive and execute test stimuli to verify a certain function of the chip design.

[0039] Optionally, the verification device 600 for the chip design solution includes a processor. When the chip design solution is verified at the system level or subsystem level, the processor can convert the C code test stimulus used for verifying the chip design solution into a binary file, and construct a virtual processor including a virtual memory, a virtual register and a virtual PC structure. The instructions in the binary file can be written into the virtual memory interval, and after the reset signal of the virtual PC is reset, the reset vector in the binary file is written to the virtual PC. At each clock signal, the processor can read an instruction to be executed in the virtual memory interval according to the address pointed to by the reset vector in the virtual PC, and execute a preset verification process on the DUT of the chip design solution based on the instruction to be executed, wherein the data returned from the DUT of the chip design solution is stored in the virtual register. After all the instructions in the virtual memory interval are read, the processor can determine the verification result of the chip design solution according to the data in the virtual register.

[0040] In combination with the above electronic device, the present disclosure provides a verification method for a chip design solution, such as Figure 2 As shown, the verification method includes:

[0041] S201, the processor converts the C code test stimulus used for chip design solution verification into a binary file, and constructs a virtual processor including virtual memory, virtual registers and virtual PC structure.

[0042] Specifically, test stimulus is an input signal or data constructed to verify the correctness of the chip design. Test stimulus is used to simulate various situations in actual chip use to verify whether the chip produced according to the chip design can work as expected. C code test stimulus refers to test stimulus written in C language.

[0043] Specifically, generating a binary file according to the C code test stimulus is to compile the code of the C code test stimulus into a file in a binary format.

[0044] Specifically, by constructing a virtual processor including virtual memory, virtual registers and virtual PC structures, an execution platform can be provided for C code test stimulus. Specifically, the virtual processor is a parser written in SystemVerilog language. The virtual memory interval is the simulated hardware memory space. The virtual PC (Program Counter) is a virtual program counter, which is a simulated hardware instruction pointer. The virtual register is a register used to store the data required during program execution in a virtual machine or a programming language execution environment.

[0045] S202, the processor writes the instructions in the binary file into the virtual memory area, and writes the reset vector in the binary file into the virtual PC after the reset signal of the virtual PC is reset.

[0046] Specifically, the instructions in the binary file are written into the virtual memory interval, that is, the process of loading the binary file into the virtual processor environment. After the reset signal of the virtual PC is reset, the reset vector in the binary file is written into the virtual PC, that is, the process of writing the address where the verification program starts to execute into the virtual PC.

[0047] S203, at each clock signal, the processor reads an instruction to be executed in the virtual memory interval according to the address pointed to by the reset vector in the virtual PC, and executes a preset verification process on the DUT of the chip design scheme based on the instruction to be executed, wherein the data returned from the DUT of the chip design scheme is stored in the virtual register.

[0048] Specifically, the clock signal is a periodic signal. Each cycle of the clock signal represents a time unit. The virtual processor completes a series of operations within this time unit.

[0049] Specifically, at the beginning of each clock signal cycle, the processor reads a to-be-executed instruction in the virtual memory interval according to the address pointed to by the reset vector in the virtual PC, and executes a preset verification process on the DUT of the chip design scheme based on this to-be-executed instruction, and the data returned by the DUT of the chip design scheme will be stored in the virtual register.

[0050] S204, after all instructions in the virtual memory area are read by the processor, the verification result of the chip design solution is determined according to the data in the virtual register.

[0051] Specifically, an instruction to be executed in the virtual memory interval is used to verify a function in the chip design scheme, and the verification result data of each function will be stored in the virtual register. After all the instructions in the virtual memory interval are read, it indicates that all the instructions in the virtual memory interval are verified in the DUT of the chip design scheme. Therefore, after all the instructions in the virtual memory interval are read, the verification result of the chip design scheme can be determined based on the data in the virtual register.

[0052] In the disclosed embodiment, when the chip design scheme is verified at the system level or subsystem level, the C code test stimulus is first converted into a binary file in a binary format. Then, the instructions in the binary file are processed by a virtual processor including virtual memory, virtual registers and virtual PC structures, and the chip design scheme is verified by interacting with the DUT of the chip design scheme. In this way, there is no need to define the function name and parameter type of the dpi-c interface on the SystemVerilog side to convert the C code test stimulus into a SystemVerilog test stimulus, so that the C code test stimulus can be written and modified more flexibly. Therefore, the disclosed embodiment can reduce the time spent by testers in developing test stimuli, improve the verification efficiency of the chip design scheme, and improve the update iteration rate of the chip design scheme.

[0053] In addition, compared with the solution of converting C code test stimulus into SystemVerilog test stimulus using DPI-C interface, the embodiment of the present disclosure can support the configuration of virtual registers by pointer mode (such as structure pointer), and can simulate the interrupt behavior of real processor. And the virtual processor in the embodiment of the present disclosure is only used to parse the information of binary file, so the virtual processor in the embodiment of the present disclosure has high code reusability.

[0054] In some embodiments, a preset verification process is executed on the DUT of the chip design scheme based on the instructions to be executed, including: parsing the instructions to be executed, and determining the operation information of the instructions to be executed; wherein the operation information of the instructions to be executed includes the operation mode, operation source address, operation destination address and operation data of the instructions to be executed; judging whether the operation source address and the operation destination address of the instructions to be executed have addresses in the DUT of the chip design scheme; in the case where the addresses in the DUT do not exist, reading data from the virtual register or writing data to the virtual register according to the operation mode of the instructions to be executed; in the case where the addresses in the DUT exist, converting the operation information of the instructions to be executed into SystemVerilog test stimuli, and sending the SystemVerilog test stimuli to the DUT of the chip design scheme for execution.

[0055] Specifically, by parsing the instruction to be executed, it can be determined whether the instruction to be executed is a write operation or a read operation, the source address to be operated, the destination address to be operated, and the data to be operated, etc. Therefore, the operation information such as the operation mode, the operation source address, the operation destination address, and the operation data of the instruction to be executed can be determined.

[0056] Specifically, by determining whether the operation source address and the operation destination address of the instruction to be executed contain addresses in the DUT of the chip design, it can be determined whether the instruction to be executed needs to be executed directly in the virtual processor or needs to be sent to the DUT of the chip design for execution.

[0057] Specifically, if the operation source address and the operation destination address of the instruction to be executed do not contain the address in the DUT, it indicates that the instruction to be executed needs to be directly executed in the virtual processor. Therefore, in this case, data needs to be read from the virtual register or written to the virtual register according to the operation mode of the instruction to be executed.

[0058] Specifically, if the operation source address and the operation destination address of the instruction to be executed contain addresses in the DUT, it indicates that the instruction to be executed needs to be sent to the DUT of the chip design for execution. However, the DUT can only execute instructions in the form of SystemVerilog language. Therefore, in this case, it is necessary to first convert the operation information of the instruction to be executed into SystemVerilog test stimulus, and then send the SystemVerilog test stimulus to the DUT of the chip design for execution.

[0059] Optionally, the SystemVerilog test stimulus is sent to the DUT of the chip design scheme for execution, including: when the SystemVerilog test stimulus is a read operation, data is read from the DUT of the chip design scheme, and the read data is stored in a virtual register; when the SystemVerilog test stimulus is a write operation, the corresponding operation data is written to a corresponding address in the DUT of the chip design scheme.

[0060] Optionally, in the process of sending the SystemVerilog test stimulus to the DUT of the chip design scheme for execution, the verification method also includes: detecting whether the bus returns a bus exception error; wherein the virtual processor is communicated with the DUT of the chip design scheme through the bus; and executing a preset interrupt response program when a bus exception error returned by the bus is received.

[0061] Specifically, the virtual processor is connected to the DUT of the chip design through a bus. If the bus returns a bus exception error, it means that the SystemVerilog test stimulus converted by the to-be-executed instruction cannot be completely sent to the DUT. Therefore, when a bus exception error is received from the bus, a preset interrupt response program needs to be executed.

[0062] In the disclosed embodiment, whether the instruction to be executed needs to be executed in the DUT is judged by the operation source address and the operation destination address of the instruction to be executed. This ensures that only the operation information corresponding to the instruction to be executed in the DUT is converted into SystemVerilog test stimulus. In this way, the number of SystemVerilog test stimulus that the DUT needs to execute is reduced, and the verification efficiency of the chip design solution is improved.

[0063] The present disclosure provides another verification method for a chip design solution. Figure 3 As shown, the verification method includes:

[0064] S301, the processor converts the C code test stimulus used for chip design solution verification into a binary file, and constructs a virtual processor including virtual memory, virtual registers and virtual PC structure.

[0065] S302, the processor writes the instructions in the binary file into the virtual memory area, and writes the reset vector in the binary file into the virtual PC after the reset signal of the virtual PC is reset.

[0066] S303: At each clock signal, the processor reads an instruction to be executed in the virtual memory area according to the address pointed to by the reset vector in the virtual PC.

[0067] S304: The processor detects whether the instruction to be executed is an illegal instruction or a division by zero exception occurs.

[0068] Specifically, if the instruction to be executed is an illegal instruction or there is a division by zero exception, then the preset verification process based on the instruction to be executed on the DUT of the chip design solution will be invalid. Therefore, after reading an instruction to be executed from the virtual memory interval, it is necessary to first detect whether the instruction to be executed is an illegal instruction or there is a division by zero exception.

[0069] S305: When the instruction to be executed is an illegal instruction or a division by zero exception occurs, the processor executes a preset interrupt response program.

[0070] After S305 is executed, the process waits for the next clock signal cycle and returns to execute S303.

[0071] Specifically, if the instruction to be executed is an illegal instruction or there is a division by zero exception, it indicates that executing a preset verification process on the DUT of the chip design scheme based on the instruction to be executed will cause the DUT to execute invalid or erroneous code. Therefore, in this case, it is necessary to execute a preset interrupt response program.

[0072] S306, when the instruction to be executed is not an illegal instruction or there is no division by zero exception, the processor executes a preset verification process on the DUT of the chip design scheme based on the instruction to be executed, wherein the data returned from the DUT of the chip design scheme is stored in a virtual register.

[0073] After S306 is executed, the process waits for the next clock signal cycle and returns to execute S303.

[0074] Specifically, if the instruction to be executed is not an illegal instruction or there is no division by zero exception, it indicates that it is effective to execute the preset verification process on the DUT of the chip design scheme based on the instruction to be executed. Therefore, in this case, the step of executing the preset verification process on the DUT of the chip design scheme based on the instruction to be executed can be performed normally.

[0075] S307, after all instructions in the virtual memory area are read by the processor, the verification result of the chip design solution is determined according to the data in the virtual register.

[0076] In the disclosed embodiment, by detecting whether the instruction to be executed is an illegal instruction or there is a division by zero exception, the execution of invalid or erroneous code can be avoided, ensuring the smooth progress of the verification process. In addition, it is also possible to find problems such as coding errors, format errors, or instruction set incompatibility that may exist in the binary file. In this way, in an actual hardware environment, the risk of processor abnormalities, system crashes, or data corruption caused by executing illegal instructions or instructions with division by zero exceptions can be reduced.

[0077] In some embodiments, during the process of executing a preset verification process on the DUT of the chip design scheme based on the instructions to be executed, the verification method also includes: detecting the interrupt exception reporting information of the DUT of the chip design scheme; and executing a preset interrupt response program when the DUT reports an interrupt exception.

[0078] Specifically, when the DUT executes a SystemVerilog test stimulus, if it encounters a situation where it cannot continue to execute (such as a division by zero error, an external device requesting a service, a user requesting a system call, etc.), an interrupt or exception will be triggered. At this time, the DUT will send an interrupt exception reporting information. Therefore, if the DUT reports an interrupt exception, the preset interrupt response program will be executed.

[0079] In some embodiments, executing a preset interrupt response program includes: saving the current address of the virtual PC, reading the vector table information in the virtual memory; searching the target vector corresponding to the current address from the vector table information, and pointing the PC address of the next virtual PC to the target vector.

[0080] The present disclosure provides another verification method for a chip design solution. Figure 4 As shown, the verification method includes:

[0081] S401, the processor converts the C code test stimulus used for chip design solution verification into a binary file, and constructs a virtual processor including virtual memory, virtual registers and virtual PC structure.

[0082] S402, the processor writes the instructions in the binary file into the virtual memory area, and writes the reset vector in the binary file into the virtual PC after the reset signal of the virtual PC is reset.

[0083] S403, the processor reads an instruction to be executed in the virtual memory area according to the address pointed to by the reset vector in the virtual PC at each clock signal.

[0084] S404: The processor detects whether the instruction to be executed is an illegal instruction or a division by zero exception occurs.

[0085] If the answer is no, execute S405; if the answer is yes, execute S410.

[0086] S405, when the instruction to be executed is not an illegal instruction or there is no division by zero exception, the processor parses the instruction to be executed and determines the operation information of the instruction to be executed; wherein the operation information of the instruction to be executed includes the operation mode, operation source address, operation destination address and operation data of the instruction to be executed.

[0087] S406: The processor determines whether the operation source address and the operation destination address of the instruction to be executed include an address in the DUT of the chip design solution.

[0088] If the address in the DUT of the chip design does not exist, S407 is executed; if the address in the DUT of the chip design exists, S408 is executed.

[0089] S407: When the address in the DUT does not exist, the processor reads data from the virtual register or writes data to the virtual register according to the operation mode of the instruction to be executed.

[0090] After S407 is completed, the process waits for the next clock signal cycle and returns to S403.

[0091] S408, when the address in the DUT exists, the processor converts the operation information of the instruction to be executed into a SystemVerilog test stimulus. When the SystemVerilog test stimulus is a read operation, the processor reads data from the DUT of the chip design solution and stores the read data in the virtual register; when the SystemVerilog test stimulus is a write operation, the processor writes the corresponding operation data to the corresponding address in the DUT of the chip design solution.

[0092] S409, the processor detects whether the bus returns a bus abnormality error; wherein the virtual processor is connected to the DUT of the chip design solution through the bus.

[0093] If no bus abnormality error is returned, wait for the next clock signal cycle and return to execute S403. If a bus abnormality error is returned, execute S410.

[0094] S410, the processor saves the current address of the virtual PC, reads the vector table information in the virtual memory, searches for a target vector corresponding to the current address from the vector table information, and points the PC address of the next virtual PC to the target vector.

[0095] After S410 is completed, the process waits for the next clock signal cycle and returns to S403.

[0096] S411, the processor detects the interrupt exception reporting information of the DUT of the chip design solution, and executes the preset interrupt response program when the DUT reports the interrupt exception. (ie S410)

[0097] S412, after all instructions in the virtual memory area are read by the processor, the verification result of the chip design solution is determined according to the data in the virtual register.

[0098] Combination Figure 5As shown, the embodiment of the present disclosure provides a verification device 500 for a chip design scheme, including: a conversion module 501, a processing module 502, a parsing module 503 and a verification module 504. The conversion module 501 is configured to convert the C code test stimulus for verifying the chip design scheme into a binary file, and construct a virtual processor including a virtual memory, a virtual register and a virtual PC structure. The processing module 502 is configured to write the instructions in the binary file into the virtual memory interval, and after the reset signal of the virtual PC is reset, write the reset vector in the binary file to the virtual PC. The parsing module 503 is configured to read a to-be-executed instruction in the virtual memory interval according to the address pointed to by the reset vector in the virtual PC at each clock signal, and execute a preset verification process on the DUT of the chip design scheme based on the to-be-executed instruction, wherein the data returned from the DUT of the chip design scheme is stored in the virtual register. The verification module 504 is configured to determine the verification result of the chip design scheme according to the data in the virtual register after all the instructions in the virtual memory interval have been read.

[0099] Combination Figure 6 As shown, the embodiment of the present disclosure provides a verification device 600 for a chip design scheme, including: a processor (processor) 601 and a memory (memory) 602. Optionally, the device may also include a communication interface (Communication Interface) 603 and a bus 604. Among them, the processor 601, the communication interface 603, and the memory 602 can communicate with each other through the bus 604. The communication interface 603 can be used for information transmission. The processor 601 can call the logic instructions in the memory 602 to execute the verification method for the chip design scheme of the above embodiment.

[0100] In addition, the logic instructions in the memory 602 described above may be implemented in the form of software functional units and when sold or used as independent products, may be stored in a computer-readable storage medium.

[0101] The memory 602 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 601 executes the functional application and data processing by running the program instructions / modules stored in the memory 602, that is, the verification method for the chip design scheme in the above embodiment is implemented.

[0102] The memory 602 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 602 may include a high-speed random access memory and may also include a non-volatile memory.

[0103] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the above-mentioned verification method for a chip design solution.

[0104] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes.

[0105] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0106] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods for each specific application to implement the described functions, but such implementations should not be considered to exceed the scope of the embodiments of the present disclosure. The technicians may clearly understand that, for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above may refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0107] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0108] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A verification method for a chip design scheme, characterized in that: include: Convert C code test stimulus used for chip design verification into binary files, and build a virtual processor including virtual memory, virtual registers and virtual PC structure; Write the instructions in the binary file into the virtual memory area, and after the reset signal of the virtual PC is reset, write the reset vector in the binary file into the virtual PC; At each clock signal, read an instruction to be executed in the virtual memory interval according to the address pointed to by the reset vector in the virtual PC, and perform a preset verification process on the DUT of the chip design scheme based on the instruction to be executed, wherein the data returned from the DUT of the chip design scheme is stored in the virtual register; After all instructions in the virtual memory area are read, the verification result of the chip design solution is determined based on the data in the virtual register.

2. The verification method according to claim 1, characterized in that: Execute a preset verification process on the DUT of the chip design solution based on the instructions to be executed, including: Parsing the instruction to be executed to determine the operation information of the instruction to be executed; wherein the operation information of the instruction to be executed includes the operation mode, operation source address, operation destination address and operation data of the instruction to be executed; Determine whether the operation source address and the operation destination address of the instruction to be executed have the address in the DUT of the chip design solution; In the absence of an address in the DUT, data is read from the virtual register or written to the virtual register in accordance with the operation mode of the instruction to be executed; In the case where the address in the DUT exists, the operation information of the instruction to be executed is converted into a SystemVerilog test stimulus, and the SystemVerilog test stimulus is sent to the DUT of the chip design solution for execution.

3. The verification method according to claim 2, characterized in that: Send SystemVerilog test stimulus to the DUT of the chip design solution for execution, including: When the SystemVerilog test stimulus is a read operation, data is read from the DUT of the chip design and the read data is stored in a virtual register; When the SystemVerilog test stimulus is a write operation, the corresponding operation data is written to the corresponding address in the DUT of the chip design solution.

4. The verification method according to claim 2, characterized in that: In the process of sending SystemVerilog test stimulus to the DUT of the chip design solution for running, the verification method also includes: Detecting whether the bus returns a bus abnormality error; wherein the virtual processor is connected to the DUT of the chip design solution through the bus; When a bus abnormality error is received, a preset interrupt response procedure is executed.

5. The verification method according to claim 1, characterized in that: Before executing a preset verification process on the DUT of the chip design solution based on the instructions to be executed, the verification method further includes: Check whether the instruction to be executed is an illegal instruction or there is a division by zero exception; When the instruction to be executed is an illegal instruction or there is a division by zero exception, a preset interrupt response program is executed; When the instruction to be executed is not an illegal instruction or there is no division by zero exception, a step of executing a preset verification process on the DUT of the chip design solution based on the instruction to be executed is determined.

6. The verification method according to claim 1, characterized in that: In the process of executing a preset verification process on the DUT of the chip design solution based on the instructions to be executed, the verification method also includes: Detect the interruption exception reporting information of the DUT of the chip design solution; When the DUT reports an interrupt exception, the preset interrupt response program is executed.

7. The verification method according to any one of claims 4 to 6, characterized in that: Execute the preset interrupt response procedure, including: Save the current address of the virtual PC and read the vector table information in the virtual memory; Find the target vector corresponding to the current address from the vector table information, and point the PC address of the next virtual PC to the target vector.

8. A verification device for a chip design scheme, characterized in that: include: A conversion module, configured to convert a C code test stimulus for chip design scheme verification into a binary file, and construct a virtual processor including a virtual memory, a virtual register, and a virtual PC structure; The processing module is configured to write the instructions in the binary file into the virtual memory area, and write the reset vector in the binary file into the virtual PC after the reset signal of the virtual PC is reset; The parsing module is configured to read a to-be-executed instruction in the virtual memory interval according to the address pointed to by the reset vector in the virtual PC at each clock signal, and execute a preset verification process on the DUT of the chip design scheme based on the to-be-executed instruction, wherein the data returned from the DUT of the chip design scheme is stored in the virtual register; The verification module is configured to determine the verification result of the chip design scheme according to the data in the virtual register after all the instructions in the virtual memory interval are read.

9. A verification device for a chip design scheme, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the verification method for a chip design solution according to any one of claims 1 to 7 when running the program instructions.

10. An electronic device, characterized in that: include: Equipment body; The verification device for chip design scheme as described in claim 8 or 9 is arranged on the device body.

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