Pixel circuit and display panel

Abstract

The invention provides a pixel circuit and a display panel. The pixel circuit comprises a driving transistor, a light emitting circuit and a control circuit. The light emitting circuit is coupled between the driving transistor and the light emitting element. The control circuit is coupled to the light emitting circuit and is coupled to the driving transistor on a first node. The control circuit sets a first voltage on the first node based on a plurality of reference voltages according to a plurality of control signals. During a light emitting period, the light emitting circuit generates a bias voltage on a first end of the light emitting element according to a light emitting signal, so that the control circuit sets a first voltage based on the bias voltage according to a plurality of control signals, and the driving transistor generates a driving current to the light emitting element according to the first voltage, therefore, the brightness of the light-emitting element is compensated at high temperature.

Description

Technical Field

[0001] The present invention relates to an electronic device, and in particular to a pixel circuit and a display panel. Background Art

[0002] Generally speaking, a light-emitting diode (LED) can be used as a light-emitting element in a display panel. During the operation of the display panel, the temperature of the LED is related to the ambient temperature and the operating time of the LED. However, when the temperature of the LED increases, the efficiency of the LED decreases, thereby reducing the brightness of the display panel. Summary of the invention

[0003] An embodiment of the present invention provides a pixel circuit, which can generate corresponding driving currents in response to light-emitting elements with different temperatures, thereby compensating the brightness of the light-emitting elements at high temperatures.

[0004] The pixel circuit of the embodiment of the present invention includes a driving transistor, a light emitting circuit and a control circuit. The driving transistor is used to provide a driving current. The light emitting circuit is coupled between the driving transistor and the light emitting element. The light emitting circuit is used to provide a driving current to the light emitting element according to a light emitting signal. The control circuit is coupled to the light emitting circuit and is coupled to the driving transistor at a first node. The control circuit is used to set a first voltage on the first node based on multiple reference voltages according to multiple control signals. During the light emitting period, the light emitting circuit generates a bias voltage on the first end of the light emitting element according to the light emitting signal, so that the control circuit sets the first voltage based on the bias voltage according to the multiple control signals, and the driving transistor generates a driving current according to the first voltage.

[0005] Another embodiment of the present invention provides a display panel, which includes a gate driving circuit and a plurality of the above-mentioned pixel circuits, which are coupled to the gate driving circuit and arranged in an array.

[0006] Based on the above, the pixel circuit and the display panel of the embodiment of the present invention set the first voltage received by the driving transistor based on the terminal voltage (i.e., bias voltage) of the light-emitting element through the control circuit, so that the driving transistor drives the light-emitting element according to the first voltage associated with the bias voltage. In this way, in response to various temperatures of the light-emitting element, the pixel circuit can adaptively operate based on the corresponding bias voltage to compensate the brightness of the light-emitting element at high temperature.

[0007] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1Ais a block diagram of a display panel according to an embodiment of the present invention.

[0009] Figure 1B According to the present invention Figure 1A A block diagram of a pixel circuit shown in the embodiment.

[0010] Figure 2 is a circuit diagram of a pixel circuit according to an embodiment of the present invention.

[0011] Figure 3 According to the present invention Figure 2 A schematic diagram of the operation of the pixel circuit shown in the embodiment.

[0012] FIG. 4A to FIG. 4C According to the present invention Figure 3 A schematic diagram of the operation of the pixel circuit shown in the embodiment.

[0013] Description of reference numerals:

[0014] 10: Display Panel

[0015] 100, 100-11~100-mn, 200: Pixel circuit

[0016] 110, 210: Control circuit

[0017] 120, 220: Light-emitting circuit

[0018] 130, 230: driving transistor

[0019] 140, 240: Light-emitting element

[0020] 211: Reset circuit

[0021] 212: Write circuit

[0022] 213: Compensation Circuit

[0023] 300: Gate drive circuit

[0024] C1: Capacitor

[0025] EM: Luminescent signal

[0026] Id: driving current

[0027] N1: First node

[0028] N2: Second node

[0029] N3: Node

[0030] NA: The first end of the light emitting element

[0031] P1: Reset period

[0032] P2: Writing and compensation period

[0033] P3: Lighting period

[0034] S1~Si, S1~S3: control signal

[0035] t1~t4: time

[0036] T1~T5: Transistor

[0037] V1~Vj: reference voltage

[0038] Vn: first reference voltage

[0039] Data: Second reference voltage

[0040] OVDD: The third reference voltage

[0041] OVSS: Fourth reference voltage

[0042] Vf: The on-state voltage of the light-emitting element

[0043] VH, VL: voltage level

[0044] Vr: The voltage across the light emitting element when it is in a floating state DETAILED DESCRIPTION

[0045] Some embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. The referenced element symbols in the following description will be regarded as the same or similar elements when the same element symbols appear in different drawings. These embodiments are only part of the present invention and do not disclose all possible implementation methods of the present invention. More specifically, these embodiments are only examples in the claims of the present invention.

[0046] Figure 1A is a block diagram of a display panel according to an embodiment of the present invention. Figure 1A The display panel 10 includes a plurality of pixel circuits 100-11 to 100-mn and a gate driving circuit 300, wherein m and n are positive integers greater than 1. The pixel circuits 100-11 to 100-mn are coupled to the gate driving circuit 300 and arranged in an array. In the present embodiment, the plurality of pixel circuits 100-11 to 100-mn have the same circuit architecture.

[0047] For reference Figure 1B , Figure 1B According to the present invention Figure 1A The pixel circuit 100 may be, for example, Figure 1AThe pixel circuit 100 includes a control circuit 110, a light emitting circuit 120, and a driving transistor 130. The control circuit 110 is coupled to the light emitting circuit 120. The control circuit 110 is coupled to the driving transistor 130 at a first node N1. The light emitting circuit 120 is coupled between the driving transistor 130 and the light emitting element 140. In some embodiments, the pixel circuit 100 further includes the light emitting element 140.

[0048] In this embodiment, the driving transistor 130 is used to provide a driving current Id. The light emitting circuit 120 receives the driving current Id from the driving transistor 130. The light emitting circuit 120 also receives a light emitting signal EM. The light emitting circuit 120 can operate during a light emitting period, and is used to provide a driving current Id to the light emitting element 140 according to the light emitting signal EM to drive the light emitting element 140.

[0049] In this embodiment, the control circuit 110 receives a plurality of control signals S1-Si and a plurality of reference voltages V1-Vj, wherein i and j are positive integers greater than 1. The control circuit 110 can operate in other periods other than the light-emitting period, and is used to set the first voltage on the first node N1 based on the plurality of reference voltages V1-Vj according to the plurality of control signals S1-Si.

[0050] In this embodiment, during the light emitting period, the light emitting circuit 120 generates a bias voltage on the first terminal NA of the light emitting element 140 according to the light emitting signal EM. The first terminal NA of the light emitting element 140 is, for example, an anode terminal of the light emitting element 140.

[0051] Continuing with the above description, during the light-emitting period, the control circuit 110 receives the bias voltage on the terminal NA through the light-emitting circuit 120. The control circuit 110 sets the first voltage on the first node N1 based on the bias voltage according to the plurality of control signals S1-Si. Thus, the driving transistor 130 generates the driving current Id according to the first voltage, so that the light-emitting element 140 emits light according to the driving current Id.

[0052] It is worth mentioning that during the light-emitting period, since the control circuit 110 operates based on the bias voltage on the first terminal NA of the light-emitting element 140, the first voltage set by the control circuit 110 on the first node N1 is related to the terminal voltage (i.e., the bias voltage) of the light-emitting element 140. By driving the transistor 130 to generate the driving current Id according to the first voltage, the pixel circuit 100 can adaptively operate based on the bias voltage to respond to the current temperature of the light-emitting element 140. In this way, under the condition that the light-emitting element 140 has various temperatures (e.g., high temperature), the pixel circuit 100 can adaptively compensate the brightness of the light-emitting element 140.

[0053] Figure 2 is a circuit diagram of a pixel circuit according to an embodiment of the present invention. Figure 2 , the pixel circuit 200 includes a control circuit 210, a light emitting circuit 220, and a driving transistor 230. In some embodiments, the pixel circuit 200 further includes a light emitting element 240. The control circuit 210, the light emitting circuit 220, the driving transistor 230, and the light emitting element 240 can refer to the relevant description of the pixel circuit 100 and be deduced by analogy.

[0054] In the present embodiment, the driving transistor 230 is implemented by a p-type Metal-Oxide-Semiconductor Field-Effect Transistor (PMOSFET), for example. The control terminal (i.e., the gate terminal) of the driving transistor 230 is coupled to the first node N1. The first terminal (i.e., the first source / drain terminal) of the driving transistor 230 receives the third reference voltage OVDD. The second terminal (i.e., the second source / drain terminal) of the driving transistor 230 is coupled to the control circuit 210 and the light-emitting circuit 220 at the node N3.

[0055] exist Figure 2 In an embodiment, the control circuit 210 includes a reset circuit 211, a write circuit 212, and a compensation circuit 213. The reset circuit 211 is coupled to the first node N1. The reset circuit 211 receives a control signal S1 and a first reference voltage Vn. The write circuit 212 is coupled to the first node N1. The write circuit 212 is coupled to the light emitting circuit 220 at a second node N2. The write circuit 212 receives a control signal S2 and a second reference voltage Data. The compensation circuit 213 is coupled to the first node N1. The compensation circuit 213 is coupled to the light emitting circuit 220 and the second end (i.e., the second source / drain end) of the driving transistor 230 at a node N3. The compensation circuit 213 receives a control signal S3.

[0056] In detail, the light emitting circuit 220 includes a plurality of transistors T1-T2. These transistors T1-T2 are implemented, for example, by PMOSFET. The control terminals (i.e., gate terminals) of the plurality of transistors T1-T2 receive the light emitting signal EM respectively. The first terminal (i.e., the first source / drain terminal) of the transistor T1 is coupled to the second terminal (i.e., the second source / drain terminal) of the driving transistor 230 and the compensation circuit 213 at the node N3. The second terminal (i.e., the second source / drain terminal) of the transistor T1 is coupled to the first terminal NA of the light emitting element 240, and is also coupled to the first terminal (i.e., the first source / drain terminal) of the transistor T2. The second terminal (i.e., the second source / drain terminal) of the transistor T2 is coupled to the writing circuit 212 at the second node N2.

[0057] In the present embodiment, the write circuit 212 includes a transistor T3 and a capacitor C1. The transistor T3 is implemented by a PMOSFET, for example. The control terminal (i.e., the gate terminal) of the transistor T3 receives the control signal S2. The first terminal (i.e., the first source / drain terminal) of the transistor T3 receives the second reference voltage Data. The second terminal (i.e., the second source / drain terminal) of the transistor T3 is coupled to the second node N2 and coupled to the second terminal (i.e., the second source / drain terminal) of the transistor T2 and the first terminal of the capacitor C1. The second terminal of the capacitor C1 is coupled to the first node N1.

[0058] In this embodiment, the reset circuit 211 includes a transistor T4. The transistor T4 is implemented, for example, by a PMOSFET. The control terminal (i.e., the gate terminal) of the transistor T4 receives the control signal S1. The first terminal (i.e., the first source / drain terminal) of the transistor T4 receives the first reference voltage Vn. The second terminal (i.e., the second source / drain terminal) of the transistor T4 is coupled to the first node N1.

[0059] In the present embodiment, the compensation circuit 213 includes a transistor T5. The transistor T5 is implemented, for example, by a PMOSFET. The control terminal (i.e., the gate terminal) of the transistor T5 receives the control signal S3. The first terminal (i.e., the first source / drain terminal) of the transistor T5 is coupled to the second terminal (i.e., the second source / drain terminal) of the driving transistor 230 and the first terminal (i.e., the first source / drain terminal) of the transistor T1 at the node N3. The second terminal (i.e., the second source / drain terminal) of the transistor T5 is coupled to the first node N1.

[0060] In this embodiment, the light emitting element 240 is implemented by, for example, a micron light emitting diode (Micro LED). The first terminal NA of the light emitting element 240 is, for example, an anode terminal of the light emitting element 240. The second terminal of the light emitting element 240 receives the fourth reference voltage OVSS.

[0061] In this embodiment, the first reference voltage Vn is, for example, a low voltage source signal. The second reference voltage Data is, for example, a brightness signal (i.e., a data signal) of the light emitting element 240 when emitting light. The third reference voltage OVDD is, for example, a high power signal. The fourth reference voltage OVSS is, for example, another low voltage source signal different from the first reference voltage Vn.

[0062] Figure 3 According to the present invention Figure 2 A schematic diagram of the operation of the pixel circuit shown in the embodiment. FIG. 4A to FIG. 4C According to the present invention Figure 3 The operation schematic diagram of the pixel circuit shown in the embodiment. Figure 3 In FIG. 1 , the horizontal axis represents the operation time of the pixel circuit 200 , and the vertical axis represents the voltage value.

[0063] In this embodiment, the luminous signal EM and the plurality of control signals S1 to S3 are, for example, independent control signals. The luminous signal EM and the plurality of control signals S1 to S3 are switched between different voltage levels VH and VL. The voltage level VH is, for example, a high voltage level. The voltage level VL is, for example, a low voltage level.

[0064] For details on the operation of the pixel circuit 200 during the reset period P1, refer to Figure 3 as well as Figure 4A At time t1, the control signal S1 is switched from the voltage level VH to the voltage level VL to generate a falling edge to start the reset operation of the pixel circuit 200. At time t2, the control signal S1 is switched from the voltage level VL to the voltage level VH to generate a rising edge to end the reset operation of the pixel circuit 200.

[0065] During the reset period P1 (i.e., time t1 to t2), the reset circuit 211 resets the first voltage on the first node N1 based on the first reference voltage Vn according to the control signal S1. Specifically, the transistor T4 is controlled by the control signal S1 having the voltage level VL to be turned on to pull the first voltage on the first node N1 to the first reference voltage Vn. At this time, the driving transistor 230 is controlled by the first voltage to be turned on.

[0066] In addition, the transistor T3 is turned on by the control signal S2 with the voltage level VL to pull the voltage on the second node N2 to the second reference voltage Data. The transistor T5 is turned off by the control signal S3 with the voltage level VH. The plurality of transistors T1-T2 are turned off by the light emitting signal EM with the voltage level VH.

[0067] Thus, the first terminal NA of the light emitting element 240 is in a floating state. The voltage on the first terminal NA of the light emitting element 240 is expressed, for example, by the following formula (1). In the formula (1), VNA is the voltage value on the terminal NA, OVSS is the voltage value of the fourth reference voltage OVSS, and Vr is the voltage across the light emitting element 240 when it is in a floating state.

[0068] VNA=OVSS+Vr Formula (1)

[0069] For details on the operation of the pixel circuit 200 during the writing and compensation period P2, refer to Figure 3 as well as Figure 4BAt time t2, the control signal S3 is switched from the voltage level VH to the voltage level VL to generate a falling edge, so that the pixel circuit 200 starts the writing and compensation operation. At time t3, the control signal S3 is switched from the voltage level VL to the voltage level VH to generate a rising edge, so that the pixel circuit 200 ends the writing and compensation operation.

[0070] During the writing and compensation period P2 (i.e., time t2 to t3), the driving transistor 230 is kept turned on. The compensation circuit 213 sets the first voltage on the first node N1 based on the third reference voltage OVDD according to the control signal S3 to compensate the threshold voltage value of the driving transistor 230. At the same time, the writing circuit 212 sets the first voltage based on the second reference voltage Data according to the control signal S2 to write the grayscale data for the light emitting element 240 to emit light.

[0071] Specifically, the transistor T4 is turned off by the control signal S1 with the voltage level VH, and the transistor T5 is turned on by the control signal S3 with the voltage level VL to pull the first voltage on the first node N1 to the voltage difference between the third reference voltage OVDD and the threshold voltage of the driving transistor 230 .

[0072] In addition, transistor T3 is turned on by control signal S2 having voltage level VL to pull the voltage on second node N2 to second reference voltage Data. Capacitor C1 stores second reference voltage Data so that writing circuit 212 sets the first voltage on first node N1 based on second reference voltage Data on second node N2.

[0073] During the writing and compensation period P2, the plurality of transistors T1-T2 are turned off by the light emitting signal EM having the voltage level VH. Thus, the first terminal NA of the light emitting element 240 is kept in a floating state. The voltage on the first terminal NA of the light emitting element 240 is expressed by, for example, formula (1).

[0074] For details on the operation of the pixel circuit 200 during the light emitting period P3, refer to Figure 3 as well as Figure 4C At time t3, the emission signal EM is switched from the voltage level VH to the voltage level VL to generate a falling edge, so that the pixel circuit 200 starts the emission operation. At time t4, the emission signal EM is switched from the voltage level VL to the voltage level VH to generate a rising edge, so that the pixel circuit 200 ends the emission operation.

[0075] During the light-emitting period P3 (i.e., time t3 to t4), the reset circuit 211 and the compensation circuit 213 are disabled according to the control signal S1 and the control signal S3. At the same time, the light-emitting circuit 220 generates a bias voltage at the first terminal NA of the light-emitting element 240 according to the light-emitting signal EM to turn on the light-emitting element 240, and pulls the voltage at the node N2 to the sum of the bias voltage and the cross-voltage value (i.e., the turn-on voltage value) when the light-emitting element 240 is turned on. The write circuit 212 couples the voltage at the node N2 (i.e., the bias voltage and the cross-voltage of the light-emitting element 240) to the first node N1 according to the control signal S2, so that the first voltage at the first node N1 is set based on the first voltage set during the write and compensation period P2 and the aforementioned coupled voltage. The driving transistor 230 generates a driving current Id according to the first voltage at the first node N1, so as to provide the driving current Id to the light-emitting element 240 through the light-emitting circuit 220.

[0076] In detail, the plurality of transistors T3 to T5 are respectively controlled by the plurality of control signals S1 to S3 having the voltage level VH to be turned off. The transistor T1 is controlled by the light emitting signal EM having the voltage level VL to be turned on. The transistor T1 generates a bias voltage at the first terminal NA of the light emitting element 240. In this embodiment, the bias voltage is associated with the turn-on voltage of the light emitting element 240.

[0077] That is, the light emitting element 240 is turned on, and the voltage on the first terminal NA of the light emitting element 240 is expressed by the following formula (2), for example. VNA in the formula (2) is the voltage value on the terminal NA (i.e., the voltage value of the bias voltage), OVSS is the voltage value of the fourth reference voltage OVSS, and Vf is the cross-voltage value when the light emitting element 240 is turned on (i.e., the turn-on voltage value).

[0078] VNA=OVSS+Vf Formula (2)

[0079] It should be noted that the on-state voltage Vf in formula (2) is related to the temperature of the light emitting element 240. As the temperature of the light emitting element 240 increases, the on-state voltage Vf becomes smaller (ie, closer to 0). The on-state voltage Vf can also be called a forward bias value.

[0080] Continuing the above description, the transistor T2 is controlled by the light emitting signal EM with the voltage level VL to be turned on. The transistor T2 pulls the voltage on the second node N2 to the bias voltage on the terminal NA. The capacitor C1 couples the bias voltage on the second node N2 to the first node N1.

[0081] Thus, the first voltage on the first node N1 is represented by the following formula (3), for example. In the formula (3), VN1 is the voltage value of the first voltage, OVDD is the voltage value of the third reference voltage OVDD, Vth is the threshold voltage value of the driving transistor 230, OVSS is the voltage value of the fourth reference voltage OVSS, Vf is the cross-voltage value (i.e., the on-voltage value) when the light emitting element 240 is turned on, and Vdata is the voltage value of the second reference voltage Data.

[0082] VN1=OVDD-|Vth|+(OVSS+Vf-Vdata) Formula (3)

[0083] Based on the operation of the driving transistor 230, the driving current Id is expressed by, for example, the following formula (4). In the formula (4), Id is the current value of the driving current Id, μ is the carrier mobility, and C ox is the unit capacitance value of the gate oxide layer, W is the gate width of the driving transistor 230, L is the gate length of the driving transistor 230, OVSS is the voltage value of the fourth reference voltage OVSS, Vf is the cross-voltage value when the light-emitting element 240 is turned on (i.e., the turn-on voltage value), and Vdata is the voltage value of the second reference voltage Data.

[0084]

[0085] It should be noted that, as shown in formulas (3) and (4), the first voltage VN1 at the first node N1 is related to the on-state voltage value Vf of the light-emitting element 240. The driving current Id generated by the driving transistor 230 based on the first voltage VN1 is also related to the on-state voltage value Vf. Since the on-state voltage value Vf is related to the temperature of the light-emitting element 240, the first voltage VN1 and the driving current Id at the first node N1 are also related to the temperature of the light-emitting element 240.

[0086] Specifically, when the temperature of the light-emitting element 240 is higher, the on-voltage value of the light-emitting element 240 is smaller (i.e., closer to 0), thereby making the current value of the driving current Id larger. In this way, when the light-emitting element 240 is at a high temperature, the pixel circuit 200 can increase the magnitude of the driving current Id, thereby compensating for the brightness of the light-emitting element 240. On the other hand, when the temperature of the light-emitting element 240 is lower, the on-voltage value of the light-emitting element 240 is larger (i.e., further away from 0), thereby making the current value of the driving current Id smaller. In this way, when the light-emitting element 240 is at a low temperature, the pixel circuit 200 can reduce the magnitude of the driving current Id, thereby compensating for the brightness of the light-emitting element 240.

[0087] In some embodiments, the transistors T1 - T5 and the driving transistor 230 are respectively implemented by N-type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET). The signals in some embodiments are opposite to the corresponding signals in this embodiment.

[0088] In summary, the pixel circuit and the display panel of the embodiment of the present invention can provide different driving currents under the condition that the light emitting element has various temperatures (for example, high temperature) by compensating the on-voltage value of the light emitting element to the control terminal (that is, the first node) of the driving transistor based on the bias voltage of the light emitting element through the control circuit. In this way, the pixel circuit can adaptively compensate the brightness of the light emitting element according to the change of the light emitting element with temperature (for example, high temperature).

[0089] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the claims.

Claims

1. A pixel circuit, comprising: A driving transistor for providing a driving current; a light emitting circuit coupled between the driving transistor and a light emitting element, for providing the driving current to the light emitting element according to a light emitting signal; as well as a control circuit coupled to the light emitting circuit and coupled to the driving transistor at a first node, for setting a first voltage at the first node based on a plurality of reference voltages according to a plurality of control signals, During a light-emitting period, the light-emitting circuit generates a bias voltage on the first end of the light-emitting element according to the light-emitting signal, so that the control circuit sets the first voltage based on the bias voltage according to the control signals, and the driving transistor generates the driving current according to the first voltage. 2 . The pixel circuit as claimed in claim 1 , wherein the bias voltage is related to a turn-on voltage of the light emitting element.

3. The pixel circuit as claimed in claim 1, wherein the control circuit comprises: a reset circuit coupled to the first node, for resetting the first voltage based on a first reference voltage among the reference voltages according to a first control signal among the control signals during a reset period; a writing circuit coupled to the first node and the light emitting circuit, for setting the first voltage based on a second reference voltage among the reference voltages according to a second control signal among the control signals during a writing and compensation period; as well as A compensation circuit is coupled to the first node, the light emitting circuit and the driving transistor, and is used to set the first voltage based on a third reference voltage among the reference voltages according to a third control signal among the control signals during the writing and compensation period.

4. A pixel circuit as described in claim 3, wherein during the light-emitting period, the reset circuit and the compensation circuit are disabled according to the first control signal and the third control signal, and the write circuit couples the bias voltage and the cross-voltage of the light-emitting element to the first node according to the second control signal.

5. The pixel circuit as claimed in claim 3, wherein the light emitting circuit comprises: A first transistor having a control terminal for receiving the light emitting signal, a first terminal of the first transistor coupled to the first terminal of the driving transistor and the compensation circuit, and a second terminal of the first transistor coupled to the first terminal of the light emitting element; as well as A second transistor has a control terminal for receiving the light emitting signal, a first terminal of the second transistor is coupled to the first terminal of the light emitting element, and a second terminal of the second transistor is coupled to the writing circuit at a second node.

6. The pixel circuit as claimed in claim 5, wherein the writing circuit comprises: a third transistor, having a control terminal for receiving the second control signal, a first terminal for receiving the second reference voltage, and a second terminal for coupling to the second node; as well as A capacitor has a first terminal coupled to the second node, and a second terminal coupled to the first node.

7. The pixel circuit as claimed in claim 6, wherein the reset circuit comprises: A fourth transistor has a control terminal for receiving the first control signal, a first terminal of the fourth transistor for receiving the first reference voltage, and a second terminal of the fourth transistor coupled to the first node.

8. The pixel circuit as claimed in claim 7, wherein the compensation circuit comprises: A fifth transistor has a control terminal for receiving the third control signal, a first terminal of the fifth transistor is coupled to the first terminal of the driving transistor, and a second terminal of the fifth transistor is coupled to the first node. 9 . The pixel circuit as claimed in claim 8 , wherein a control terminal of the driving transistor is coupled to the first node, and a second terminal of the driving transistor receives the third reference voltage.

10. A display panel, comprising: a gate driving circuit; as well as A plurality of pixel circuits as claimed in claim 1 are coupled to the gate driving circuit and arranged in an array.

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