A gate driving circuit and a display panel

Abstract

The application discloses a gate driving circuit and a display panel. The gate driving circuit comprises: a Q-point signal processor receiving a third voltage, generating a Q-point signal in response to a first sub-control signal; a first node signal processor receiving a first voltage, generating a first node signal in response to the Q-point signal and the first sub-control signal; a second node signal processor receiving a second voltage, generating a second node signal in response to the first node signal and a second sub-control signal; a P-point signal processor receiving the second voltage, generating a P-point signal in response to the Q-point signal, the first node signal and the second sub-control signal; an output controller receiving the first voltage, generating the Q-point signal in response to the second node signal and the first sub-control signal; and an output signal processor receiving the first voltage and the second voltage, generating an output signal in response to the P-point signal and the Q-point signal. The output control unit is arranged, so that the output can be stabilized when the clock signal is high.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and specifically relates to a gate drive circuit and a display panel. Background Art

[0002] OLED foldable products are becoming increasingly popular in the market. Consumers have higher and higher requirements for the usage time of mobile phones, and accordingly have higher requirements for screen power consumption.

[0003] The gate drive circuit can output a negative polarity row-by-row scan signal Nscan. The scan signal Nscan controls the on / off state of each pixel in the liquid crystal display panel within the pixel drive circuit. Each pixel consists of a light-emitting device and a driver transistor. The scan signal Nscan can be connected to the control electrode of an N-channel driver transistor. The high-level N-level scan signal Nscan can be used to turn on the corresponding N-channel driver transistor, connecting the light-emitting device to a power source and emitting light. When the N-level scan signal Nscan is low, the driver transistor is turned off, disconnecting the light-emitting device from the voltage source. Current cannot flow through the light-emitting device, and the light-emitting device is unable to emit light.

[0004] The current gate drive circuit outputs a negative polarity row-by-row scan signal Nscan. It uses a hold time to set the clock signal (Clock signal) to VGH, so that the scan signal Nscan is always low, thereby reducing IC power consumption. However, after the clock signal (Clock signal) is set to VGH for a long time, the stability of the output scan signal Nscan is poor. Summary of the Invention

[0005] The present application provides a gate drive circuit and a display panel to solve the technical problem of poor stability of the scan signal output by the current gate drive circuit.

[0006] In a first aspect, an embodiment of the present application provides a gate drive circuit, comprising:

[0007] A Q-point signal processor having a Q-point, the Q-point signal processor receiving a third voltage and generating a Q-point signal in response to the first sub-control signal;

[0008] a first node signal processor having a first node, the first node signal processor receiving a first voltage and generating a first node signal in response to a first sub-control signal;

[0009] a second node signal processor having a second node, the second node signal processor receiving a second voltage and generating a second node signal in response to the first node signal and the second sub-control signal;

[0010] A point P signal processor having a point P, the point P signal processor receiving the second voltage and generating a point P signal in response to the Q point signal, the first node signal and the second sub-control signal;

[0011] an output controller receiving the first voltage and generating the Q-point signal in response to the second node signal and the first sub-control signal;

[0012] An output signal processor receives the first voltage and the second voltage, and generates an output signal in response to the P point signal and the Q point signal.

[0013] In some embodiments, the second node signal processor includes:

[0014] a first transistor having a gate terminal connected to the first node and a source terminal to which the second voltage is applied;

[0015] a second transistor having a drain terminal connected to the drain terminal of the first transistor, a source terminal to which the second sub-control signal is applied, and a gate terminal connected to the second node;

[0016] a first capacitor having a first electrode connected to the drain terminal of the first transistor and a second electrode connected to the second node;

[0017] The second node signal is output from the second electrode of the first capacitor and the gate terminal of the second transistor which are connected to each other.

[0018] In some embodiments, the Q-point signal processor comprises:

[0019] The third transistor has a source terminal to which a third voltage is applied, a gate terminal to which the first sub-control signal is applied, and a drain terminal connected to the Q point.

[0020] In some embodiments, the first node signal processor includes:

[0021] a fourth transistor having a source terminal to which the first voltage is applied, a gate terminal to which the first sub-control signal is applied, and a drain terminal connected to the first node;

[0022] A fifth transistor has a gate terminal connected to the Q point, a source terminal to which the first sub-control signal is applied, and a drain terminal connected to the first node.

[0023] In some embodiments, the point P signal processor includes:

[0024] a sixth transistor having a gate terminal connected to the first node and a source terminal to which the second sub-control signal is applied;

[0025] a seventh transistor having a gate terminal to which the second sub-control signal is applied, a source terminal connected to the drain terminal of the sixth transistor, and a drain terminal connected to the P point;

[0026] a second capacitor having a first electrode connected to the first node and a second electrode connected to the drain terminal of the sixth transistor;

[0027] The third capacitor has a first electrode to which the second voltage is applied and a second electrode connected to the P point.

[0028] In some embodiments, the output signal processor comprises:

[0029] a ninth transistor having a gate terminal connected to the Q point and a drain terminal to which the first voltage is applied;

[0030] a tenth transistor having a gate terminal connected to the P point, a source terminal to which the second voltage is applied, and a drain terminal connected to the source terminal of the ninth transistor;

[0031] The source terminal of the ninth transistor and the drain terminal of the tenth transistor connected to each other generate the output signal.

[0032] In some embodiments, the output controller comprises:

[0033] an eleventh transistor having a gate terminal to which the first sub-control signal is applied and a drain terminal connected to the Q point;

[0034] a twelfth transistor having a gate terminal to which the first voltage is applied, a source terminal connected to the second node, and a drain terminal connected to the source terminal of the eleventh transistor;

[0035] a thirteenth transistor having a gate terminal connected to the second node, a source terminal connected to the second node, and a drain terminal connected to the Q point;

[0036] The drain terminal of the eleventh transistor and the drain terminal of the thirteenth transistor output the Q-point signal.

[0037] In some embodiments, the gate driving circuit further includes a fifteenth transistor;

[0038] The fifteenth transistor has a gate terminal to which the first voltage is applied, a source terminal connected to the drain terminal of the eleventh transistor, and a drain terminal connected to the drain terminal of the thirteenth transistor.

[0039] In some embodiments, the gate driving circuit further includes a fourteenth transistor;

[0040] The fourteenth transistor has a gate terminal to which the third sub-control signal is applied, a source terminal to which the second voltage is applied, and a drain terminal connected to the Q point.

[0041] In a second aspect, an embodiment of the present application provides a display panel, comprising a gate driving circuit as described in any embodiment of the first aspect.

[0042] Compared with the prior art, the gate drive circuit provided in the embodiment of the present application includes an output control unit, which is used to maintain the potential of the second node when the clock signal becomes high, thereby stabilizing the output. In the existing gate drive circuit, when the first sub-control signal XCK and the second sub-control signal CK are set to the second voltage VGH, the N2 node changes from the original jump signal to a relatively high potential. As time goes by, the potential of the N2 node is affected by the leakage of the transistor (such as a thin film transistor or a field effect transistor), and the potential rises, causing the output signal N_OUT to also rise, resulting in display abnormality. By setting an output control unit, the embodiment of the present application can maintain the potential of the second node when the clock signal becomes high, thereby stabilizing the output.

[0043] In the gate drive circuit provided by the embodiment of the present application, the output control unit includes a thirteenth transistor, which implements the function of a diode and is unidirectionally conductive. The potential can only be charged to the Q point from the second node N2. Therefore, the potential of the Q point will not be recharged to the second node N2. The parasitic capacitance of the ninth transistor T9 in the output signal processor will pull down the Q point, and the potential of the Q point will be lower and will not rise. Therefore, after the second sub-control signal CK or the first sub-control signal XCK is set to VGH, the second node N2 can be stabilized at approximately 2*VGL, and the output signal OUT waveform can stably output VGL. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 is a circuit diagram of an existing gate drive circuit;

[0046] Figure 2 for Figure 1 The working timing diagram of the gate drive circuit shown;

[0047] Figure 3 for Figure 1 The gate drive circuit node signal waveform diagram shown;

[0048] Figure 4A circuit diagram of a gate drive circuit provided in one embodiment of the present application;

[0049] Figure 5 A circuit diagram of a gate drive circuit provided in another embodiment of the present application;

[0050] Figure 6 for Figure 5 The gate drive circuit node signal waveform diagram shown;

[0051] Marking Description:

[0052] 11-Q point signal processor, 12-first node signal processor, 13-second node signal processor, 14-P point signal processor, 15-output controller, 16-output signal processor, 17-Q point reset unit, 101-N1 node control unit, 102-N3 node control unit, 103-P1 point control unit, 104-Q1 point control unit, 105-N2 node control unit. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0054] It should be understood that in the following description, "circuit" refers to a conductive loop composed of at least one element or subcircuit connected electrically or electromagnetically. When an element or circuit is said to be "connected to" another element, an element or circuit is "connected" to another element, or an element / circuit is said to be "connected" between two nodes, it can be directly coupled or connected to the other element or there can be intervening elements. The connection between the elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements between the two elements.

[0055] The terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0056] Explanation of symbols in this application:

[0057] XCK-first sub-control signal, CK-second sub-control signal, Control-third sub-control signal, VGL-first voltage, VGH-second voltage, STV-third voltage, N_in-control voltage. The first voltage VGL is a low potential, and the second voltage VGH is a high potential.

[0058] Figure 1 FIG1 shows a circuit diagram of an existing gate drive circuit. The gate drive circuit of the prior art can be applied to a display panel. Figure 1 As shown, it is a 13T3C circuit (consisting of 13 TFTs and 3 capacitors), including: N1 node control unit 101, N3 node control unit 102, P1 point control unit 103, high-end output transistor (transistor T10), Q1 point control unit 104, N2 node control unit 105 and low-end output transistor (transistor T9).

[0059] The Q1 point control unit 104 has a Q1 point, and the Q1 point control unit 104 is electrically connected to the control voltage terminal, the first clock terminal and the Q1 point respectively. The control voltage terminal provides a control voltage N_in. The Q1 point control unit 104 is used to control the Q1 point to be connected to the control voltage terminal under the control of the first sub-control signal XCK provided by the first clock terminal.

[0060] The N1 node control unit 101 has an N1 node, and the N1 node control unit 101 is electrically connected to the first voltage terminal, the first clock terminal, the N1 node and the Q1 point, and is used to control the N1 node to be connected to the first voltage terminal under the control of the first sub-control signal XCK provided by the first clock terminal, and the first voltage terminal provides the first voltage VGL; the N1 node control unit 101 is also used to control the N1 node to be connected to the first clock terminal under the control of the Q1 point potential.

[0061] The N3 node control unit 102 has an N3 node, and the N3 node control unit 102 is electrically connected to the N1 node, the N3 node and the second clock end respectively, and the second clock end provides a second sub-control signal CK; the N3 node control unit 102 is used to control the connection between the N3 node and the second clock end under the potential control of the N1 node, and control the potential of the N3 node according to the potential of the N1 node.

[0062] Node P1 control unit 103 includes a node P1. Node P1 control unit 103 is electrically connected to node N3, a second clock terminal, node P1, node Q1, and a second voltage terminal. The second voltage terminal provides a second voltage VGH, and the second clock terminal provides a second sub-control signal CK. Node P1 control unit 103 is configured to, under the control of the second sub-control signal CK provided by the second clock terminal, control the connection between node N3 and node P1 and maintain the potential of node P1. Furthermore, under the control of the potential of node Q1, control the connection between node P1 and the second voltage terminal.

[0063] The N2 node control unit 105 has an N2 node, and the N2 node control unit 105 is electrically connected to the N1 node, the second voltage terminal (providing the second voltage VGH), the N2 node, the Q1 point and the second clock terminal (providing the second sub-control signal CK), respectively, and is used to control the connection between the N2 node and the second voltage terminal under the potential control of the N1 node and the control of the second sub-control signal CK.

[0064] Figure 2 for Figure 1 The working timing diagram of the gate drive circuit shown in FIG. Figure 2 As shown, in the first stage, the second voltage VGH is fed into point Q1, at which point transistor T9 is turned off and point P1 is floating. In the second stage, the first voltage VGL is fed into point P1, turning on transistor T10 and setting the output terminal potential N_out from L to H. In the third stage, the second voltage VGH is fed into point Q1, turning off transistor T9. Under the action of capacitor C2, transistor T2 remains on. In the fourth stage, the fourth stage is the same as the second stage. In the fifth stage, the first voltage VGL is fed into point Q1, turning on transistor T9 and outputting the first voltage VGL to the output terminal. The second voltage VGH is fed into point P1, turning off transistor T2. In the sixth stage, point Q1 is floating and is coupled by capacitor C2 to a lower potential, i.e., lower than the first voltage VGL, to the first voltage VGL-Vth. Point P1 maintains the second voltage VGH, where Vth is the threshold voltage of the transistor.

[0065] Figure 3 for Figure 1 The gate drive circuit node signal waveform is shown in FIG. Figure 3 As shown, it is mainly manifested that when the first sub-control signal XCK and the second sub-control signal CK are set to the second voltage VGH, the N2 node changes from the original jump signal to a relatively high potential. As time goes by, the potential of the N2 node is affected by the leakage of the transistor (such as a thin film transistor or a field effect transistor), and the potential rises, causing the output signal OUT1 and the output signal OUT2 (OUT1 is the output signal of the previous level gate drive circuit, and OUT2 is the output signal of the next level gate drive circuit) to also rise, resulting in display abnormality.

[0066] At least one embodiment of the present application provides a gate driving circuit that is applied to a display panel.

[0067] In a specific embodiment, the display panel may include a display area and a non-display area. The display area is provided with multiple rows and columns of pixel units, each pixel unit includes a pixel driving circuit and a light-emitting device, and the non-display area is provided with a gate driving module and a display driving module. The gate driving module outputs a row scanning signal, and the display driving module outputs a data signal. The pixel driving circuit controls the light-emitting device to emit light under the control of the row scanning signal and the data signal.

[0068] In some embodiments, the display driving module further outputs a light emitting control signal EM, and the pixel driving circuit controls the light emitting device to emit light under the control of the row scanning signal, the data signal and the light emitting control signal EM.

[0069] The gate driving module may include a plurality of cascaded gate driving circuits. The structure of the N-th gate driving circuit for outputting the N-th gate driving signal may be as follows: Figure 4 shown.

[0070] In the present application, the transistor may include one selected from a bipolar transistor or a field effect transistor, the first pole and the second pole of the transistor are respectively the high potential end and the low potential end on the current path, and the control pole is used to receive a control signal to control the conduction and shutdown of the transistor.

[0071] MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first electrode, a second electrode and a control electrode. When the MOSFET is in the on state, current flows from the first electrode to the second electrode.

[0072] The first electrode, second electrode and control electrode of the P-type MOSFET are the source, drain and gate respectively; the first electrode, second electrode and control electrode of the N-type MOSFET are the drain, source and gate respectively.

[0073] like Figure 4 、 Figure 5 The transistors in the gate drive circuit shown can be thin film transistors or field effect transistors. In this embodiment, thin film transistors are used, and all are P-type transistors. In other embodiments, they can also be N-type transistors, and the corresponding wiring is adjusted accordingly. There is no need to limit this.

[0074] The circuit diagram of the gate drive circuit provided in this embodiment is as follows Figure 4 As shown, the gate driving circuit provided in this embodiment includes: a Q point signal processor 11, a first node signal processor 12, a second node signal processor 13, a P point signal processor 14, an output controller 15 and an output signal processor 16.

[0075] The Q-point signal processor 11 has a Q-point. The Q-point signal processor 11 receives the third voltage and generates a Q-point signal in response to the first sub-control signal XCK.

[0076] By way of example, the Q-point signal processor 11 is electrically connected to the third voltage terminal, the first clock terminal, and the Q-point, respectively. Under control of a first sub-control signal XCK provided by the first clock terminal, the Q-point signal processor 11 controls the Q-point to be connected to the third voltage terminal, which provides a third voltage STV. The Q-point signal processor 11 includes a third transistor T3, wherein a gate terminal of the third transistor T3 is connected to the first clock terminal, which provides the first sub-control signal XCK. A source terminal of the third transistor T3 is connected to the third voltage terminal to receive the third voltage STV, and a drain terminal of the third transistor T3 is connected to the Q-point.

[0077] The first node signal processor 12 has a first node N1 , receives a first voltage, and generates a first node signal in response to a Q-point signal and a first sub-control signal.

[0078] By way of example, the first node signal processor 12 is electrically connected to a first voltage terminal, a first clock terminal, a first node N1, and a Q point. Under control of a first sub-control signal XCK provided by the first clock terminal, the first node signal processor 12 controls the first node N1 to be connected to the first voltage terminal, which provides a first voltage VGL. Under control of the potential at the Q point, the first node signal processor 12 controls the first node N1 to be connected to the first clock terminal. The first node signal processor 12 includes a fourth transistor T4 and a fifth transistor T5. The control electrode of the fourth transistor T4 is connected to the first clock terminal, the source terminal of the fourth transistor T4 is connected to the first voltage terminal, and the drain terminal of the fourth transistor T4 is connected to the first node N1. The control electrode of the fifth transistor T5 is connected to the Q point, the source terminal of the fifth transistor T5 is connected to the first clock terminal, and the drain terminal of the fifth transistor T5 is connected to the first node N1.

[0079] The second node signal processor 13 has a second node N2 , receives the second voltage, and generates a second node signal in response to the first node signal and the second sub-control signal.

[0080] By way of example, the second node signal processor 13 is electrically connected to the first node N1, the second node N2, the second voltage terminal, and the second clock terminal, respectively. The second voltage terminal provides the second voltage VGH, and the second clock terminal provides the second sub-control signal CK. The second node signal processor 13 includes a first transistor T1, a second transistor T2, and a first capacitor C1. The first transistor T1 has a gate terminal connected to the first node N1 and a source terminal to which the second voltage VGH is applied. The second transistor T2 has a drain terminal connected to the drain terminal of the first transistor T1, a source terminal to which the second sub-control signal CK is applied, and a gate terminal connected to the second node N2. The first capacitor C1 has a first electrode connected to the drain terminal of the first transistor T1 and a second electrode connected to the second node N2. The second node signal is output from the second electrode of the first capacitor C1 and the gate terminal of the second transistor T2, which are connected to each other.

[0081] The P-point signal processor 14 has a P-point. The P-point signal processor 14 receives the second voltage and generates a second-node signal in response to the first-node signal and the second sub-control signal.

[0082] By way of example, the signal processor 14 at point P is electrically connected to a first node N1, a second node N2, a second clock terminal, point P, point Q, and a second voltage terminal, respectively. The second voltage terminal provides a second voltage VGH, and the second clock terminal provides a second sub-control signal CK. The signal processor 14 at point P includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a second capacitor C2, and a third capacitor C3. The sixth transistor T6 has a gate terminal connected to the first node N1 and a source terminal to which the second sub-control signal CK is applied. The seventh transistor T7 has a gate terminal to which the second sub-control signal is applied, a source terminal connected to the drain terminal of the sixth transistor T6, and a drain terminal connected to point P. The eighth transistor T8 has a gate terminal connected to point Q, a source terminal to which the second voltage is applied, and a drain terminal connected to point P. The second capacitor C2 has a first electrode connected to the first node N1 and a second electrode connected to the drain terminal of the sixth transistor T6. The third capacitor C3 has a first electrode to which the second voltage is applied and a second electrode connected to point P.

[0083] Under the control of the second sub-control signal CK provided by the second clock terminal, the drain terminal of the sixth transistor T6 is controlled to be connected to the P point, and the potential of the P point is maintained. Under the potential control of the Q point, the P point is controlled to be connected to the second voltage terminal, and the second voltage terminal provides the second voltage VGH.

[0084] The output controller 15 receives the first voltage and generates a Q-point signal in response to the second node signal and the first sub-control signal.

[0085] As an example, the output controller 15 is connected to the second node N2, the Q point, the first clock terminal and the first voltage terminal, and is used to control the second node N2 to be connected to the Q point under the control of the first voltage provided by the first voltage terminal and the control of the first sub-control signal provided by the first clock terminal.

[0086] In this embodiment, the output controller 15 includes an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13. The eleventh transistor T11 has a gate terminal to which the first sub-control signal is applied and a drain terminal connected to the Q point; the twelfth transistor T12 has a gate terminal to which the first voltage is applied, a source terminal connected to the second node, and a drain terminal connected to the source terminal of the eleventh transistor; the thirteenth transistor T13 has a gate terminal connected to the second node, a source terminal connected to the second node, and a drain terminal connected to the Q point; wherein the drain terminal of the eleventh transistor T11 and the drain terminal of the thirteenth transistor T13 output the Q point signal.

[0087] The thirteenth transistor T13 is connected between the second node N2 and the point Q, and is used to control the current of the second node N2 to flow to the point Q according to the potential of the second node N2, and prevent the current of the point Q from flowing to the second node N2.

[0088] In this embodiment, the thirteenth transistor T13 implements a diode function (in some embodiments, the thirteenth transistor T13 may be a diode instead of a transistor, with the anode of the diode connected to the second node N2 and the cathode of the diode connected to the Q point). It is unidirectionally conductive, and the potential can only be charged from the second node N2 to the Q point. Therefore, the potential of the Q point will not be recharged to the second node N2, and the Q point will be pulled down through the parasitic capacitance of the ninth transistor T9. The potential of the Q point will be even lower and will not rise. Therefore, after the second sub-control signal CK or the first sub-control signal XCK is set to a high level (the second voltage VGH), the second node N2 can be stabilized at approximately 2*VGL, and the output signal OUT waveform can stably output VGL.

[0089] As an example, the output signal processor (16) includes a ninth transistor T9 and a tenth transistor T10. The ninth transistor T9 has a gate terminal connected to the Q point and a drain terminal to which a first voltage is applied; the tenth transistor T10 has a gate terminal connected to the P point and a source terminal to which a second voltage is applied, and a drain terminal connected to the source terminal of the ninth transistor; wherein the source terminal of the ninth transistor T9 and the drain terminal of the tenth transistor T10 connected to each other generate an output signal.

[0090] In some embodiments, as Figure 5As shown, the fifteenth transistor T15 is connected between the Q point signal processor 11 and the gate terminal of the ninth transistor T9, the drain terminal of the fifteenth transistor T15 is connected to the Q point, the source terminal of the fifteenth transistor T15 is connected to the gate terminal of the ninth transistor T9, the gate terminal of the eighth transistor T8 is connected to the Q point, the drain terminal of the eleventh transistor T11 is connected to the Q point, and the drain terminal of the thirteenth transistor is connected to the source terminal of the fifteenth transistor T15.

[0091] Because the ninth transistor T9 is turned on to output the full first voltage VGL, the potential at point Q is extremely low. This creates a significant voltage difference between the potential at point Q and the gate terminal of the second transistor T2 (the potential at point N2), thereby affecting the stability of point Q. With the addition of the fifteenth transistor T15, the low potential at point Q acts only on the fifteenth transistor T15. The voltage difference between the source and drain terminals of the twelfth transistor T12 is not significant, and thus the voltage difference between the potential at point Q and the gate terminal of the fifteenth transistor T15 is not too significant, thereby improving the stability of the output signal processor 16.

[0092] In some embodiments, a sixteenth transistor T16 is connected between the first node signal processor 12 and the point P signal processor 14. The source terminal of the sixteenth transistor T16 is connected to the first node N1, and the drain terminal of the sixteenth transistor T16 is connected to the gate terminal of the sixth transistor T6. The gate terminal of the first transistor T1 is connected to the first node N1, and the drain terminal of the fifth transistor T5 is connected to the first node N1. The sixteenth transistor T16 functions similarly to the fifteenth transistor T15. The fourth transistor T4 is also driven by the first voltage VGL. After the sixteenth transistor T16 is added, the voltage difference between the source and drain terminals of the sixteenth transistor T16 is not too large.

[0093] like Figure 5 As shown, this embodiment further includes a Q point reset unit 17, which is connected between the reset control terminal, the second voltage terminal, and the Q point. The reset terminal controls the output of the third sub-control signal Control. The Q point reset unit 17 includes a fourteenth transistor T14, the control electrode of the fourteenth transistor T14 being connected to the reset control terminal, the source terminal of the fourteenth transistor T14 being connected to the second voltage terminal, and the drain terminal of the fourteenth transistor T14 being connected to the Q point, i.e., the drain terminal of the third transistor T3.

[0094] The timing diagram of the gate drive circuit provided in this embodiment is as follows: Figure 6 shown.

[0095] Phase ①: The first sub-control signal XCK is changed to the first voltage VGL, the control voltage STV changes from high to low, the third transistor T3 is turned on, and the low potential enters the second node N2 through the eleventh transistor T11 and the twelfth transistor T12. The second sub-control signal CK changes from VGH to VGL. Because the second node N2 is at a low potential, the second transistor T2 is turned on, and the low potential will be transmitted to the upper plate of the first capacitor C1. The upper plate of the first capacitor C1 was originally VGH. After the low potential is added, it changes from VGH to VGL. Through capacitive coupling, the potential of the third node N3 is pulled down, and the particularly low potential is transmitted to the Q point through the thirteenth transistor T13. Then the potential of the Q potential becomes lower, so that the ninth transistor T9 is better turned on. Figure 1 In the illustrated gate drive circuit, the N2 node is affected by the first capacitor C1, and its potential may jump around. However, in this embodiment, the thirteenth transistor T13 implements a diode function and is unidirectionally conductive. The potential can only be charged from the second node N2 to the Q point. Therefore, the potential of the Q point will not be fed back to the second node N2. Instead, the Q point will be pulled down through the parasitic capacitance of the ninth transistor T9, and the potential of the Q point will be even lower and will not rise. Therefore, after the second sub-control signal CK or the first sub-control signal XCK is set to VGH, the second node N2 can be stabilized at approximately 2*VGL, and the output signal OUT waveform can stably output VGL.

[0096] Phase ②: the second sub-control signal CK jumps, the thirteenth transistor T13 continuously charges the Q point to maintain a low potential.

[0097] Phase ③: the second sub-control signal CK stops maintaining the second voltage VGH. Since the thirteenth transistor T13 is a diode, the Q point potential remains low, the ninth transistor T9 remains turned on, and the output signal OUT can be stabilized at the first voltage VGL.

[0098] While the embodiments of the present application are described above, these embodiments do not exhaustively describe all details, nor do they limit the present application to specific embodiments. Clearly, many modifications and variations are possible based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present application, thereby enabling those skilled in the art to effectively utilize the present application and its modifications.

Claims

1. A gate drive circuit, applied to a display panel, characterized in that: include: A Q-point signal processor (11) having a Q-point, wherein the Q-point signal processor (11) receives a third voltage and generates a Q-point signal in response to the first sub-control signal; A first node signal processor (12) having a first node, wherein the first node signal processor (12) receives a first voltage and generates a first node signal in response to the Q-point signal and a first sub-control signal; A second node signal processor (13) having a second node, wherein the second node signal processor (13) receives a second voltage and generates a second node signal in response to the first node signal and the second sub-control signal; A P point signal processor (14) having a P point, the P point signal processor (14) receiving the second voltage and generating a P point signal in response to the Q point signal, the first node signal and the second sub-control signal; An output controller (15) receives the first voltage and generates the Q-point signal in response to the second node signal and the first sub-control signal; the output controller (15) includes a thirteenth transistor, the thirteenth transistor having a gate terminal connected to the second node, a source terminal connected to the second node, and a drain terminal connected to the Q-point, the drain terminal of the thirteenth transistor outputting the Q-point signal, and realizing a diode function through the thirteenth transistor, which is unidirectionally conductive, and the potential can only charge the Q-point from the second node; An output signal processor (16) receives the first voltage and the second voltage, and generates an output signal in response to the P point signal and the Q point signal.

2. The gate drive circuit according to claim 1, wherein: The second node signal processor (13) includes: A first transistor having a gate terminal connected to the first node and a source terminal to which the second voltage is applied; a second transistor having a drain terminal connected to the drain terminal of the first transistor, a source terminal to which the second sub-control signal is applied, and a gate terminal connected to the second node; a first capacitor having a first electrode connected to the drain terminal of the first transistor and a second electrode connected to the second node; The second node signal is output from the second electrode of the first capacitor and the gate terminal of the second transistor which are connected to each other.

3. The gate drive circuit according to claim 1, wherein: The Q-point signal processor (11) comprises: The third transistor has a source terminal to which a third voltage is applied, a gate terminal to which the first sub-control signal is applied, and a drain terminal connected to the Q point.

4. The gate drive circuit according to claim 1, wherein: The first node signal processor (12) comprises: a fourth transistor having a source terminal to which the first voltage is applied, a gate terminal to which the first sub-control signal is applied, and a drain terminal connected to the first node; A fifth transistor has a gate terminal connected to the Q point, a source terminal to which the first sub-control signal is applied, and a drain terminal connected to the first node.

5. The gate driving circuit according to claim 1, wherein: The P point signal processor (14) includes: a sixth transistor having a gate terminal connected to the first node and a source terminal to which the second sub-control signal is applied; a seventh transistor having a gate terminal to which the second sub-control signal is applied, a source terminal connected to the drain terminal of the sixth transistor, and a drain terminal connected to the P point; an eighth transistor having a gate terminal connected to the Q point, a source terminal to which the second voltage is applied, and a drain terminal connected to the P point; a second capacitor having a first electrode connected to the first node and a second electrode connected to the drain terminal of the sixth transistor; The third capacitor has a first electrode to which the second voltage is applied and a second electrode connected to the P point.

6. The gate driving circuit according to claim 1, wherein: The output signal processor (16) comprises: a ninth transistor having a gate terminal connected to the Q point and a drain terminal to which the first voltage is applied; a tenth transistor having a gate terminal connected to the point P, a source tube to which the second voltage is applied, and a drain terminal connected to the source terminal of the ninth transistor; The source terminal of the ninth transistor and the drain terminal of the tenth transistor connected to each other generate the output signal.

7. The gate driving circuit according to claim 1, wherein: The output controller (15) comprises: an eleventh transistor having a gate terminal to which the first sub-control signal is applied and a drain terminal connected to the Q point; a twelfth transistor having a gate terminal to which the first voltage is applied, a source terminal connected to the second node, and a drain terminal connected to the source terminal of the eleventh transistor; The drain terminal of the eleventh transistor outputs the Q-point signal.

8. The gate driving circuit according to claim 7, wherein: The gate driving circuit further includes a fifteenth transistor; The fifteenth transistor has a gate terminal to which the first voltage is applied, a source terminal connected to the drain terminal of the eleventh transistor, and a drain terminal connected to the drain terminal of the thirteenth transistor.

9. The gate driving circuit according to claim 1, wherein: The gate drive circuit further includes a fourteenth transistor; The fourteenth transistor has a gate terminal to which the third sub-control signal is applied, a source terminal to which the second voltage is applied, and a drain terminal connected to the Q point.

10. A display panel, characterized in that: The gate drive circuit comprises the gate drive circuit according to any one of claims 1 to 9.

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