Display device and driving method thereof

Abstract

The invention provides a display device and a driving method thereof, and the display device comprises a display panel and a driving system electrically connected to the display panel. The driving system comprises a clock module used for generating a clock signal, a judgment module used for generating a reset signal according to the relation between clock information in the clock signal and preset information, and a processing module used for obtaining a display signal used for controlling the display panel to display a picture according to reset information in the reset signal. And the processing module is also used for processing the display signal, so that the blank screen phenomenon when the display device is powered on is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display device and a driving method thereof. Background Art

[0002] As the integration of the timing controller of the display module becomes higher and higher, the technology of integrating the timing controller and the data driver into a "timing controller embedded data driver" chip has been gradually applied to display products. However, the current "timing controller embedded data driver" chip needs to meet strict timing requirements during the power-on of the display device. How to meet the above timing requirements to avoid the black screen phenomenon of the display device when it is powered on has become a current problem. Summary of the invention

[0003] The object of the present invention is to provide a display device and a driving method thereof, so as to improve the black screen phenomenon when the display device is powered on.

[0004] The present invention provides a display device, including a display panel and a driving system electrically connected to the display panel, wherein the driving system includes:

[0005] A clock module, used for generating a clock signal;

[0006] A judgment module, used for generating a reset signal according to a relationship between clock information in the clock signal and preset information;

[0007] A processing module is used to obtain a display signal for controlling the display panel to display a picture according to the reset information in the reset signal, and to process the display signal.

[0008] In some embodiments, the clock signal includes a plurality of clock pulses, the clock information includes the number of the clock pulses, the preset information includes a preset value, and the determination module includes:

[0009] a counting unit, configured to generate a first control signal according to the clock signal, wherein the first control signal is an effective first control potential when the number of the clock pulses is greater than or equal to the preset value, and the effective first control potential is used to control the reset information to be a first sub-reset signal;

[0010] Wherein, the processing module is used to obtain the display signal according to the first sub-reset signal.

[0011] In some embodiments, the counting unit comprises:

[0012] A plurality of triggers, used for generating a corresponding plurality of trigger signals according to the clock signal;

[0013] A signal processor is used to generate the first control signal according to the multiple trigger signals.

[0014] In some embodiments, the first and second ends of the trigger are electrically connected to a first voltage line for transmitting a first voltage signal, the clock end of the first-level trigger is electrically connected to the clock module, and the clock end of each of the second to last-level triggers is electrically connected to the output end of the trigger in the previous level.

[0015] In some embodiments, the signal processor is used to control the first control signal to be the corresponding effective first control potential when each of the plurality of trigger signals is a first sub-trigger signal.

[0016] In some embodiments, a power manager electrically connected to the driving system is further included, the power manager is used to generate a second voltage signal, and the judgment module further includes:

[0017] An AND gate unit is electrically connected to the counting unit and the power manager, and is used to control the reset signal to be the first sub-reset signal according to the effective first control potential corresponding to the second voltage signal and the first control signal.

[0018] In some embodiments, a reset circuit electrically connected to the driving system is further included, wherein the reset circuit is used to generate an initial reset signal;

[0019] The AND gate unit is used to generate a second control signal according to the second voltage signal and the first control signal, and the second control signal is used to adjust the initial reset signal to the reset signal.

[0020] In some embodiments, the power manager is further used to generate a third voltage signal, and the clock module is used to generate the clock signal according to the third voltage signal.

[0021] In some embodiments, the driving system includes a driving chip, and the driving chip includes the clock module, the judgment module, the processing module and the data driving module;

[0022] The processing module is used to generate an image signal according to the clock signal and the display signal;

[0023] The data driving module is used to control the display panel to display a picture according to the image signal.

[0024] In some embodiments, the driving system includes a timing control chip electrically connected to the display panel, and a source driving chip electrically connected between the display panel and the timing control chip, and the timing control chip includes the clock module, the judgment module and the processing module;

[0025] The processing module is used to generate an image signal according to the clock signal and the display signal;

[0026] The source driver chip is used to control the display panel to display an image according to the image signal.

[0027] The present invention also provides a method for driving a display device, wherein the display device includes a display panel and a driving system electrically connected to the display panel, wherein the driving system includes a clock module, a judgment module and a processing module, and the method includes:

[0028] The clock module generates a clock signal;

[0029] The judgment module generates a reset signal according to the relationship between the clock information in the clock signal and the preset information;

[0030] The processing module obtains a display signal for controlling the display panel to display a picture according to the reset information in the reset signal, and processes the display signal.

[0031] In some embodiments, the clock signal includes a plurality of clock pulses, the clock information includes the number of the clock pulses, the preset information includes a preset value, the judgment module includes a counting unit, and the step of the judgment module generating a reset signal according to the relationship between the clock information in the clock signal and the preset information includes:

[0032] The counting unit generates a first control signal according to the clock signal, the first control signal is a corresponding effective first control potential when the number of the clock pulses is greater than or equal to the preset value, and the effective first control potential is used to control the reset information to be a first sub-reset signal;

[0033] The step of the processing module acquiring a display signal for controlling the display panel to display a picture according to the reset information in the reset signal includes:

[0034] The processing module acquires the display signal when the reset information is the first sub-reset signal.

[0035] The present invention provides a display device and a driving method thereof. The display device includes a display panel and a driving system electrically connected to the display panel. The driving system includes a clock module for generating a clock signal, a judgment module for generating a reset signal according to the clock signal, and a processing module for obtaining a display signal for controlling the display panel to display a picture according to reset information in the reset signal. The judgment module is set to generate a reset signal according to a relationship between clock information and preset information in the clock signal, so that the driving system can determine the moment to obtain a display signal according to the clock signal. The reset signal has an effective potential only when the clock signal is stable to control the driving system to obtain the display signal and then perform effective analysis, thereby avoiding the display signal being obtained when the clock signal is not stable, resulting in confusion in the analysis, and improving the black screen phenomenon when the display device is powered on. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 and Figure 2 This is a diagram of the architecture of a display device provided by an embodiment of the present invention.

[0037] Figure 3 , Figure 5 and Figure 6 The waveform diagram of some signals of the display device provided by the embodiment of the present invention.

[0038] Figure 4 A circuit diagram of the counting unit 2021 provided in an embodiment of the present invention.

[0039] Figure 7 The present invention provides a flow chart of a method for driving a display device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0041] In the description of the present invention, the terms "first", "second", etc. are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include one or more of the said features. In addition, it should be noted that the drawings only provide structures that are closely related to the present invention, and some details that are not closely related to the invention are omitted. The purpose is to simplify the drawings and make the invention clear at a glance, rather than to indicate that the actual device is the same as the attached structure. Figure 1 The same is not a limitation of the actual device.

[0042] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase at various times in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0043] The present invention provides a display device, which may include but is not limited to the following embodiments and combinations of the following embodiments.

[0044] In some embodiments, in combination Figure 1 and Figure 2 As shown, the display device 100 includes a display panel 10 and a driving system 20 electrically connected to the display panel 10, wherein the driving system 20 includes: a clock module 201, for generating a clock signal CLK; a judgment module 202, for generating a reset signal Reset according to a relationship between clock information in the clock signal CLK and preset information; a processing module 203, wherein the processing module 203 is used to obtain a display signal for controlling the display panel 10 to display a screen according to the reset information in the reset signal Reset, and the processing module 203 is also used to process the display signal.

[0045] The display device 100 may be, but is not limited to, an organic self-luminous display device, an inorganic self-luminous display device, or a liquid crystal display device. The display device 100 may further include a gate driver 50. The gate driver 50 may be a gate drive circuit located on a substrate of the display panel 10 or a chip ( Figure 1 For ease of description, only the former is used as an example. Figure 1 In the description, only the array arrangement of a plurality of sub-pixels P in the display panel 10 is taken as an example, for example, the sub-pixels P may be arranged in n rows and m columns (n ​​and m are both positive integers).

[0046] Specifically, the display panel 10 may further include a plurality of gate lines (GL1 to GLn) electrically connected to the gate driver 50, and a plurality of data lines (DL1 to DLm) electrically connected to the source driver. The gate driver 50 generates a plurality of gate signals gate corresponding to a plurality of rows of sub-pixels P, each gate line (one of GL1 to GLn) is electrically connected to a corresponding row of sub-pixels P to transmit the corresponding gate signal gate to the corresponding row of sub-pixels P, each gate signal gate includes a gate effective pulse for controlling the corresponding pixel group to be turned on, and the plurality of gate effective pulses are arranged sequentially on the time axis so that the corresponding plurality of pixel groups are turned on sequentially; each data line (one of DL1 to DLm) is electrically connected to a corresponding column of sub-pixels P to transmit the gate signal gate to the corresponding row of sub-pixels P by the source driver (e.g., Figure 1 , 2 A corresponding data signal data is generated by the data driving module 205 in the pixel group, each data signal data includes multiple data voltages corresponding to the multiple sub-pixels P in the column, and the multiple data signals data corresponding to the multiple columns of sub-pixels P are matched so that when each pixel group is turned on, the multiple data voltages corresponding to the multiple sub-pixels P in the pixel group can be respectively transmitted to the corresponding multiple sub-pixels P through multiple data lines (DL1 to DLm).

[0047] Among them, Figure 1 and Figure 2 As shown, the above-mentioned data driving module 205 and timing control module 204 can be integrated in the same driving system 20, that is, the driving system 20 can be a driving chip of "timing controller embedded data driver". Among them, the timing control module 204 can include a clock module 201, a judgment module 202 and a processing module 203, the processing module 203 is used to generate an image signal according to the clock signal CLK and the display signal, and the data driving module 205 is used to control the display panel 10 to display the picture according to the image signal.

[0048] Of course, different from Figure 1 and Figure 2 As shown, the data driving module 205 and the timing control module 204 can also be set independently. In this case, the data driving module 205 can be considered as a source driving chip, and the timing control module 204 can be considered as a timing control chip; the timing control chip can be electrically connected to the display panel 10, and the source driving chip can be electrically connected between the display panel 10 and the timing control chip. The timing control chip includes the above-mentioned clock module 201, the judgment module 202 and the processing module 203. The source driving chip is used to control the display panel 10 to display the picture according to the image signal (generated by the processing module 203).

[0049] Regardless of whether the data driving module 205 and the timing control module 204 are independently configured (the present invention only takes the example of integrating the two in the same driving system 20 as an example), the display device 100 also includes a power manager 30, which is used to supply power to the gate driver 50, the data driving module 205 and the timing control module 204. The timing control module 204 generates a timing signal and transmits it to the gate driver 50 and the data driving module 205, and generates an image signal and transmits it to the data driving module 205, so that the gate driver 50 generates the above-mentioned multiple gate signals gate, and the data driving module 205 generates the above-mentioned multiple data signals data, thereby driving the multiple sub-pixels P to emit light.

[0050] Specifically, if Figure 2 As shown, the clock module 201 (for example, a crystal oscillator) in the driving system 20 (timing control module 204) generates a clock signal CLK, and the processing module 203 in the driving system 20 (timing control module 204) needs to parse the display signal obtained from the storage module according to the clock signal CLK, so as to obtain the system signal (the information required for the operation of the driving system 20), the image signal, the control signal and the above-mentioned timing signal; the above-mentioned timing signal can be used as the working timing of the gate driver 50 and the data driving module 205; and the data driving module 205 can process the image signal according to the control signal and the above-mentioned timing signal to generate the above-mentioned multiple data signals data, and the gate driver 50 can generate the above-mentioned multiple gate signals gate according to the control signal and the above-mentioned timing signal.

[0051] In combination with the above discussion, it can be seen that since the clock signal CLK needs to be used to parse the display signal to generate the timing signal for controlling the working timing of the gate driver 50 and the data driving module 205 as well as the above-mentioned system signal, image signal and control signal, if the driving system 20 (timing control module 204) obtains the display signal when the clock signal CLK is not stable, it will cause confusion in the parsing of the display signal and generate erroneous timing signals, system signals, image signals and control signals, ultimately leading to a black screen phenomenon when power is turned on.

[0052] It can be understood that in this embodiment, based on the processing module 203, the driving system 20 is controlled to obtain the display signal according to the reset signal Reset. By setting a judgment module 202 for generating the reset signal Reset according to the clock signal CLK, the time when the driving system 20 obtains the display signal can at least be determined according to the clock signal CLK. The reset signal Reset can have a valid potential only when the clock signal CLK is stable to control the driving system 20 to obtain the display signal and then perform effective analysis, thereby avoiding the display signal being obtained when the clock signal CLK is not stable, resulting in confusion in the analysis, and improving the black screen phenomenon of the display device 100 when it is powered on.

[0053] In some embodiments, in combination Figure 2 and Figure 3 The clock signal CLK shown includes a plurality of clock pulses p, the clock information includes the number of the clock pulses p, the preset information includes a preset value, and the judgment module 202 includes: a counting unit 2021, which is used to control the reset information to be a first sub-reset signal (that is, the amplitude of the reset signal Reset is the amplitude of the first sub-reset signal) when the number of the clock pulses p is greater than or equal to the preset value, and the processing module 203 is used to obtain the display signal according to the first sub-reset signal. The "control" here can be understood as direct control or indirect control, and the specific meaning is understood in conjunction with the following discussion.

[0054] In combination with the above discussion, it can be seen that in this embodiment, taking into account that the clock signal CLK generated by the clock module 201 is not very stable in the initial period (for example, at least one of the period and peak-to-peak value of the clock signal CLK is unstable), the processing module 203 cannot accurately parse the display signal at this time. Therefore, a counting unit 2021 is set to count the number of clock pulses p in the clock signal CLK, and the reset signal Reset is controlled to be the first sub-reset signal only when the number of clock pulses p is greater than or equal to a preset value, and the processing module 203 is used to obtain the display signal according to the first sub-reset signal in the Reset reset signal, and does not obtain the display signal when the Reset reset signal becomes the second sub-reset signal before the first sub-reset signal.

[0055] The preset value may be set according to the number of pulses required for the clock signal CLK to be stable. It can be considered that when the number of clock pulses p is greater than or equal to the preset value, the period and peak-to-peak value of the clock signal CLK are both stable.

[0056] It can be seen that by setting the counting unit 2021 to count the number of clock pulses p in the clock signal CLK, the processing module 203 can obtain the display signal only when the number of clock pulses p is greater than or equal to the preset value, and then perform effective analysis, thereby avoiding obtaining the display signal when the clock signal CLK is not stable, resulting in confusion in the analysis.

[0057] In some embodiments, in combination Figures 2 to 4 As shown, the counting unit 2021 includes: a plurality of triggers 01, used to generate a corresponding plurality of trigger signals Qi (i is an integer greater than or equal to 0) according to the clock signal CLK; a signal processor 02, used to control the reset signal Reset to be the first sub-reset signal when the plurality of trigger signals Qi are respectively corresponding to a plurality of sub-preset values.

[0058] Among them, the counting function can be realized by using a corresponding number of triggers 01 according to the numerical size of the preset value and the type of trigger 01. Each trigger 01 can generate a corresponding trigger signal Qi according to the clock signal CLK. When the number of clock pulses p is greater than or equal to the preset value, that is, when the numerical values ​​of multiple trigger signals Qi are the corresponding sub-preset values, the signal processor 02 controls the reset signal Reset to be the above-mentioned first sub-reset signal.

[0059] Considering that the trigger signal Qi generated by each trigger 01 can be 0 or 1, n triggers 01 can output 2 n Therefore, to realize the counting function, the number n of triggers 01 and the preset value N can satisfy "2 n ≥N”, that is, the number of results output by n flip-flops 012 n It must not be less than the preset value N, so that the maximum value of the count can be 2 n is not less than the preset value N, and multiple sub-preset values ​​are further set in combination with the preset value N to satisfy that when multiple trigger signals Qi correspond to multiple sub-preset values, they also correspond to the decimal preset value N. In this embodiment, the preset value N is 31 as an example. Considering 2 5 ≥31≥2 4 , so 5 triggers 01 need to be set.

[0060] Specifically, Figure 4 As shown, here the trigger 01 is taken as a JK trigger as an example, the J terminal and the K terminal of the JK trigger are electrically connected to a first voltage line for transmitting a logic high potential (for example, corresponding to a first voltage signal VCC), the clock terminal CP of the first-stage JK trigger is electrically connected to the clock module to obtain the clock signal CLK, and the clock terminal CP of each of the second to last-stage JK triggers is electrically connected to the output terminal of the JK trigger of the previous stage to obtain the trigger signal of the previous stage.

[0061] Combined with the control principle of the JK trigger, it can be seen that when the rising edge or falling edge of the signal at the clock end CP arrives, the output state of the JK trigger will be updated according to the inputs of J and K, including the flip-flop mode, that is, when the J and K terminals are both at a logic high potential "1", the trigger signal Qi output by the output terminal Q flips, that is, if Qi was previously at a logic low potential "0", it will flip to a logic high potential "1", and vice versa.

[0062] like Figure 4As shown, in this embodiment, the clock signal CLK is transmitted to the clock terminal CP of each trigger 01, and the J terminal and the K terminal are electrically connected to the first voltage line for transmitting a logic high potential "1" (for example, corresponding to the first voltage signal VCC), that is, the first voltage signal VCC is a constant voltage signal with an amplitude of a logic high potential "1", and the clock terminal CP of the first-level JK trigger is loaded with the clock signal CLK, and the clock terminal CP of each subsequent level of JK trigger is loaded with the trigger signal of the previous level.

[0063] Combination Figure 3 , Figure 4 and Figure 5 As shown, in this embodiment, taking n=5 and the falling edge of the signal at the clock terminal CP being valid as an example, at the starting moment of the first clock pulse p0 of the clock signal CLK, the reset terminal R of each JK flip-flop is reset (for example, set to "0") by the signal processor 02, so that the five trigger signals (i.e., Q0 to Q4) of the five JK flip-flops are all set to "0" during the first clock pulse p0. Thereafter, the trigger signal Q0 of the first-stage JK flip-flop is flipped once at each falling edge of the clock signal CLK, i.e., the period of the trigger signal Q0 is twice that of the clock signal CLK. The trigger signal Q1 of the second-stage JK flip-flop is flipped once at each falling edge of the trigger signal Q0, i.e., the period of the trigger signal Q1 is twice that of the trigger signal Q0. By analogy, the period of the trigger signal Qj is twice that of the trigger signal Qj-1, and j is a positive integer in [1, 4].

[0064] Among them, "Q4Q3Q2Q1Q0" counts from "00000" (decimal 0) to "11111" (decimal 31), which means that 32 pulses of the clock signal CLK appear (the first clock pulse p0 to the thirty-second clock pulse p31). The signal processor 02 can be set to control the reset signal Reset to be the first sub-reset signal when "Q4Q3Q2Q1Q0" is "11111", which is equivalent to controlling the reset signal Reset to be the first sub-reset signal after 32 pulses of the clock signal CLK appear, and then controlling the processing module 203 to obtain the display signal, and effectively analyze the display signal through the stable clock signal CLK at this time, so as to avoid obtaining the display signal when the clock signal CLK is not stable, resulting in confusion in the analysis.

[0065] Of course, since N=31, the signal processor 02 can also be set to control the reset signal Reset to be the first sub-reset signal when "Q4Q3Q2Q1Q0" is "11110" (decimal 30), because this is equivalent to controlling the reset signal Reset to be the first sub-reset signal after the clock signal CLK has 31 pulses, which also meets the above requirements.

[0066] It should be noted that when "Q4Q3Q2Q1Q0" counts to the required "11111" or "11110" above, the reset terminal R can be controlled to prevent multiple triggers 01 from continuing to count, so that "Q4Q3Q2Q1Q0" is maintained as the required "11111" or "11110" above.

[0067] In some embodiments, in combination Figure 4 and Figure 5 As shown, the signal processor 02 is used to control the reset signal Reset to be the first sub-reset signal when each of the multiple trigger signals Qi is the first sub-trigger signal (for example, "1"). That is, this embodiment makes full use of the upper limit value of the count of the multiple triggers 01, and controls the reset signal Reset to be the first sub-reset signal only when the maximum count value is reached. When the number of triggers 01 is constant (that is, the storage resources are the same), the time when the first sub-reset signal appears can be fully delayed, and the display signal is obtained and effectively analyzed after the clock signal CLK is fully stable, so as to minimize the risk of obtaining the display signal when the clock signal CLK is not stable and causing confusion in the analysis.

[0068] Of course, the number of triggers 01 can be appropriately selected according to the preset value N, and the upper limit of the count of multiple triggers 01 can be fully utilized. k instead of 2 k+1 When (k is a positive integer greater than 0), n can be set to k instead of k+1 to avoid wasting storage resources due to excessive number of triggers 01.

[0069] In some embodiments, in combination Figure 1 , Figure 2 and Figure 6 As shown, the display device 100 further includes a power manager 30 electrically connected to the driving system 20, the power manager 30 is used to generate a second voltage signal, the counting unit 2021 is used to generate a first control signal Con1 according to the clock signal CLK, and the judgment module 202 includes: an AND gate unit 2022 electrically connected to the counting unit 2021 and the power manager 30, and used to control the reset signal Reset to be the first sub-reset signal according to the second voltage signal and the first control signal Con1. It can be understood that the counting unit 2021 indirectly controls the reset signal Reset to be the first sub-reset signal by generating the first control signal Con1 according to the clock signal CLK. Of course, the counting unit 2021 can also directly control the reset signal Reset to be the first sub-reset signal according to the clock signal CLK.

[0070] Specifically, the second voltage signal may include but is not limited to a first sub-voltage signal PAVDD, a second sub-voltage signal VCore, and a third sub-voltage signal VDDIO. The first sub-voltage signal PAVDD may act on the data driver module 205, and the data driver module 205 generates a plurality of gamma reference voltages according to the first sub-voltage signal PAVDD, and generates the above-mentioned data signal data according to the plurality of gamma reference voltages and the above-mentioned image signal; the second sub-voltage signal VCore may act on the timing control module 204 as its core voltage; the third sub-voltage signal VDDIO may act on the timing control module 204 to power the I / O module therein, and may also act on the data driver module 205 to power the logic module therein.

[0071] Understandable, combined Figure 3 and Figure 6 As shown, the counting unit 2021 in this embodiment is used to generate the first control signal Con1 according to the clock signal CLK, and to generate the reset signal Reset according to the first control signal Con1 and the second voltage signal by setting the AND gate unit 2022, that is, the reset signal Reset is not only related to whether the clock signal CLK is stable, but also related to the amplitude of the second voltage signal. It can be understood that when the first sub-voltage signal PAVDD, the second sub-voltage signal VCore, the third sub-voltage signal VDDIO and the clock signal CLK are all stable, the AND gate unit 2022 controls the reset signal Reset to be the first sub-reset signal, and then controls the processing module 203 to obtain the display signal. At this time, not only the risk of confusing the display signal analysis is reduced, but also the second voltage signal is stable, the timing control module 204 and the data driving module 205 also have corresponding working voltages, and the reliability of the driving system 20 is further improved.

[0072] In some embodiments, Figure 1 As shown, the display device 100 also includes a reset circuit 40 electrically connected to the driving system 20, and the reset circuit 40 is used to generate an initial reset signal Reset0; wherein the AND gate unit 2022 is used to generate a second control signal Con2 according to the second voltage signal and the first control signal Con1, and the second control signal Con2 is used to adjust the initial reset signal Reset0 to the reset signal Reset.

[0073] Specific, combined Figure 1 and Figure 2As shown, it can be considered that the above three sub-voltage signals in the second voltage signal reach stability after the first time period T1, and the initial reset signal Reset0 generated by the reset circuit 40 is not controlled by the second control signal Con2 generated by the judgment module 202. It can be considered that the initial reset signal Reset0 reaches stability after the second time period T2 after the first time period T1. At this time, it can be considered that the clock signal CLK has not reached stability. If the judgment module 202 in the present invention is not set, the initial reset signal Reset0 will directly act on the processing module 203, causing it to obtain and analyze the display signal when the clock signal CLK has not reached stability, resulting in the risk of a black screen when the computer is turned on.

[0074] It can be understood that in this embodiment, by setting the counting unit 2021 to generate the first control signal Con1 according to the clock signal CLK, and the gate unit 2022 to generate the second control signal Con2 according to the second voltage signal and the first control signal Con1, it can be considered that the moment when the clock signal CLK reaches stability is the starting moment of the effective potential of the first control signal Con1, and the moment when the first control signal Con1 reaches the effective potential and the second voltage signal both reach stability is the starting moment of the effective potential of the second control signal Con2, that is, the starting moment of the first sub-reset signal in the reset signal Reset, so that the processing module 203 only obtains and analyzes the display signal when the clock signal CLK and the second voltage signal both reach stability, thereby reducing the risk of a black screen when starting up.

[0075] That is, compared with the second time period T2, in the present invention, since the judgment module 202 is set, the first control signal Con1 is a valid potential only when the clock signal CLK reaches stability after the first time period T1 (for example, at the end of the third time period T3), and then the second control signal Con2 is a valid potential, that is, the reset signal Reset is the first sub-reset signal only after the third time period T3 which is greater than the second time period T2.

[0076] Among them, Figure 2 As shown, the reset circuit 40 may include a first resistor R1 and a first capacitor C1 arranged in series, one end of the first resistor R1 is loaded with a constant voltage signal such as the above-mentioned first voltage signal VCC, one end of the first capacitor C1 can be grounded, and the connection point of the first resistor R1 and the first capacitor C1 can be electrically connected to the AND gate unit 2022.

[0077] In some embodiments, in combination Figure 1 and Figure 2As shown, the power manager 30 is further used to generate a third voltage signal STB, and the clock module 201 is used to generate the clock signal CLK according to the third voltage signal STB. That is, it can be considered that the clock module 201 generates the clock signal CLK to generate a plurality of clock pulses p only when the third voltage signal STB reaches a corresponding effective potential (e.g., a high potential), and it can be considered that the effective potential of the third voltage signal STB is a trigger signal for the clock module 201 to generate the clock signal CLK.

[0078] Specifically, when the power manager 30 is powered on, the third voltage signal STB can reach a corresponding effective potential, so that the level conversion circuit in the driving system 20 (which may also be included in the above-mentioned processing module 203) can generate a sub-timing signal acting on the gate driver 50 according to the above-mentioned timing signal, thereby controlling the gate driver 50 to generate a plurality of gate signals gate; and when the power manager 30 is powered off, the third voltage signal STB can be changed to a corresponding invalid potential, so that the gate driver 50 is no longer affected by the sub-timing signal but is an invalid potential, so that the gate driver 50 discharges, thereby reducing the risk of power-off afterimages in the display panel 10.

[0079] Among them, Figure 2 As shown, the power manager 30 can be electrically connected to the clock module 201 through a circuit composed of a second resistor R2 and a second capacitor C2, one end of the second resistor R2 is loaded with a constant voltage signal such as the above-mentioned first voltage signal VCC, one end of the second capacitor C2 can be grounded, and the terminal for outputting the third voltage signal STB in the power manager 30 can be connected to the connection point of the second resistor R2 and the second capacitor C2.

[0080] In order to better illustrate the above display device, the present invention also provides a driving method for the display device, which may include but is not limited to the following embodiments and combinations of the following embodiments.

[0081] In some embodiments, Figure 7 As shown, the driving method of the display device may include but is not limited to the following steps and a combination of the following steps.

[0082] S1, the clock module generates a clock signal;

[0083] S2, the judgment module generates a reset signal according to the relationship between the clock information in the clock signal and the preset information;

[0084] S3, the processing module controls the driving system to obtain a display signal for controlling the display panel to display a picture according to the reset information in the reset signal, and processes the display signal.

[0085] Among them, the clock module, the judgment module, the processing module, the clock signal, the reset signal and the display signal can refer to the relevant description above.

[0086] It can be understood that in the driving method of the display device, the processing module 203 controls the driving system 20 to obtain the display signal according to the reset signal Reset, and the control judgment module 202 is used to generate the reset signal Reset according to the clock signal CLK, so that the time when the driving system 20 obtains the display signal can at least be determined according to the clock signal CLK. The reset signal Reset can have an effective potential only when the clock signal CLK is stable to control the driving system 20 to obtain the display signal and then perform effective analysis, thereby avoiding the display signal being obtained when the clock signal CLK is not stable, resulting in confusion in the analysis, and improving the black screen phenomenon of the display device 100 when it is powered on.

[0087] Specifically, the clock information includes the number of the clock pulses p, the preset information includes a preset value, and step S2 may include but is not limited to the following steps:

[0088] S201, the counting unit generates a first control signal according to the clock signal, the first control signal is a corresponding effective first control potential when the number of the clock pulses is greater than or equal to the preset value, and the effective first control potential is used to control the reset information to be a first sub-reset signal.

[0089] The preset value may refer to the above description.

[0090] Correspondingly, step S3 may include but is not limited to the following steps:

[0091] S301: The processing module obtains the display signal when the reset information is the first sub-reset signal.

[0092] It can be understood that by counting the number of clock pulses p in the clock signal CLK through the counting unit 2021, the processing module 203 can obtain the display signal only when the number of clock pulses p is greater than or equal to the preset value, and then perform effective analysis, thereby avoiding obtaining the display signal when the clock signal CLK is not stable, resulting in confusion in the analysis.

[0093] Wherein, step S3 may include but is not limited to the following steps:

[0094] S302, the processing module generates an image signal according to the clock signal and the display signal;

[0095] Further, when the driving system 20 includes a driving chip, and the driving chip includes a clock module 201, a judgment module 202, a processing module 203 and a data driving module 205, that is, when the driving system 20 (driving chip 0 is a timing controller embedded data driver, the steps after step S302 may include but are not limited to the following steps:

[0096] S3021, the data driving module is used to control the display panel to display a picture according to the image signal.

[0097] Alternatively, when the driving system 20 includes a timing control chip electrically connected to the display panel 10, a source driving chip electrically connected between the display panel 10 and the timing control chip, and the timing control chip includes a clock module 201, a judgment module 202, and a processing module 203, that is, when the driving system 20 is a separate architecture, the steps after step S302 may include but are not limited to the following steps:

[0098] S3022, the source driver chip is used to control the display panel to display an image according to the image signal.

[0099] For specific details of step S3021 and step S3022, reference may be made to the above description of the display device 100.

[0100] The display device and the driving method thereof provided in the embodiments of the present invention are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display device, characterized in that: The invention comprises a display panel and a driving system electrically connected to the display panel, wherein the driving system comprises: A clock module, used for generating a clock signal; A determination module, configured to generate a reset signal according to a relationship between clock information in the clock signal and preset information; A processing module is used to obtain a display signal for controlling the display panel to display a picture according to the reset information in the reset signal, and to process the display signal.

2. The display device according to claim 1, wherein: The clock signal includes a plurality of clock pulses, the clock information includes the number of the clock pulses, the preset information includes a preset value, and the judgment module includes: a counting unit, configured to generate a first control signal according to the clock signal, wherein the first control signal is an effective first control potential when the number of the clock pulses is greater than or equal to the preset value, and the effective first control potential is used to control the reset information to be a first sub-reset signal; Wherein, the processing module is used to obtain the display signal according to the first sub-reset signal.

3. The display device according to claim 2, wherein: The counting unit comprises: A plurality of triggers, used to generate a corresponding plurality of trigger signals according to the clock signal; A signal processor is used to generate the first control signal according to the multiple trigger signals.

4. The display device according to claim 3, characterized in that The first and second ends of the trigger are electrically connected to a first voltage line for transmitting a first voltage signal, the clock end of the first-stage trigger is electrically connected to the clock module, and the clock end of each of the second to last-stage triggers is electrically connected to the output end of the trigger in the previous stage.

5. The display device according to claim 3 or 4, characterized in that: The signal processor is used for controlling the first control signal to be the corresponding effective first control potential when each of the plurality of trigger signals is a first sub-trigger signal.

6. The display device according to any one of claims 2 to 4, characterized in that: It also includes a power manager electrically connected to the driving system, the power manager is used to generate a second voltage signal, and the judgment module also includes: An AND gate unit is electrically connected to the counting unit and the power manager, and is used to control the reset signal to be the first sub-reset signal according to the effective first control potential corresponding to the second voltage signal and the first control signal.

7. The display device according to claim 6, wherein: Also included is a reset circuit electrically connected to the drive system, the reset circuit is used to generate an initial reset signal; The AND gate unit is used to generate a second control signal according to the second voltage signal and the first control signal, and the second control signal is used to adjust the initial reset signal to the reset signal.

8. The display device according to claim 6, wherein: The power manager is further configured to generate a third voltage signal, and the clock module is configured to generate the clock signal according to the third voltage signal.

9. The display device according to any one of claims 1 to 4, 7 to 8, characterized in that: The driving system comprises a driving chip, and the driving chip comprises the clock module, the judgment module, the processing module and the data driving module; The processing module is used to generate an image signal according to the clock signal and the display signal; The data driving module is used to control the display panel to display a picture according to the image signal.

10. The display device according to any one of claims 1 to 4, 7 to 8, characterized in that: The driving system includes a timing control chip electrically connected to the display panel, and a source driving chip electrically connected between the display panel and the timing control chip, wherein the timing control chip includes the clock module, the judgment module and the processing module; The processing module is used to generate an image signal according to the clock signal and the display signal; The source driver chip is used to control the display panel to display an image according to the image signal.

11. A method for driving a display device, characterized in that: The display device includes a display panel and a driving system electrically connected to the display panel, the driving system includes a clock module, a judgment module and a processing module, and the method includes: The clock module generates a clock signal; The judgment module generates a reset signal according to the relationship between the clock information in the clock signal and the preset information; The processing module obtains a display signal for controlling the display panel to display a picture according to the reset information in the reset signal, and processes the display signal.

12. The method for driving a display device according to claim 11, wherein: The clock signal includes a plurality of clock pulses, the clock information includes the number of the clock pulses, the preset information includes a preset value, the judgment module includes a counting unit, and the step of the judgment module generating a reset signal according to the relationship between the clock information in the clock signal and the preset information includes: The counting unit generates a first control signal according to the clock signal, the first control signal is a corresponding effective first control potential when the number of the clock pulses is greater than or equal to the preset value, and the effective first control potential is used to control the reset information to be a first sub-reset signal; The step of the processing module acquiring a display signal for controlling the display panel to display a picture according to the reset information in the reset signal includes: The processing module acquires the display signal when the reset information is the first sub-reset signal.

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