Field sequence Vth self-compensation grid control circuit and method

Abstract

The invention discloses a field sequence Vth self-compensation gate control circuit and method. The field sequence Vth self-compensation gate control circuit comprises a compensation unit and a control unit, wherein the compensation unit comprises a first transistor, a second transistor, a fourth transistor, a fifth transistor and a pre-storage capacitor; a grid electrode of the first transistor is coupled to a reset signal line, a first source and drain electrode of the first transistor is coupled to a data signal line, a second source and drain electrode of the first transistor is coupled to one end of the pre-storage capacitor, the other end of the pre-storage capacitor is coupled to a second source and drain electrode of the fourth transistor, and a grid electrode of the fourth transistor is coupled to a setting signal line. The first source-drain electrode of the fourth transistor is coupled to the second source-drain electrode of the second transistor, the first source-drain electrode of the second transistor is coupled to the reference signal line, and the grid electrode of the second transistor is coupled to the second source-drain electrode of the first transistor. The beneficial effects of the invention are that the threshold voltage is eliminated by using the conduction characteristic of the transistor, thereby avoiding the image abnormity phenomenon caused by the drift of the threshold voltage.

Description

Technical Field

[0001] The present invention relates to the field of pixel display technology, and in particular to a field sequential Vth self-compensation gate control circuit and method. Background Art

[0002] Field sequential or color sequential display driving technology directly utilizes the RGB three-color light source to mix colors through the residual effect of human visual pause to achieve full-color display effect. No color filter is required, which improves the utilization rate of the light source on the one hand and reduces the power consumption of the light source on the other hand. The backlight can be turned on only after all the screen data is written and the liquid crystal is deflected to a stable state, otherwise there will be a chaotic picture, so a lot of time needs to be reserved for the liquid crystal to deflect before the backlight is turned on. This makes it difficult to achieve high brightness and high frequency display within the average time, and at the same time, the requirements for backlight brightness specifications and life are increased, which increases the cost.

[0003] Due to the influence of the transistor process, the threshold voltage of the driving transistors at different spatial positions is likely to be different. For a-Si, the threshold voltage of hydrogenated amorphous silicon transistors changes over time. The change or inconsistency of the threshold voltage of the driving transistor will cause the LCD display to display unevenly. When displaying an image, the brightness of the image is determined by the current. If the current is related to the threshold voltage of the driving tube, the difference in the threshold voltage of each driving tube in each pixel will cause the brightness of the displayed image to be not the desired brightness. In fact, due to the deviation of the transistor manufacturing process, it is inevitable that the threshold voltage of each driving transistor is different and there is a certain deviation. Therefore, it is necessary to obtain a driving current that is independent of the threshold voltage to eliminate the adverse effect of the threshold voltage deviation on the brightness of the screen display.

[0004] Therefore, the present invention proposes a field sequential Vth self-compensation gate control circuit and method to eliminate the influence of the threshold voltage, thereby avoiding the influence of abnormal picture display. Summary of the invention

[0005] The purpose of the present invention is to provide a field sequence Vth self-compensation gate control circuit and method, which can eliminate the influence of threshold voltage.

[0006] The object of the present invention is to realize a field sequential Vth self-compensation gate control circuit through the following technical scheme, including a compensation unit and a driving unit; The compensation unit includes a first transistor, a second transistor, a fourth transistor, a fifth transistor and a pre-storage capacitor; The gate of the first transistor is coupled to a reset signal line, the first source and drain of the first transistor are coupled to a data signal line, the second source and drain of the first transistor are coupled to one end of a pre-storage capacitor, the other end of the pre-storage capacitor is coupled to a first source and drain of a fourth transistor, the gate of the fourth transistor is coupled to a setting signal line, the second source and drain of the fourth transistor are coupled to a second source and drain of the second transistor, the first source and drain of the second transistor are coupled to a reference signal line, and the gate of the second transistor is coupled to the second source and drain of the first transistor; The gate of the fifth transistor is coupled to the row gate signal line, the first source and drain of the fifth transistor are coupled to the data signal line, and the second source and drain of the fifth transistor are coupled to the second source and drain of the fourth transistor and the driving unit.

[0007] Furthermore, the driving unit includes a third transistor and a pixel electrode; the gate of the third transistor is coupled to the transfer signal line, the first source and drain of the third transistor are coupled to the second source and drain of the second transistor, the second source and drain of the third transistor are coupled to the pixel electrode, and the other end of the pixel electrode is coupled to the common signal line.

[0008] Furthermore, the driving unit further includes a storage capacitor, one end of the storage capacitor is coupled to the second source and drain of the third transistor, and the other end of the storage capacitor is coupled to the common signal line.

[0009] The present invention also provides a field sequential Vth self-compensation gate control circuit control method, comprising: During the backlight on phase: The row gate signal line jumps to a high level, the fifth transistor is turned on, the set signal line is a high level, and the fourth transistor is turned on; the data signal line pre-writes the data signal voltage to the pre-storage capacitor through the fourth transistor and the fifth transistor; According to the charge conservation principle, the current potential of the first node is obtained as a first preset potential, and the first preset potential is the sum of the data signal voltage and the threshold voltage; After the pre-writing is completed, the row gate signal line jumps to a low level, the fifth transistor is turned off, the setting signal line is a low level, and the fourth transistor is turned off; The potential of the reference signal line is a first high potential, and the first node is a first preset potential. At this time, there is a voltage difference between the first node and the reference signal line, and the second transistor is turned on; When the second transistor is turned on to the cut-off region, the potential of the second node is a second preset potential, and the second preset potential is a standard data signal voltage that needs to be written into the pixel electrode; During the backlight off phase: The transfer signal line jumps to a high level, and the third transistor is turned on; the reference signal line jumps to a common level, so that the pixel electrode is reset through the third transistor and the second transistor; After the reset is completed, the reference signal line jumps to the second high potential, and the second transistor is turned on, so that the reference signal line writes a high level to the pixel electrode through the second transistor and the third transistor; The reference signal line jumps to a first high potential, so that the second transistor reaches a cut-off region, and the pixel electrode drops from a high level to a pixel voltage; After the pixel voltage is written, the transfer signal line jumps to a low level, and the third transistor is turned off; the reset signal line jumps to a high level, and the first transistor is turned on; the setting signal line jumps to a high level, and the fourth transistor is turned on; the reference signal line jumps to a first high potential; The data signal line passes through the first transistor so that the first node is at the first high potential until the cut-off region of the second transistor, at which time the second node is the difference between the current potential of the first node and the threshold voltage of the second transistor.

[0010] The present invention also provides a field sequential Vth self-compensation gate control circuit control method, comprising: During the backlight on phase: The row gate signal line jumps to a high level, the fifth transistor is turned on, the set signal line is a high level, and the fourth transistor is turned on; the data signal line pre-writes the data signal voltage to the pre-storage capacitor through the fourth transistor and the fifth transistor; According to the charge conservation principle, the potential of the first node A is a first preset potential; After the pre-writing is completed, the row gate signal line jumps to a low level, the fifth transistor is turned off, the setting signal line is a low level, and the fourth transistor is turned off; The reference signal line is at a first high level, the second node is at a high potential, and the first node is at a high potential. At this time, there is a voltage difference between the first node and the reference signal line, and the second transistor is turned on; When the second transistor is in the cut-off region, the potential of the second node is a second preset potential; During the backlight off phase: The row gate signal line jumps to a high level, and the fifth transistor is turned on; the data signal line outputs a first high potential; The transfer signal line jumps to a high level, and the third transistor is turned on; the data signal line writes a first high potential to the pixel electrode; The row gate signal line jumps to a low level, the fifth transistor is turned off, and the reference signal line jumps to a common level; The second transistor is continuously turned on, and the pixel electrode discharges to the reference signal line to a pixel voltage After the pixel voltage is written, the transfer signal line jumps to a low level, and the third transistor is turned off; the reset signal line jumps to a high level, and the first transistor is turned on; the setting signal line jumps to a high level, and the fourth transistor is turned on; the reference signal line jumps to a first high potential; The data signal line passes through the first transistor so that the potential of the first node is the first high potential; similarly, the second transistor is turned on to the cut-off region, and the second node is the difference between the current potential of the first node and the threshold voltage of the second transistor.

[0011] Furthermore, before the backlight-on stage of the first frame, a pre-extraction stage is also included; The pre-extraction stage includes: The reset signal line jumps to a high level, and the first transistor is turned on; the placement signal line jumps to a high level, and the fourth transistor is turned on; the data signal line inputs a high potential signal to the pre-storage capacitor; the potentials of the first node and the second node are both high potentials; The reset signal line jumps to a low level, and the first transistor is turned off; the placement signal line jumps to a low level, and the fourth transistor is turned off; The reference signal line jumps to a common level, the first node is at a high potential, the second node is at a high potential, and the second node discharges to the reference signal line until the second transistor reaches a cut-off region, at which time the potential of the second node is lower than the potential of the first node; The reference signal line jumps to a first high potential, and the reference signal line charges the second node until the second transistor reaches a cut-off region, at which time the potential of the second node is the difference between the current voltage of the first node and the threshold voltage of the second transistor.

[0012] The present invention has the following advantages: The present invention sets a compensation unit, stores a high potential in advance through a storage capacitor, and uses the conduction characteristics of a transistor to make the potential difference between the first node and the second node equal to the threshold voltage of the second transistor; then, when the display is officially performed, the charge conservation principle is used to store the data signal voltage and the threshold voltage in the pre-storage capacitor, and the conduction characteristics of the transistor are used again to make the potential of the second node equal to the data signal voltage, thereby eliminating the influence of the threshold voltage by pre-compensating the threshold voltage, reducing the influence of the data signal writing into the pixel electrode, thereby avoiding the abnormal display of the screen caused by uneven in-plane process and the drift of the threshold voltage of the transistor over time. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a circuit diagram of Embodiment 1 of the present invention; Figure 2 is a timing diagram of the second embodiment of the present invention; Figure 3 This is a timing diagram of the third embodiment of the present invention. DETAILED DESCRIPTION

[0014] The present invention is further described below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following description.

[0015] It should be noted that the directions or positional relationships indicated by "left", "right", etc. are based on the directions or positional relationships shown in the drawings, or are the directions or positional relationships in which the invention product is usually placed when in use, or are directions or positional relationships commonly understood by those skilled in the art. Such terms are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the invention. It should be noted that the embodiments of the invention and the features and technical solutions in the embodiments can be combined with each other without conflict. Example

[0016] See also Figure 1 , the present invention provides an embodiment 1, the embodiment 1 is a field sequential Vth self-compensation gate control circuit, including a compensation unit and a driving unit; The compensation unit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5 and a pre-storage capacitor Cs1; The gate of the first transistor T1 is coupled to the reset signal line Reset, the first source and drain of the first transistor T1 are coupled to the data signal line Data, the second source and drain of the first transistor T1 are coupled to one end of the pre-storage capacitor Cs1, the other end of the pre-storage capacitor Cs1 is coupled to the second source and drain of the fourth transistor T4, the gate of the fourth transistor T4 is coupled to the set signal line Set, the first source and drain of the fourth transistor T4 are coupled to the second source and drain of the second transistor T2, the first source and drain of the second transistor T2 are coupled to the reference signal line Vref, and the gate of the second transistor T2 is coupled to the second source and drain of the first transistor T1; the gate of the fifth transistor T5 is coupled to the row gate signal line Scan, the first source and drain of the fifth transistor T5 are coupled to the data signal line Data, and the second source and drain of the fifth transistor T5 are coupled to the second source and drain of the fourth transistor T4 and the driving unit.

[0017] Further, the driving unit includes a third transistor T3, a storage capacitor Cs2 and a pixel electrode Clc; the gate of the third transistor T3 is coupled to the transfer signal line Tran, the first source and drain of the third transistor T3 are coupled to the second source and drain of the second transistor T2, the second source and drain of the third transistor T3 are coupled to the pixel electrode Clc, and the other end of the pixel electrode Clc is coupled to the common signal line Com; one end of the storage capacitor Cs2 is coupled to the second source and drain of the third transistor T3, and the other end of the storage capacitor Cs2 is coupled to the common signal line Com.

[0018] Before the circuit performs display work and before the backlight start-up phase of the first frame, a pre-extraction phase is also included; The pre-extraction phase includes: The reset signal line Reset jumps to a high level, and the first transistor T1 is turned on; the set signal line Set jumps to a high level, and the fourth transistor T4 is turned on; the data signal line Data sends a high potential signal to the pre-storage capacitor Cs1, and the potentials of the first node A and the second node Q are both high potentials; The reset signal line Reset jumps to a low level, and the first transistor T1 is turned off; the set signal line Set jumps to a low level, and the fourth transistor T4 is turned off; The reference signal line Vref jumps to the common level, the first node A is at a high potential, so that there is a potential difference between the gate and the source and drain of the second transistor T2, and the second transistor T2 is turned on; the second node Q is at a high potential, and the second node Q is discharged to the reference signal line Vref through the second transistor T2 until the second transistor T2 reaches the cut-off region, at which time the potential of the second node Q is lower than the potential of the first node A; The reference signal line Vref jumps to a high potential, and the reference signal line Vref charges the second node Q until the second transistor T2 reaches the cut-off region. At this time, the potential of the second node Q is the difference between the current voltage of the first node A and the threshold voltage Vth of the second transistor T2.

[0019] The pre-extraction stage is used to obtain the threshold voltage Vth of the second transistor T2, so that the difference between the potentials of the first node A and the second node Q is the threshold voltage Vth.

[0020] The state of the second transistor T2 changes until it reaches the cut-off region; the threshold voltage Vth of the second transistor T2 is extracted by the coordination of the changes of the fourth transistor T4 and the reference signal line Vref, thereby achieving pre-compensation of the threshold voltage Vth.

[0021] When working, the timing of the circuit is configured as follows during the backlight on phase: The row gate signal line Scan jumps to a high level, the fifth transistor T5 is turned on, the set signal line Set is a high level, and the fourth transistor T4 is turned on; the data signal line Data pre-writes the data signal voltage to the pre-storage capacitor Cs1 through the fourth transistor T4 and the fifth transistor T5; In the pre-extraction stage, the potential difference between the first node A and the second node Q is Vth. If the original potential of the first node A is the first high potential VH, then the original potential of the second node Q is the difference between the first high potential VH and the threshold voltage Vth, that is, VQ=VH-Vth; According to the charge conservation principle, the voltage across the pre-storage capacitor Cs1 is calculated using the following formula: Cs1*(VA-Vdata)=Cs1*(VH-(VH-Vth)); Where: Cs1: capacitance value of pre-storage capacitor Cs1; Vdata: data signal voltage; VH: first high potential; VA: potential of the first node A; It can be obtained that the potential of the first node A is the first preset potential, and the first preset potential is: VA=Vdata+Vth; After the pre-writing is completed, the row gate signal line Scan jumps to a low level, the fifth transistor T5 is turned off, the set signal line Set is a low level, and the fourth transistor T4 is turned off; The reference signal line Vref is at a first high level VH, the potential VA of the first node A is at a high potential, and there is a voltage difference between the potential VA of the first node A and the voltage VH of the reference signal line Vref, and the second transistor T2 is turned on; Until the second transistor T2 reaches the cut-off region, the potential of the second node Q is now the second preset potential, which is now Vdata; By changing the level of the reference signal line Vref, the conduction state of the second transistor T2 is changed, and the condition that the transistor reaches the cut-off region is utilized to make the second node Q reach the second preset potential, so that the potential connected to the third transistor T3 is the data signal voltage Vdata, thereby avoiding the situation where the potential written into the third transistor T3 due to the second transistor T2 is the difference Vth between the data signal voltage Vdata and the threshold voltage.

[0022] During the backlight off phase: The transfer signal line Tran jumps to a high level, and the third transistor T3 is turned on; the reference signal line Vref jumps to a common level Vcom, so that the pixel electrode Clc is reset through the third transistor T3 and the second transistor T2; By turning on the third transistor T3, turning on the second transistor T2 and the reference signal line Vref jumping to the first low potential, the pixel electrode Clc can release the residual charge of the previous frame through the third transistor T3 and the second transistor T2 to avoid affecting the display of the pixel voltage that currently needs to be written. The second transistor T2 assists the pixel electrode Clc in completing the resetting.

[0023] After the reset is completed, the reference signal line Vref jumps to the second high potential VH2, VH2=Vcom+Vop, where: Vop is the data signal voltage corresponding to the maximum grayscale; at this time, the second transistor T2 is turned on, so that the reference signal line Vref writes a high level to the pixel electrode Clc through the second transistor T2 and the third transistor T3, that is, the potential VQ of the second node Q=VH2; The reference signal line Vref jumps to a first high potential VH, wherein VH>VH2, so that the second transistor T2 is turned on again until it reaches the cut-off region of the second transistor T2; When the second transistor T2 reaches the cut-off region, the potential of the first node A remains unchanged at the first preset potential, that is, VA=Vdata+Vth. Therefore, the potential of the second node Q VQ=Vdata, so that the pixel electrode Clc drops from a high level to the pixel voltage Vdata. In this embodiment, the data signal line Vdata is pre-written into the pre-storage capacitor Cs1 through the fifth transistor T5 in the circuit structure, and the threshold voltage is compensated through the fourth transistor T4 and the second transistor T2, so that when the second transistor T2 and the third transistor T3 write the data signal voltage Vdata to the pixel electrode Clc, the influence of the threshold voltage Vth can be removed.

[0024] After the pixel voltage is written, the transfer signal line Tran jumps to a low level, and the third transistor T3 is turned off; the reset signal line Reset jumps to a high level, and the first transistor T1 is turned on; the setting signal line Set jumps to a high level, and the fourth transistor T4 is turned on; the reference signal line Vref jumps to a first high potential VH; The data signal line Data inputs the first high potential VH to the pre-storage capacitor Cs1 through the first transistor T1, so that the first node A is VH at this time; the second transistor T2 is turned on until it reaches the cut-off region, and the second node Q is VH-Vth at this time.

[0025] After the nth frame pixel voltage is written, a high potential signal is first written by turning on and off the first transistor T1 and the fourth transistor T4, and then the state of the second transistor T2 is changed in conjunction with the state change of the reference signal line Vref, thereby extracting the current threshold voltage Vth of the second transistor T2, which is used to compensate for the threshold voltage Vth and write it into the second node Q. By constantly extracting and correcting the threshold voltage Vth, the abnormal screen display caused by the fluctuation of the threshold voltage Vth of the transistor during the display working time can be avoided.

[0026] The present invention sets a compensation unit and, through the law of charge conservation, stabilizes the potential of the first node A at Vdata+Vth. Through the on-off and cut-off voltage characteristics of the second transistor T2, when the second transistor T2 reaches the cut-off region, the potential of the second node Q can be Vdata, so that the voltage written into the pixel electrode Clc is an accurate data signal voltage with the threshold voltage Vth eliminated. By utilizing the charge conservation and transistor conduction characteristics, the influence of the threshold voltage Vth on the writing of the data signal into the pixel electrode can be eliminated, thereby avoiding the abnormal screen display caused by uneven in-plane process and the drift of the threshold voltage Vth of the transistor over time. Example

[0027] like Figure 2 As shown, the second embodiment is a field sequential Vth self-compensation gate control circuit control method.

[0028] Before the circuit works and displays, and before the backlight is turned on in the first frame, a pre-extraction stage is also included; The pre-extraction phase includes: The reset signal line Reset jumps to a high level, and the first transistor T1 is turned on; the set signal line Set jumps to a high level, and the fourth transistor T4 is turned on; the data signal line Data sends a high potential signal to the pre-storage capacitor Cs1, and the potentials of the first node A and the second node Q are both high potentials; The reset signal line Reset jumps to a low level, and the first transistor T1 is turned off; the set signal line Set jumps to a low level, and the fourth transistor T4 is turned off; The reference signal line Vref jumps to the common level, the first node A is at a high potential, the second node Q is at a high potential, and the second node Q discharges to the reference signal line Vref until the second transistor T2 reaches the cut-off region, at which time the potential of the second node Q is lower than the potential of the first node A; The reference signal line Vref jumps to a high potential, and the reference signal line Vref charges the second node Q until the second transistor T2 reaches the cut-off region. At this time, the potential of the second node Q is the difference between the current voltage of the first node A and the threshold voltage Vth of the second transistor T2.

[0029] The pre-extraction stage is used to obtain the threshold voltage Vth of the second transistor T2 so that the difference between the potentials of the first node A and the second node Q is the threshold voltage Vth of the transistor.

[0030] During the backlight on phase: The row gate signal line Scan jumps to a high level, the fifth transistor T5 is turned on, the set signal line Set is a high level, and the fourth transistor T4 is turned on; the data signal line Data pre-writes the data signal voltage to the pre-storage capacitor Cs1 through the fourth transistor T4 and the fifth transistor T5; In the pre-extraction, the potential difference between the first node A and the second node Q is Vth. Assuming that the original potential of the first node A is the first high potential VH, the original potential of the second node Q is the difference between the first high potential VH and the threshold voltage Vth, that is, VQ=VH-Vth; According to the charge conservation principle, the voltage across the pre-storage capacitor Cs1 is calculated using the following formula: Cs1*(VA-Vdata)=Cs1*(VH-(VH-Vth)); Where: Cs1: capacitance value of pre-storage capacitor Cs1; Vdata: data signal voltage; VH: first high potential; It can be obtained that the potential of the first node A is the first preset potential, and the first preset potential is: VA=Vdata+Vth; After the pre-writing is completed, the row gate signal line Scan jumps to a low level, the fifth transistor T5 is turned off, the set signal line Set is a low level, and the fourth transistor T4 is turned off; The reference signal line Vref is at a first high level VH, the potential VA of the first node A is at a high potential, and there is a voltage difference between the potential VA of the first node A and the voltage VH of the reference signal line Vref, and the second transistor T2 is turned on; Until the second transistor T2 reaches the cut-off region, the potential of the second node Q is now the second preset potential, namely Vdata; During the backlight off phase: The transfer signal line Tran jumps to a high level, and the third transistor T3 is turned on; the reference signal line Vref jumps to a common level Vcom, so that the pixel electrode Clc is reset through the third transistor T3 and the second transistor T2; After the reset is completed, the reference signal line Vref jumps to the second high potential VH2, VH2=Vcom+Vop, where: Vop is the data signal voltage corresponding to the maximum grayscale; at this time, the second transistor T2 is turned on, so that the reference signal line Vref writes a high level to the pixel electrode Clc through the second transistor T2 and the third transistor T3, that is, the potential VQ of the second node Q=VH2; The reference signal line Vref jumps to a first high potential VH, wherein VH>VH2, so that the second transistor T2 is turned on again until it reaches the cut-off region of the second transistor T2; When the second transistor T2 reaches the cut-off region, the potential of the first node A remains unchanged at the first preset potential, that is, VA=Vdata+Vth. Therefore, the potential of the second node Q VQ=Vdata, so that the pixel electrode Clc drops from a high level to the pixel voltage Vdata. After the pixel voltage is written, the transfer signal line Tran jumps to a low level, and the third transistor T3 is turned off; the reset signal line Reset jumps to a high level, and the first transistor T1 is turned on; the setting signal line Set jumps to a high level, and the fourth transistor T4 is turned on; the reference signal line Vref jumps to a first high potential VH; The data signal line Data inputs the first high potential VH to the pre-storage capacitor Cs1 through the first transistor T1, so that the first node A is VH at this time; the second transistor T2 is turned on until it reaches the cut-off area, and the second node Q is VH-Vth at this time; this is used when the next frame is turned on, so that the threshold voltage Vth can be pre-existed at the first node A and the second node Q.

[0031] This embodiment is used to control the specific circuit shown in the first embodiment, and the beneficial effects of this embodiment are the same as those of the first embodiment. Example

[0032] like Figure 3 As shown, the third embodiment is a field sequential Vth self-compensation gate control circuit control method.

[0033] Before the circuit works and displays, and before the backlight is turned on in the first frame, a pre-extraction stage is also included; The pre-extraction phase includes: The reset signal line Reset jumps to a high level, and the first transistor T1 is turned on; the set signal line Set jumps to a high level, and the fourth transistor T4 is turned on; the data signal line Data sends a high potential signal to the pre-storage capacitor Cs1, and the potentials of the first node A and the second node Q are both high potentials; The reset signal line Reset jumps to a low level, and the first transistor T1 is turned off; the set signal line Set jumps to a low level, and the fourth transistor T4 is turned off; The reference signal line Vref jumps to the common level, the first node A is at a high potential, the second node Q is at a high potential, and the second node Q discharges to the reference signal line Vref until the second transistor T2 reaches the cut-off region, at which time the potential of the second node Q is lower than the potential of the first node A; The reference signal line Vref jumps to a high potential, and the reference signal line Vref charges the second node Q until the second transistor T2 reaches the cut-off region. At this time, the potential of the second node Q is the difference between the current voltage of the first node A and the threshold voltage Vth of the second transistor T2.

[0034] The pre-extraction stage is used to obtain the threshold voltage Vth of the second transistor T2, so that the difference between the potentials of the first node A and the second node Q is Vth.

[0035] When working in the Nth frame, the timing of the circuit is configured as follows during the backlight on stage: The row gate signal line Scan jumps to a high level, the fifth transistor T5 is turned on, the set signal line Set is a high level, and the fourth transistor T4 is turned on; the data signal line Data pre-writes the data signal voltage Vdata to the pre-storage capacitor Cs1 through the fourth transistor T4 and the fifth transistor T5; According to the charge conservation principle, the current potential of the first node A is obtained as the first preset potential, that is, VA=Vdata+Vth; After the pre-writing is completed, the row gate signal line Scan jumps to a low level, the fifth transistor T5 is turned off, the set signal line Set is a low level, and the fourth transistor T4 is turned off; The level of the reference signal line Vref jumps to the first high level VH, and the second transistor T2 is turned on; When the second transistor T2 is in the cut-off region, the potential of the second node Q is a second preset potential, that is, VQ=Vdata; During the backlight off phase: The row gate signal line Scan jumps to a high level, and the fifth transistor T5 is turned on; the data signal line Data outputs a first high potential VH; The transfer signal line Tran jumps to a high level, and the third transistor T3 is turned on; the data signal line Data writes a first high potential VH to the pixel electrode Clc; The row gate signal line Scan jumps to a low level, the fifth transistor T5 is turned off, and the reference signal line Vref jumps to a common level Vcom; The second transistor T2 is continuously turned on, and the pixel electrode Clc discharges to the reference signal line Vref to a pixel voltage Vdata; After the pixel voltage is written, the transfer signal line Tran jumps to a low level, and the third transistor T3 is turned off; the reset signal line Reset jumps to a high level, and the first transistor T1 is turned on; the setting signal line Set jumps to a high level, and the fourth transistor T4 is turned on; the reference signal line Vref jumps to a first high potential VH; The data signal line Data makes the potential of the first node A the first high potential VH through the first transistor T1; similarly, the second transistor T2 is turned on to the cut-off area. At this time, the second node Q is the difference between the current potential of the first node A and the threshold voltage Vth of the second transistor T2, that is, VH-Vth.

[0036] This embodiment provides a control method different from that of the second embodiment. This embodiment provides a method for gradually discharging from a high potential to an accurate data signal voltage.

[0037] The above embodiments only express preferred implementation modes, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention. It should be pointed out that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the invention, and these all belong to the protection scope of the invention.

Claims

1. A field sequential Vth self-compensation gate control circuit, characterized in that: It includes a compensation unit and a driving unit; The compensation unit includes a first transistor (T1), a second transistor (T2), a fourth transistor (T4), a fifth transistor (T5) and a pre-storage capacitor (Cs1); The gate of the first transistor (T1) is coupled to a reset signal line (Reset), the first source and drain of the first transistor (T1) are coupled to a data signal line (Data), the second source and drain of the first transistor (T1) are coupled to one end of a pre-storage capacitor (Cs1), the other end of the pre-storage capacitor (Cs1) is coupled to a first source and drain of a fourth transistor (T4), the gate of the fourth transistor (T4) is coupled to a set signal line (Set), the second source and drain of the fourth transistor (T4) are coupled to a second source and drain of the second transistor (T2), the first source and drain of the second transistor (T2) are coupled to a reference signal line (Vref), and the gate of the second transistor (T2) is coupled to the second source and drain of the first transistor (T1); The gate of the fifth transistor (T5) is coupled to the row gate signal line (Scan), the first source and drain of the fifth transistor (T5) are coupled to the data signal line (Data), and the second source and drain of the fifth transistor (T5) are coupled to the second source and drain of the fourth transistor (T4) and the driving unit.

2. The field sequential Vth self-compensation gate control circuit according to claim 1, characterized in that: The driving unit includes a third transistor (T3) and a pixel electrode (Clc); The gate of the third transistor (T3) is coupled to the transfer signal line (Tran), the first source and drain of the third transistor (T3) are coupled to the second source and drain of the second transistor (T2), the second source and drain of the third transistor (T3) are coupled to the pixel electrode (Clc), and the other end of the pixel electrode (Clc) is coupled to the common signal line (Com).

3. The field sequential Vth self-compensation gate control circuit according to claim 2, characterized in that: The driving unit further comprises a storage capacitor (Cs2), one end of the storage capacitor (Cs2) is coupled to the second source and drain of the third transistor (T3), and the other end of the storage capacitor (Cs2) is coupled to the common signal line (Com).

4. A field sequential Vth self-compensation gate control circuit control method, applied to any pixel circuit described in claims 1 to 3, characterized in that: include: During the backlight on phase: The row gate signal line (Scan) jumps to a high level, the fifth transistor (T5) is turned on, the set signal line (Set) is a high level, and the fourth transistor (T4) is turned on; the data signal line (Data) pre-writes the data signal voltage Vdata into the pre-storage capacitor (Cs1) through the fourth transistor (T4) and the fifth transistor (T5); According to the charge conservation principle, the current potential of the first node (A) is obtained as a first preset potential; After the pre-writing is completed, the row gate signal line (Scan) jumps to a low level, the fifth transistor (T5) is turned off, the set signal line (Set) is a low level, and the fourth transistor (T4) is turned off; The level of the reference signal line (Vref) jumps to a first high potential, and the second transistor (T2) is turned on; until the second transistor (T2) reaches the cut-off region, at which time the potential of the second node (Q) is a second preset potential; During the backlight off phase: The transfer signal line (Tran) jumps to a high level, and the third transistor (T3) is turned on; the reference signal line (Vref) jumps to a common level, so that the pixel electrode (Clc) is reset through the third transistor (T3) and the second transistor (T2); After the reset is completed, the level of the reference signal line (Vref) jumps to the second high potential, and the second transistor (T2) is turned on again, so that the reference signal line (Vref) writes a high level to the pixel electrode (Clc) through the second transistor (T2) and the third transistor (T3); The reference signal line (Vref) jumps to a first high potential, so that the second transistor (T2) reaches a cut-off region, and the pixel electrode (Clc) drops from a high level to a pixel voltage; After the pixel voltage is written, the transfer signal line (Tran) jumps to a low level, and the third transistor (T3) is turned off; the reset signal line (Reset) jumps to a high level, and the first transistor (T1) is turned on; The setting signal line (Set) jumps to a high level, and the fourth transistor (T4) is turned on; the reference signal line (Vref) jumps to a first high potential; The data signal line (Data) makes the potential of the first node A a first high potential through the first transistor (T1); similarly, the second transistor (T2) is turned on to the cut-off region, and at this time, the second node Q is the difference between the current potential of the first node A and the threshold voltage of the second transistor.

5. A field sequential Vth self-compensation gate control circuit control method, applied to any pixel circuit according to claim 1 to claim 3, characterized in that: include: During the backlight on phase: The row gate signal line (Scan) jumps to a high level, the fifth transistor (T5) is turned on, the set signal line (Set) is a high level, and the fourth transistor (T4) is turned on; the data signal line (Data) pre-writes the data signal voltage to the pre-storage capacitor (Cs1) through the fourth transistor (T4) and the fifth transistor (T5); According to the charge conservation principle, the current potential of the first node (A) is obtained as a first preset potential; After the pre-writing is completed, the row gate signal line (Scan) jumps to a low level, the fifth transistor (T5) is turned off, the set signal line (Set) is a low level, and the fourth transistor (T4) is turned off; The level of the reference signal line (Vref) jumps to a first high level, and the second transistor (T2) is turned on; When the second transistor (T2) is in the cut-off region, the potential of the second node (Q) is a second preset potential; During the backlight off phase: The row gate signal line (Scan) jumps to a high level, and the fifth transistor (T5) is turned on; the data signal line (Data) outputs a first high potential; The transfer signal line (Tran) jumps to a high level, and the third transistor (T3) is turned on; the data signal line (Data) writes a first high potential to the pixel electrode (Clc); The row gate signal line (Scan) jumps to a low level, the fifth transistor (T5) is turned off, and the reference signal line (Vref) jumps to a common level; The second transistor (T2) is continuously turned on, and the pixel electrode (Clc) discharges to the reference signal line (Vref) to a pixel voltage After the pixel voltage is written, the transfer signal line (Tran) jumps to a low level, and the third transistor (T3) is turned off; the reset signal line (Reset) jumps to a high level, and the first transistor (T1) is turned on; The setting signal line (Set) jumps to a high level, and the fourth transistor (T4) is turned on; the reference signal line (Vref) jumps to a first high potential; The data signal line (Data) makes the potential of the first node (A) a first high potential through the first transistor (T1); similarly, the second transistor (T2) is turned on to the cut-off region, and at this time, the second node (Q) is the difference between the current potential of the first node (A) and the threshold voltage of the second transistor.

6. A field sequential Vth self-compensation gate control circuit control method according to claim 4 or 5, characterized in that: include: Before the backlight-on stage of the first frame, a pre-extraction stage is also included; The pre-extraction stage includes: The reset signal line (Reset) jumps to a high level, and the first transistor (T1) is turned on; the set signal line (Set) jumps to a high level, and the fourth transistor (T4) is turned on; the data signal line (Data) inputs a high potential signal to the pre-storage capacitor (Cs1); the potentials of the first node (A) and the second node (Q) are both high potentials; The reset signal line (Reset) jumps to a low level, and the first transistor (T1) is turned off; the set signal line (Set) jumps to a low level, and the fourth transistor (T4) is turned off; The reference signal line (Vref) jumps to a common level, the first node (A) is at a high potential, the second node (Q) is at a high potential, and the second node (Q) discharges to the reference signal line (Vref) until the second transistor (T2) reaches a cut-off region, at which time the potential of the second node (Q) is lower than the potential of the first node (A); The reference signal line (Vref) jumps to a first high potential, and the reference signal line (Vref) charges the second node (Q) until the second transistor (T2) reaches a cut-off region, at which time the potential of the second node (Q) is the difference between the current voltage of the first node (A) and the threshold voltage of the second transistor (T2).

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