Memory repair circuit, system and method and electronic equipment

Abstract

The invention belongs to the field of integrated circuits, and particularly relates to a memory repair circuit, system and method and electronic equipment. The memory repair circuit comprises a plurality of transceivers and a distribution controller, wherein the distribution controller is respectively connected with each transceiver; each transceiver is used for connecting a memory; the distribution controller is configured to read a repair data packet for logically repairing a memory from a nonvolatile memory, and distribute the repair data packet to each transceiver; wherein the repair data packet comprises a target identity identifier and repair data; and each transceiver is configured to acquire the target identity identifier in the repair data packet, perform identifier matching on the target identity identifier and the identity identifier of the transceiver, and issue the repair data in the repair data packet to the memory connected with the transceiver if the target identity identifier is matched with the identity identifier of the transceiver. The memory repairing efficiency can be improved.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuits, and specifically relates to a memory repair circuit, system, method and electronic device. Background Art

[0002] As chip design becomes more complex and integrated, the number and capacity of internal memory in the chip are on the rise. As the process improves, more circuits can be placed per unit area, which increases the probability of circuit failure, because any problem with a small circuit may lead to overall yield loss. In order to ensure the yield requirements, many internal memories of chips have a repair function. Even if a row or column of the memory is physically damaged, there is a chance to repair it through the memory's repair data, thereby ensuring the normal use of the memory, which can reduce the yield loss to a certain extent.

[0003] As the scale of chip design increases and the number of on-chip memory applications increases, the chip's demand for repair data also increases. Therefore, improving the efficiency of memory defect repair is more important for product reliability. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide a memory repair circuit, system, method and electronic device to improve the efficiency of memory defect repair.

[0005] The embodiment of the present application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a memory repair circuit, comprising: a distribution controller and multiple transceivers, the distribution controller being connected to each of the transceivers respectively, and each of the transceivers being used to connect to the memory; the distribution controller being configured to read a repair data packet for logically repairing the memory from a non-volatile memory, and distribute the repair data packet to each of the transceivers; wherein the repair data packet contains a target identity and repair data; each of the transceivers being configured to obtain a target identity in the repair data packet, and to match the target identity with the identity of the transceiver, and if the identities match, to send the repair data in the repair data packet to the memory connected to the transceiver.

[0007] In the above embodiment, multiple transceivers are set to connect the memory, so that each transceiver can be connected to a small number of memories. Since the number of memories connected to each transceiver is small, the length of a single repair data packet can be reduced, thereby improving the efficiency of repairing memory defects. At the same time, the distribution controller can be connected to each transceiver through the same pin, so that when sending a data packet, the data packet can be sent to all transceivers at the same time, thereby improving data transmission efficiency. Moreover, after receiving the repair data packet, each transceiver determines whether to receive the repair data in the repair data packet by matching the target identity with the identity of the transceiver. Only when the identity matches, the transceiver sends the repair data in the repair data packet to the memory connected to the transceiver. This can further improve the efficiency of memory defect repair and save circuit power consumption.

[0008] In combination with a possible implementation manner of the embodiment of the first aspect, the target identity identifier and the identity identifier of the transceiver both include a multicast identifier and a unicast identifier; each of the transceivers is configured to perform at least one of the following identifier matches: i. matching the multicast identifier in the target identity identifier with the multicast identifier of the transceiver; ii. matching the unicast identifier in the target identity identifier with the unicast identifier of the transceiver; wherein, if any one of the identifiers matches, the repair data in the repair data packet is sent to a memory connected to the transceiver.

[0009] In the above embodiment, by setting the target identity and the identity of the transceiver to include both the multicast identity and the unicast identity, when performing identity matching, the multicast identity in the target identity is matched with the multicast identity of the transceiver, and / or the unicast identity in the target identity is matched with the unicast identity of the transceiver, so that it can be quickly determined whether the identity matches, and the efficiency of identity matching can be improved; at the same time, by setting the multicast identity and the unicast identity to adapt to various scenarios, the flexibility of the solution is enhanced.

[0010] In combination with a possible implementation manner of the embodiment of the first aspect, if the identifiers do not match, each of the transceivers is further configured to clear the repair data in the memory connected to the transceiver when the target identity identifier is a data clearing identifier.

[0011] In the above embodiment, the target identity can also be used as a data clearing identifier to clear the repair data in the memory connected to the transceiver. This operation can occur in the early stage of memory repair. After the repair data in the memory is cleared, the required repair data is subsequently transmitted to repair the memory, which can reduce the adverse effects of the repair data already in the memory on the repair and improve the success rate of the repair. And because each transceiver can identify the clearing identifier, it can achieve the effect of quickly clearing the repair data of the memories connected to multiple transceivers at the same time, thereby improving the repair efficiency.

[0012] In combination with a possible implementation manner of the embodiment of the first aspect, the distribution controller includes: an interface module and a bit width conversion circuit, the bit width conversion circuit is respectively connected to the interface module and each of the transceivers; the interface module is used to connect to the non-volatile memory, and the interface module is configured to read the repair data packet from the non-volatile memory; the bit width conversion circuit is configured to receive the repair data packet sent by the interface module based on the first data line, and distribute the repair data packet to each of the transceivers based on the second data line; wherein the bus bit width of the first data line is the first bit width, and the bus bit width of the second data line is the second bit width.

[0013] In the above embodiment, the distribution controller with the above structure is adopted, so that the distribution controller can be applicable to complex scenarios in which the data bit width changes from wide to narrow, or from narrow to wide during data transmission, so that data of the second bit width can be sent to each transceiver within one clock, thereby improving the flexibility of the system structure.

[0014] In combination with a possible implementation manner of the embodiment of the first aspect, if the size of the received repair data packet is not an integer multiple of the second bit width; the bit width conversion circuit is further configured to perform a zero-padded operation on the received repair data packet, and distribute the zero-padded repair data packet to each of the transceivers based on the second data line; wherein the size of the zero-padded repair data packet is an integer multiple of the second bit width.

[0015] In the above embodiment, if the size (i.e., bit width) of the received repair data packet is not an integer multiple of the second bit width, the received repair data packet is padded with zeros so that the size of the repair data packet after the zero padding is an integer multiple of the second bit width. This can speed up the transceiver's judgment on whether the received data packet is complete data, and reduce the probability of using part of the data of the latter data packet as part of the data of the former data packet, or using part of the data of the former data packet as part of the data of the latter data packet. In addition, since the data packet bit width is aligned with the second bit width after the zero padding, the data packet start bit appears at a fixed line position of the second data line, and there is no need to consider whether the data packet start bit appears at other line positions, thereby reducing the design complexity of the transceiver.

[0016] In combination with a possible implementation manner of the embodiment of the first aspect, each of the transceiver includes: an identification extraction module, a comparison module and a repair information extraction module; the identification extraction module is configured to obtain the target identity in the repair data packet; a comparison module is connected to the identification extraction module, and the comparison module is configured to match the target identity with the identity of the transceiver to obtain a matching result; a repair information extraction module is connected to the comparison module, and the repair information extraction module is configured to obtain the repair data in the repair data packet if the matching result indicates an identification match, and send the repair data to a memory connected to the transceiver.

[0017] In the above embodiment, an identification extraction module is used to extract the target identity in the repair data packet, a comparison module is used to match the target identity with the identity of the transceiver, and then a repair information extraction module is used to obtain the repair data in the repair data packet, and the repair data is sent to a memory connected to the transceiver. In this way, the design difficulty of the transceiver can be reduced while realizing the required functions of the transceiver.

[0018] In combination with a possible implementation manner of the first aspect, the memory repair circuit also includes a logic circuit, which is located on the line between the distribution controller and the transceiver; the logic circuit is configured to optimize the data signal sent by the distribution controller to the transceiver.

[0019] In the above embodiment, by adding a logic circuit on the line between the distribution controller and the transceiver, the data signal sent from the distribution controller to the transceiver is optimized, which is beneficial to improving the timing, stability and strength of the signal.

[0020] In a second aspect, an embodiment of the present application further provides a memory repair circuit, comprising: a distribution controller and a plurality of transceivers, wherein the distribution controller is respectively connected to each of the transceivers, and each of the transceivers is used to connect to a memory; the distribution controller is configured to read a repair data packet for logically repairing the memory from a non-volatile memory, and distribute the repair data packet to a target transceiver whose identity matches the target identity in the repair data packet; wherein the repair data packet contains a target identity and repair data; and each of the target transceivers is configured to send the repair data in the repair data packet to the memory connected to the target transceiver.

[0021] In the above embodiment, multiple transceivers are set to connect the memories, so that each transceiver can be connected to a small amount of memories. Since the number of memories connected to each transceiver is small, the length of a single repair data packet can be reduced, thereby improving the efficiency of repairing memory defects; at the same time, the distribution controller can be connected to each transceiver through different pins, so that when sending data packets, one-to-one sending can be achieved, which is more flexible; at the same time, by adding a target identity identifier in the data packet, when sending a data packet, the data packet can be sent only to the target transceiver whose identity identifier matches the target identity identifier in the repair data packet, and there is no need to send data packets to other transceivers whose identity identifiers do not match the target identity identifier in the repair data packet, thereby saving circuit power consumption.

[0022] In a third aspect, an embodiment of the present application further provides a memory repair system, comprising: a memory to be repaired and a memory repair circuit provided in the embodiment of the first aspect above and / or any possible implementation method in combination with the embodiment of the first aspect, or a memory repair circuit provided in the embodiment of the second aspect above, wherein the memory repair circuit is connected to the memory to be repaired.

[0023] In a fourth aspect, an embodiment of the present application also provides a memory repair method, comprising: obtaining a repair data packet for logically repairing a memory, wherein the repair data packet includes a target identity and repair data; obtaining the target identity in the repair data packet, and matching the target identity with a preset identity; if the identities match, sending the repair data in the repair data packet to the memory to be repaired.

[0024] In combination with a possible implementation manner of the fourth aspect embodiment, the target identity identifier and the preset identity identifier both include a multicast identifier and a unicast identifier; the target identity identifier is matched with the preset identity identifier, including: matching the multicast identifier in the target identity identifier with the multicast identifier in the preset identity identifier; and / or matching the unicast identifier in the target identity identifier with the unicast identifier in the preset identity identifier; wherein, if any one of the identifiers matches, the repair data in the repair data packet is sent to the memory to be repaired.

[0025] In combination with a possible implementation manner of the fourth aspect, if the identifier does not match, the method also includes: identifying whether the target identity identifier is a data clearing identifier; when the target identity identifier is the data clearing identifier, clearing the repair data in the memory to be repaired.

[0026] In the fifth aspect, an embodiment of the present application also provides an electronic device, comprising: a memory and a processor, the processor being connected to the memory; the memory being used to store programs; the processor being used to call the programs stored in the memory to execute a method provided in the above-mentioned fourth aspect embodiment and / or any possible implementation method in combination with the fourth aspect embodiment.

[0027] Other features and advantages of the present application will be described in the following description. The purpose and other advantages of the present application can be realized and obtained through the structures specifically pointed out in the written description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. The above and other purposes, features and advantages of the present application will be more clearly shown in the drawings.

[0029] Figure 1 A schematic diagram showing the connection between a memory repair circuit and a memory provided in an embodiment of the present application is shown.

[0030] Figure 2a A schematic diagram of the transceiver transmission and reception principle of an embodiment of the present application is shown.

[0031] Figure 2b Another schematic diagram of the transceiver transmission and reception principle provided by an embodiment of the present application is shown.

[0032] Figure 3 A schematic diagram of the connection between a distribution controller and an OTP device provided in an embodiment of the present application is shown.

[0033] Figure 4 A schematic diagram of the principle of a distribution controller provided in an embodiment of the present application is shown.

[0034] Figure 5 A schematic diagram of the connection between a transceiver and a memory provided in an embodiment of the present application is shown.

[0035] Figure 6 A schematic diagram showing the connection between another memory repair circuit and a memory provided in an embodiment of the present application is shown.

[0036] Figure 7 A principle schematic diagram of a logic circuit provided in an embodiment of the present application is shown.

[0037] Figure 8 A flow chart of a memory repair method provided in an embodiment of the present application is shown.

[0038] Fig. 9 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The following embodiments can be used as examples to more clearly illustrate the technical solutions of the present application, and cannot be used to limit the scope of protection of the present application. It will be appreciated by those skilled in the art that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other.

[0040] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0041] Furthermore, the term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In the embodiments of this application, the term "multiple" is assumed to be 2 or more when its meaning is not clear.

[0042] In the description of the embodiments of the present application, unless otherwise clearly specified or limited, the technical term "connection" may refer to a direct connection or an indirect connection through an intermediate medium.

[0043] In order to improve the efficiency of memory defect repair, the present application embodiment provides a memory repair circuit. Figure 1 The principle is explained. The memory repair circuit provided in the embodiment of the present application includes a non-volatile memory, a distribution controller and a plurality of transceivers. The distribution controller is respectively connected to the non-volatile memory and each transceiver, and each transceiver is used to connect the memory to be repaired. In a possible implementation, the memory repair circuit may not include a non-volatile memory.

[0044] The non-volatile memory is configured to store a repair data packet for logically repairing the memory. The repair data packet includes a target identity and repair data, wherein the repair data is repair information actually required to be transmitted to the memory to be repaired, and is used to logically repair the memory to be repaired.

[0045] The target identity may be a pre-configured identity, and in some implementations, may be used to clear the repair data in the memory connected to the transceiver, in which case the target identity is a data clearing identity. In one possible implementation, the target identity may be used to verify and identify the identity of the transceiver, and only the transceiver with the same identity is eligible to receive the repair data.

[0046] Among them, the repair data in the repair data packet can be obtained according to the test results of the memory. For example, the repair information can be obtained in advance using the memory built-in self-test circuit (Built In Self Test, BIST) test, and then the target identity is set according to the identity of the transceiver connected to the memory to be repaired, thereby forming the required repair data packet, and then the repair data packet is stored in the non-volatile memory.

[0047] In some implementations, the repair data packet may further include a packet header, which may include some necessary information for describing the data packet so that the receiver can identify the type, length, etc. of the data packet.

[0048] Among them, the non-volatile memory in the present application is a memory whose data will not be lost after power failure, which can be an OTP (One Time Program, a one-time programmable device), OTP can include an eFuse memory, or the non-volatile memory can also be other non-volatile memories, such as a programmable read-only memory (Programmable Read-Only Memory, PROM), an erasable read-only memory (Erasable Programmable Read-Only Memory, EPROM), an electrically erasable read-only memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.

[0049] The memory connected to each transceiver can be regarded as a memory to be repaired. The memory connected to each transceiver can be a single memory or a memory in which multiple memories are connected in series in the form of a chain. That is, the memory connected to each transceiver can be a memory chain formed by connecting multiple memories in series. Figure 1Only the case where the memory connected to each transceiver is a memory chain formed by connecting a plurality of memories in series is shown.

[0050] Each memory to be repaired is provided with a Repair Register (RR), and the transceiver distributes multi-bit repair data to the RR of each memory to be repaired through a Repair Chain to implement the repair action of the memory to be repaired. The memory to be repaired in this application can be a Random Access Memory (RAM), a Static Random-Access Memory (SRAM), etc.

[0051] In an embodiment of the present application, multiple transceivers are set to connect memories, so that the number of memories connected to each transceiver is relatively small. For example, assuming that there are 50 memories, if an equal distribution method is adopted, assuming that the number of transceivers is 2, each transceiver is connected to 25 memories; if the number of transceivers is 5, each transceiver is only connected to 10 memories. It can be seen that the more transceivers there are, the fewer memories connected to each transceiver, so that when performing logic repairs, the memory repair speed is faster.

[0052] Since the fewer memories connected to each transceiver, the shorter the time it takes to send repair data, when the memory connected to each transceiver is a memory chain formed by multiple memories connected in series, when sending repair data (repair information), the repair information is moved into the memory by serial shifting. Even if most memories do not need repair information, it still takes time. For example, the number of memories connected to each transceiver is 6. Assuming that repairing a single memory requires 20 bits of data, taking the repair of 6 memories as an example, a total of 120 bits of data are required. In the serial distribution mode, assuming that a repair clock can only transmit 1 repair bit, a total of 120 repair clocks are required. If only one memory needs to be repaired, theoretically only the repair information needs to be transmitted to the broken memory, that is, only 20 repair clocks are needed to complete the repair, but in reality 120 repair clocks are required, resulting in a lot of time wasted. If each transceiver is connected to only one memory, only 20 repair clocks are needed to complete the repair. It can be seen that setting multiple transceivers to reduce the number of memories connected to each transceiver is beneficial to improving the memory repair efficiency.

[0053] In a first possible implementation, a distribution controller is configured to read a repair data packet for a logical repair memory from a non-volatile memory, and distribute the repair data packet to a target transceiver whose identity matches the target identity in the repair data packet. Accordingly, each target transceiver is configured to send the repair data in the repair data packet from the distribution controller to a memory connected to the target transceiver.

[0054] In this embodiment, the distribution controller can be connected to each transceiver through different pins (PINs), so that one-to-one transmission can be achieved when sending data packets. By adding a target identity in the data packet, when sending a data packet, the data packet can be sent only to the target transceiver whose identity matches the target identity in the repair data packet, and there is no need to send data packets to other transceivers whose identity does not match the target identity in the repair data packet, thereby saving circuit power consumption.

[0055] Under the first possible implementation, the distribution controller can store the identity of each transceiver inside, and the identity is used to match the target identity in the repair data packet, thereby achieving the purpose of distributing the repair data packet only to the target transceiver whose identity matches the target identity in the repair data packet.

[0056] It can be understood that under the first possible implementation method mentioned above, each target transceiver can also be configured to obtain the target identity in the repair data packet, and match the target identity with the identity of the target transceiver. If the identifications match (i.e., the identifications hit), the repair data in the repair data packet will be sent to the connected memory. Through double verification, it is ensured that the received data packet is indeed the required data packet to increase data security.

[0057] In a second possible implementation, the distribution controller is configured to read a repair data packet for a logical repair memory from a non-volatile memory, and distribute the repair data packet to each transceiver. Accordingly, each transceiver is configured to obtain a target identity in the repair data packet, and match the target identity with the identity of the transceiver. If the identity matches, the repair data in the repair data packet is sent to the memory connected to the transceiver. In this implementation, the distribution controller can be connected to each transceiver through the same pin, so that when sending a data packet, a data packet can be sent to all transceivers, thereby saving pin data. At the same time, after receiving the repair data packet, each transceiver determines whether to receive the repair data in the repair data packet by matching the target identity with the identity of the transceiver. Only when the identity matches, the transceiver sends the repair data in the repair data packet to the memory connected to the transceiver, which can also save circuit power consumption.

[0058] In one possible implementation, the above-mentioned target identity identifier can be divided into a unicast identifier and a multicast identifier according to the number of receivers. Among them, the multicast identifier indicates that multiple transceivers can receive the repair information at the same time, while the unicast identifier indicates that only a single transceiver can receive the repair information. The multicast identifier can be further subdivided into: a broadcast identifier or a multicast identifier. The broadcast identifier means that all transceivers can receive the repair information at the same time, while the multicast identifier means that all transceivers in a specific group can receive the repair information at the same time.

[0059] By setting the identification mode, it is possible to transmit repair information only to the memory that needs to be repaired. Other memories that do not need to be repaired do not need to transmit repair information, which can save memory repair time. The multicast identifier can be set to a broadcast identifier, so that all memories can receive repair information at the same time. The multicast identifier can also be set to a multicast identifier, which divides the memory into multiple groups. The transceivers in each group receive repair information at the same time, and the groups are independent of each other.

[0060] In some possible implementations, the above-mentioned target identity identifier can also be a data clearing identifier. When the target identity identifier in the data packet is a data clearing identifier, since the function of the data clearing identifier is to reset the repair data in the memory, that is, to clear it to zero, therefore, in this implementation, the repair data packet may not carry repair data, and the data in the repair data field defaults to all 0s. Since there is no need to transmit repair data, the efficiency of data transmission is improved. When setting the target identity identifier, the identifier bit width in the data packet can be reasonably set according to the number of transceivers and the number of multicast scenarios to reduce unnecessary waste of bus bandwidth.

[0061] In a possible implementation, the target identity and the identity of the transceiver both include a multicast identity and a unicast identity, and each transceiver is configured to perform at least one of the following identity matching: i. matching the multicast identity in the target identity with the multicast identity of the transceiver; ii. matching the unicast identity in the target identity with the unicast identity of the transceiver. If any of the identities match, the repair data in the repair data packet is sent to a memory connected to the transceiver.

[0062] When performing multicast identifier matching and unicast identifier matching, multicast identifier matching (or unicast identifier matching) may be performed first. If the matching fails, unicast identifier matching (or multicast identifier matching) may be performed. If the matching succeeds, no subsequent matching is required, which can improve matching efficiency.

[0063] In a possible implementation, the high bit in the target identification field may represent the multicast identification, and the remaining bits may represent the unicast identification. For example, assuming that the target identification field is 10 bits, bits 0-7 represent the unicast identification, bits 8-9 represent the multicast identification, and different values ​​represent different groups. Assuming that there are 4 transceivers, represented by M0, M1, M2, and M3 respectively, the corresponding relationship between the multicast identification and the unicast identification corresponding to each transceiver can be shown in Table 1.

[0064] Table 1

[0065]

[0066]

[0067] When data is sent only to M0, the values ​​of the multicast identifier and the unicast identifier in the target identification field sent by the distribution controller can be {0, 11}; similarly, if data is sent only to M1, the values ​​of the multicast identifier and the unicast identifier in the target identification field sent by the distribution controller can be {0, 12}; similarly, if data is sent only to M2, the values ​​of the multicast identifier and the unicast identifier in the target identification field sent by the distribution controller can be {0, 13}; similarly, if data is sent only to M3, the values ​​of the multicast identifier and the unicast identifier in the target identification field sent by the distribution controller can be {0, 14}. When data is sent to M0 and M1 at the same time, the values ​​of the multicast identifier and the unicast identifier in the target identification field sent by the distribution controller can be {1, 0}; similarly, when data is sent to M2 and M3 at the same time, the values ​​of the multicast identifier and the unicast identifier in the target identification field sent by the distribution controller can be {2, 0}.

[0068] In a possible implementation mode, if the identifiers do not match, each transceiver is further configured to identify whether the target identity is a data clearing identifier, and when the target identity is a data clearing identifier, the repair data in the memory connected to the transceiver is cleared. For example, the values ​​of the multicast identifier and the unicast identifier in the target identity field sent by the distribution controller can be {0, 0}, and the target identity can be considered to be a data clearing identifier. When the transceiver clears the repair data in the repair data packet, the implementation method can be: clear the repair data in the repair data packet, and then send the repair data (all zero) in the repair data packet to the memory connected to the transceiver. Since the repair data sent by the transceiver to the memory is all zero data, the repair data in the repair data packet can be cleared. It can be understood that the value of the multicast identifier and the unicast identifier in the target identity field is {0, 0} is only a representation of a data clearing identifier, and it can also be implemented in other ways. For example, when the value of the multicast identifier and the unicast identifier in the target identity field is {0, 1}, it indicates that the target identity is a data clearing identifier.

[0069] The operation of clearing the repair data in the memory connected to the transceiver can occur in the early stage of memory repair. After the repair data in the memory is cleared, the required repair data is subsequently transmitted to repair the memory, which can reduce the adverse effects of the repair data already in the memory on the repair. In one possible implementation, after the repair data in the memory connected to the transceiver is cleared, the above-mentioned actions are repeated. For example, the distribution controller reads the repair data packet for logically repairing the memory from the non-volatile memory, and distributes the repair data packet to each transceiver. Each transceiver obtains the target identity in the repair data packet and matches the target identity with the identity of the transceiver. If the identities match, the repair data in the repair data packet is sent to the memory connected to the transceiver.

[0070] When the target identity includes a multicast identity and a unicast identity, the above-mentioned identity mismatch may be that the multicast identity in the target identity does not match the multicast identity of the transceiver, and the unicast identity in the target identity does not match the unicast identity of the transceiver.

[0071] In a possible implementation, the transceiver's transceiver principle may be as follows: Figure 2a , Figure 2b As shown, Figure 2b In the embodiment shown, the target identity includes only one identifier, Figure 2a The target identity includes a multicast identity and a unicast identity. When performing identity hit matching, Figure 2a The matching order in is replaced by: first match the unicast identifier, and if the match fails, then match the multicast identifier.

[0072] The connection line between the distribution controller and the transceiver can be called the repair data bus, which includes a clock repair_clk line and an N-bit repair_data data line, so that one repair clock can transmit N repair bits. The repair_clk line is connected to the repair_clk port of the transceiver, and the repair_data data line is connected to the repair_data port of the transceiver. Among them, the repair clk line is used to transmit repair_clk, and the repair_data data line is used to transmit repair_data. N is an integer greater than or equal to 1, that is, the bit width of the repair_data data line can be 1 bit or >1 bit.

[0073] In a possible implementation, the above distribution controller can be implemented based on a programmable logic device. Figure 3 As shown, the distribution controller includes: an interface module and a bit width conversion circuit, and the bit width conversion circuit is connected to the interface module and each transceiver respectively. The interface module is used to connect the non-volatile memory (such as Figure 3 The interface module is configured to read the repair data packet from the non-volatile memory.

[0074] In a possible implementation, when the non-volatile memory is an OTP device, the principle of the distribution controller can be as follows: Figure 4 As shown. In this embodiment, the bit width conversion circuit is configured to receive the repair data packet sent by the interface module based on the first data line, and distribute the repair data packet to each transceiver based on the second data line (i.e., the above-mentioned repair data bus). In this embodiment, the bit width conversion circuit can be a commonly used bit width conversion circuit in the prior art.

[0075] In another embodiment, the bit width conversion circuit is configured to receive the repair data packet sent by the interface module based on the first data line, and distribute the repair data packet to the target transceiver whose identity matches the target identity in the repair data packet based on the second data line. In this embodiment, based on the bit width conversion circuit in the previous embodiment, an identification recognition module and a comparison module can be added inside the circuit to identify the target identity of the repair data packet and match the target identity with the identity of the built-in transceiver.

[0076] The bus width of the first data line is a first bit width K, and the bus width of the second data line is a second bit width N. K is an integer greater than or equal to 1. In a possible implementation, K and N may not be equal.

[0077] In some implementations, if the size of the received repair data packet is not an integer multiple of the second bit width, that is, if the size of the repair data packet cannot be divided by the second bit width, the bit width conversion circuit is configured to perform a zero padding operation on the received repair data packet, and distribute the zero-padded repair data packet to each transceiver based on the second data line. The size of the zero-padded repair data packet is an integer multiple of the second bit width. Assuming that the size of the zero-padded repair data packet is Mbit, M is an integer multiple of N.

[0078] In one implementation, the size of the repair data packet may be learned based on the header of the repair data packet.

[0079] When the bit width of the repair_data data line is N and N=1, the size of the repair data packet received at this time can be divided by N. The corresponding relationship between the data packet and the data line is shown in Table 2.

[0080] Table 2

[0081] repair_data data line bit 0 Packet bit0 Packet bit1 … Packet bit M-1

[0082] When the bit width of the repair_data data line is N and N>1, the corresponding relationship between the data packet after zero padding and the data line is shown in Table 3.

[0083] Table 3

[0084] repair_data data line bit N-1 Packet bit N-1 … Packet bit M-1 … … … Pack bit M-2 repair_data data line bit 0 Packet bit0 Pack bit N Pack bit M-3

[0085] In one possible implementation, the transceiver may be a common transceiver for transmitting and receiving data. In another possible implementation, as Figure 5 As shown, each transceiver includes: an identification extraction module, a comparison module, and a repair information extraction module. In some possible implementations, if the repair data packet can also include a packet header, each transceiver also includes: a packet header detection module. At the same time, the identification extraction module and the comparison module can be integrated together and can be called an identification extraction and comparison module.

[0086] The header detection module is configured to detect the header of the data packet, and when a valid header is detected, the subsequent operation is started. The identification extraction module is connected to the header detection module, and the identification extraction module is configured to extract the target identity from the repair data packet when the header is valid, obtain the target identity in the repair data packet, and send the extracted target identity to the comparison module. The comparison module is connected to the identification extraction module, and the comparison module is configured to match the target identity with the identity of the transceiver (i.e., ID) to obtain a matching result. The repair information extraction module is connected to the comparison module, and the repair information extraction module is configured to indicate that if the matching result indicates an identification match, the subsequent repair information of the data packet is sent to the current transceiver, otherwise the repair information is ignored. When the identification matches, the repair data in the repair data packet is obtained, and the repair data is sent to the memory connected to the transceiver.

[0087] In one possible implementation, Figure 6 As shown, the memory repair circuit also includes a logic circuit, which is located on the line between the distribution controller and the transceiver. The logic circuit is configured to optimize the data signal sent by the distribution controller to the transceiver. Signal optimization refers to the use of various technologies and methods to improve the quality, performance and reliability of the signal. For example, the logic circuit delays and beats the data signal sent by the distribution controller to the transceiver to increase the timing convergence, or enhances the strength and stability of the data signal sent by the distribution controller to the transceiver. When the physical location of the transceiver is relatively far or the timing is relatively tight, one or more logic circuits can be inserted in the line between the distribution controller and the transceiver to optimize the data signal sent by the distribution controller to the transceiver. It can be understood that if the timing of the data signal sent by the distribution controller to the transceiver can converge, or the signal strength and stability can meet the circuit requirements, the logic circuit may not be inserted.

[0088] In one implementation, the principle of the logic circuit can be as follows Figure 7 As shown, the logic circuit can be a register delay beat logic, which delays the signal by introducing a register (flip-flops) in the signal path, thereby reducing or eliminating the metastable problem and ensuring the timing stability of the signal.

[0089] In a possible implementation, the logic circuit may be a buffer to ensure that the signal is not lost due to attenuation during transmission.

[0090] An embodiment of the present application further provides a memory repair system, which includes: a memory to be repaired and the above-mentioned memory repair circuit, wherein the memory repair circuit is connected to the memory to be repaired.

[0091] The memory repair system provided in the embodiment of the present application has the same implementation principle and technical effects as those of the aforementioned memory repair circuit embodiment. For the sake of brief description, for matters not mentioned in the system embodiment, reference may be made to the corresponding contents in the aforementioned memory repair circuit embodiment.

[0092] The present application also provides a memory repair method, such as Figure 8 As shown below, combined Figure 8 The memory repair method provided in the embodiment of the present application is described. The memory repair method provided in the embodiment of the present application can be applied to the above-mentioned transceiver, or to other electronic devices with the function.

[0093] S1: Obtain a repair data packet for logically repairing a memory.

[0094] The repair data packet contains the target identity and the repair data. The target identity can be used to verify and identify the identity of the receiver. Only the receiver with the same identity is eligible to receive the repair data.

[0095] S2: Obtain a target identity in the repair data packet, and perform identity matching between the target identity and a preset identity.

[0096] In one possible implementation, the target identity and the preset identity both include a multicast identity and a unicast identity. The implementation process of the above S2 may be: matching the multicast identity in the target identity with the multicast identity in the preset identity; and / or matching the unicast identity in the target identity with the unicast identity in the preset identity; wherein, if any of the identities match, the repair data in the repair data packet is sent to the storage to be repaired.

[0097] When the memory repair method provided in the embodiment of the present application is applied to an electronic device, the above-mentioned preset identity is the identity of the electronic device. In a possible implementation manner, the above-mentioned preset identity may be the identity of a transceiver.

[0098] S3: If the identifiers match, the repair data in the repair data packet is sent to the storage to be repaired.

[0099] In one possible implementation, if the identifiers do not match, the above-mentioned memory repair method further includes: identifying whether the target identity identifier is a data clearing identifier; when the target identity identifier is a data clearing identifier, clearing the repair data in the memory to be repaired. When clearing the repair data in the memory to be repaired, the repair data in the repair data packet may be cleared, and then the repair data (all zeros) in the repair data packet is sent to the memory to be repaired, and the repair data in the memory to be repaired is cleared by setting the repair data in the repair data packet to all zeros. When the target identity identifier is not a data clearing identifier, the repair data packet may be ignored.

[0100] The memory repair method provided in the embodiment of the present application has the same implementation principle and technical effects as those of the aforementioned memory repair circuit embodiment. For the sake of brief description, for matters not mentioned in the method embodiment, reference may be made to the corresponding contents in the aforementioned memory repair circuit embodiment.

[0101] like Fig. 9 As shown, Fig. 9 The electronic device 200 provided in the embodiment of the present application is shown in the structural block diagram. The electronic device 200 comprises: a transceiver 210, a memory 220, a communication bus 230 and a processor 240.

[0102] The transceiver 210, the memory 220, and the processor 240 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses 230 or signal lines. Among them, the transceiver 210 is used to send and receive data. The memory 220 is used to store computer programs, which include at least one software function module that can be stored in the memory 220 in the form of software or firmware or solidified in the operating system (OS) of the electronic device 200. The processor 240 is used to execute the computer program stored in the memory 220 to execute the above-mentioned memory repair method.

[0103] The memory 220 may be, but is not limited to, a random access memory, a programmable read-only memory, an erasable read-only memory, an electrically erasable read-only memory, etc.

[0104] The processor 240 may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a graphics processor (GPU), an accelerated processing unit (Accelerated Processing Unit), a multimedia application processor (MAP), a microprocessor, etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The disclosed methods, steps and logic block diagrams in the embodiments of the present application may be implemented or executed. Alternatively, the processor 240 may also be any conventional processor, etc.

[0105] The electronic device 200 mentioned above includes but is not limited to a mobile phone, a tablet, a computer, a server, etc.

[0106] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0107] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0108] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0109] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a computer-readable storage medium, including several instructions for a computer device (which can be a personal computer, a laptop, a server, or an electronic device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned computer-readable storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0110] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A memory repair circuit, characterized in that: include: A plurality of transceivers, each of the transceivers is used to connect to a memory; A distribution controller is connected to each of the transceivers, and is configured to read a repair data packet for logical repair memory from a non-volatile memory and distribute the repair data packet to each of the transceivers; wherein the repair data packet includes a target identity and repair data; Each of the transceivers is configured to obtain a target identity in the repair data packet, and match the target identity with the identity of the transceiver. If the identities match, the repair data in the repair data packet is sent to a memory connected to the transceiver.

2. The memory repair circuit according to claim 1, characterized in that: The target identity and the identity of the transceiver both include a multicast identity and a unicast identity; each of the transceivers is configured to perform at least one of the following identity matching: i. matching the multicast identifier in the target identity with the multicast identifier of the transceiver; ii. matching the unicast identifier in the target identity with the unicast identifier of the transceiver; If any of the identifiers matches, the repair data in the repair data packet is sent to a memory connected to the transceiver.

3. The memory repair circuit according to claim 1, characterized in that: If the identifiers do not match, each of the transceivers is further configured to clear the repair data in the memory connected to the transceiver when the target identity identifier is a data clearing identifier.

4. The memory repair circuit according to claim 1, characterized in that: The distribution controller comprises: An interface module, used to connect to the non-volatile memory, and the interface module is configured to read the repair data packet from the non-volatile memory; A bit width conversion circuit is connected to the interface module and each of the transceivers respectively; the bit width conversion circuit is configured to receive a repair data packet sent by the interface module based on a first data line, and distribute the repair data packet to each of the transceivers based on a second data line; The bus width of the first data line is a first bit width, and the bus width of the second data line is a second bit width.

5. The memory repair circuit according to claim 4, characterized in that: If the size of the received repair data packet is not an integer multiple of the second bit width; the bit width conversion circuit is further configured to perform a zero padding operation on the received repair data packet, and distribute the zero-padded repair data packet to each of the transceivers based on the second data line; The size of the repair data packet after zero padding is an integer multiple of the second bit width.

6. The memory repair circuit according to claim 1, characterized in that: Each of the transceivers comprises: An identification extraction module is configured to obtain a target identification in the repair data packet; A comparison module connected to the identification extraction module, wherein the comparison module is configured to perform identification matching between the target identification and the identification of the transceiver to obtain a matching result; A repair information extraction module is connected to the comparison module, and is configured to obtain the repair data in the repair data packet if the matching result indicates a match, and send the repair data to a memory connected to the transceiver.

7. The memory repair circuit according to any one of claims 1 to 6, characterized in that: The memory repair circuit also includes a logic circuit, the logic circuit being located on a line between the distribution controller and the transceiver; The logic circuit is configured to optimize the data signal sent by the distribution controller to the transceiver.

8. A memory repair circuit, characterized in that: include: A plurality of transceivers, each of the transceivers is used to connect to a memory; a distribution controller connected to each of the transceivers, respectively, the distribution controller being configured to read a repair data packet for logically repairing the memory from a non-volatile memory, and distribute the repair data packet to a target transceiver whose identity matches a target identity in the repair data packet; wherein the repair data packet includes a target identity and repair data; Each of the target transceivers is configured to send the repair data in the repair data packet to a memory connected to the target transceiver.

9. A memory repair system, characterized in that: include: A memory to be repaired and a memory repair circuit as described in any one of claims 1 to 7, or a memory repair circuit as described in claim 8, wherein the memory repair circuit is connected to the memory to be repaired.

10. A memory repair method, characterized in that: include: Acquire a repair data packet for logically repairing the memory, wherein the repair data packet includes a target identity and repair data; Obtaining a target identity in the repair data packet, and matching the target identity with a preset identity; If the identifiers match, the repair data in the repair data packet is sent to the storage to be repaired.

11. The method according to claim 10, characterized in that The target identity and the preset identity both include a multicast identity and a unicast identity; matching the target identity with the preset identity includes: Matching the multicast identifier in the target identity identifier with the multicast identifier in the preset identity identifier; and / or; Matching the unicast identifier in the target identity identifier with the unicast identifier in the preset identity identifier; If any of the identifiers matches, the repair data in the repair data packet is sent to the memory to be repaired.

12. The method according to claim 10, characterized in that If the identifiers do not match, the method further includes: Identify whether the target identity is a data clearing identity; When the target identity is the data clearing identifier, the repair data in the memory to be repaired is cleared.

13. An electronic device, characterized in that: include: A memory and a processor, wherein the processor is connected to the memory; The memory is used to store programs; The processor is used to call the program stored in the memory to execute the method according to any one of claims 10-12.

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