Method and device for testing protocol consistency function of network switching chip

Abstract

The present invention provides a method and device for testing the protocol consistency function of a network switch chip. The method includes a PGC module disposed within each port of the network switch chip, and the PGC module is used to perform a protocol consistency test on the network switch chip. The PGC module is located in the core switch and the transmission path direction of each port in the network switch chip. PGC refers to packet generation and packet capture. The method specifically includes: using the PGC module to configure two ports of the network switch chip as a packet generation port and a packet capture port, respectively; using the PGC module to write a protocol packet at the packet generation port and send it out, and capturing the protocol packet routed through the core switch at the packet capture port; and determining the connectivity and protocol consistency of all ports on the routing path based on the protocol packet written at the packet generation port and the protocol packet captured at the packet capture port.

Description

Technical Field

[0001] The present invention relates to the technical field of chip function debugging, and in particular to a method and device for testing the protocol consistency function of a network switching chip. Background Art

[0002] Protocol conformance testing is a key test metric for high-speed network switching chips. Existing port protocol conformance testing methods for network switching chips typically involve interfacing the chip under test with a protocol tester or standard equipment available on the market to verify the port protocol conformance of the chip under test.

[0003] Currently, relevant testing technologies include chip built-in self-test (BIST) technology (such as CN116758968A and CN114036885A), technologies related to communication protocol consistency testing (such as CN116668346A), and technologies related to external standard test equipment or self-developed packet generators (such as FPGA-based software-defined traffic generators [J]).

[0004] Built-in self-test (BIST) technology integrates functional circuitry into circuits during design to provide self-test capabilities, thereby reducing the reliance on automatic test equipment (ATE) for device testing. BIST technology can be broadly categorized into two types: logic BIST (LBIST) and memory BIST (MBIST). BIST can detect most defects during chip manufacturing, but it cannot fully test internal chip functions. Therefore, BIST is typically used in chip screening.

[0005] CN116668346A provides a network protocol consistency testing method and system device, which includes: obtaining a mirror file of a target container, and constructing a target test topology environment based on the mirror file and the target device to be tested; in the target test topology environment, testing the network protocol consistency of the target device to be tested based on the test tool in the mirror file to obtain the target test result; however, this method depends on the mirror file in the target container and the network protocol consistency testing tool.

[0006] The "FPGA-based software-defined traffic generator" proposes a software-defined traffic generator based on FPGA (field programmable gate array) or hardware implementation. It supports configuring the protocol type, quantity, length, interval, etc. of each port data packet, and has high speed, flexibility and scalability. However, it is used as an external test tool to connect with the device under test for docking testing. The traditional protocol function consistency testing method that uses docking with standard test instruments and equipment has made testing costs increasingly uncontrollable due to complex test environment construction, long test time, limited I / O channels and expensive memory resources. Summary of the Invention

[0007] The present invention provides a method and device for testing the protocol consistency function of a network switching chip, which aims to complete functional testing of the connectivity of each port of a high-speed network switching chip and protocol function consistency testing without relying on external testing tools.

[0008] In a first aspect, the present invention provides a method for testing the protocol consistency function of a network switch chip, wherein a PGC module is provided inside each port of the network switch chip, and the protocol consistency function test of the network switch chip is performed using the PGC module; wherein the PGC module is located in the core switch and the sending path direction of each port in the network switch chip, and PGC refers to packet generation and packet capture; the method specifically comprises:

[0009] Using the PGC module, two ports of the network switch chip are configured as a packet generation port and a packet capture port respectively;

[0010] Using the PGC module to write a protocol packet at the packet generation port and send it out, and capturing the protocol packet routed via the core switch at the packet capture port;

[0011] The connectivity and protocol consistency of all ports on the routing path are determined according to the protocol packet written at the packet generation port and the protocol packet captured at the packet capture port.

[0012] Furthermore, the PGC module is used to write a protocol packet at the packet generation port and send it out, and the protocol packet routed via the core switch is captured at the packet capture port, specifically including:

[0013] Writing a protocol request packet at the packet generation port and sending it to the standard device at the other end of the link and receiving a response packet returned by the standard device at the other end of the link;

[0014] The packet generation port forwards the response packet to the packet capture port via the core switch route, and the packet capture port captures the response packet via the core switch route.

[0015] Furthermore, the PGC module is used to write a protocol packet at the packet generation port and send it out, and the protocol packet routed via the core switch is captured at the packet capture port, specifically including:

[0016] Writing a request protocol packet at the packet generation port, and forwarding the request protocol packet to one of the ports C of the network switch chip through the core switch router in a port loopback manner, so that the port C forwards the request protocol packet to the standard device at the other end of the link and receives a response packet returned by the standard device at the other end of the link;

[0017] The port C forwards the response packet to the packet capture port via the core switch route, and the packet capture port captures the response packet via the core switch route.

[0018] Furthermore, the PGC module is used to write a protocol packet at the packet generation port and send it out, and the protocol packet routed via the core switch is captured at the packet capture port, specifically including:

[0019] A protocol data packet is written at the packet generation port, and the protocol data packet is forwarded to the packet capture port via the core switch routing in a port loopback manner. The packet capture port captures the protocol data packet via the core switch routing.

[0020] Furthermore, the PGC module is used to write a protocol packet at the packet generation port and send it out, and the protocol packet routed via the core switch is captured at the packet capture port, specifically including:

[0021] A protocol data packet is written at the packet generation port, and the protocol data packet is forwarded to at least one port of the network switching chip through the core switching router using a port loopback method. The last port forwards the protocol data packet through the core switching router to the packet capture port using a port loopback method. The packet capture port captures the protocol data packet passing through the core switching router.

[0022] Furthermore, the PGC module includes a configuration bus synchronization unit, a PGC register, a PG state machine, a PC state machine, a PGC cache and a multiplexer; wherein PG refers to packet generation and PC refers to packet capture;

[0023] The configuration bus synchronization unit is used to convert the AXI configuration bus into a local configuration bus;

[0024] The PGC register includes a PGC control register and a PGC data register; the PGC controller is used to control the working mode of the current port, the working mode includes a normal data path mode and a PGC mode, and the PGC mode includes a PG mode and a PC mode; the PGC data register is used to store the protocol packet written to the current port in the PG mode, and to store the protocol packet read out of the current port in the PC mode;

[0025] The PG state machine is configured to write the protocol packet in the PGC data register into the PGC cache according to the configuration value of the PGC control register;

[0026] The PC state machine is configured to read the protocol packet sent by the core switch to the PGC cache into the PGC data register according to the configuration value of the PGC control register;

[0027] The PGC cache is used to cache a protocol packet of a maximum length;

[0028] The multiplexer is used to select a data path according to the configuration value of the PGC control register.

[0029] Furthermore, the PGC control register includes five valid fields: TX_Start, RX_Done, SOP, EOP, Start_Port and End_Port;

[0030] The TX_Start field is used to indicate whether the current port can send out the protocol packet written into the PGC cache in PG mode.

[0031] The RX_Done field is used to indicate whether the current port can read the protocol packet in the PGC buffer in PC mode;

[0032] The SOP field is used to indicate whether the current port is writing a protocol packet for the first time in PG mode, and whether the current port is reading a protocol packet for the first time in PC mode;

[0033] The EOP field is used to indicate whether the current port has last written a protocol packet in PG mode, and whether the current port has last read a protocol packet in PC mode;

[0034] The Start_Port field is used to indicate whether the current port's working mode is PG mode;

[0035] The End_Port field is used to indicate whether the current port's working mode is PC mode.

[0036] In a second aspect, the present invention provides an apparatus for testing the protocol consistency function of a network switch chip, comprising a PGC module and a test module disposed within each port of the network switch chip; wherein the PGC module is located in the core switch and the sending path direction of each port in the network switch chip; PGC refers to packet generation and packet capture;

[0037] The PGC module is used to configure two ports of the network switch chip as a packet generation port and a packet capture port respectively; and is used to write a protocol packet at the packet generation port and send it out, and capture the protocol packet routed by the core switch at the packet capture port;

[0038] The testing module is used to determine the connectivity and protocol consistency of all ports on the routing path according to the protocol packet written at the packet generation port and the protocol packet captured at the packet capture port.

[0039] Furthermore, the PGC module includes a configuration bus synchronization unit, a PGC register, a PG state machine, a PC state machine, a PGC cache and a multiplexer; wherein PG refers to packet generation and PC refers to packet capture;

[0040] The configuration bus synchronization unit is used to convert the AXI configuration bus into a local configuration bus;

[0041] The PGC register includes a PGC control register and a PGC data register; the PGC controller is used to control the working mode of the current port, the working mode includes a normal data path mode and a PGC mode, and the PGC mode includes a PG mode and a PC mode; the PGC data register is used to store the protocol packet written to the current port in the PG mode, and to store the protocol packet read out of the current port in the PC mode;

[0042] The PG state machine is configured to write the protocol packet in the PGC data register into the PGC cache according to the configuration value of the PGC control register;

[0043] The PC state machine is configured to read the protocol packet sent by the core switch to the PGC cache into the PGC data register according to the configuration value of the PGC control register;

[0044] The multiplexer is used to select a data path according to the configuration value of the PGC control register.

[0045] Furthermore, the PGC control register includes five valid fields: TX_Start, RX_Done, SOP, EOP, Start_Port and End_Port;

[0046] The TX_Start field is used to indicate whether the current port can send out the protocol packet written into the PGC cache in PG mode.

[0047] The RX_Done field is used to indicate whether the current port can read the protocol packet in the PGC buffer in PC mode;

[0048] The SOP field is used to indicate whether the current port is writing a protocol packet for the first time in PG mode, and whether the current port is reading a protocol packet for the first time in PC mode;

[0049] The EOP field is used to indicate whether the current port has last written a protocol packet in PG mode, and whether the current port has last read a protocol packet in PC mode;

[0050] The Start_Port field is used to indicate whether the current port's working mode is PG mode;

[0051] The End_Port field is used to indicate whether the current port's working mode is PC mode.

[0052] Beneficial effects of the present invention:

[0053] 1. Simplifies the process of building a functional consistency test environment for network switching chips. Using the method and device provided by this invention, after chip tape-out, without relying on external protocol test equipment, chip functional debugging and port connectivity testing can be quickly completed in a laboratory environment. This allows for determination of whether the designed functions of the tested chip meet expectations and whether there are any defects in chip manufacturing, thereby improving chip testing efficiency.

[0054] 2. Connectivity and protocol function consistency tests can be completed using standard equipment at the other end of the link; or, in the absence of standard equipment at the other end of the link, port connectivity and protocol function consistency tests can be completed on an ATE machine in combination with a port loopback method. ATE is a system for testing electronic equipment that can automatically execute test programs and compare test results with expected results. By using the method and device provided by the present invention, the preparation of the protocol function consistency offline test program is completed before the chip is returned, and the debugging of the test program is completed after the chip is returned. Automated testing of port connectivity and protocol function consistency is completed on the ATE machine, which helps ensure that the chip performs tasks correctly under various working conditions, helps discover and resolve potential quality problems that may cause chip failure, improves the performance of the chip in actual applications, and meets the ever-changing market demands. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1A flowchart of a method for testing the protocol consistency function of a network switch chip provided by an embodiment of the present invention;

[0056] Figure 2 The location of the PGC module provided in the embodiment of the present invention in the network switching chip;

[0057] Figure 3 A block diagram of the PGC module structure provided in an embodiment of the present invention;

[0058] Figure 4 Schematic diagram of each field segment of the PGC register provided in an embodiment of the present invention: (a) PGC control register, (b) PGC data register;

[0059] Figure 5 This is one of the typical application scenarios of PGC provided by the embodiment of the present invention;

[0060] Figure 6 The second typical application scenario of PGC provided by the embodiment of the present invention;

[0061] Figure 7 The third typical application scenario of PGC provided by the embodiment of the present invention;

[0062] Figure 8 This is the fourth typical application scenario of PGC provided by the embodiment of the present invention. DETAILED DESCRIPTION

[0063] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0064] Figure 1 The present invention provides a flowchart of a method for testing the protocol consistency function of a network switch chip. Figure 2 This paper describes the implementation structure diagram of the network switching chip and the location of the PGC module in the network switching chip. Figure 1 and Figure 2As shown, an embodiment of the present invention provides a method for testing the protocol consistency function of a network switching chip, wherein a PGC module is provided inside each port (Port) of the network switching chip, and the protocol consistency function test of the network switching chip is performed using the PGC module; wherein the PGC module is located in the core switch (Switch Fabric) of the network switching chip and the sending path direction of each port, PGC: Packet Generation and Capture, refers to packet generation and packet capture; it can be understood that the embodiment of the present invention can implant a PGC module with packet generation and packet capture functions when designing the chip, so that the PGC module can be used to complete the generation and capture of protocol packets subsequently.

[0065] The method specifically includes:

[0066] S101: using the PGC module to configure two ports of the network switch chip as a packet generation port (also called a start port) and a packet capture port (also called an end port);

[0067] S102: Using the PGC module to write a protocol packet at the packet generation port and send it out, and capturing the protocol packet routed through the core switch at the packet capture port;

[0068] In this embodiment, a complete protocol packet is written word by word (32 bits) through I2C or JTAG at the Start Port and sent, and the protocol packet forwarded through the core switch is captured at the End Port, and the captured protocol packet is subsequently read out word by word in a 32-bit manner.

[0069] S103: Determine connectivity and protocol consistency of all ports on the routing path according to the protocol packet written at the packet generation port and the protocol packet captured at the packet capture port.

[0070] The method for testing the protocol consistency function of a network switch chip provided by an embodiment of the present invention utilizes the packet generation and packet capture functions of the PGC module to perform functional testing of port path connectivity and protocol consistency. After the chip is returned from tape-out, the method of the present invention can be used to quickly complete chip functional debugging and port connectivity testing in a laboratory environment without relying on standard protocol testing equipment, thereby determining whether the design function of the chip under test meets expectations and whether there are defects in chip production. Therefore, the present invention greatly simplifies the process of building a functional consistency testing environment for network switch chips. At the same time, the method of the present invention supports the completion of port connectivity and protocol function consistency testing on an ATE machine. ATE is a system for testing electronic devices that can automatically execute test programs and compare test results with expected results. Using the method of the present invention, the preparation of the protocol function consistency offline test program is completed before the chip is returned, and the debugging of the test program is completed after the chip is returned. Automated testing of port connectivity and protocol function consistency is completed on the ATE machine, which helps ensure that the chip performs its tasks correctly under various working conditions, helps discover and resolve potential quality issues that may cause chip failure, improves the performance of the chip in actual applications, and meets the ever-changing market needs. It should be noted that the protocol function consistency testing method based on packet generation and packet capture provided by the present invention does not conflict with the built-in self-test technology, and the two can coexist in the same chip.

[0071] In one embodiment, Figure 3 An implementation structure of the PGA module is given, such as Figure 3 As shown in the figure, the implementation structure of the PGC module mainly includes five major units: configuration bus synchronization unit, PGC register, PG state machine, PC state machine, PGC cache (also called PGC_buffer) and multiplexer; among them, PG: Packet Generation, refers to packet generation, PC: PacketCapture, refers to packet capture;

[0072] Specifically, the configuration bus synchronization unit is used to convert the AXI configuration bus to the local configuration bus. The PGC register includes a PGC control register and a PGC data register; wherein the PGC controller is used to control the working mode of the current port, and the working mode includes a normal data path mode and a PGC mode, and the PGC mode includes a PG mode and a PC mode. The PGC data register is used to store the protocol packets written to the current port in PG mode, and to store the protocol packets read out of the current port in PC mode; the PG state machine is used to write the protocol packets in the PGC data register into the PGC cache according to the configuration value of the PGC control register; the PC state machine is used to read the protocol packets sent by the core exchange to the PGC cache into the PGC data register according to the configuration value of the PGC control register; the multiplexer is used to select a data path according to the configuration value of the PGC control register, such as a PG port mode path, a PC port mode path, and a normal data path (i.e., a non-PGC mode path).

[0073] In this embodiment, the PGC control register and the PGC data register are both 32-bit registers. It will be appreciated that the configuration values ​​of the various fields of the PGC control register are used to enable or disable PGC mode, and to distinguish, within PGC mode, whether the current port is used for PG (i.e., configuring the current port as a Start Port) or PC (i.e., configuring the current port as an End Port). It will be appreciated that when a port is configured in PGC mode, it can only be used in PG mode or PC mode and cannot be used for normal data exchange.

[0074] In this embodiment, based on the configuration value of the PGC control register, the PG state machine sequentially writes the data in the 32-bit PGC data register to the PGC_buffer module until a complete protocol packet (including the header and payload) is written. Similarly, based on the configuration value of the PGC control register, the PC state machine sequentially reads a complete packet sent by the core switch to the PGC_buffer module in a 32-bit manner.

[0075] Further, Figure 4 This section describes the schematic diagram of each field segment of the PGC control register and the PGC data register. The meaning of the register field segments can make it easier to understand the function implementation of the PGC. Figure 4(a) lists only the fields closely related to the PGC function. The Reserved field [31:6] can be expanded as needed. The valid fields of the PGC control register include TX_Start, RX_Done, SOP (Start of Packet), EOP (End of Packet), Start_Port, and End_Port, a total of five fields.

[0076] Among them, the TX_Start field is used to indicate whether the current port can send out the protocol packet written in the PGC cache in PG mode. The RX_Done field is used to indicate whether the current port can read the protocol packet in the PGC cache in PC mode. The SOP field is used to indicate whether the current port writes a protocol packet for the first time in PG mode, and indicates whether the current port reads a protocol packet for the first time in PC mode. The EOP field is used to indicate whether the current port writes a protocol packet for the last time in PG mode, and indicates whether the current port reads a protocol packet for the last time in PC mode. The Start_Port field is used to indicate whether the working mode of the current port is PG mode. The End_Port field is used to indicate whether the working mode of the current port is PC mode.

[0077] Specifically, the TX_Start field is used in PG mode. After all protocol packets have been written to the PGC_buffer in 32-bit increments, the TX_Start field can be set to 1 to indicate that the current Start_Port can send the protocol packet. The RX_Done field is read-only and is used in PC mode. In PC mode, a 1 in this field indicates that the current End_Port has received a complete protocol packet and can now read the packet from the PGC_buffer in 32-bit increments. A 1 in the SOP field indicates the first 32-bit write of a protocol packet in PG mode or the first 32-bit read of a protocol packet from the PGC_buffer in PC mode. A 1 in the EOP field indicates the last 32-bit write of a protocol packet in PG mode or the last 32-bit read of a protocol packet from the PGC_buffer in PC mode. When the Start_Port field is set to 1, the port is configured in PG mode. When the End_Port field is set to 1, the port is configured in PC mode.

[0078] It is understood that in PGC mode, one of the Start_Port and End_Port fields must be configured as 1. When both the Start_Port and End_Port fields are configured as 0, it means that the port is in non-PGC mode, that is, the port is a normal protocol packet forwarding port.

[0079] Figure 4 (b) lists the Data field of the PGC data register, where the Data field represents the 32-bit protocol packet data written word by word to the PGC_buffer in PG mode, or represents the 32-bit protocol packet data read from the PGC_buffer in PC mode.

[0080] By alternately configuring the PGC control register and the PGC data register multiple times, the generation of protocol packets in PG mode or the capture of protocol packets in PC mode can be completed.

[0081] In one embodiment, Figure 5 One of the typical application scenarios of PGC module is given below. Figure 5 The figure shows the two ports (Port A and Port B) of the network switch chip and the standard equipment at the other end of the link. Port A is configured in PG mode, that is, Start Port A; Port B is configured in PC mode, that is, End Port B. A protocol request packet is written to Start Port A (in this embodiment, directly using Figure 3 The PGC module structure shown in the figure corresponds to the process of writing a protocol request packet, which includes: configuring the PGC control register and PGC data register in sequence according to the packet generation method, then sending the protocol request packet to the standard device at the other end of the link. After receiving the protocol request packet, the standard device at the other end of the link sends a response packet to StartPort A. StartPort A forwards the response packet to EndPort B through the core switching route, and then reads the response packet captured by EndPort B by register access, thereby verifying the connectivity and protocol consistency of PortA and PortB.

[0082] In one embodiment, Figure 6 Another typical application scenario of PGC module is given. Figure 5The application scenario is similar to that of [1]. Port A is configured in PG mode, namely Start Port A; Port B is configured in PC mode, namely End Port B. The difference is that this scenario also adds a port, Port C, which is connected to the standard device at the other end of the link. In this scenario, Start Port A first forwards the protocol request packet generated in PG mode to Port C through port loopback. Port C sends the received protocol request packet to the standard device at the other end of the link. The standard device at the other end of the link then sends the response packet to Port C. Port C then forwards the response packet to End Port B through the core switching route. Finally, the response packet captured by Port B is read out through register access to verify the connectivity and protocol consistency of Ports A, B, and C.

[0083] In one embodiment, Figure 7 This paper describes the application of the PGC module in scenarios where there is no standard equipment on the other end of the link, such as in ATE machine testing. In this case, Port A is configured in PG mode, namely Start Port A; Port B is configured in PC mode, namely End Port B; and Port A uses port loopback mode. At Start Port A, the PGC control registers and PGC data registers are sequentially configured according to packet generation. Protocol packets are sent out through the transmitter and then looped back to the receiver of Start Port A using port loopback mode. The protocol packets from Start Port A are then forwarded to End Port B via the core switching route. The protocol packets captured by End Port B are then read out using register access. This method verifies the connectivity and protocol consistency of Ports A and B.

[0084] In one embodiment, Figure 7 The application scenario is similar. Figure 8This paper describes an application scenario where the PGC module is used in a scenario without standard link peer devices, and verifies the connectivity and protocol conformance of multiple ports using port loopback mode. In this scenario, Port A is configured in PG mode (Start Port A), and Port B is configured in PC mode (End Port B). However, two additional ports are added to the routing path. Port A uses port loopback mode. The PGC control registers and PGC data registers are sequentially configured at Start Port A using packet generation. Protocol packets are sent from the transmitter and then looped back to Start Port A's receiver using port loopback mode. The protocol packets from Start Port A are then forwarded via the core switch routing to one of the newly added ports. This port also uses port loopback to forward the protocol packets via the core switch routing to another newly added port. This other port also uses port loopback to forward the protocol packets via the core switch routing to End Port B. The protocol packets captured by End Port B are then read using register access. This process verifies the connectivity and protocol conformance of Port A, Port B, and the two newly added ports.

[0085] An embodiment of the present invention further provides a device for testing the protocol consistency function of a network switch chip, comprising a PGC module and a test module disposed inside each port of the network switch chip; wherein the PGC module is located in the core switch of the network switch chip and in the sending path direction of each port; PGC refers to packet generation and packet capture;

[0086] Among them, the PGC module is used to configure two ports of the network switching chip as a packet generation port and a packet capture port respectively; and is used to write a protocol packet at the packet generation port and send it out, and capture the protocol packet routed through the core switch at the packet capture port; the test module is used to determine the connectivity and protocol consistency of all ports on the routing path based on the protocol packet written at the packet generation port and the protocol packet captured at the packet capture port.

[0087] In one embodiment, the structure of the PGC module in this embodiment is as follows: Figure 3 and Figure 4 It is understood that the apparatus for testing the protocol consistency function of a network switch chip provided by the embodiment of the present invention is for the purpose of implementing the above method, and its specific functions can be referred to the above method embodiments, which will not be described in detail here.

[0088] The method and device for testing the protocol consistency function of a network switching chip proposed in the present invention are as follows: a PGC module with packet generation and packet capture functions is set inside each port of the network switching chip, and the chip protocol consistency function test is implemented by using the PGC module, without the need for external docking with standard test equipment, thereby simplifying the construction of the test environment; and, the method and device can be applied to scenarios with link peer devices, and also support automatic testing on ATE, that is, it can be applied to scenarios without link peer devices through port loopback mode.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A method for testing the protocol consistency function of a network switch chip, characterized in that: A PGC module is provided inside each port of the network switching chip, and the PGC module is used to perform protocol consistency function testing on the network switching chip; wherein the PGC module is located in the core switching and the sending path direction of each port in the network switching chip, and PGC refers to packet generation and packet capture; the PGC module includes a configuration bus synchronization unit, a PGC register, a PG state machine, a PC state machine, a PGC cache and a multiplexer; wherein PG refers to packet generation, and PC refers to packet capture; The configuration bus synchronization unit is used to convert the AXI configuration bus into a local configuration bus; The PGC register includes a PGC control register and a PGC data register; the PGC controller is used to control the working mode of the current port, the working mode includes a normal data path mode and a PGC mode, and the PGC mode includes a PG mode and a PC mode; the PGC data register is used to store the protocol packet written to the current port in the PG mode, and to store the protocol packet read out of the current port in the PC mode; The PG state machine is configured to write the protocol packet in the PGC data register into the PGC cache according to the configuration value of the PGC control register; The PC state machine is configured to read the protocol packet sent by the core switch to the PGC cache into the PGC data register according to the configuration value of the PGC control register; The PGC cache is used to cache a protocol packet of a maximum length; The multiplexer is used to select a data path according to the configuration value of the PGC control register; The method specifically includes: Using the PGC module, two ports of the network switch chip are configured as a packet generation port and a packet capture port respectively; Using the PGC module to write a protocol packet at the packet generation port and send it out, and capturing the protocol packet routed via the core switch at the packet capture port; The connectivity and protocol consistency of all ports on the routing path are determined according to the protocol packet written at the packet generation port and the protocol packet captured at the packet capture port.

2. A method for testing the protocol consistency function of a network switch chip according to claim 1, characterized in that: Utilizing the PGC module to write a protocol packet at the packet generation port and send it out, and capturing the protocol packet routed via the core switch at the packet capture port, specifically includes: Writing a protocol request packet at the packet generation port and sending it to the standard device at the other end of the link and receiving a response packet returned by the standard device at the other end of the link; The packet generation port forwards the response packet to the packet capture port via the core switch route, and the packet capture port captures the response packet via the core switch route.

3. The method for testing the protocol consistency function of a network switch chip according to claim 1, wherein: Utilize the PGC module to write a protocol packet at the packet generation port and send it out, and capture the protocol packet routed via the core switch at the packet capture port, specifically also including: Writing a request protocol packet at the packet generation port, and forwarding the request protocol packet to one of the ports C of the network switch chip through the core switch router in a port loopback manner, so that the port C forwards the request protocol packet to the standard device at the other end of the link and receives a response packet returned by the standard device at the other end of the link; The port C forwards the response packet to the packet capture port via the core switch route, and the packet capture port captures the response packet via the core switch route.

4. The method for testing the protocol consistency function of a network switch chip according to claim 1, wherein: Utilize the PGC module to write a protocol packet at the packet generation port and send it out, and capture the protocol packet routed via the core switch at the packet capture port, specifically also including: A protocol data packet is written at the packet generation port, and the protocol data packet is forwarded to the packet capture port via the core switch routing in a port loopback manner. The packet capture port captures the protocol data packet via the core switch routing.

5. The method for testing the protocol consistency function of a network switch chip according to claim 1, wherein: Utilize the PGC module to write a protocol packet at the packet generation port and send it out, and capture the protocol packet routed via the core switch at the packet capture port, specifically also including: A protocol data packet is written at the packet generation port, and the protocol data packet is forwarded to at least one port of the network switching chip through the core switching router using a port loopback method. The last port forwards the protocol data packet through the core switching router to the packet capture port using a port loopback method. The packet capture port captures the protocol data packet passing through the core switching router.

6. The method for testing the protocol consistency function of a network switch chip according to claim 1, wherein: The PGC control register includes five valid fields: TX_Start, RX_Done, SOP, EOP, Start_Port and End_Port; The TX_Start field is used to indicate whether the current port can send out the protocol packet written into the PGC cache in PG mode. The RX_Done field is used to indicate whether the current port can read the protocol packet in the PGC buffer in PC mode; The SOP field is used to indicate whether the current port is writing a protocol packet for the first time in PG mode, and whether the current port is reading a protocol packet for the first time in PC mode; The EOP field is used to indicate whether the current port has last written a protocol packet in PG mode, and whether the current port has last read a protocol packet in PC mode; The Start_Port field is used to indicate whether the current port's working mode is PG mode; The End_Port field is used to indicate whether the current port's working mode is PC mode.

7. A device for testing the protocol consistency function of a network switching chip, characterized in that: The invention comprises a PGC module and a test module arranged inside each port of the network switching chip; wherein the PGC module is located in the core switching of the network switching chip and the sending path direction of each port; PGC refers to packet generation and packet capture; The PGC module is used to configure two ports of the network switch chip as a packet generation port and a packet capture port respectively; and is used to write a protocol packet at the packet generation port and send it out, and capture the protocol packet routed by the core switch at the packet capture port; The testing module is used to determine the connectivity and protocol consistency of all ports on the routing path according to the protocol packet written at the packet generation port and the protocol packet captured at the packet capture port; The PGC module includes a configuration bus synchronization unit, a PGC register, a PG state machine, a PC state machine, a PGC cache and a multiplexer; wherein PG refers to packet generation and PC refers to packet capture; The configuration bus synchronization unit is used to convert the AXI configuration bus into a local configuration bus; The PGC register includes a PGC control register and a PGC data register; the PGC controller is used to control the working mode of the current port, the working mode includes a normal data path mode and a PGC mode, and the PGC mode includes a PG mode and a PC mode; the PGC data register is used to store the protocol packet written to the current port in the PG mode, and to store the protocol packet read out of the current port in the PC mode; The PG state machine is configured to write the protocol packet in the PGC data register into the PGC cache according to the configuration value of the PGC control register; The PC state machine is configured to read the protocol packet sent by the core switch to the PGC cache into the PGC data register according to the configuration value of the PGC control register; The multiplexer is used to select a data path according to the configuration value of the PGC control register.

8. The device for testing the protocol consistency function of a network switch chip according to claim 7, characterized in that: The PGC control register includes five valid fields: TX_Start, RX_Done, SOP, EOP, Start_Port and End_Port; The TX_Start field is used to indicate whether the current port can send out the protocol packet written into the PGC cache in PG mode. The RX_Done field is used to indicate whether the current port can read the protocol packet in the PGC buffer in PC mode; The SOP field is used to indicate whether the current port is writing a protocol packet for the first time in PG mode, and whether the current port is reading a protocol packet for the first time in PC mode; The EOP field is used to indicate whether the current port has last written a protocol packet in PG mode, and whether the current port has last read a protocol packet in PC mode; The Start_Port field is used to indicate whether the current port's working mode is PG mode; The End_Port field is used to indicate whether the current port's working mode is PC mode.

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