Semiconductor device and preparation method thereof, and electronic equipment

Abstract

The invention discloses a semiconductor device and a preparation method thereof, and electronic equipment, the semiconductor device comprises a substrate, a gate, a gate dielectric layer, a semiconductor layer and a passivation layer, and the gate is located at one side of the substrate; the gate dielectric layer is at least partially located on one side of the gate away from the substrate; the semiconductor layer is located on the side, away from the substrate, of the gate dielectric layer and comprises a source region, a drain region and a channel region located between the source region and the drain region; the passivation layer is located on the side, away from the substrate, of the channel region and used for achieving heavy doping on the channel region. The semiconductor device provided by the invention is provided with the passivation layer covering the channel region, on one hand, the passivation layer can protect the channel region, and the stability of the semiconductor device is improved; and on the other hand, heavy doping and interface optimization of the channel region can be realized, so that the electrical property and the photoelectric property of the semiconductor device are improved. In addition, defects in the semiconductor device are further reduced through the annealing process, so that the electrical characteristics and the photoelectric characteristics of the semiconductor device are improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a semiconductor device and a method for manufacturing the same, and an electronic device. Background Art

[0002] Since the mid-20th century, integrated circuit technology has experienced rapid development under the guidance of Moore's Law. However, with the advancement of technology, traditional silicon-based semiconductor devices are gradually approaching physical limits in terms of size reduction and performance improvement, which limits their application potential under higher performance requirements and makes the performance of semiconductor devices unable to meet the use requirements. Summary of the invention

[0003] The purpose of this application is to at least solve the problem that the performance of semiconductor devices cannot meet the use requirements. This purpose is achieved through the following technical solutions:

[0004] The first aspect of the present application provides a semiconductor device, comprising:

[0005] substrate;

[0006] A gate, located on one side of the substrate;

[0007] a gate dielectric layer, at least partially located on a side of the gate facing away from the substrate;

[0008] A semiconductor layer, located on a side of the gate dielectric layer away from the substrate, the semiconductor layer comprising a source region, a drain region and a channel region between the source region and the drain region;

[0009] The passivation layer is located on a side of the channel region away from the substrate and is used to achieve heavy doping and interface optimization for the channel region.

[0010] The semiconductor device provided in the present application adopts a back-gate structure, that is, the gate is located between the substrate and the semiconductor layer. This design method has a simple preparation process and does not require the preparation of a dielectric layer with a high dielectric constant on the semiconductor layer. However, the back-gate structure will cause the channel region of the semiconductor layer to be exposed. In the semiconductor device provided in the present application, a passivation layer covering the channel region is provided. On the one hand, the passivation layer can protect the channel region and improve the stability of the semiconductor device; on the other hand, the passivation layer can achieve heavy doping of the channel region and interface optimization, thereby improving the performance of the semiconductor device.

[0011] The second aspect of the present application also provides a method for preparing a semiconductor device, comprising:

[0012] providing a substrate;

[0013] forming a gate on one side of the substrate;

[0014] Forming a gate dielectric layer on a side of the gate facing away from the substrate, wherein the gate dielectric layer is at least partially located on a side of the gate facing away from the substrate;

[0015] forming a semiconductor layer on a side of the gate dielectric layer facing away from the substrate, the semiconductor layer comprising a source region, a drain region, and a channel region located between the source region and the drain region;

[0016] A passivation layer is formed on a side of the channel region away from the substrate, and the passivation layer is used to achieve heavy doping and interface optimization for the channel region.

[0017] The third aspect of the present application also provides an electronic device, which includes at least one semiconductor device provided by the first aspect of the present application, and / or includes at least one semiconductor device prepared by the semiconductor device preparation method provided by the second aspect of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Also, the same reference numerals are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0019] Figure 1 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0020] Figure 2 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present application;

[0021] Figure 3 is a structural schematic diagram of another semiconductor device provided in an embodiment of the present application;

[0022] Figure 4 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present application;

[0023] Figure 5 is a flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0024] Figure 6 is a front view of a substrate in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0025] Figure 7 is a top view of a substrate in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0026] Figure 8 It is a front view of a method for preparing a semiconductor device provided in an embodiment of the present application when preparing a gate;

[0027] Fig. 9 It is a top view of a method for preparing a semiconductor device provided in an embodiment of the present application when preparing a gate;

[0028] Fig.10 It is a front view of a method for preparing a semiconductor device provided in an embodiment of the present application when preparing a gate dielectric layer;

[0029] Fig.11 It is a top view of a method for preparing a semiconductor device provided in an embodiment of the present application when preparing a gate dielectric layer;

[0030] Fig.12 It is a front view of a method for preparing a semiconductor device provided in an embodiment of the present application when preparing a carbon nanotube film;

[0031] Fig.13 It is a top view of a method for preparing a semiconductor device provided in an embodiment of the present application when preparing a carbon nanotube film;

[0032] Fig.14 It is a front view of a method for preparing a semiconductor device provided in an embodiment of the present application when preparing a source electrode and a drain electrode;

[0033] Fig.15 It is a top view of a method for preparing a semiconductor device provided in an embodiment of the present application when preparing a source electrode and a drain electrode;

[0034] Fig.16 It is a front view of patterning a carbon nanotube film in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0035] Fig.17 It is a top view of a carbon nanotube film patterned in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0036] Fig.18 It is a top view of a method for preparing a semiconductor device provided in an embodiment of the present application when preparing a passivation layer;

[0037] Fig.19 It is a front view of another method for preparing a semiconductor device provided in an embodiment of the present application when preparing a barrier material layer and a metal material layer;

[0038] Fig. 20 It is a top view of another method for preparing a semiconductor device provided in an embodiment of the present application when preparing a barrier material layer and a metal material layer;

[0039] Fig.21 It is a front view of the patterning of a barrier material layer and a metal material layer in another method for preparing a semiconductor device provided in an embodiment of the present application.

[0040] The reference numerals are as follows:

[0041] 1. Semiconductor device; 11. Substrate; 12. Gate; 1210. Barrier material layer; 1220. Metal material layer; 121. Barrier layer; 122. Metal layer; 13. Gate dielectric layer; 14. Semiconductor layer; 140. Carbon nanotube film; 141. Source region; 142. Drain region; 143. Channel region; 15. Passivation layer; 16. Source; 17. Drain; 18. Isolation layer. DETAILED DESCRIPTION

[0042] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0043] It should be understood that the terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0044] Although the terms first, second, third, etc. can be used in the text to describe multiple elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can only be used to distinguish an element, component, region, layer or section from another region, layer or section. Unless the context clearly indicates, terms such as "first", "second" and other numerical terms do not imply order or sequence when used in the text. Therefore, the first element, component, region, layer or section discussed below can be referred to as the second element, component, region, layer or section without departing from the teaching of the example embodiments.

[0045] For ease of description, spatial relative terms may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figure, such as "inside", "outside", "inner side", "outer side", "below", "below", "above", "above", etc. Such spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure is turned over, then the elements described as "below other elements or features" or "below other elements or features" will subsequently be oriented as "above other elements or features" or "above other elements or features". Therefore, the example term "below..." can include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or in other directions) and the spatial relative descriptors used in the text are interpreted accordingly.

[0046] Since the mid-20th century, integrated circuit technology has experienced rapid development under the guidance of Moore's Law. However, with the advancement of technology, traditional silicon-based semiconductor devices 1 are gradually approaching physical limits in terms of size reduction and performance improvement, which limits the application potential of semiconductor devices 1 under higher performance requirements.

[0047] In order to overcome these limitations and promote the continuous development of integrated circuit technology, the inventor provides a semiconductor device 1 with better performance. The semiconductor device 1 has better electrical performance and can adapt to usage scenarios with higher performance requirements.

[0048] like Figure 1 As shown, according to an embodiment of the present application, a semiconductor device 1 is proposed, comprising a substrate 11, a gate 12, a gate dielectric layer 13, a semiconductor layer 14 and a passivation layer 15. The gate 12 is located on one side of the substrate 11. The gate dielectric layer 13 is at least partially located on the side of the gate 12 away from the substrate 11. The semiconductor layer 14 is located on the side of the gate dielectric layer 13 away from the substrate 11, and the semiconductor layer 14 includes a source region 141, a drain region 142 and a channel region 143 located between the source region 141 and the drain region 142. The passivation layer 15 is located on the side of the channel region 143 away from the substrate 11, and is used to achieve heavy doping and interface optimization of the channel region 143.

[0049] In the semiconductor device 1 provided in the present application, a back-gate structure is adopted, that is, the gate 12 is located between the substrate 11 and the semiconductor layer 14. This design method has a simple preparation process and there is no need to prepare a dielectric layer with a high dielectric constant on the semiconductor layer 14. However, the back-gate structure will cause the channel region 143 of the semiconductor layer 14 to be exposed. By providing a passivation layer 15 covering the channel region 143, on the one hand, the passivation layer 15 can protect the channel region 143 and improve the stability of the semiconductor device 1; on the other hand, the passivation layer 15 can achieve heavy doping and interface optimization of the channel region 143, thereby improving the performance of the semiconductor device 1.

[0050] In the semiconductor device 1 provided in the present application, a back-gate structure is adopted, thereby eliminating the step of preparing a high dielectric constant dielectric layer on the surface of the semiconductor layer 14 required for a top-gate device or a ring-gate device. Since the material used for part of the semiconductor layer 14 is not conducive to the formation of a high dielectric constant dielectric layer on the surface of the semiconductor layer 14, eliminating the step of forming a high dielectric constant dielectric layer on the surface of the semiconductor layer 14 can improve the preparation yield of the semiconductor device 1.

[0051] Specifically, the substrate 11 can be any substrate material known to those skilled in the art for supporting the semiconductor device 1, such as silicon-on-insulator (SOI), bulk silicon, silicon carbide, germanium, silicon germanium, gallium arsenide or germanium-on-insulator, etc. The substrate 11 can also be a stacked structure of multiple layers of semiconductor materials.

[0052] Specifically, Figure 2 As shown, an isolation layer 18 may be included between the substrate 11 and the gate 12, and the gate 12 may be located on a surface of the isolation layer 18 that is away from the substrate 11. The isolation layer 18 is used to isolate the substrate 11 from the influence of subsequent preparation processes, thereby protecting the substrate 11 and improving the yield of the semiconductor device 1. The orthographic projection of the isolation layer 18 on the substrate 11 may cover the substrate 11 to achieve a good isolation effect.

[0053] Specifically, the material of the isolation layer 18 may include silicon dioxide.

[0054] In a possible implementation, Figure 3 As shown, the gate 12 includes a barrier layer 121 and a metal layer 122 which are sequentially arranged in a direction away from the substrate 11 .

[0055] Specifically, the orthographic projection of the metal layer 122 on the substrate 11 is located within the orthographic projection of the barrier layer 121 on the substrate 11 , so that the barrier layer 121 can achieve a good barrier effect.

[0056] In the above-mentioned embodiment, the barrier layer 121 can be used to reduce the probability of the metal layer 122 being oxidized, thereby improving the yield of the gate 12 .

[0057] Specifically, the barrier layer 121 can be located on the surface of the isolation layer 18 facing away from the substrate 11. The isolation layer 18 can be made of titanium nitride. The barrier layer 121 can prevent the metal layer 122 from reacting with silicon dioxide and being oxidized, thereby improving the yield of the gate 12 and helping to improve the performance of the device.

[0058] Specifically, the material of the metal layer 122 may be tungsten.

[0059] In a feasible implementation, the gate dielectric layer 13 is made of a material with a high dielectric constant (high-K material) to achieve insulation between the gate 12 and the semiconductor layer 14 .

[0060] Specifically, the gate dielectric layer 13 may include multiple configurations, one of which is: Figures 1 to 3 As shown, the orthographic projection of the gate dielectric layer 13 on the substrate 11 covers and exceeds the orthographic projection of the gate 12 on the substrate 11. The gate 12 includes a first surface close to the side of the substrate 11 and a second surface facing away from the substrate 11. The gate 12 also includes a side surface, which is connected between the first surface and the second surface. The gate dielectric layer 13 covers the first surface and covers at least part of the side surface of the gate 12. Part of the gate dielectric layer 13 can also be located on the same surface as the gate 12, that is, when the gate 12 is located on the side of the isolation layer 18 facing away from the substrate 11, the gate dielectric layer 13 extends from the side surface of the gate 12 to the side of the barrier layer 121 facing away from the substrate 11, so that part of the gate dielectric layer 13 is located on the same surface as the gate 12. A step portion is formed between the part of the gate dielectric layer 13 that is located on the same surface as the gate 12 and the part that covers the first surface. In this arrangement, the area of ​​the orthographic projection of the gate 12 on the substrate 11 is small.

[0061] Another way to set it up is: Figure 4 As shown, the orthographic projection of the gate dielectric layer 13 on the substrate 11 coincides with the orthographic projection of the gate 12 on the substrate 11, that is, the gate dielectric layer 13 only covers the first surface. In this arrangement, the orthographic projection area of ​​the gate 12 on the substrate 11 is larger.

[0062] In a possible implementation, Figures 1 to 4 As shown, the semiconductor device 1 also includes a source 16 and a drain 17 , wherein the source 16 is connected to the source region 141 and is located on a surface of the source region 141 that is away from the substrate 11 , and the drain 17 is connected to the drain region 142 and is located on a surface of the drain region 142 that is away from the substrate 11 .

[0063] In the above embodiment, in the semiconductor layer 14 , the source region 141 , the channel region 143 and the drain region 142 may be arranged along a direction parallel to the plane where the substrate 11 is located.

[0064] In the above embodiment, when the gate dielectric layer 13 covers the first surface, covers at least part of the side surface of the gate 12, and part of the gate dielectric layer 13 is located on the same surface as the gate 12, the orthographic projection of the semiconductor layer 14 on the substrate 11 covers and exceeds the orthographic projection of the gate 12 on the substrate 11. Specifically, the semiconductor layer 14 is partially located on the side surface of the gate dielectric layer 13 and the first surface that is away from the substrate 11, partially located on the side surface of the gate dielectric layer 13 and the gate 12 that are located on the same surface that is away from the substrate 11, and partially located on the side surface of the gate dielectric layer 13 that is in contact with the side surface that is away from the gate 12. The channel region 143 is located on the side of the gate dielectric layer 13 that is away from the gate 12 and the substrate 11, and the source region 141 and the drain region 142 are located on both sides of the channel region 143 and cover the step portion.

[0065] In the above embodiment, when the gate dielectric layer 13 is only located on the surface of the gate electrode 12 facing away from the substrate 11, the semiconductor layer 14 is located on the surface of the gate dielectric layer 13 facing away from the substrate 11, and the substrate 11, the gate electrode 12, the gate dielectric layer 13 and the semiconductor layer 14 are stacked along the thickness direction of the substrate 11. The channel region 143 is located on the side of the gate dielectric layer 13 facing away from the gate electrode 12 and the substrate 11. The source electrode 16 and the drain electrode 17 are located on the surface of the semiconductor layer 14 facing away from the substrate 11 and are in contact with the semiconductor layer 14.

[0066] In a feasible implementation, the passivation layer 15 is located on the side of the channel region 143 away from the substrate 11, and is used to heavily dope the channel region 143. The orthographic projection of the passivation layer 15 on the substrate 11 can cover the orthographic projection of the channel region 143 on the substrate 11, so that the surface of the side of the channel region 143 away from the substrate 11 can be well protected, and the channel region 143 can be heavily doped as a whole, so as to further improve the yield of the semiconductor device 1.

[0067] In a feasible implementation manner, the material of the semiconductor layer 14 includes carbon nanotubes.

[0068] Carbon nanotubes (CNTs) have great potential for application in the field of nanoelectronics due to their unique electronic, optical and mechanical properties. CNTs have excellent electrical and optical properties such as high electron / hole mobility, direct band gap energy band structure and high infrared absorption coefficient.

[0069] Specifically, since there are no dangling bonds and lack of nucleation points on the surface of the carbon nanotube material, it is not conducive to directly preparing a dielectric layer with a high dielectric constant. The semiconductor device 1 provided in the present application adopts a back-gate structure, so there is no need to prepare a dielectric layer with a high dielectric constant on the surface of the semiconductor layer 14, thereby improving the preparation yield of the semiconductor device 1.

[0070] In a feasible implementation manner, the material of the passivation layer 15 includes yttrium oxide.

[0071] In the above embodiment, yttrium oxide is a wide bandgap semiconductor, and metallic yttrium has good wettability with carbon nanotubes. It has significant advantages in growing on the surface of carbon nanotubes (CNTs), and can grow into a film uniformly on the surface of carbon nanotubes without forming a clustered structure, thereby simplifying the preparation process and improving the preparation yield.

[0072] Before preparing the passivation layer 15, the channel region 143 is in contact with the air, which will not only cause a large hysteresis problem, but also may damage the channel region 143 due to impurities and moisture in the air, resulting in poor stability of the semiconductor device 1. By setting the passivation layer 15, the channel region 143 can be effectively protected to prevent it from being adversely affected by the external environment. At the same time, since yttrium oxide has good wettability with carbon nanotubes, the interface between the channel layer and the passivation layer 15 can be optimized, thereby reducing the subthreshold swing and optimizing the threshold voltage, thereby improving the performance of the semiconductor device 1. Among them, the optimized threshold voltage means that the semiconductor device 1 can operate at a lower voltage, thereby reducing power consumption, and the smaller subthreshold swing can increase the switching speed and sensitivity of the semiconductor device 1, so that the semiconductor device 1 can be used in high-speed electronic devices.

[0073] In the above embodiment, the channel layer adopts a carbon nanotube material with a network structure, and the material of the passivation layer 15 includes yttrium oxide. During the preparation process of the passivation layer 15, metal yttrium is evaporated by electron beam, and then annealed and passivated in an air atmosphere to form an yttrium oxide film. During this process, metal yttrium reacts with oxygen atoms in oxygen to form yttrium oxide. After the metal yttrium is oxidized, there are incompletely oxidized parts. After yttrium oxide passivation, more trap states will be introduced into the carbon nanotube channel region 143. The increase in trap states will cause more holes to jump to the valence band, thereby increasing the on-state current, that is, forming P-type heavy doping in the channel region 143, thereby improving the electrical performance of the semiconductor device 1.

[0074] Among them, annealing is a heat treatment process that can make the crystal structure of the material more stable, reduce defects, and thus improve the performance of the device.

[0075] During the preparation process, the source electrode 16 and the drain electrode 17 may be prepared first, and then the passivation layer 15 may be prepared. The passivation layer 15 may include an annealing step during the preparation process, and the contact between the source electrode 16 and the drain electrode 17 and the semiconductor layer 14 may be optimized during the annealing step. This optimization may reduce the contact resistance, thereby increasing the on-state current of the semiconductor device 1. The on-state current refers to the current allowed to pass through when the semiconductor device 1 is in the on state, which is an important parameter for measuring the performance of the semiconductor device 1. The higher the on-state current, the stronger the current carrying capacity of the device in the on state, so that the semiconductor device 1 has a high current output, that is, the electrical performance of the semiconductor device 1 is further improved.

[0076] The passivation layer 15 may also be prepared by other preparation methods, which are not particularly limited in the present application.

[0077] In a feasible implementation manner, the passivation layer 15 is a light-transmitting film layer.

[0078] In the above embodiment, the semiconductor device 1 may be a photosensitive device, which can convert optical signals into electrical signals and is widely used in the fields of image sensors, optical fiber communications, etc. Specifically, the semiconductor device 1 may be a phototransistor. In this case, the passivation layer 15 is required to not only protect the device and improve the electrical characteristics of the semiconductor device 1, but also maintain light transmittance to ensure the photosensitivity of the semiconductor device 1.

[0079] In the above embodiment, the passivation layer 15 is a light-transmitting film layer to avoid adverse effects on the photosensitivity of the channel region 143 , thereby improving the optical performance of the semiconductor device 1 .

[0080] In a feasible implementation manner, the thickness of the passivation layer 15 is in the range of 5 nm to 10 nm.

[0081] In the above embodiment, the semiconductor device 1 may be a photosensitive device, specifically a phototransistor. At this time, the thickness of the passivation layer 15 is set to be thinner to improve the transmittance of the passivation layer 15, thereby optimizing the optical properties of the semiconductor device 1, for example, the sensing speed of the photoelectric sensor can be improved, thereby improving the reaction speed of the semiconductor device 1.

[0082] Specifically, the thickness of the passivation layer 15 along the thickness direction of the substrate 11 is smaller than the thickness of the source electrode 16 and the drain electrode 17 along the thickness direction of the substrate 11 .

[0083] Specifically, the thickness of the passivation layer 15 may be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, etc.

[0084] It can be understood that when the semiconductor device 1 is a non-photoelectric device, the transmittance and thickness of the passivation layer 15 are not particularly limited. The transmittance of the passivation layer 15 can be higher or lower, and the thickness can be lower than the source 16 and the drain 17, or exceed the source 16 and the drain 17.

[0085] The present application also provides a method for preparing a semiconductor device 1, such as Figure 5 As shown, including:

[0086] S200, such as Figure 6 and Figure 7 As shown, a substrate 11 is provided.

[0087] S400, such as Figure 8 and Fig. 9 As shown, a gate 12 is formed on one side of a substrate 11 .

[0088] S600, such as Fig.10 and Fig.11 As shown, a gate dielectric layer 13 is formed on the side of the gate 12 facing away from the substrate 11 , and the gate dielectric layer 13 is at least partially located on the side of the gate 12 facing away from the substrate 11 .

[0089] S800, such as Figures 12 to 18 As shown, a semiconductor layer 14 is formed on the side of the gate dielectric layer 13 facing away from the substrate 11 , and the semiconductor layer 14 includes a source region 141 , a drain region 142 , and a channel region 143 located between the source region 141 and the drain region 142 .

[0090] S1000 , forming a passivation layer 15 on a side of the channel region 143 facing away from the substrate 11 , wherein the passivation layer 15 is used to achieve heavy doping and interface optimization for the channel region 143 .

[0091] In the above-mentioned preparation method, the semiconductor device 1 provided in the present application adopts a back-gate structure, that is, the gate 12 is located between the substrate 11 and the semiconductor layer 14. This design method has a simple preparation process and does not require the preparation of a dielectric layer with a high dielectric constant on the semiconductor layer 14. However, the back-gate structure will cause the channel region 143 of the semiconductor layer 14 to be exposed. By setting a passivation layer 15 covering the channel region 143, on the one hand, the passivation layer 15 can protect the channel region 143 and improve the stability of the semiconductor device 1; on the other hand, the passivation layer 15 can achieve heavy doping and interface optimization of the channel region 143, thereby improving the performance of the semiconductor device 1.

[0092] In the above preparation method, before preparing the gate 12, an isolation layer 18 is formed on the surface of the substrate 11 to reduce the adverse effects of subsequent film layers on the substrate 11, such as preventing impurity diffusion, reducing mechanical stress and chemical corrosion, etc.

[0093] Specifically, the material of the isolation layer 18 may include silicon dioxide, and the isolation layer 18 may be formed by a deposition process.

[0094] When preparing the gate 12, as Fig.19 and Fig. 20 As shown, a barrier material layer 1210 and a metal material layer 1220 may be sequentially deposited and patterned to form a barrier layer 121 and a metal layer 122, as shown in FIG. Fig.21 As shown, a gate 12 is formed.

[0095] Specifically, the material of the barrier layer 121 may include titanium nitride. Titanium nitride (TiN) is a material with good electrical conductivity and chemical stability, which can effectively prevent the mutual diffusion between the metal layer 122 and the substrate 11 and protect the electrical characteristics of the semiconductor device 1. The material of the metal layer 122 may include tungsten (W), which has a lower resistivity and a higher melting point and is suitable as a conductive material for the gate 12.

[0096] In the above preparation method, Fig.10 and Fig.11 As shown, when forming the gate dielectric layer 13, a material with a high dielectric constant can be deposited on the entire surface, so that a portion of the gate dielectric layer 13 can be located on the side surface of the gate 12 facing away from the substrate 11, a portion of the gate dielectric layer 13 can cover the side surface of the gate 12, and a portion of the gate dielectric layer 13 can be in contact with the side surface of the isolation layer 18 facing away from the substrate 11.

[0097] In the above preparation method, Figures 12 to 18 As shown, a carbon nanotube film 140 having a network structure is prepared and patterned to form a semiconductor layer 14, wherein the portion of the semiconductor layer 14 located on the side of the gate 12 away from the substrate 11 is a channel region 143, and the two sides of the channel region 143 are respectively a source region 141 and a drain region 142. Specifically, a carbon nanotube dispersion is used to form a carbon nanotube layer having a network structure, thereby forming the semiconductor layer 14.

[0098] In the above preparation method, before forming the passivation layer 15, the following steps are further included:

[0099] like Fig.14 and Fig.15 As shown, a source electrode 16 is formed on the side of the carbon nanotube film 140 used as the source region 141 away from the substrate 11 , and a drain electrode 17 is formed on the side of the carbon nanotube film 140 used as the drain region 142 away from the substrate 11 .

[0100] Specifically include: Fig.16 and Fig.17As shown, a metal material layer is deposited on the side of the carbon nanotube film 140 away from the substrate and patterned to form a source electrode 16 and a drain electrode 17. Then, the area not covered by the source electrode 16 in the area used as the source region 141 in the carbon nanotube film 140 can be removed, and the area not covered by the drain electrode 17 in the area used as the drain region 142 in the carbon nanotube film 140 can be removed. At the same time, the area used as the channel region 143 in the carbon nanotube film 140 can be etched synchronously, and only a part of the area between the source electrode 16 and the drain electrode 17 is retained. The material of the source electrode 16 and the drain electrode 17 is a stack of metal titanium and metal palladium, wherein the metal titanium layer is relatively thin and mainly plays an adhesion role, and the work function of the metal palladium matches the work function of the carbon nanotube film 140, which is conducive to the formation of a P-type transistor.

[0101] The above preparation method further comprises: Figure 1 and Fig.18 As shown, a passivation layer 15 is formed on the side of the channel region 143 facing away from the substrate 11. The passivation layer 15 can be formed by depositing yttrium oxide.

[0102] Specifically, it includes: using electron beam to evaporate metal yttrium to form a metal yttrium film layer, and then using a first annealing process to anneal the metal yttrium film layer in an air atmosphere to form an yttrium oxide film layer, thereby forming the passivation layer 15.

[0103] In the above embodiment, yttrium oxide is a wide bandgap semiconductor that can grow uniformly on the surface of carbon nanotubes to form a film without forming a clustered structure, thereby facilitating preparation and achieving a good yield. Before preparing the passivation layer 15, the channel layer is in contact with air. After preparing the passivation layer 15, since yttrium oxide has good wettability with carbon nanotubes, the interface between the channel layer and the passivation layer 15 can be optimized, thereby reducing the subthreshold swing and optimizing the threshold voltage, thereby improving the performance of the semiconductor device 1.

[0104] In the above embodiment, the channel layer is made of a carbon nanotube material with a mesh structure, and the material of the passivation layer 15 includes yttrium oxide. During the preparation process of the passivation layer 15, metal yttrium is evaporated by electron beam, and then annealed in an air atmosphere to form an yttrium oxide film. After the metal yttrium is oxidized, there are incompletely oxidized parts. After the yttrium oxide is passivated, more trap states will be introduced into the carbon nanotube channel region 143. The increase in trap states will cause more holes to jump to the valence band, thereby increasing the on-state current, that is, forming a P-type heavy doping on the channel region 143. In addition, the first annealing process can optimize the contact between the source 16 and the drain 17 and the semiconductor layer 14. This optimization can reduce the contact resistance, thereby increasing the on-state current of the semiconductor device 1.

[0105] The passivation layer 15 may also be prepared by other preparation methods, which are not particularly limited in the present application.

[0106] Specifically, the temperature for annealing the metal film layer may be 250° C. and the annealing time may be 30 minutes. The temperature condition of this step will not affect the performance of other film layers in the semiconductor device 1, and specifically, meets the temperature limit of the BEOL process in 3DIC.

[0107] The above preparation method also includes:

[0108] The semiconductor device 1 is annealed by a second annealing process in a vacuum or nitrogen environment, and the temperature of the second annealing process is 300°C. The temperature condition of this step will not affect the performance of other film layers in the semiconductor device 1. Specifically, it meets the temperature restrictions of the BEOL process in 3DIC. The BEOL process temperature (Back-End-of-Line Temperature) is the back-end temperature, which refers to the temperature of the circuit structure during the circuit connection and wiring stages of the metal layer 122, contact layer, etc. during the manufacturing process of the semiconductor device 1. The BEOL process temperature is generally between tens of degrees Celsius and hundreds of degrees Celsius. The temperatures of the first annealing process and the second annealing process are both less than or equal to 300 degrees Celsius, which can meet the temperature restrictions of the BEOL process, so that the preparation method of the semiconductor device 1 provided in the present application can be fully compatible with the existing mainstream preparation method of the semiconductor device 1.

[0109] Specifically, the second annealing process can further optimize the source-drain contact, thereby further improving the on-state current. In addition, the vacuum annealing can reduce defects in the carbon nanotubes, thereby further improving the performance of the semiconductor device 1.

[0110] Specifically, in the preparation method provided by the present application, the passivation layer 15 can be a light-transmitting film layer, and the thickness of the passivation layer 15 can be controlled to be in the range of 5nm-10nm to improve the light transmittance of the passivation layer 15, thereby optimizing the optical properties of the semiconductor device 1, so as to achieve the preparation of the photosensitive semiconductor device 1. The optical and electrical properties of the semiconductor device 1 prepared by the preparation method of the semiconductor device 1 provided by the present application are improved, and the process flow is simple, which can reduce the preparation cost.

[0111] The preparation method of the semiconductor device 1 provided in the present application is fully compatible with the mainstream silicon-based CMOS process, and the preparation method is simple. The simple preparation method simultaneously improves the electrical and photoelectric properties of the semiconductor device 1. After the photoelectric response of the photosensitive semiconductor device 1 is improved, the application field is more extensive.

[0112] The present application also provides an electronic device, which includes at least one semiconductor device 1 provided in any of the above embodiments of the present application, and / or includes at least one semiconductor device 1 prepared by a preparation method of any of the semiconductor devices 1 provided in the above embodiments of the present application.

[0113] In the semiconductor device 1 in the electronic device, a back-gate structure is adopted, that is, the gate 12 is located between the substrate 11 and the semiconductor layer 14. This design method has a simple preparation process and does not require a dielectric layer with a high dielectric constant to be prepared on the semiconductor layer 14. However, the back-gate structure will cause the channel region 143 of the semiconductor layer 14 to be exposed. By providing a passivation layer 15 covering the channel region 143, on the one hand, the passivation layer 15 can protect the channel region 143 and improve the stability of the semiconductor device 1; on the other hand, the passivation layer 15 can achieve heavy doping of the channel region 143, thereby improving the performance of the semiconductor device 1, thereby improving the performance of the electronic device and improving the user experience.

[0114] When the electronic device includes a photosensitive semiconductor device 1, the passivation layer 15 needs to use a light-transmitting film layer. After the performance of the semiconductor device 1 is improved by the passivation layer 15, the speed of the photoelectric response is improved, thereby improving the photoelectric characteristics of the semiconductor device 1. Therefore, the speed of the photoelectric response of the electronic device is improved, thereby achieving a better user experience.

[0115] The above are only preferred specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A gate, located on one side of the substrate; a gate dielectric layer, at least partially located on a side of the gate facing away from the substrate; A semiconductor layer, located on a side of the gate dielectric layer away from the substrate, the semiconductor layer comprising a source region, a drain region and a channel region between the source region and the drain region; The passivation layer is located on a side of the channel region away from the substrate and is used to achieve heavy doping and interface optimization for the channel region.

2. The semiconductor device according to claim 1, wherein: The material of the semiconductor layer includes carbon nanotubes.

3. The semiconductor device according to claim 1, wherein: The material of the passivation layer includes yttrium oxide.

4. The semiconductor device according to claim 1, wherein: The passivation layer is a light-transmitting film layer.

5. The semiconductor device according to claim 1, wherein: The thickness of the passivation layer is in the range of 5nm-10nm.

6. The semiconductor device according to claim 1, wherein: The gate includes a barrier layer and a metal layer which are sequentially arranged in a direction away from the substrate.

7. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; forming a gate on one side of the substrate; Forming a gate dielectric layer on a side of the gate facing away from the substrate, wherein the gate dielectric layer is at least partially located on a side of the gate facing away from the substrate; forming a semiconductor layer on a side of the gate dielectric layer facing away from the substrate, the semiconductor layer comprising a source region, a drain region, and a channel region located between the source region and the drain region; A passivation layer is formed on a side of the channel region away from the substrate, and the passivation layer is used to achieve heavy doping and interface optimization for the channel region.

8. The method for preparing a semiconductor device according to claim 7, characterized in that: Before forming the passivation layer, the method further comprises: A source electrode is formed on a side of the source region facing away from the substrate, and a drain electrode is formed on a side of the drain region facing away from the substrate.

9. The method for preparing a semiconductor device according to claim 7, characterized in that: The step of forming a passivation layer on a side of the channel region away from the substrate, wherein the passivation layer is used to implement heavy doping and interface optimization for the channel region comprises: The metal yttrium is evaporated by electron beam to form a metal yttrium film layer, and then the metal yttrium film layer is annealed by a first annealing process in an air atmosphere to form an yttrium oxide film layer, thereby forming a passivation layer.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: The first annealing process has a temperature of 250° C. and a duration of 30 minutes.

11. The method for preparing a semiconductor device according to claim 9, characterized in that: Also includes: The semiconductor device is annealed by a second annealing process in a vacuum or nitrogen environment, and the temperature of the second annealing process is 300°C.

12. An electronic device, characterized in that: The electronic device comprises at least one semiconductor device according to any one of claims 1 to 6, and / or comprises at least one semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 7 to 11.

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