Density driven variable rate coloring

Abstract

Aspects provided herein relate to methods and apparatus for graphics processing, including devices, such as a GPU or CPU. The apparatus can obtain visibility information for a set of primitives in at least one frame associated with the graphics processing, where the at least one frame includes a plurality of bins such that at least one bin of the plurality of bins includes at least one primitive of the set of primitives. The apparatus can also configure a density map based on the visibility information for the set of primitives, wherein the density map includes density data associated with an amount of the set of primitives in each bin of the plurality of bins. Further, the apparatus can map the density data for each bin of the plurality of bins to a shading rate for each bin of the plurality of bins.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. patent application serial number 17 / 816,362, filed on July 29, 2022, entitled “DENSITY DRIVEN VARIABLE RATESHADING,” which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to processing systems and, more particularly, to one or more techniques for graphics processing. Background Art

[0004] Computing devices typically perform graphics and / or display processing (e.g., using a graphics processing unit (GPU), a central processing unit (CPU), a display processor, etc.) to render and display visual content. Such computing devices may include, for example, computer workstations, mobile phones (such as smart phones), embedded systems, personal computers, tablet computers, and video game consoles. The GPU is configured to execute a graphics processing pipeline that includes one or more processing stages that operate together to execute graphics processing commands and output frames. The central processing unit (CPU) can control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern CPUs are typically capable of executing multiple applications concurrently, and each application may need to utilize the GPU during execution. The display processor is configured to convert digital information received from the CPU into analog values, and may issue commands to the display panel to display visual content. A device that provides content for visual presentation on a display may utilize a GPU and / or a display processor.

[0005] The GPU of a device may be configured to perform processes in a graphics processing pipeline. Additionally, a display processor or display processing unit (DPU) may be configured to perform processes for display processing. However, with the advent of wireless communications and smaller handheld devices, the need for improved graphics or display processing continues to increase. Summary of the invention

[0006] The following presents a simplified summary of one or more aspects in order to provide a basic understanding of these aspects. This summary is not an extensive overview of all contemplated aspects, and is neither intended to identify key or important elements of all aspects, nor to describe the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to a more detailed description presented later.

[0007] In one aspect of the present disclosure, a method, a computer-readable medium, and a device are provided. The device may be a graphics processing unit (GPU), a central processing unit (CPU), or any device that can perform graphics processing. The device may obtain an indication of a primitive set in at least one frame from at least one component in a graphics processing unit (GPU) pipeline, wherein the indication is obtained before obtaining visibility information for the primitive set. The device may also obtain visibility information for a primitive set in at least one frame associated with the graphics processing, wherein the at least one frame includes a plurality of bins, such that at least one bin of the plurality of bins includes at least one primitive in the primitive set. In addition, the device may configure a density map based on the visibility information for the primitive set, wherein the density map includes density data associated with the amount of the primitive set in each bin of the plurality of bins. The device may also calculate a ratio or percentage of the primitive set in each bin of the plurality of bins based on the amount of the primitive set in each bin of the plurality of bins. In addition, the device may map the density data for each bin of the plurality of bins to a shading rate for each bin of the plurality of bins. The apparatus may also send an indication of a shading rate for each of the plurality of bins, wherein the indication is sent after the density data for each of the plurality of bins is mapped to the shading rate for each of the plurality of bins.

[0008] The details of one or more examples of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will become apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating an example content generation system.

[0010] Figure 2 An example graphics processing unit (GPU) is illustrated.

[0011] Figure 3 Example images or surfaces are illustrated in accordance with one or more techniques of this disclosure.

[0012] Figure 4 is a graph illustrating an example of GPU rendering performance.

[0013] Figure 5 is a diagram illustrating an example software flow for graphics processing.

[0014] Figure 6 is a diagram illustrating an example density map for graphics processing.

[0015] Figure 7 is a diagram illustrating an example density map for graphics processing.

[0016] Figure 8 is a communication flow diagram illustrating example communications between GPU components.

[0017] Fig. 9 is a flow chart of an example method of graphics processing.

[0018] Fig.10 is a flow chart of an example method of graphics processing. DETAILED DESCRIPTION

[0019] Variable rate shading (VRS) can be applied using several different methods, including setting different shading rates via a predefined buffer of quality levels mapped to tiles within a frame buffer, which can be referred to as an image VRS (i.e., each tile in the frame buffer can have its own shading rate). One problem when applying any VRS without explicit dictation from the application is to automatically select quality levels in a way that maximizes the amount of work saved while minimizing the amount of perceptible image degradation in the final result. In theory, this quality degradation is most noticeable in screen areas that the end user is focused on, such as character models or game objects. These screen areas may be characterized by high geometric complexity, such as including a large number of visible primitives, sharp edges, and / or abrupt transitions in color or depth. Because the user is likely to focus on these areas with high geometric complexity, reducing the shading rate is more likely to produce a noticeable quality loss when compared to areas with less geometric complexity. Some methods that attempt to use historical data to estimate such areas to generate quality levels (i.e., methods that infer where the area of ​​interest for the current frame is located based on the location in the previous frame) may be inherently reactive and may sacrifice quality / performance benefits if the geometric complexity changes from frame to frame. In some aspects, areas with high geometric complexity and low geometric complexity can be identified in the visibility process. In addition, there are methods for dynamically updating the VRS state before rendering the same workload. Various aspects of the present disclosure can apply different shading rates to different areas of a frame or frame buffer based on the impact on visual fidelity. For example, various aspects of the present disclosure can apply one shading rate (e.g., a more conservative or increased shading rate) to an area of ​​the frame buffer that has a higher impact on visual fidelity, and another shading rate (e.g., a more aggressive or reduced shading rate) to an area with less detail. Additionally, in some examples, various aspects of the present disclosure can automatically apply these different shading rates to different areas of the frame. Various aspects provided herein can also configure a density map based on visibility information for primitives, which can include density data associated with the amount of primitives in each of the bins / areas. In addition, aspects provided herein can map density data for multiple bins / regions in a frame to different shading rates for the bins / regions. In this way, aspects provided herein can optimize the shading rates used on different parts of a frame or scene in graphics processing. This in turn can help optimize the power and / or performance used to shade a frame or scene at the GPU.

[0020] Various aspects of the system, device, computer program product, and method will be described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be interpreted as being limited to any specific structure or function presented throughout the present disclosure. On the contrary, these aspects are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Based on the teachings of this article, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the system, device, computer program product, and method disclosed herein, whether it is implemented independently of other aspects of the present disclosure or implemented in combination with other aspects of the present disclosure. For example, any number of aspects set forth herein may be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such devices or methods practiced using other structures, functionality, or structures and functionality in addition to or different from the various aspects of the disclosure set forth herein. Any aspect disclosed herein may be embodied by one or more elements of the claims.

[0021] Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of the present disclosure. Although some potential benefits and advantages of various aspects of the present disclosure are mentioned, the scope of the present disclosure is not intended to be limited to specific benefits, uses or objectives. On the contrary, various aspects of the present disclosure are intended to be widely applicable to different wireless technologies, system configurations, networks and transmission protocols, some of which are illustrated by way of example in the drawings and the description below. The specific embodiments and drawings merely illustrate the present disclosure rather than limit it, and the scope of the present disclosure is defined by the attached claims and their equivalent technical solutions.

[0022] Several aspects are presented with reference to various devices and methods. These devices and methods are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0023] For example, an element or any part of an element or any combination of elements may be implemented as a "processing system" including one or more processors (which may also be referred to as a processing unit). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems on chip (SOCs), baseband processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic devices, discrete hardware circuits, and other suitable hardware configured to perform the various functions described in this disclosure. One or more processors in a processing system may execute software. Software may be broadly interpreted as meaning instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, processes, functions, etc., whether expressed in software, firmware, middleware, microcode, hardware description languages, or other terms. The term "application" may refer to software. As described herein, one or more technologies may refer to an application, i.e., software, configured to perform one or more functions. In such examples, the application may be stored in a memory (e.g., an on-chip memory of a processor, a system memory, or any other memory). The hardware described herein (such as a processor) may be configured to execute an application. For example, an application may be described as including a code that, when executed by hardware, causes the hardware to perform one or more technologies described herein. As an example, the hardware may access the code from the memory and execute the code accessed from the memory to perform one or more technologies described herein. In some examples, components are identified in the present disclosure. In such examples, the components may be hardware, software, or a combination thereof. Each component may be a separate component or a subcomponent of a single component.

[0024] Therefore, in one or more examples described herein, the functions described can be implemented in hardware, software, or any combination thereof. If implemented with software, the functions can be stored or encoded on a computer-readable medium as one or more instructions or codes. Computer-readable media include computer storage media. Storage media can be any available media that can be accessed by a computer. As an example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), optical disk storage device, magnetic disk storage device, other magnetic storage devices, a combination of computer-readable media of the above type, or any other medium that can be used to store instructions or data structure forms that can be accessed by a computer.

[0025] In summary, this disclosure describes techniques for having a graphics processing pipeline in a single device or multiple devices to improve rendering of graphics content and / or reduce load on a processing unit (i.e., any processing unit, such as a GPU, configured to perform one or more of the techniques described herein). For example, this disclosure describes techniques for performing graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout this disclosure.

[0026] As used herein, instances of the term "content" may refer to "graphic content," "images," and vice versa. This is true regardless of whether these terms are used as adjectives, nouns, or other parts of speech. In some examples, as used herein, the term "graphic content" may refer to content produced by one or more processes of a graphics processing pipeline. In some examples, as used herein, the term "graphic content" may refer to content produced by a processing unit configured to perform graphics processing. In some examples, as used herein, the term "graphic content" may refer to content produced by a graphics processing unit.

[0027] In some examples, as used herein, the term "display content" may refer to content generated by a processing unit configured to perform display processing. In some examples, as used herein, the term "display content" may refer to content generated by a display processing unit. Graphics content may be processed to become display content. For example, a graphics processing unit may output graphics content (such as a frame) to a buffer (which may be referred to as a frame buffer). The display processing unit may read graphics content (such as one or more frames) from the buffer and perform one or more display processing techniques thereon to generate display content. For example, the display processing unit may be configured to perform synthesis on one or more rendering layers to generate a frame. For another example, the display processing unit may be configured to synthesize, mix or otherwise combine two or more layers into a single frame. The display processing unit may be configured to perform scaling on the frame, such as zooming in or out. In some examples, a frame may refer to a layer. In other examples, a frame may refer to two or more layers that have been mixed together to form the frame, that is, the frame includes two or more layers, and the frame including two or more layers may be subsequently mixed.

[0028] Figure 11 is a block diagram illustrating an example content generation system 100 configured to implement one or more techniques of the present disclosure. The content generation system 100 includes a device 104. The device 104 may include one or more components or circuits for performing various functions described herein. In some examples, one or more components of the device 104 may be components of a SOC. The device 104 may include one or more components configured to perform one or more techniques of the present disclosure. In the example shown, the device 104 may include a processing unit 120, a content encoder / decoder 122, and a system memory 124. In some aspects, the device 104 may include several components, such as a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. References to the display 131 may refer to one or more displays 131. For example, the display 131 may include a single display or multiple displays. The display 131 may include a first display and a second display. The first display may be a left-eye display, and the second display may be a right-eye display. In some examples, the first display and the second display may receive different frames for presentation thereon. In other examples, the first display and the second display may receive the same frame for presentation thereon. In further examples, the results of the graphics processing may not be displayed on the device, for example, the first display and the second display may not receive any frames for presentation thereon. Instead, the frames or graphics processing results may be passed to another device. In some aspects, this may be referred to as split rendering.

[0029] Processing unit 120 may include internal memory 121. Processing unit 120 may be configured to perform graphics processing, such as in graphics processing pipeline 107. Content encoder / decoder 122 may include internal memory 123. In some examples, device 104 may include a display processor (such as display processor 127) to perform one or more display processing techniques on one or more frames generated by processing unit 120 before being presented by one or more displays 131. Display processor 127 may be configured to perform display processing. For example, display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by processing unit 120. One or more displays 131 may be configured to display or otherwise present frames processed by display processor 127. In some examples, one or more displays 131 may include one or more of the following: a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head mounted display, or any other type of display device.

[0030] Memory external to the processing unit 120 and the content encoder / decoder 122, such as the system memory 124, may be accessible to the processing unit 120 and the content encoder / decoder 122. For example, the processing unit 120 and the content encoder / decoder 122 may be configured to read from and / or write to the external memory, such as the system memory 124. The processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to the system memory 124 via a bus. In some examples, the processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to each other via the bus or a different connection.

[0031] The content encoder / decoder 122 may be configured to receive graphics content from any source, such as the system memory 124 and / or the communication interface 126. The system memory 124 may be configured to store the received encoded or decoded graphics content. The content encoder / decoder 122 may be configured to receive the encoded or decoded graphics content in the form of encoded pixel data, for example, from the system memory 124 and / or the communication interface 126. The content encoder / decoder 122 may be configured to encode or decode any graphics content.

[0032] Internal memory 121 or system memory 124 may include one or more volatile or non-volatile memories or storage devices. In some examples, internal memory 121 or system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic data media, or optical storage media, or any other type of memory.

[0033] According to some examples, the internal memory 121 or the system memory 124 may be a non-transitory storage medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or propagation signal. However, the term "non-transitory" should not be interpreted to mean that the internal memory 121 or the system memory 124 is non-removable or that its contents are static. For example, the system memory 124 may be removed from the device 104 and moved to another device. For another example, the system memory 124 may not be removable from the device 104.

[0034] The processing unit 120 may be a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or any other processing unit that may be configured to perform graphics processing. In some examples, the processing unit 120 may be integrated into the motherboard of the device 104. In some examples, the processing unit 120 may be present on a graphics card installed in a port in the motherboard of the device 104, or may be otherwise incorporated into a peripheral device configured to interoperate with the device 104. The processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the processing unit 120 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 121), and may use one or more processors to execute instructions in hardware to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) may be considered to be one or more processors.

[0035] The content encoder / decoder 122 may be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 may be integrated into the mainboard of the device 104. The content encoder / decoder 122 may include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the content encoder / decoder 122 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 123), and may use one or more processors to execute instructions in hardware to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) may be considered to be one or more processors.

[0036] In some aspects, the content generation system 100 may include a communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any receiving functions described herein with respect to the device 104. Additionally, the receiver 128 may be configured to receive information from another device, such as eye or head position information, rendering commands, or positioning information. The transmitter 130 may be configured to perform any sending functions described herein with respect to the device 104. For example, the transmitter 130 may be configured to send information to another device, which may include a request for content. The receiver 128 and the transmitter 130 may be combined into a transceiver 132. In such examples, the transceiver 132 may be configured to perform any receiving functions and / or sending functions described herein with respect to the device 104.

[0037] Reference again Figure 1 In some aspects, the processing unit 120 may include a density component 198 configured to obtain an indication of a primitive set in at least one frame from at least one component in a graphics processing unit (GPU) pipeline, wherein the indication is obtained before obtaining visibility information for the primitive set. The density component 198 may also be configured to obtain visibility information for the primitive set in at least one frame associated with the graphics processing, wherein the at least one frame includes a plurality of bins, such that at least one bin in the plurality of bins includes at least one primitive in the primitive set. The density component 198 may also be configured to configure a density map based on the visibility information for the primitive set, wherein the density map includes density data associated with an amount of the primitive set in each of the plurality of bins. The density component 198 may also be configured to calculate a ratio or percentage of the primitive set in each of the plurality of bins based on the amount of the primitive set in each of the plurality of bins. The density component 198 may also be configured to map the density data for each of the plurality of bins to a shading rate for each of the plurality of bins. The density component 198 may also be configured to send an indication of a shading rate for each of the plurality of bins, wherein the indication is sent after the density data for each of the plurality of bins is mapped to the shading rate for each of the plurality of bins. Although the following description may focus on graphics processing, the concepts described herein may be applicable to other similar processing technologies.

[0038] As described herein, a device such as device 104 may refer to any device, apparatus or system configured to perform one or more technologies described herein. For example, a device may be a server, a base station, a user equipment, a client device, a station, an access point, a computer (e.g., a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation or a mainframe computer), a final product, an apparatus, a phone, a smart phone, a server, a video game platform or console, a handheld device (e.g., a portable video game device or a personal digital assistant (PDA)), a wearable computing device (e.g., a smart watch, an augmented reality device or a virtual reality device), a non-wearable device, a display or display device, a television, a television set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, a vehicle-mounted computer, any mobile device, any device configured to generate graphics content, or any device configured to perform one or more technologies described herein. The process herein may be described as being performed by a specific component (e.g., a GPU), but in further embodiments, other components (e.g., a CPU) consistent with the disclosed embodiments may be used to perform.

[0039] The GPU may process multiple types of data or data packets in the GPU pipeline. For example, in some aspects, the GPU may process two types of data or data packets, such as context register packets and draw call data. The context register packet may be a collection of global state information, such as information about global registers, shaders, or constant data, which may adjust how the graphics context is to be processed. For example, the context register packet may include information about the color format. In some aspects of the context register packet, there may be a bit indicating which workload belongs to the context register. In addition, there may be multiple functions or programs running simultaneously and / or in parallel. For example, a function or program may describe an operation, such as a color mode or color format. Therefore, the context register may define multiple states of the GPU.

[0040] The context state may be used to determine how a single processing unit (e.g., a vertex fetcher (VFD), a vertex shader (VS), a shader processor, or a geometry processor) operates and / or in which mode the processing unit operates. To this end, the GPU may use context registers and programming data. In some aspects, the GPU may generate workloads (e.g., vertex or pixel workloads) in a pipeline based on context register definitions of a mode or state. Certain processing units (e.g., VFDs) may use these states to determine certain functions, such as how to assemble vertices. Since these modes or states may change, the GPU may need to change the corresponding context. Additionally, the workload corresponding to the mode or state may follow the changed mode or state.

[0041] Figure 2 An example GPU 200 is illustrated in accordance with one or more techniques of this disclosure. Figure 2 As shown, GPU 200 includes a command processor (CP) 210, a draw call group 212, a VFD 220, a VS 222, a vertex cache (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z pass engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a rendering back end (RB) 236, a second level (L2) cache (UCHE) 238, and a system memory 240. Although Figure 2 GPU 200 is shown to include processing units 220 to 238, but GPU 200 may include multiple additional processing units. Additionally, processing units 220 to 238 are merely examples, and any combination or order of processing units may be used with a GPU according to the present disclosure. GPU 200 also includes command buffer 250, context register group 260, and context state 261.

[0042] like Figure 2 As shown, the GPU may parse the command buffer into context register packets (e.g., context register packets 260) and / or draw call data packets (e.g., draw call packets 212) using a CP (e.g., CP 210) or a hardware accelerator. Subsequently, the CP 210 may transmit the context register packets 260 or the draw call packets 212 to a processing unit or block in the GPU through a separate path. In addition, the command buffer 250 may alternate different states of context registers and draw calls. For example, the command buffer may be constructed in the following manner: context registers of context N, draw calls of context N, context registers of context N+1, and draw calls of context N+1.

[0043] The GPU can render images in a variety of different ways. In some instances, the GPU can use rendering and / or tile rendering to render images. In a tile rendering GPU, the image can be divided or split into different parts or tiles. After the image is divided, each part or tile can be rendered separately. The tile rendering GPU can divide the computer graphics image into a grid format so that each part of the grid (i.e., tile) is rendered separately. In some aspects, during the binning process, the image can be divided into different boxes or tiles. In some aspects, during the binning process, a visibility stream can be constructed in which visible primitives or drawing calls can be identified. In contrast to tile rendering, direct rendering does not divide the frame into smaller boxes or tiles. On the contrary, in direct rendering, the entire frame is rendered at once. Additionally, some types of GPUs may allow both tile rendering and direct rendering.

[0044] In some aspects, the GPU may apply a drawing or rendering process to different boxes or tiles. For example, the GPU may render for a box and perform all drawing for the primitives or pixels in the box. During the process of rendering for the box, the rendering target may be located in GMEM. In some instances, after rendering for a box, the contents of the rendering target may be moved to system memory and GMEM may be released to render the next box. Additionally, the GPU may render for another box and perform drawing for the primitives or pixels in the box. Therefore, in some aspects, there may be a small number of boxes (e.g., four boxes) that cover all the drawing in a surface. In addition, the GPU may loop through all the drawing in a box, but perform drawing of visible drawing calls, i.e., drawing calls containing visible geometry. In some aspects, a visibility stream may be generated (e.g., in a binning process) to determine visibility information for each primitive in an image or scene. For example, such a visibility stream may identify whether a primitive is visible. In some aspects, this information may be used to remove invisible primitives, such as during a rendering process. In addition, at least some of the primitives identified as visible may be rendered during a rendering process.

[0045] In some aspects of tile rendering, there may be multiple processing stages or processes. For example, rendering may be performed in two processes, such as a visibility or box visibility process and a rendering or box rendering process. During the visibility process, the GPU may input a rendering workload, record the position of a primitive or triangle, and then determine which primitives or triangles fall into which box or region. In some aspects of the visibility process, the GPU may also identify or mark the visibility of each primitive or triangle in the visibility stream. During the rendering process, the GPU may input a visibility stream and process one box or region at a time. In some aspects, the visibility stream may be analyzed to determine which primitives or primitive vertices are visible or invisible. Thus, visible primitives or primitive vertices may be processed. In this way, the GPU may reduce the unnecessary workload of processing or rendering invisible primitives or triangles.

[0046] In some aspects, during the visibility process, certain types of primitive geometry may be processed, e.g., positional geometry only. Additionally, primitives may be classified into different bins or regions based on the position or positioning of the primitives or triangles. In some instances, the classification of primitives or triangles into different bins may be performed by determining visibility information for these primitives or triangles. For example, the GPU may determine visibility information for each primitive in each bin or region or write it, for example, to system memory. The visibility information may be used to determine or generate a visibility stream. During the rendering process, the primitives in each bin may be rendered separately. In these cases, the visibility stream may be extracted from a memory for discarding primitives that are not visible to the bin.

[0047] Some aspects of the GPU or GPU architecture may provide a number of different options for rendering (e.g., software rendering and hardware rendering). In software rendering, the driver or CPU may process each view. Figure 1 In hardware rendering, the hardware or GPU may be responsible for copying or processing the geometry of each viewpoint in the image. Therefore, the hardware can manage the copying or processing of primitives or triangles for each viewpoint in the image.

[0048] Figure 3 An example image or surface 300 is shown, which includes a plurality of primitives divided into a plurality of bins. Figure 3 As shown, image or surface 300 includes region 302, which includes primitives 321, 322, 323, and 324. Primitives 321, 322, 323, and 324 are divided or placed into different bins, such as bins 310, 311, 312, 313, 314, and 315. Figure 3 An example of using multiple viewpoints for sub-tile rendering for primitives 321-324 is illustrated. For example, primitives 321-324 are in a first viewpoint 350 and a second viewpoint 351. Therefore, GPU processing or rendering of an image or surface 300 including region 302 may utilize multi-viewpoint or multi-view rendering.

[0049] As indicated herein, a GPU or graphics processor unit may use a tiled rendering architecture to reduce power consumption or save memory bandwidth. As further described above, this rendering method may divide a scene into multiple boxes and include a visibility process that identifies visible triangles in each box. Thus, in tiled rendering, a full screen may be divided into multiple boxes or tiles. The scene may then be rendered multiple times, for example, once or multiple times for each box.

[0050] In various aspects of graphics rendering, some graphics applications may render to a single target (i.e., a render target) one or more times. For example, in graphics rendering, a frame buffer on a system memory may be updated multiple times. A frame buffer may be a portion of a memory or random access memory (RAM) (e.g., containing a bitmap or storage device) to facilitate storage of display data for a GPU. A frame buffer may also be a memory buffer containing a complete frame of data. Additionally, a frame buffer may be a logical buffer. In some aspects, updating a frame buffer may be performed in box or tile rendering, where, as described above, a surface is divided into multiple boxes or tiles, and then each box or tile may be rendered separately. Furthermore, in tile rendering, a frame buffer may be divided into multiple boxes or tiles.

[0051] Some aspects of graphics processing can utilize different types of shading, such as variable rate shading (VRS). Variable rate shading is a way to allocate rendering performance or power at different rates. For example, a graphics processing unit (GPU) can utilize variable rate shading to allocate rendering performance / power at different rates across a rendered image. That is, variable rate shading is a feature that improves rendering performance and quality by changing the shading rate of different areas of an image or frame. Additionally, variable rate shading can be referred to as coarse pixel shading.

[0052] In some instances, variable rate shading can significantly improve the performance of certain applications by reducing the amount of work performed at a graphics processing unit (GPU). For example, variable rate shading can reduce the number of times a fragment shader executes instructions at the GPU. Variable rate shading can also reduce the shading rate with a small amount of perceptible parallax. For example, variable rate shading can result in a reduced shading rate with little or no reduction in perceptible visual quality at the output image.

[0053] Figure 4 Graph 400 illustrates an example of GPU rendering performance utilizing VRS rates. More specifically, Figure 4 The graph 400 in FIG. 4 shows rendering performance in terms of frames per second (fps) using a VRS rate with forced draw states. Figure 4 As shown, the amount of fps for different applications (e.g., application 410 and application 420) can increase as the amount of forced rendering state VRS rate increases. For example, for 1x1 variable rate shading, the fps for application 410 and application 420 can be 69 and 71, respectively. For example, for 2x2 variable rate shading, the fps for application 410 and application 420 can be 83 and 82, respectively. For example, for 4x4 variable rate shading, the fps for application 410 and application 420 can be 88 and 89, respectively. Figure 4As depicted, variable rate shading can significantly improve the performance of certain applications by reducing the amount of work performed at the GPU.

[0054] One issue when applying any VRS without explicit dictation from the application is a way to automatically select quality levels that maximize the amount of work saved while minimizing the amount of perceptible image degradation in the final result. In theory, this quality degradation is most noticeable in areas of the screen that the end user is focusing on, such as character models or game objects. These screen areas may be characterized by high geometric complexity, such as including a large number of visible primitives, sharp edges, and / or abrupt transitions in color or depth. Since the user is likely to focus on these areas with high geometric complexity, reducing the shading rate is more likely to produce a noticeable loss of quality when compared to areas with less geometric complexity.

[0055] Some methods that attempt to use historical data to estimate such areas to generate quality levels (i.e., methods that infer where the area of ​​interest for the current frame is located based on the location in the previous frame) may be inherently reactive and may sacrifice quality / performance benefits if the geometric complexity changes from frame to frame. In some aspects, areas with high geometric complexity and low geometric complexity can be identified in the visibility process. In addition, there are methods for dynamically updating the VRS state before rendering the same workload. Based on the above, it may be beneficial to apply different shading rates to different areas of a frame or frame buffer based on the impact on visual fidelity. That is, it may be beneficial to apply one shading rate (e.g., a more conservative or increased shading rate) to areas of the frame buffer that have a higher impact on visual fidelity and another shading rate (e.g., a more aggressive or reduced shading rate) to areas with less detail. In addition, it may be beneficial to automatically apply these different shading rates to different areas of the frame.

[0056] Aspects of the present disclosure may apply different shading rates to different regions of a frame or frame buffer based on the impact on visual fidelity. For example, aspects of the present disclosure may apply a shading rate (e.g., a more conservative or increased shading rate) to a region of a frame buffer that has a higher impact on visual fidelity, and another shading rate (e.g., a more aggressive or reduced shading rate) to a region with less detail. Additionally, in some examples, aspects of the present disclosure may automatically apply these different shading rates to different regions of a frame. Aspects provided herein may also configure a density map based on visibility information for primitives, which may include density data associated with the amount of primitives in each of the boxes / regions. In addition, aspects provided herein may map density data for multiple boxes / regions in a frame to different shading rates for boxes / regions. In this way, aspects provided herein may optimize the shading rates used on different parts of a frame or scene in graphics processing. This in turn may help optimize the tradeoff between visual fidelity and the power and / or performance used to shade a frame or scene at a GPU.

[0057] In some cases, aspects of the present disclosure may utilize different types of VRS (e.g., image VRS) to implement certain VRS methods (e.g., a VRS method based on geometric density or an automatic VRS method). In addition, geometry data (e.g., raw geometry data) may be generated without additional overhead on a GPU (e.g., a GPU that typically runs a bin visibility process prior to a rendering process for a given workload). Aspects provided herein may also utilize software flows for a binning process and / or a rendering process. For example, a binning process may receive visibility data on a per-bin basis and then generate a density map, where values ​​in the density map may be mapped to different shading rates. During the rendering process, the shading rates may be sent to the GPU, and the GPU may then apply the shading rates when rendering data associated with the bins.

[0058] Figure 5 5 is a diagram 500 illustrating an example software flow for graphics processing. More specifically, diagram 500 depicts a software flow 510 for a frame 501 (eg, frame "N" within a plurality of frames in a scene associated with graphics processing). Figure 5As shown in FIG. 500 , the diagram 500 includes a software flow 510, a binning process 520 (e.g., a binning process for frame 501) including steps 530, 540, and 550, and a rendering process 560 (e.g., a rendering process for frame 501) including steps 570 and 580. At step 530 in the binning process 520, the software flow 510 can configure the GPU to receive per-bin primitive visibility data. At step 540 in the binning process 520, the software flow 510 can configure the GPU to generate a density map of primitives distributed across bins from the visibility data. At step 550 in the binning process 520, the software flow 510 can configure the GPU to map a density value (e.g., a per-bin density value) to a shading rate to be applied to a particular bin. At step 570 in the rendering process 560, the software flow 510 can configure the GPU to send the shading rate to the GPU hardware associated with the VRS. At step 580 in the rendering process 560 , the software flow 510 may configure the GPU (eg, GPU hardware) to apply a shading rate when rendering the bins.

[0059] In some aspects, the GPU (e.g., GPU hardware) may generate per-box metrics for visible primitives within a box from a visibility process. The GPU or GPU hardware may also calculate the amount of primitives for the entire frame buffer present within the box (e.g., the ratio of primitives). In some examples, software may configure the GPU or GPU hardware to calculate the amount of primitives (e.g., the ratio of primitives). This primitive ratio may provide an indication of the complexity of the box based on its geometry (e.g., the amount of primitives located within the box). That is, a high primitive ratio may indicate that a particular box is complex (i.e., most of the primitives in the scene are encapsulated into a particular box). Similarly, a low primitive ratio may indicate that a particular box is not complex (i.e., a smaller portion of the primitives in the scene are encapsulated into a particular box). The aggregation of all primitive ratios may constitute a density map, which may be configured or generated by the GPU. For example, a density map may be configured or generated based on visibility information for primitives in a scene or frame. A density map may include density data associated with the amount of primitives in each box in a box in a scene or frame. Additionally, the density map may plot which bins are geometrically dense or geometrically heavy (i.e., the bin includes a large number of primitives compared to other bins) and / or which bins are geometrically sparse or geometrically light (i.e., the bin includes a small number of primitives compared to other bins).

[0060] Figure 6 6 is a diagram illustrating an example density map for use in graphics processing. More specifically, diagram 600 depicts a density map 610 including many primitives per bin. Figure 6As shown in , density map 610 includes many boxes 640, each of which includes a certain amount of primitives. For example, there may be 24 boxes (e.g., box 640) associated with density map 610, and each box in box 640 may include a corresponding primitive amount (e.g., primitive amount 611, primitive amount 612, primitive amount 613, primitive amount 614, primitive amount 615, primitive amount 616, primitive amount 617, primitive amount 618, primitive amount 621, primitive amount 622, primitive amount 623, primitive amount 624, primitive amount 625, primitive amount 626, primitive amount 627, primitive amount 628, primitive amount 631, primitive amount 632, primitive amount 633, primitive amount 634, primitive amount 635, primitive amount 636, primitive amount 637, and primitive amount 638). Although Figure 6 24 bins are shown in density map 610 , but density map 610 may include any suitable number of bins 640 (eg, 4, 8, 12, 16, 20, 27, 32, etc.). Figure 6 The density map 610 is depicted to provide an indication of the complexity of each of the bins in terms of its geometry (e.g., the amount of primitives located within the bin). For example, each bin in bins 640 includes an amount of primitives that corresponds to the amount of primitives in the particular bin compared to the total amount of primitives within the entire scene or frame depicted by the density map 610. A high amount of primitives (or ratio / percentage) can indicate that the particular bin is complex (i.e., a large portion of the primitives in the scene or frame are packed into the particular bin). Additionally, a low amount of primitives (or ratio / percentage) can indicate that the particular bin is not complex (i.e., a smaller portion of the primitives in the scene or frame are packed into the particular bin). The density map 610 may include an aggregation of all primitive amounts or ratios within a particular scene or frame. Additionally, primitive amounts may be expressed as ratios or percentages, such as Figure 7 as indicated in .

[0061] Figure 7 7 is a diagram illustrating an example density map for use in graphics processing. More specifically, diagram 700 depicts a density map 710 including many primitives per bin. Figure 7As shown in , density map 710 includes many boxes 740, each of which includes a ratio or percentage of all primitives in the scene. For example, there are 24 boxes (e.g., box 740) associated with density map 710, and each box in box 740 includes a corresponding primitive ratio (e.g., primitive ratio 711, primitive ratio 712, primitive ratio 713, primitive ratio 714, primitive ratio 715, primitive ratio 716, primitive ratio 717, primitive ratio 718, primitive ratio 721, primitive ratio 722, primitive ratio 723, primitive ratio 724, primitive ratio 725, primitive ratio 726, primitive ratio 727, primitive ratio 728, primitive ratio 731, primitive ratio 732, primitive ratio 733, primitive ratio 734, primitive ratio 735, primitive ratio 736, primitive ratio 737 and primitive ratio 738). Although Figure 7 24 bins are shown in density map 710 , but density map 710 may include any suitable number of bins 740 (eg, 4, 8, 12, 16, 20, 27, 32, etc.). Figure 7 It is depicted that density map 710 may provide an indication of the complexity of each of the bins in terms of its geometry (e.g., the ratio of primitives located within the bin). For example, each of bins 740 includes a primitive ratio (or percentage) that corresponds to the ratio of primitives in the particular bin compared to the total amount of primitives within the entire scene or frame depicted by density map 710. A high primitive ratio (or percentage) may indicate that the particular bin is complex (i.e., a large portion of the primitives in the scene or frame are packed into the particular bin). Additionally, a low primitive ratio (or percentage) may indicate that the particular bin is not complex (i.e., a smaller portion of the primitives in the scene or frame are packed into the particular bin). Density map 710 may include an aggregation of all primitive quantities (e.g., ratios or percentages) within a particular scene or frame. As Figure 7 As shown in , the amount of primitives included in each of the bins 740 in the density map 710 may be expressed as a ratio or a percentage.

[0062] Figure 6 and Figure 7 Depicted are examples of density maps utilized by aspects of the present disclosure (and more particularly, how density maps are configured by a GPU). In some cases, software may configure a GPU to generate a density map. Figure 6 and Figure 7 Each summary box in corresponds to a box (e.g., a particular box in box 640 and box 740). Figure 6 In , each quantity (e.g., primitive quantities 611 to 638) in each particular bin (e.g., bin 640) represents the quantity of primitives present in that particular bin in the entire workload (e.g., graphics workload). Figure 7In , each ratio (e.g., primitive ratios 711 to 738) in each particular bin (e.g., bin 740) represents a ratio or percentage of primitives present in that particular bin in the entire workload (e.g., graphics workload). Figure 6 and Figure 7 Of the two, bins 640 and 740, which contain the subject of the scene (e.g., the most obvious or prominent part of the scene), may be the densest bins. Figure 7 The subject of the scene in may correspond to a center bin including primitive ratio 724 and primitive ratio 725 , each of which includes the highest primitive ratio in bin 740 (eg, ratio 0.15).

[0063] In some cases, aspects provided herein may store data (e.g., density data) corresponding to a density map. This data (e.g., density data) may be associated with the amount of primitives in each of the bins in the density map. Additionally, the density data for each of the bins may be mapped (i.e., converted or translated) to a shading rate for each of the bins. For example, once the density data is stored (e.g., in a GPU accessible buffer), various operations (e.g., memory manipulation operations) may be triggered to update a buffer (e.g., an image VRS quality buffer) and adjust the shading rate for each bin. In some aspects, the shading rate may be dynamically updated for each bin based on the corresponding density data in the density map.

[0064] Some aspects of the present disclosure may utilize certain algorithms to update the VRS process (e.g., image VRS update algorithms). These algorithms (e.g., VRS update algorithms) may be used with binned rendering or direct rendering at the GPU. In some examples, the bin visibility process may be run first in binned rendering or direct rendering, but once the visible primitive data is saved (e.g., if direct rendering is utilized), the bin visibility process may be discarded. In addition, for each primitive amount / ratio in the density map, the various aspects provided herein may: (1) read the visible primitive ratio from memory and / or (2) use the ratio to look up a pre-programmed table that maps the ratio to a VRS shading rate. For example, a primitive ratio of 0.04 (i.e., less than 4% of all primitives in the scene are in this bin) may be mapped to a certain shading rate (e.g., a 2x2 shading rate, etc.). This table may be adjusted or regulated (e.g., offline regulation) for the throughput capabilities of the target GPU. Additionally, the various aspects provided herein may write the retrieved VRS shading rate for the bin to each time slot in a buffer (e.g., a hardware image VRS quality buffer) corresponding to a particular bin (e.g., many time slots may correspond to one bin). After this, the GPU can continue normal rendering (binning or other rendering).In addition, the VRS hardware at the GPU can automatically apply the quality level programmed in the buffer (eg, image VRS quality buffer).

[0065] Aspects of the present disclosure may include multiple benefits or advantages. For example, the aspects provided herein may apply different shading rates to different regions of a frame or frame buffer based on the impact on visual fidelity. For example, the aspects of the present disclosure may apply a shading rate (e.g., a more conservative or increased shading rate) to a region of the frame buffer that has a higher impact on visual fidelity, and another shading rate (e.g., a more aggressive or reduced shading rate) to a region with less detail. The aspects provided herein may also configure a density map based on visibility information for primitives, which may include density data associated with the amount of primitives in each of the boxes / regions. In addition, the aspects provided herein may map density data for multiple boxes / regions in a frame to different shading rates for boxes / regions. In this way, the aspects provided herein may optimize the shading rates for different parts of a frame or scene in graphics processing. This in turn may help optimize the power and / or performance used to shade a frame or scene at a GPU.

[0066] Figure 8 FIG. 8 is a communication flow diagram 800 of a graphical process according to one or more techniques of the present disclosure. Figure 8As shown in , diagram 800 includes example communications between a GPU component 802 (e.g., a GPU or a component in a GPU pipeline, software for controlling a GPU, or a processor for controlling a GPU), a GPU component 804 (e.g., a GPU or a component in a GPU pipeline or other graphics processor), and a GPU component 806 (e.g., a GPU or a component in a GPU pipeline or other graphics processor) in accordance with one or more techniques of the present disclosure.

[0067] At 810, GPU component 802 may obtain an indication of a primitive set in at least one frame from at least one component in a graphics processing unit (GPU) pipeline (e.g., obtain indication 812 from GPU component 804), wherein the indication is obtained before obtaining visibility information for the primitive set.

[0068] At 820, GPU component 802 may obtain visibility information for a primitive set in at least one frame associated with graphics processing, wherein the at least one frame includes a plurality of bins such that at least one bin of the plurality of bins includes at least one primitive in the primitive set. The visibility information for the primitive set may be associated with a binning process for the at least one frame. The at least one frame may correspond to at least one graphics workload for the graphics processing.

[0069] At 830, GPU component 802 may configure a density map based on visibility information for the primitive set, wherein the density map includes density data associated with an amount of the primitive set in each of the plurality of bins. The density data associated with the amount of the primitive set in each of the plurality of bins may correspond to a density of visible primitives of a first amount of the primitive set in each of the plurality of bins. In some aspects, configuring the density map based on the visibility information may include generating the density map based on the visibility information. Thus, GPU component 802 may generate the density map based on the visibility information.

[0070] At 840, GPU component 802 can calculate a ratio or percentage of primitive sets in each of the plurality of bins based on the amount of primitive sets in each of the plurality of bins. For example, the amount of primitive sets in each of the plurality of bins can be associated with a ratio or percentage of primitive sets in each of the plurality of bins.

[0071] At 850, the GPU component 802 may map density data for each of the plurality of bins to a shading rate for each of the plurality of bins. A first shading rate for at least one first bin of the plurality of bins may be different from a second shading rate for at least one second bin of the plurality of bins. During a rendering process at a graphics processing unit (GPU), the first shading rate for at least one first bin may be different from the second shading rate for at least one second bin. Additionally, the shading rate for each of the plurality of bins may be associated with a quality level for shading a plurality of draws associated with at least one frame. Furthermore, the shading rate for each of the plurality of bins may be associated with variable rate shading (VRS). In some aspects, mapping the density data for each of the plurality of bins to a shading rate for each of the plurality of bins may include converting the density data for each of the plurality of bins to a shading rate for each of the plurality of bins. Thus, the GPU component 802 may convert the density data for each of the plurality of bins to a shading rate for each of the plurality of bins.

[0072] At 860, GPU component 802 may send an indication of a shading rate for each of the plurality of bins (e.g., sending indication 862 to GPU component 806), wherein the indication is sent after density data for each of the plurality of bins is mapped to a shading rate for each of the plurality of bins. The indication of the shading rate for each of the plurality of bins may be sent to at least one component in a graphics processing unit (GPU) pipeline. Additionally, the shading rate for each of the plurality of bins may be applied to a rendered image associated with at least one frame.

[0073] Fig. 9 900 is a flowchart of an example method of graphics processing according to one or more techniques of the present disclosure. The method can be performed by a GPU, a GPU component (e.g., a component in a GPU or a GPU pipeline, software for controlling a GPU, or a processor for controlling a GPU), a graphics processor, a CPU (or other central processing unit), an apparatus for graphics processing, a wireless communication device, and / or a combination thereof. Figures 1 to 8 The examples may be performed using any device that can perform graphics processing.

[0074] At 904, the GPU may obtain visibility information for a primitive set in at least one frame associated with graphics processing, wherein the at least one frame includes a plurality of bins, such that at least one bin in the plurality of bins includes at least one primitive in the primitive set, such as in conjunction with Figures 1 to 8 For example, Figure 8As described in 820 of , the GPU component 802 may obtain visibility information for a primitive set in at least one frame associated with graphics processing, wherein the at least one frame includes a plurality of bins, such that at least one bin in the plurality of bins includes at least one primitive in the primitive set. In addition, step 904 may be performed by Figure 1 The visibility information for the primitive set may be associated with a binning process for at least one frame. The at least one frame may correspond to at least one graphics workload for graphics processing.

[0075] At 906, the GPU may configure a density map based on the visibility information for the primitive set, wherein the density map includes density data associated with an amount of the primitive set in each of the plurality of bins, such as in conjunction with Figures 1 to 8 For example, Figure 8 As described in 830 of , the GPU component 802 can configure a density map based on the visibility information for the primitive set, wherein the density map includes density data associated with the amount of the primitive set in each of the plurality of bins. In addition, step 906 can be performed by Figure 1 The processing unit 120 in the GPU component 802 may be executed. The density data associated with the amount of the primitive set in each of the plurality of bins may correspond to the density of visible primitives of the first amount of the primitive set in each of the plurality of bins. In some aspects, configuring the density map based on the visibility information may include generating the density map based on the visibility information. Thus, the GPU component 802 may generate the density map based on the visibility information.

[0076] At 910, the GPU may map density data for each of the plurality of bins to a shading rate for each of the plurality of bins, such as in conjunction with Figures 1 to 8 For example, Figure 8 As described in 850 of , the GPU component 802 can map the density data for each of the plurality of bins to the shading rate for each of the plurality of bins. In addition, step 910 can be performed by Figure 1120 in the processing unit 120. A first shading rate for at least one first box in the plurality of boxes may be different from a second shading rate for at least one second box in the plurality of boxes. During a rendering process at a graphics processing unit (GPU), the first shading rate for at least one first box may be different from the second shading rate for at least one second box. Additionally, the shading rate for each of the plurality of boxes may be associated with a quality level for shading a plurality of draws associated with at least one frame. Furthermore, the shading rate for each of the plurality of boxes may be associated with variable rate shading (VRS). In some aspects, mapping density data for each of the plurality of boxes to a shading rate for each of the plurality of boxes may include: converting density data for each of the plurality of boxes to a shading rate for each of the plurality of boxes. Thus, the GPU component 802 may convert density data for each of the plurality of boxes to a shading rate for each of the plurality of boxes.

[0077] Fig.10 1000 is a flowchart of an example method of graphics processing according to one or more techniques of the present disclosure. The method can be performed by a GPU, a GPU component (e.g., a component in a GPU or a GPU pipeline, software for controlling a GPU, or a processor for controlling a GPU), a graphics processor, a CPU (or other central processing unit), an apparatus for graphics processing, a wireless communication device, and / or a combination thereof. Figures 1 to 8 The examples may be performed using any device that can perform graphics processing.

[0078] At 1002, the GPU may obtain an indication of a primitive set in at least one frame from at least one component in the GPU pipeline, wherein the indication is obtained before obtaining visibility information for the primitive set, such as in conjunction with Figures 1 to 8 For example, Figure 8 As described in 810 of , the GPU component 802 may obtain an indication of a primitive set in at least one frame from at least one component in the GPU pipeline, wherein the indication is obtained before obtaining visibility information for the primitive set. In addition, step 1002 may be performed by Figure 1 The processing unit 120 executes.

[0079] At 1004, the GPU may obtain visibility information for a primitive set in at least one frame associated with graphics processing, wherein the at least one frame includes a plurality of bins, such that at least one bin in the plurality of bins includes at least one primitive in the primitive set, such as in conjunction with Figures 1 to 8 For example, Figure 8As described in 820 of , the GPU component 802 may obtain visibility information for a primitive set in at least one frame associated with graphics processing, wherein the at least one frame includes a plurality of bins, such that at least one bin in the plurality of bins includes at least one primitive in the primitive set. In addition, step 1004 may be performed by Figure 1 The visibility information for the primitive set may be associated with a binning process for at least one frame. The at least one frame may correspond to at least one graphics workload for graphics processing.

[0080] At 1006, the GPU may configure a density map based on the visibility information for the primitive set, wherein the density map includes density data associated with an amount of the primitive set in each of the plurality of bins, such as in conjunction with Figures 1 to 8 For example, Figure 8 As described in 830 of , the GPU component 802 can configure a density map based on the visibility information for the primitive set, wherein the density map includes density data associated with the amount of the primitive set in each of the plurality of bins. In addition, step 1006 can be performed by Figure 1 The processing unit 120 in the GPU component 802 may be executed. The density data associated with the amount of the primitive set in each of the plurality of bins may correspond to the density of visible primitives of the first amount of the primitive set in each of the plurality of bins. In some aspects, configuring the density map based on the visibility information may include generating the density map based on the visibility information. Thus, the GPU component 802 may generate the density map based on the visibility information.

[0081] At 1008, the GPU may calculate a ratio or percentage of the primitive sets in each of the plurality of bins based on the amount of the primitive sets in each of the plurality of bins, such as in combination with Figures 1 to 8 For example, Figure 8 As described in 840 of FIG. 1008 , the GPU component 802 may calculate a ratio or percentage of the primitive sets in each of the plurality of bins based on the amount of the primitive sets in each of the plurality of bins. In addition, step 1008 may be performed by Figure 1 For example, the amount of the primitive set in each of the plurality of bins may be associated with a ratio or percentage of the primitive set in each of the plurality of bins.

[0082] At 1010, the GPU may map density data for each of the plurality of bins to a shading rate for each of the plurality of bins, such as in conjunction with Figures 1 to 8 For example, Figure 8As described in 850 of , the GPU component 802 can map the density data for each of the plurality of bins to the shading rate for each of the plurality of bins. In addition, step 1010 can be performed by Figure 1 120 in the processing unit 120. A first shading rate for at least one first box in the plurality of boxes may be different from a second shading rate for at least one second box in the plurality of boxes. During a rendering process at a graphics processing unit (GPU), the first shading rate for at least one first box may be different from the second shading rate for at least one second box. Additionally, the shading rate for each of the plurality of boxes may be associated with a quality level for shading a plurality of draws associated with at least one frame. Furthermore, the shading rate for each of the plurality of boxes may be associated with variable rate shading (VRS). In some aspects, mapping density data for each of the plurality of boxes to a shading rate for each of the plurality of boxes may include: converting density data for each of the plurality of boxes to a shading rate for each of the plurality of boxes. Thus, the GPU component 802 may convert density data for each of the plurality of boxes to a shading rate for each of the plurality of boxes.

[0083] At 1012, the GPU may send an indication of a shading rate for each of the plurality of bins, wherein the indication is sent after density data for each of the plurality of bins is mapped to a shading rate for each of the plurality of bins, as in conjunction with Figures 1 to 8 For example, Figure 8 As described in 860 of , the GPU component 802 can send an indication of a shading rate for each of the plurality of bins, wherein the indication is sent after density data for each of the plurality of bins is mapped to a shading rate for each of the plurality of bins. In addition, step 1012 can be performed by Figure 1 The shading rate for each of the plurality of bins may be sent to at least one component in a graphics processing unit (GPU) pipeline. Additionally, the shading rate for each of the plurality of bins may be applied to a rendered image associated with at least one frame.

[0084] In a configuration, a method or apparatus for graphics processing is provided. The apparatus may be a GPU, a GPU component (e.g., a component in a GPU or GPU pipeline, software for controlling a GPU, or a processor for controlling a GPU), a graphics processor, a CPU (or other central processing unit), an apparatus for graphics processing, a wireless communication device, and / or some other processor that can perform graphics processing. In various aspects, the apparatus may be a processing unit 120 within a device 104, or may be some other hardware within a device 104 or another device. The apparatus (e.g., processing unit 120) may include a component for obtaining visibility information for a set of primitives in at least one frame associated with graphics processing, wherein the at least one frame includes a plurality of bins, such that at least one bin of the plurality of bins includes at least one primitive in the set of primitives. The apparatus (e.g., processing unit 120) may also include a component for configuring a density map based on the visibility information for the set of primitives, wherein the density map includes density data associated with the amount of the set of primitives in each bin of the plurality of bins. The apparatus (e.g., processing unit 120) may also include a component for mapping the density data for each bin of the plurality of bins to a shading rate for each bin of the plurality of bins. The apparatus (e.g., processing unit 120) may also include means for calculating a ratio or percentage of the primitive sets in each of the plurality of bins based on the amount of the primitive sets in each of the plurality of bins. The apparatus (e.g., processing unit 120) may also include means for obtaining an indication of the primitive sets in at least one frame from at least one component in a graphics processing unit (GPU) pipeline, wherein the indication is obtained before obtaining visibility information for the primitive sets. The apparatus (e.g., processing unit 120) may also include means for sending an indication of a shading rate for each of the plurality of bins, wherein the indication is sent after density data for each of the plurality of bins is mapped to a shading rate for each of the plurality of bins.

[0085] The subject matter described herein can be implemented to achieve one or more benefits or advantages. For example, the described graphics processing techniques can be used by a GPU, a GPU component, a CPU, a graphics processor, a device for graphics processing, or some other processor that can perform graphics processing to implement the density-driven variable rate shading techniques described herein. This can also be implemented at a low cost compared to other graphics processing techniques. In addition, the graphics processing techniques herein can improve or accelerate data processing or execution. In addition, the graphics processing techniques herein can improve resource or data utilization and / or resource efficiency. Additionally, various aspects of the present disclosure can utilize density-driven variable rate shading techniques to improve memory bandwidth efficiency and / or increase processing speed at the GPU or CPU.

[0086] It should be understood that the specific order or hierarchy of the blocks in the disclosed process / flowchart is merely an illustration of the exemplary method. It should be understood that the specific order or hierarchy of the blocks in the process / flowchart can be rearranged based on design preferences. In addition, some blocks can be combined or omitted. The attached method claims provide the elements of each block in a sample order, but are not meant to be limited to the specific order or hierarchy provided.

[0087] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the various aspects shown herein, but should be given the full scope consistent with the language of the claims, wherein unless otherwise specified, reference to an element in the singular is not intended to mean "one and only one", but rather "one or more". The word "exemplary" is used herein to mean "used as an example, instance, or illustration". Any aspect described herein as "exemplary" is not necessarily to be interpreted as being preferred or having advantages over other aspects.

[0088] Unless specifically stated otherwise, the term “some” refers to one or more, and the term “or” may be interpreted as “and / or” if the context does not dictate otherwise. Combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” include any combination of A, B, and / or C, and may include multiple A, multiple B, or multiple C. Specifically, combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” may be only A, only B, only C, A and B, A and C, B and C, or A and B and C, where any such combination may include one or more members of A, B, or C. All structural and functional equivalents of the elements of the various aspects described throughout this disclosure that are known or will later become known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, regardless of whether such disclosure is explicitly recited in the claims, nothing disclosed herein is intended to be disclosed to the public. Words such as "module," "mechanism," "element," and "device" are not substituted for the word "component." Therefore, no claim element will be construed as a part-plus-function unless the element is expressly stated using the phrase "component for..."

[0089] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module described herein may be stored or sent as one or more instructions or codes on a computer-readable medium.

[0090] According to the present disclosure, the term "or" may be understood as "and / or" in the absence of context dictating otherwise. Additionally, while phrases such as "one or more" or "at least one" may have been used for some features disclosed herein but not for other features, features not using such language may be understood to have such implicit meanings in the absence of context dictating otherwise.

[0091] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module described herein may be stored on a computer-readable medium or sent on a computer-readable medium as one or more instructions or codes. Computer-readable media may include computer data storage media and communication media, including any media that facilitates the transfer of computer programs from one place to another. In this way, computer-readable media may generally correspond to (1) a non-transient tangible computer-readable storage medium or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, codes, and / or data structures for implementing the techniques described in this disclosure. As an example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM, or other optical disk storage devices, magnetic disk storage devices, or other magnetic storage devices. As used herein, disk and disc include: compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. A computer program product may include a computer-readable medium.

[0092] The code may be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), arithmetic logic units (ALUs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Therefore, the term "processor" as used herein may refer to any of the above structures or any other structure suitable for implementing the techniques described herein. In addition, these techniques may be fully implemented in one or more circuits or logic elements.

[0093] The technology of the present disclosure can be implemented in a variety of devices or apparatuses, including wireless mobile phones, integrated circuits (ICs) or IC groups (e.g., chipsets). Various components, modules, or units are described in the present disclosure to emphasize the functional aspects of devices configured to perform the disclosed technology, but they do not necessarily need to be implemented by different hardware units. On the contrary, as described above, the various units can be combined in any hardware unit, or provided by a collection of interoperable hardware units (including one or more processors as described above) in combination with appropriate software and / or firmware. Therefore, the term "processor" as used herein can refer to any of the above structures or any other structure suitable for implementing the technology described herein. Similarly, these technologies can be fully implemented in one or more circuits or logic elements.

[0094] The following aspects are merely illustrative and may be combined with other aspects or teachings described herein without limitation.

[0095] Aspect 1 is a device for graphics processing, comprising a memory and at least one processor coupled to the memory, and based at least in part on information stored in the memory, the at least one processor is configured to: obtain visibility information for a set of primitives in at least one frame associated with the graphics processing, wherein the at least one frame comprises a plurality of bins such that at least one bin of the plurality of bins comprises at least one primitive in the set of primitives; configure a density map based on the visibility information for the set of primitives, wherein the density map comprises density data associated with an amount of the set of primitives in each of the plurality of bins; and map the density data for each of the plurality of bins to a shading rate for each of the plurality of bins.

[0096] Aspect 2 is an apparatus according to aspect 1, wherein the amount of the set of primitives in each of the plurality of bins is associated with a ratio or percentage of the set of primitives in each of the plurality of bins.

[0097] Aspect 3 is an apparatus according to any one of Aspects 1 and 2, wherein the at least one processor is further configured to: calculate the ratio or the percentage of the set of primitives in each of the multiple boxes based on the amount of the set of primitives in each of the multiple boxes.

[0098] Aspect 4 is an apparatus according to any one of Aspects 1 to 3, wherein the density data associated with the amount of the set of primitives in each of the plurality of boxes corresponds to the density of visible primitives of a first amount of the set of primitives in each of the plurality of boxes.

[0099] Aspect 5 is an apparatus according to any one of aspects 1 to 4, wherein a first shading rate for at least one first bin of the plurality of bins is different from a second shading rate for at least one second bin of the plurality of bins.

[0100] Aspect 6 is an apparatus according to any one of aspects 1 to 5, wherein during a rendering process at a graphics processing unit (GPU), the first shading rate for the at least one first bin is different from the second shading rate for the at least one second bin.

[0101] Aspect 7 is an apparatus according to any one of Aspects 1 to 6, wherein the at least one processor is further configured to: obtain an indication of the set of primitives in the at least one frame from at least one component in a graphics processing unit (GPU) pipeline, wherein the indication is obtained before obtaining the visibility information for the set of primitives.

[0102] Aspect 8 is an apparatus according to any one of Aspects 1 to 7, wherein the at least one processor is further configured to: send an indication of the shading rate for each of the multiple bins, wherein the indication is sent after the density data for each of the multiple bins is mapped to the shading rate for each of the multiple bins.

[0103] Aspect 9 is an apparatus according to any one of aspects 1 to 8, wherein the shading rate for each bin of the plurality of bins is applied to a rendered image associated with the at least one frame.

[0104] Aspect 10 is an apparatus according to any one of aspects 1 to 9, wherein the indication of the shading rate for each bin in the plurality of bins is sent to at least one component in a graphics processing unit (GPU) pipeline.

[0105] Aspect 11 is an apparatus according to any one of aspects 1 to 10, wherein the shading rate for each of the plurality of bins is associated with a quality level for shading a plurality of draws associated with the at least one frame.

[0106] Aspect 12 is an apparatus according to any one of aspects 1 to 11, wherein the shading rate for each bin in the plurality of bins is associated with variable rate shading (VRS).

[0107] Aspect 13 is an apparatus according to any one of aspects 1 to 12, wherein in order to configure the density map based on the visibility information, the at least one processor is configured to: generate the density map based on the visibility information.

[0108] Aspect 14 is an apparatus according to any one of Aspects 1 to 13, wherein in order to map the density data for each of the multiple bins to the shading rate for each of the multiple bins, the at least one processor is configured to: convert the density data for each of the multiple bins to the shading rate for each of the multiple bins.

[0109] Aspect 15 is an apparatus according to any one of aspects 1 to 14, wherein the visibility information for the primitive set is associated with a binning process for the at least one frame.

[0110] Aspect 16 is an apparatus according to any one of aspects 1 to 15, wherein the at least one frame corresponds to at least one graphics workload for the graphics process.

[0111] Aspect 17 is an apparatus according to any one of aspects 1 to 16, wherein the apparatus is a wireless communication device, the apparatus further comprising at least one of an antenna or a transceiver coupled to the at least one processor.

[0112] Aspect 18 is a graphics processing method for implementing any one of aspects 1 to 16.

[0113] Aspect 19 is an apparatus for graphics processing, comprising means for implementing any one of aspects 1 to 16.

[0114] Aspect 20 is a computer-readable medium (eg, a non-transitory computer-readable medium) storing computer-executable code, which, when executed by at least one processor, causes the at least one processor to implement any one of aspects 1 to 16.

Claims

1. A device for graphics processing, comprising: Memory; and at least one processor coupled to the memory and based at least in part on the information stored in the memory, the at least one processor configured to: Obtaining visibility information for a primitive set in at least one frame associated with the graphics process, wherein the at least one frame includes a plurality of bins such that at least one bin of the plurality of bins includes at least one primitive in the primitive set; configuring a density map based on the visibility information for the set of primitives, wherein the density map includes density data associated with an amount of the set of primitives in each of the plurality of bins; and The density data for each bin of the plurality of bins is mapped to a shading rate for each bin of the plurality of bins. 2 . The apparatus of claim 1 , wherein the amount of the set of primitives in each of the plurality of bins is associated with a ratio or percentage of the set of primitives in each of the plurality of bins.

3. The apparatus of claim 2, wherein the at least one processor is further configured to: The ratio or the percentage of the set of primitives in each of the plurality of bins is calculated based on the amount of the set of primitives in each of the plurality of bins. 4 . The apparatus of claim 1 , wherein the density data associated with the amount of the primitive set in each of the plurality of bins corresponds to a density of visible primitives of a first amount of the primitive set in each of the plurality of bins. 5 . The apparatus of claim 1 , wherein a first shading rate for at least one first bin of the plurality of bins is different from a second shading rate for at least one second bin of the plurality of bins.

6. The apparatus of claim 5, wherein during a rendering process at a graphics processing unit (GPU), the first shading rate for the at least one first bin is different from the second shading rate for the at least one second bin.

7. The apparatus of claim 1, wherein the at least one processor is further configured to: An indication of the set of primitives in the at least one frame is obtained from at least one component in a graphics processing unit (GPU) pipeline, wherein the indication is obtained before obtaining the visibility information for the set of primitives.

8. The apparatus of claim 1, wherein the at least one processor is further configured to: An indication of the shading rate for each of the plurality of bins is sent, wherein the indication is sent after the density data for each of the plurality of bins is mapped to the shading rate for each of the plurality of bins. 9 . The apparatus of claim 8 , wherein the shading rate for each bin of the plurality of bins is applied to a rendered image associated with the at least one frame.

10. The apparatus of claim 8, wherein the indication of the shading rate for each bin of the plurality of bins is sent to at least one component in a graphics processing unit (GPU) pipeline.

11. The apparatus of claim 1, wherein the shading rate for each of the plurality of bins is associated with a quality level for shading a plurality of draws associated with the at least one frame.

12. The apparatus of claim 1, wherein the shading rate for each bin of the plurality of bins is associated with variable rate shading (VRS). 13 . The apparatus of claim 1 , wherein to configure the density map based on the visibility information, the at least one processor is configured to: generate the density map based on the visibility information.

14. The apparatus of claim 1 , wherein, in order to map the density data for each of the plurality of bins to the shading rate for each of the plurality of bins, the at least one processor is configured to: convert the density data for each of the plurality of bins to the shading rate for each of the plurality of bins.

15. The apparatus of claim 1, wherein the visibility information for the primitive set is associated with a binning process for the at least one frame.

16. The apparatus of claim 1, further comprising at least one of an antenna or a transceiver coupled to the at least one processor, wherein the at least one frame corresponds to at least one graphics workload for the graphics processing.

17. A graphics processing method, comprising: Obtaining visibility information for a primitive set in at least one frame associated with the graphics process, wherein the at least one frame includes a plurality of bins such that at least one bin of the plurality of bins includes at least one primitive in the primitive set; configuring a density map based on the visibility information for the set of primitives, wherein the density map includes density data associated with an amount of the set of primitives in each of the plurality of bins; and The density data for each bin of the plurality of bins is mapped to a shading rate for each bin of the plurality of bins. 18 . The method of claim 17 , wherein the amount of the set of primitives in each of the plurality of bins is associated with a ratio or percentage of the set of primitives in each of the plurality of bins.

19. The method according to claim 18, further comprising: The ratio or the percentage of the set of primitives in each of the plurality of bins is calculated based on the amount of the set of primitives in each of the plurality of bins.

20. The method of claim 17, wherein the density data associated with the amount of the primitive set in each of the plurality of bins corresponds to a density of visible primitives of a first amount of the primitive set in each of the plurality of bins.

21. The method of claim 17, wherein a first shading rate for at least one first bin of the plurality of bins is different than a second shading rate for at least one second bin of the plurality of bins.

22. The method of claim 21, wherein during a rendering process at a graphics processing unit (GPU), the first shading rate for the at least one first bin is different than the second shading rate for the at least one second bin.

23. The method of claim 17, further comprising: An indication of the set of primitives in the at least one frame is obtained from at least one component in a graphics processing unit (GPU) pipeline, wherein the indication is obtained before obtaining the visibility information for the set of primitives.

24. The method of claim 17, further comprising: An indication of the shading rate for each of the plurality of bins is sent, wherein the indication is sent after the density data for each of the plurality of bins is mapped to the shading rate for each of the plurality of bins.

25. The method of claim 24, wherein the shading rate for each of the plurality of bins is applied to a rendered image associated with the at least one frame, and wherein the indication of the shading rate for each of the plurality of bins is sent to at least one component in a graphics processing unit (GPU) pipeline.

26. The method of claim 17, wherein the shading rate for each of the plurality of bins is associated with a quality level for shading a plurality of draws associated with the at least one frame, and wherein the shading rate for each of the plurality of bins is associated with variable rate shading (VRS).

27. The method of claim 17, wherein configuring the density map based on the visibility information comprises: The density map is generated based on the visibility information, and wherein mapping the density data for each of the plurality of bins to the shading rate for each of the plurality of bins comprises converting the density data for each of the plurality of bins to the shading rate for each of the plurality of bins.

28. The method of claim 17, wherein the visibility information for the primitive set is associated with a binning process for the at least one frame, wherein the at least one frame corresponds to at least one graphics workload for the graphics processing.

29. A device for graphics processing, comprising: means for obtaining visibility information for a set of primitives in at least one frame associated with the graphics process, wherein the at least one frame includes a plurality of bins such that at least one bin of the plurality of bins includes at least one primitive in the set of primitives; means for configuring a density map based on the visibility information for the set of primitives, wherein the density map comprises density data associated with an amount of the set of primitives in each of the plurality of bins; and Means for mapping the density data for each of the plurality of bins to a shading rate for each of the plurality of bins.

30. A computer readable medium storing computer executable code for graphics processing, the code when executed by a processor causing the processor to: Obtaining visibility information for a primitive set in at least one frame associated with the graphics process, wherein the at least one frame includes a plurality of bins such that at least one bin of the plurality of bins includes at least one primitive in the primitive set; configuring a density map based on the visibility information for the set of primitives, wherein the density map includes density data associated with an amount of the set of primitives in each of the plurality of bins; and The density data for each bin of the plurality of bins is mapped to a shading rate for each bin of the plurality of bins.

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