Display panel and display device

Abstract

The invention discloses a display panel. The display panel comprises a plurality of first sub-pixels, a plurality of second sub-pixels, a first signal line and a second signal line. The plurality of second sub-pixels at least partially surround the plurality of first sub-pixels. The first signal line is electrically connected with the first sub-pixel and is configured to transmit at least one of a first positive voltage signal, a first negative voltage signal, a first initial voltage signal and a data signal to the first sub-pixel. And the second signal line is electrically connected with the second sub-pixel and is configured to transmit at least one of a second positive voltage signal, a second negative voltage signal, a second initial voltage signal and a data signal to the first sub-pixel. Wherein under the condition that the same gray scale is displayed, the brightness of the first sub-pixel is smaller than that of the second sub-pixel.

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the rapid development of display technology, large-format display (LFD) technology has gradually become a development demand of the display industry. One of the main methods for achieving large-screen display is to splice multiple display panels together to form an ultra-large spliced ​​display device (spliced ​​screen). Spliced ​​display devices contain splicing seams between the multiple display panels. How to reduce the impact of splicing seams on spliced ​​display devices is an urgent problem that needs to be solved in current splicing screens.

[0003] Summary of the Invention

[0004] In one aspect, a display panel is provided. The display panel includes a plurality of first sub-pixels, a plurality of second sub-pixels, a first signal line, and a second signal line. The plurality of second sub-pixels at least partially surround the plurality of first sub-pixels. The first signal line is electrically connected to the first sub-pixels and configured to transmit at least one of a first positive voltage signal, a first negative voltage signal, a first initial voltage signal, and a data signal to the first sub-pixels. The second signal line is electrically connected to the second sub-pixels and configured to transmit at least one of a second positive voltage signal, a second negative voltage signal, a second initial voltage signal, and a data signal to the second sub-pixels. When displaying the same grayscale, the brightness of the first sub-pixels is lower than that of the second sub-pixels.

[0005] In some embodiments, the first signal line includes a first positive voltage signal line configured to transmit a first positive voltage signal. The second signal line includes a second positive voltage signal line configured to transmit a second positive voltage signal. The first positive voltage signal has a voltage value less than the second positive voltage signal.

[0006] In some embodiments, the plurality of second sub-pixels surround the plurality of first sub-pixels. The second positive voltage signal line extends along a circumferential edge of the plurality of first sub-pixels, and the second positive voltage signal line is electrically connected to the plurality of second sub-pixels. The display panel includes a plurality of conductive layers, and the first positive voltage signal line and the second positive voltage signal line are located on different conductive layers.

[0007] In some embodiments, at least some of the plurality of second sub-pixels are arranged in multiple columns, at least one column of second sub-pixels is provided on both sides of the plurality of first sub-pixels along a first direction, and the column of second sub-pixels includes a plurality of second sub-pixels arranged along a second direction; the first direction and the second direction intersect. The display panel includes a plurality of second positive voltage signal lines, each of which is electrically connected to a column of second sub-pixels. The display panel includes multiple conductive layers, and the first positive voltage signal lines and the second positive voltage signal lines are provided on the same layer.

[0008] In some embodiments, the display panel has a display area and a peripheral area, wherein the plurality of first sub-pixels and the plurality of second sub-pixels are located in the display area; the peripheral area surrounds the display area. The display panel further includes a positive voltage signal bus disposed in the peripheral area and surrounding the display area. The first positive voltage signal line and the second positive voltage signal line are both electrically connected to the positive voltage signal bus, and the line width of the first positive voltage signal line is smaller than the line width of the second positive voltage signal line.

[0009] In some embodiments, the display panel has a display area and a peripheral area, wherein the plurality of first sub-pixels and the plurality of second sub-pixels are located in the display area; the peripheral area surrounds the display area. The display panel further includes a first positive voltage signal bus and a second positive voltage signal bus. The first positive voltage signal bus is disposed in the peripheral area and surrounds the display area, and is configured to transmit the first positive voltage signal. The second positive voltage signal bus is disposed in the peripheral area and surrounds the display area, and is configured to transmit the second positive voltage signal. The first positive voltage signal line is electrically connected to the first positive voltage signal bus, and the second positive voltage signal line is electrically connected to the second positive voltage signal bus.

[0010] In some embodiments, the first sub-pixel includes a first pixel circuit and a first light-emitting device, the first pixel circuit including a first node, the first node being electrically connected to the first light-emitting device. The second sub-pixel includes a second pixel circuit and a second light-emitting device, the second pixel circuit including a second node, the second node being electrically connected to the second light-emitting device. The first signal line also includes a first initial voltage signal line, the first initial voltage signal line being configured to transmit a first initial voltage signal and to initialize the first node. The second signal line also includes a second initial voltage signal line, the second initial voltage signal line being configured to transmit a second initial voltage signal and to initialize the second node. The voltage value of the first initial voltage signal is greater than the voltage value of the second initial voltage signal.

[0011] In some embodiments, the plurality of second sub-pixels surround the plurality of first sub-pixels. The second initial voltage signal line extends along a circumferential edge of the plurality of first sub-pixels. The display panel includes a plurality of conductive layers, and the first initial voltage signal line and the second initial voltage signal line are located in different conductive layers.

[0012] In some embodiments, at least some of the plurality of second sub-pixels are arranged in multiple rows, each side of the plurality of first sub-pixels along the second direction includes at least one row of second sub-pixels, and the row of second sub-pixels includes multiple second sub-pixels arranged along the first direction; the first direction and the second direction intersect. The second initial voltage signal lines extend along the first direction, and each second initial voltage signal line is electrically connected to a row of second sub-pixels. The display panel includes multiple conductive layers, and the first initial voltage signal lines and the second initial voltage signal lines are disposed on the same layer.

[0013] In some embodiments, the first sub-pixel includes a first light-emitting device, and the second sub-pixel includes a second light-emitting device. The first signal line further includes a first negative voltage signal line, which is configured to transmit the first negative voltage signal and is electrically connected to the cathode of the first light-emitting device. The second signal line further includes a second negative voltage signal line, which is configured to transmit the second negative voltage signal and is electrically connected to the cathode of the second light-emitting device. The voltage value of the first negative voltage signal is greater than the voltage value of the second negative voltage signal.

[0014] In some embodiments, the first negative voltage signal line and the second negative voltage signal line are disposed in the same layer, and there is a gap between the first negative voltage signal line and the second negative voltage signal line.

[0015] In some embodiments, the first signal line includes a first data signal line, the second signal line includes a second data signal line, and a resistance of the first data signal line is smaller than a resistance of the second data signal line.

[0016] In some embodiments, the plurality of second sub-pixels surround the plurality of first sub-pixels. The display panel includes a plurality of conductive layers; the first data signal line and the second data signal line are located in different conductive layers, and the resistivity of the material of the first data signal line is lower than the resistivity of the material of the second data signal line.

[0017] In some embodiments, at least some of the plurality of second sub-pixels are arranged in multiple columns, at least one column of second sub-pixels is provided on both sides of the plurality of first sub-pixels along a first direction, and the column of second sub-pixels includes a plurality of second sub-pixels arranged along a second direction. The first direction and the second direction intersect. The display panel includes multiple conductive layers. The first data signal line and the second data signal line are located on the same conductive layer, and the line width of the first data signal line is greater than the line width of the second data signal line.

[0018] In some embodiments, the first subpixel includes a first drive transistor and a first capacitor, one plate of the first capacitor being electrically connected to the gate of the first drive transistor. The second subpixel includes a second drive transistor and a second capacitor, one plate of the second capacitor being electrically connected to the gate of the second drive transistor. The capacitance of the second capacitor is greater than the capacitance of the first capacitor.

[0019] In some embodiments, a facing area between at least two plates included in the second capacitor is larger than a facing area between at least two plates included in the first capacitor.

[0020] In some embodiments, the second capacitor includes a greater number of plates than the first capacitor.

[0021] In some embodiments, the first sub-pixel includes a first driving transistor, the second sub-pixel includes a second driving transistor, and a width-to-length ratio of a channel structure of the first driving transistor is smaller than a width-to-length ratio of a channel structure of the second driving transistor.

[0022] In some embodiments, the display panel has a display area and a binding area located on one side of the display area, the binding area is provided with a connecting pin and a dummy pin, the first signal line is electrically connected to the connecting pin, and the second signal line is electrically connected to the connecting pin and / or the dummy pin.

[0023] In another aspect, a display device is provided, comprising a plurality of display panels according to any one of the above embodiments, wherein a seam is formed between two adjacent display panels, the display panels include a first side edge proximate to the seam, and a second sub-pixel in the display panel is closer to the first side edge than the first sub-pixel. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0025] FIG1 is a structural diagram of a display device according to some embodiments;

[0026] FIG2 is a planar structural diagram of a display panel according to some embodiments;

[0027] FIG3 is a cross-sectional structural diagram of a display panel according to some embodiments;

[0028] FIG4 is an equivalent circuit diagram of a pixel circuit according to some embodiments;

[0029] FIG5 is a structural diagram of a display panel including a first signal line and a second signal line according to some embodiments;

[0030] 6 to 15 are structural diagrams of display panels according to some embodiments. DETAILED DESCRIPTION

[0031] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0032] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0033] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0034] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0035] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0036] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0037] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0038] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0039] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0040] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0041] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0042] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0043] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0044] Referring to FIG. 1 , FIG. 1 is a structural diagram of a spliced ​​display device. Some embodiments of the present disclosure provide a display device 1000 . The display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images. The display device 1000 can be a large-size display device. For example, the display device 1000 can be a spliced ​​screen display device using LFD technology, and the display device 1000 is composed of multiple display panels 1100 spliced ​​together.

[0045] According to the light-emitting method of the display device 1000, the display device 1000 can be classified as a light-emitting diode (LED) liquid crystal splicing display device, an organic light-emitting diode (OLED) self-luminous splicing display device, or a digital light processing (DLP) rear-projection splicing display device. Among them, the OLED self-luminous splicing display device has the advantages of self-luminescence and no light leakage. At the same time, compared with LCD displays, the OLED self-luminous splicing display device has the advantages of wider viewing angle, faster response, simple structure, ultra-thin design, etc. due to the lack of a liquid crystal layer. It is also easier to achieve high-end splicing display devices such as seamless splicing, anisotropic splicing, and curved splicing. Therefore, it has received more and more attention.

[0046] For example, in the following embodiments of the present disclosure, some embodiments of the present disclosure are schematically described by taking the display device 1000 as an OLED self-luminous spliced ​​display device as an example, but the implementation methods of the present disclosure are not limited to this, and any other display devices can also be considered as long as the same technical ideas are applied.

[0047] As shown in FIG1 , a display device 1000 includes a plurality of display panels 1100, which are spliced ​​together to form the display device 1000. Specifically, if the display device 1000 is an OLED self-luminous spliced ​​display device, the display panels 1100 may be OLED display panels. A splicing seam 1200 is provided between each two adjacent display panels 1100. The side of the display panel 1100 close to the splicing seam 1200 is a first side 1101, and the side close to the edge of the display device 1000 is a second side 1102.

[0048] For example, as shown in FIG1 , the display device 1000 includes 20 display panels 1100 arranged in an array (4 rows and 5 columns), wherein the sides of the 6 display panels 1100 located in the middle of the display device 1000 are all first sides. The display panels 1100 near the edge of the display device 1000 include a first side 1101 and a second side 1102, and the second side 1102 is close to the edge of the display device 1000.

[0049] As shown in Figure 2, Figure 2 is a planar structural diagram of a single display panel 1100. Display panel 1100 includes a display area AA and a peripheral area BB. Display area AA is provided with a plurality of sub-pixels P. A sub-pixel P is the smallest light-emitting unit in display panel 1100 and is used to display images. The plurality of sub-pixels P are arranged in a matrix in multiple rows and columns within display area AA. Each row of sub-pixels X includes a plurality of sub-pixels P arranged along a first direction X, and the plurality of rows of sub-pixels P are arranged along a second direction Y. Each column of sub-pixels P includes a plurality of sub-pixels P arranged along the second direction Y, and the plurality of columns of sub-pixels P are arranged along the first direction X.

[0050] 1 and 2 , the display device 1000 has an overall display area AA′, and an area of ​​the display area AA of the multiple display panels 1100 of the display device 1000 away from the joint 1200 (the third display area AA3) is referred to as the first display area AA1, and an area close to the joint 1200 is referred to as the second display area AA2. The first display area AA1 and the second display area AA2 together constitute the overall display area AA′ of the display device 1000.

[0051] Exemplarily, at least one sub-pixel P is included between the first display area AA1 and the stitching seam 1200; the second display area AA2 may include the stitching seam 1200, the peripheral area BB of the display panel 1100 near the stitching seam 1200, and at least one row of sub-pixels P or at least one column of sub-pixels P near the first side 1101 (fourth display area AA4).

[0052] Since the joint seam 1200 has a certain width, that is, there is a certain gap between two adjacent display panels 1100, the display panel 1100 has a peripheral area BB, and no sub-pixels P are set in the peripheral area BB, resulting in the pixel density in the second display area AA2 being lower than the pixel density in the display area AA of the display panel 1100.

[0053] To prevent the brightness of the second display area AA2 from being lower than that of the first display area AA1 when displaying the same grayscale, related art uses an algorithmic compensation solution. This performs optical algorithmic compensation on the entire display area AA' of the display device 1000, altering the grayscale levels of sub-pixels in different areas and increasing the brightness of the sub-pixels within the second display area AA2, thereby achieving a uniform display. However, this algorithmic compensation solution reduces the luminance of the sub-pixels P within the first display area AA1, resulting in a lower overall luminance of the display device 1000, which is detrimental to improving the display quality of the display device 1000.

[0054] In order to solve the above technical problems, referring to Figure 2, the display panel 1100 provided in the embodiment of the present disclosure includes the display panel 1100 provided in the embodiment of the present disclosure including multiple first sub-pixels P1 and multiple second sub-pixels P2, that is, the multiple sub-pixels P included in the display panel 1100 can be divided into multiple first sub-pixels P1 and second sub-pixels P2.

[0055] The plurality of first sub-pixels P1 can be arranged in multiple rows and columns, with each row comprising a plurality of first sub-pixels P1 arranged along a first direction X, and the rows of first sub-pixels P1 arranged along a second direction Y. Each column comprises a plurality of second sub-pixels P2 arranged along the second direction Y, and the columns of second sub-pixels P2 are arranged along the first direction X. The plurality of second sub-pixels P2 at least partially surround the plurality of first sub-pixels P1. In the embodiment of the present disclosure, the area where the plurality of first sub-pixels P1 are located is defined as a third display area AA3, and the area where the plurality of second sub-pixels P2 are located is defined as a fourth display area AA4, with the fourth display area AA4 at least partially surrounding the third display area AA3.

[0056] In some embodiments, the plurality of second sub-pixels P2 may surround the plurality of first sub-pixels P1, that is, the fourth display area AA4 surrounds the third display area AA3. Alternatively, the plurality of second sub-pixels P2 may be arranged along the extension direction of the first side 1101 of the display panel 1100, that is, the second sub-pixels P2 may be disposed only near the first side 1101 of the display panel 1100.

[0057] Exemplarily, the first subpixel P1 is located in the first display area AA1 of the display device 1000, and the second subpixel P2 is located in the second display area AA2 of the display device 1000. In other words, the third display areas AA3 of the multiple display panels 1100 collectively constitute the first display area AA1 of the display device, and the fourth display areas BB2 of the multiple display panels 1100, the seams 1200 between the multiple display panels 1100, and the peripheral area between the fourth display areas BB2 and the seams 1200 collectively constitute the second display area AA2.

[0058] Multiple sub-pixels P can emit light of the same color, such as white light or blue light. Based on this, the display panel 1100 also includes a color filter layer arranged on the display side, that is, the display panel 1100 adopts a COE (full name in English: CF on Encapsulation; Chinese name: color filter layer on encapsulation film) structure. Alternatively, multiple sub-pixels P can emit light of different colors. For example, multiple sub-pixels P include red sub-pixels that emit red light, green sub-pixels that emit green light, and blue sub-pixels that emit blue light. Exemplarily, the multiple sub-pixels P can be divided into multiple pixel units, each pixel unit including a red sub-pixel, a blue sub-pixel, and one (or two) green sub-pixels.

[0059] As shown in FIG3 , when the display panel 1100 is an OLED display panel, the display panel 1100 may include a stacked array substrate 100, a plurality of light-emitting devices 200, and an encapsulation layer 300. Of course, the display panel 1100 may also include a functional stack disposed on a side of the encapsulation layer 300 away from the array substrate 100. The functional stack may include, for example, one or more of a touch function layer, an anti-reflection layer, a hardening layer, a color filter layer (the display panel adopts a COE structure), and an anti-fingerprint layer, so that the display panel 1100 can achieve corresponding functions. The embodiments of the present disclosure do not specifically limit the type and number of the above-mentioned functional stacks.

[0060] In some embodiments, referring to FIG. 3 , the array substrate 100 may include a substrate 10 , a semiconductor layer Poly disposed on the substrate 10 , and a plurality of conductive layers 20 disposed on a side of the semiconductor layer Poly away from the substrate 10 .

[0061] As an example, as shown in FIG3 , the plurality of conductive layers 20 include a first gate conductive layer 21, a second gate conductive layer 22, a first source-drain conductive layer 23, and a second source-drain conductive layer 24, which are sequentially arranged along a direction Z away from the substrate 10. However, the embodiments of the present disclosure are not limited thereto. The plurality of conductive layers 20 may also include other film layers. For example, the plurality of conductive layers 20 may include a third gate conductive layer, a third source-drain conductive layer, or other film layers. Display devices including any other conductive layers may be considered, as long as the same technical concepts are applied. The array substrate 100 may also include an insulating layer disposed between adjacent conductive layers 20, which will not be described in detail here.

[0062] 3 , the light-emitting device 200 may include, for example, a stacked anode 201, a light-emitting functional layer 202, and a cathode layer 203. The display panel 1100 may further include a pixel defining layer (PDL), which is disposed on a side of the anode 201 away from the array substrate 100 and includes a plurality of openings, with each light-emitting device 200 located within an opening region.

[0063] The encapsulation layer 300 is configured to reduce the risk of moisture and oxygen from the external environment entering the light-emitting device 200, thereby increasing the service life of the display panel 1100. The encapsulation layer 300 can be an encapsulation film or an encapsulation substrate. For example, as shown in FIG3 , the encapsulation layer 300 can be an encapsulation film. In this case, the encapsulation layer 300 can include a first inorganic encapsulation layer 301, an organic encapsulation layer 302, and a second inorganic encapsulation layer 303, which are stacked in sequence.

[0064] Each sub-pixel P includes a pixel circuit and a light-emitting device 200 electrically connected to the pixel circuit. The pixel circuit includes multiple thin-film transistors (TFTs) and at least one capacitor Cst. For example, the pixel circuit can be a "7T1C" circuit or an "8T1C" circuit, where "T" refers to TFT and the number before "T" refers to the number of TFTs; "C" refers to capacitor Cst and the number before "C" refers to the number of capacitors Cst. The thin-film transistor can be a P-type transistor or an N-type transistor. The P-type transistor is turned on by a low level and turned off by a high level; the N-type transistor is turned on by a high level and turned off by a low level.

[0065] As shown in FIG3 , the TFT may include a semiconductor pattern 101 located on the semiconductor layer Poly, a gate electrode 102 located on the first gate conductive layer 21, and a source electrode 103 and a drain electrode 104 located on the first source-drain conductive layer 23. The capacitor Cst may include a first electrode 106 located on the first gate conductive layer 21 and a second electrode 107 located on the second gate conductive layer 22. The orthographic projections of the first electrode 106 and the second electrode 107 on the substrate 10 at least partially overlap.

[0066] In the following embodiments of the present disclosure, as shown in FIG4 , a pixel circuit is a “7T1C” circuit, and the thin film transistor included in the pixel circuit is a P-type transistor as an example for schematic illustration, but the implementation of the present disclosure is not limited thereto, and any other pixel circuits may also be considered, as long as the same technical concept is applied.

[0067] Taking the first subpixel P1 as an example, the first subpixel P1 includes a first pixel circuit 410. As shown in FIG4 , the first pixel circuit 410 includes a first drive transistor DT10, a third reset transistor T11, a compensation transistor T12, a data write transistor T13, a first emission control transistor T14, a second emission control transistor T15, a first reset transistor T16, and a first capacitor Cst1. The first drive transistor DT10 has a gate electrically connected to the third node N3, a source electrically connected to the fourth node N4, and a drain electrically connected to the fifth node N5.

[0068] The third reset transistor T11 has a gate electrically connected to the initialization signal line Reset, a source electrically connected to the third initial voltage signal line VINIT3, and a drain electrically connected to the third node N3. The compensation transistor T12 has a gate electrically connected to the first scan signal line GL1, a source electrically connected to the fourth node N4, and a drain electrically connected to the fifth node N5. The data write transistor T13 has a gate electrically connected to the first scan signal line GL1, a source electrically connected to the first data signal line DL1, and a drain electrically connected to the fourth node N4. The first emission control transistor T14 has a gate electrically connected to the emission control signal line EM, a source electrically connected to the first positive voltage signal line VDD1, and a drain electrically connected to the fourth node N4. The second emission control transistor T15 has a gate electrically connected to the emission control signal line EM, a source electrically connected to the fifth node N5, and a drain electrically connected to the first node N1. The first node N1 is also electrically connected to the first light-emitting device 210. The first reset transistor T16 has a gate electrically connected to the second scan signal line GL2, a source electrically connected to the first initial voltage signal line VINIT1, and a drain electrically connected to the first node N1. One plate of the first capacitor Cst1 is electrically connected to the first positive voltage signal line VDD1, and the other plate is electrically connected to the third node N3.

[0069] It is understood that the second sub-pixel P2 includes a second pixel circuit 420, which includes a second driving transistor DT20, a third reset transistor T21, a compensation transistor T22, a data writing transistor T23, a first emission control transistor T24, a second emission control transistor T25, a second reset transistor T26, and a second capacitor Cst2. The structure and connection relationship of the second pixel circuit 420 are similar to those of the first pixel circuit 410 and are not further described here.

[0070] FIG5 is a structural diagram of a display panel including first signal lines 30 and second signal lines 40. Referring to FIG2 and FIG5 , the display panel 1100 further includes first signal lines 30 and second signal lines 40. The first signal line 30 is electrically connected to the first subpixel P1 and is configured to transmit at least one of a first positive voltage signal Vdd1, a first negative voltage signal Vss1, a first initialization voltage signal Vinit1, and a data signal Data1 to the first subpixel P1. The second signal line 40 is electrically connected to the second subpixel P2 and is configured to transmit at least one of a second positive voltage signal Vdd2, a second negative voltage signal Vss2, a second initialization voltage signal Vinit2, and a data signal Data2 to the second subpixel P2.

[0071] It can be understood that in FIG5 , the first signal line 30 is identified by a thin solid line, and the second signal line 40 is identified by a thick solid line. The first signal line 30 and the second signal line 40 are insulated from each other so that the first signal line 30 and the second signal line 40 can transmit different voltage signals respectively.

[0072] When displaying the same grayscale, the brightness of the first subpixel P1 is lower than that of the second subpixel P2. In other words, when displaying the same grayscale, the first subpixel P1 displays a first brightness under the control of the first signal line 30, and the second subpixel P2 displays a second brightness under the control of the second signal line 40, with the first brightness being lower than the second brightness. Increasing the brightness of the second subpixel P2 can increase the overall brightness of the second display area AA2 of the display device 1000, reduce the brightness difference between the second display area AA2 and the first display area AA1, and improve the brightness uniformity of the entire display area of ​​the display device 1000. This also helps increase the maximum brightness within the first display area AA1, and thus the maximum brightness of the first subpixel P1, thereby improving the display quality of the display device 1000.

[0073] It is understood that the first signal line 30 may include multiple signal lines. For example, the first signal line 30 may include at least one of a first positive voltage signal line VDD1, a first negative voltage signal line VSS1, a first data line DL1, and a first initial voltage signal line VINIT1. Similarly, the second signal line 40 may include multiple signal lines. For example, the second signal line 40 may include at least one of a second positive voltage signal line VDD2, a second negative voltage signal line VSS2, a second data line DL2, and a second initial voltage signal line VINIT2.

[0074] In some embodiments, referring to FIG. 6 , FIG. 6 is a structural diagram of a display panel 1100 including a first positive voltage signal line VDD1 and a second positive voltage signal line VDD2 .

[0075] The first signal lines 30 include a first positive voltage signal line VDD1, which is configured to transmit a first positive voltage signal Vdd1. The first positive voltage signal Vdd1 may also be referred to as a first operating voltage signal or a first power supply signal. The first positive voltage signal line VDD1 is electrically connected to the pixel circuit of the first sub-pixel P1.

[0076] The second signal line 40 includes a second positive voltage signal line VDD2 configured to transmit a second positive voltage signal Vdd2 . The second positive voltage signal line VDD2 is electrically connected to the pixel circuit of the second sub-pixel P2 .

[0077] As shown in Figure 4, the first positive voltage signal line VDD1 is electrically connected to the source of the first emission control transistor T14 and is configured to transmit the first positive voltage signal Vdd1 to the source of the first drive transistor DT10 when the first emission control transistor T14 is turned on. The drive current of the first drive transistor DT10 is positively correlated with the voltage value of the first positive voltage signal Vdd1. The brightness of the light-emitting device 200 is positively correlated with the current flowing through the light-emitting device. The voltage value of the first positive voltage signal Vdd1 is lower than the voltage value of the second positive voltage signal Vdd2. This allows the drive current of the first drive transistor DT10 to be lower than the drive current of the second drive transistor DT20 when the first data signal Data and the second data signal Data2 are identical (displaying the same grayscale). The brightness of the second subpixel P2 is higher than that of the first subpixel P1, which helps improve the brightness uniformity across the entire display area AA' of the display device 1000 and enhances the display quality of the display device 1000.

[0078] In some embodiments, as shown in FIG6 , when multiple second sub-pixels P2 surround multiple first sub-pixels P1, the second positive voltage signal line VDD2 can extend along the circumferential edges of the multiple first sub-pixels P1. That is, the second positive voltage signal line VDD2 can extend in a ring shape along the arrangement direction of the second sub-pixels P2, or in other words, the second positive voltage signal line VDD2 extends in a ring shape along the extension direction of the fourth display area AA4. The second positive voltage signal line VDD2 is electrically connected to the multiple second sub-pixels P2 (all the second sub-pixels P2). This facilitates the electrical connection of the second positive voltage signal line VDD2 to the multiple second sub-pixels P2 and ensures that the second positive voltage signal Vdd2 received by all second sub-pixels P2 is the same in magnitude.

[0079] As shown in FIG6 , the display panel 1100 may include a plurality of first positive voltage signal lines VDD1 spaced apart along a first direction X, each first positive voltage signal line VDD1 extending substantially along a second direction Y, and each first positive voltage signal line VDD1 electrically connected to a column of first sub-pixels P1.

[0080] The first positive voltage signal line VDD1 and the second positive voltage signal line VDD2 are located in different conductive layers 20 to avoid signal interference between the first positive voltage signal line VDD1 and the second positive voltage signal line VDD2 and increase wiring space for the first positive voltage signal line VDD1 and the second positive voltage signal line VDD2.

[0081] Of course, when the first positive voltage signal line VDD1 and the second positive voltage signal line VDD2 are located in different conductive layers 20, the display panel 1100 may also include a plurality of second positive voltage signal lines VDD2 spaced apart along the first direction X, and each second positive voltage signal line VDD2 is electrically connected to a plurality of second sub-pixels P2 located in a column.

[0082] In other embodiments, referring to FIG. 7 , at least a portion of the plurality of second sub-pixels P2 are arranged in multiple columns, and at least one column of second sub-pixels P2 is provided on both sides of the plurality of first sub-pixels P1 along the first direction X. A column of second sub-pixels P2 includes a plurality of second sub-pixels P2 arranged along the second direction Y. The first direction X and the second direction Y intersect, and illustratively, the first direction X and the second direction Y are perpendicular to each other.

[0083] The display panel 1100 includes a plurality of second positive voltage signal lines VDD2, each of which is electrically connected to a column of second sub-pixels P2. In other words, the second positive voltage signal lines VDD2 can be electrically connected only to the second sub-pixels P2 on both sides of the plurality of first sub-pixels P1 along the first direction X. Based on this, the second positive voltage signal lines VDD2 can be located on the same conductive layer as the first positive voltage signal lines VDD1. This helps reduce the number of conductive layers 20 in the display panel 1100, lowering the manufacturing cost of the display panel 1100 and reducing the thickness of the display panel 1100.

[0084] In some other embodiments, referring to FIG. 8 , FIG. 8 is a structural diagram illustrating a display panel 1100 including a positive voltage signal bus VL. The display panel 1100 further includes a positive voltage signal bus VL, which is disposed in the peripheral area BB and surrounds the display area AA. A first positive voltage signal line VDD1 and a second positive voltage signal line VDD2 are both electrically connected to the positive voltage signal bus VL, and the line width of the first positive voltage signal line VDD1 is smaller than the line width of the second positive voltage signal line VDD2. This ensures that the resistance of the second positive voltage signal line VDD2 is smaller than the resistance of the first positive voltage signal line VDD1, and that the voltage drop of the second positive voltage signal Vdd2 on the second positive voltage signal line VDD2 is smaller than the voltage drop of the first positive voltage signal Vdd1 on the first positive voltage signal line VDD1. This ensures that the voltage value of the second positive voltage signal Vdd2 is greater than the voltage value of the first positive voltage signal line VDD1. This helps reduce the number of wirings in the peripheral area BB, decreases the width of the peripheral area BB, and further reduces the width of the joint seam 1200 , thereby improving the display effect of the display device.

[0085] In some other embodiments, referring to FIG. 9 , FIG. 9 is a structural diagram of a display panel including a first positive voltage signal bus VL1 and a second positive voltage signal bus VL2. The display panel 1100 further includes a first positive voltage signal bus VL1 and a second positive voltage signal bus VL2. The first positive voltage signal bus VL1 is disposed in the peripheral area BB and surrounds the display area AA. The first positive voltage signal bus VL1 is configured to transmit a first positive voltage signal Vdd1. The second positive voltage signal bus VL2 is disposed in the peripheral area BB and surrounds the display area AA. The second positive voltage signal bus VL2 is configured to transmit a second positive voltage signal Vdd2. The first positive voltage signal bus VL1 and the second positive voltage signal bus VL2 are electrically isolated from each other, and the voltage value of the second positive voltage signal Vdd2 is greater than the voltage value of the first positive voltage signal Vdd1.

[0086] The first positive voltage signal line VDD1 is electrically connected to the first positive voltage signal bus VL1, and the second positive voltage signal line VDD2 is electrically connected to the second positive voltage signal bus VL2. In other words, the first positive voltage signal line VDD1 and the second positive voltage signal line VDD2 transmit signals via two different buses, which helps improve the stability and accuracy of the second positive voltage signal Vdd2 and the first positive voltage signal Vdd1.

[0087] In some embodiments, as shown in FIG4 , the first subpixel P1 includes a first pixel circuit 410 and a first light-emitting device 210, the first pixel circuit including a first node N1 electrically connected to the first light-emitting device 210. The second subpixel P2 includes a second pixel circuit 420 and a second light-emitting device 220, the second pixel circuit 420 including a second node N2 electrically connected to the second light-emitting device 220.

[0088] In some embodiments, referring to FIG. 10 , FIG. 10 illustrates a structure of a display panel 1100 including a first initial voltage signal line VINIT1 and a second initial voltage signal line VINIT2. The first signal line 30 further includes a first initial voltage signal line VINIT1, which is configured to transmit a first initial voltage signal Vinit1 and initialize the first node N1. The second signal line 40 further includes a second initial voltage signal line VINIT2, which is configured to transmit a second initial voltage signal Vinit2 and initialize the second node N2.

[0089] The inventors have discovered that the lower the initial voltage value of the first node N1 (or N2), the greater the drive current generated by the pixel circuit. The voltage value of the first initial voltage signal Vinit1 is greater than the voltage value of the second initial voltage signal Vinit2. Based on this, it is beneficial to increase the drive current of the second pixel circuit 420 (compared to the drive current of the first pixel circuit 410), thereby increasing the brightness of the second light-emitting device 220, and thus increasing the overall brightness of the second display area AA2 in the display device 1000, reducing the brightness difference between the second display area AA2 and the first display area AA1, improving the brightness uniformity of the entire display area of ​​the display device 1000, and helping to increase the maximum brightness within the first display area AA1, and thus the maximum brightness of the first sub-pixel P1, thereby improving the display effect of the display device 1000.

[0090] Continuing with FIG. 10 , multiple second sub-pixels P2 surround multiple first sub-pixels P1. The second initial voltage signal line VINIT2 extends along the circumferential edges of the multiple first sub-pixels P1 and is electrically connected to the multiple second sub-pixels P2 (all the second sub-pixels P2). In other words, the second initial voltage signal line VINIT2 can extend in a ring shape along the arrangement direction of the second sub-pixels P2, or in other words, the second initial voltage signal line VINIT2 extends in a ring shape along the extension direction of the fourth display area AA4. The second initial voltage signal line VINIT2 is electrically connected to the multiple second sub-pixels P2 (all the second sub-pixels P2). This facilitates the electrical connection of the second initial voltage signal line VINIT2 with all the second sub-pixels P2, and ensures that the voltage value of the second initial voltage signal Vinit2 received by all the second sub-pixels P2 is the same.

[0091] As shown in FIG10 , the display panel 1100 further includes a plurality of first initial voltage signal lines VINIT1 spaced apart along the second direction Y. Each first initial voltage signal line VINIT1 extends substantially along the first direction X and is electrically connected to a row of first sub-pixels P1.

[0092] The display panel 1100 includes a plurality of conductive layers 20, and the first initial voltage signal line VINIT1 and the second initial voltage signal line VINIT2 are located on different conductive layers to prevent signal interference between the first initial voltage signal line VINIT1 and the second initial voltage signal line VINIT2 and to increase wiring space for the first initial voltage signal line VINIT1 and the second initial voltage signal line VINIT2.

[0093] Of course, when the first initial voltage signal line VINIT1 and the second initial voltage signal line VINIT2 are located in different conductive layers 20, the display panel 1100 may also include a plurality of second initial voltage signal lines VINIT2 spaced apart along the second direction Y, and each second initial voltage signal line VINIT2 is electrically connected to a plurality of second sub-pixels P2 located in a row (not shown in the figure).

[0094] In other embodiments, referring to FIG. 11A , FIG. 11A illustrates a structure in which the second initial voltage signal line VINIT2 extends along the first direction X. At least a portion of the plurality of second sub-pixels P2 are arranged in multiple rows, and at least one row of second sub-pixels P2 is provided on both sides of the plurality of first sub-pixels P1 along the second direction Y. In other words, at least one row of second sub-pixels P2 is provided on both sides of the third display area AA3 along the second direction Y.

[0095] The display panel 1100 includes a plurality of second initial voltage signal lines VINIT2, each of which is electrically connected to a row of second subpixels P2. In other words, the second initial voltage signal lines VINIT2 can be electrically connected only to the second subpixels P2 on both sides of the plurality of first subpixels P1 along the second direction Y. Based on this, the second initial voltage signal lines VINIT2 can be located on the same conductive layer as the first initial voltage signal lines VINIT1. This helps reduce the number of conductive layers 20 in the display panel 1100, lowering the manufacturing cost of the display panel 1100 and reducing the thickness of the display panel 1100.

[0096] It can be understood that, as shown in Figure 11B, when the second initial voltage signal line VINIT2 and the first initial voltage signal line VINIT1 are located in different conductive layers, the second initial voltage signal line VINIT2 can also extend along the first direction X, and each second initial voltage signal line VINIT2 is electrically connected to a plurality of second sub-pixels P2 located in a row.

[0097] In some embodiments, the display panel 1100 may include an initial voltage signal bus, wherein both a first initial voltage signal line VINIT1 and a second initial voltage signal line VINIT2 are electrically connected to the initial voltage signal bus, and the line width of the first initial voltage signal line VINIT1 is smaller than the line width of the second initial voltage signal line VINIT2. Alternatively, the display panel 1100 includes a first initial voltage signal bus and a second initial voltage signal bus, wherein the first initial voltage signal bus is used to transmit the first initial voltage signal Vinit1, and the second initial voltage signal bus is used to transmit the second initial voltage signal Vinit2. The first initial voltage signal line VINIT1 is electrically connected to the first initial voltage signal bus, and the second initial voltage signal line VINIT2 is electrically connected to the second initial voltage signal bus.

[0098] In one specific embodiment, as shown in FIG12 , the plurality of second sub-pixels P2 are arranged in multiple rows and columns. At least one column of second sub-pixels P2 is provided on each side of the plurality of first sub-pixels P1 (third display area AA3) along the first direction X, and at least one row of second sub-pixels P2 is provided on each side of the plurality of first sub-pixels P1 (third display area AA3) along the second direction Y. The display panel 1100 includes a plurality of second positive voltage signal lines VDD2 and a plurality of second initial voltage signal lines VINIT2. Each second positive voltage signal line VDD2 is electrically connected to a column of second sub-pixels P2, and each second initial voltage signal line VINIT2 is electrically connected to a row of second sub-pixels P2.

[0099] As shown in Figure 12, the fourth display area AA4 can be divided into two first sub-areas AA41, two second sub-areas AA42, and four third sub-areas AA43. The two first sub-areas AA41 are located on either side of the third display area AA3 along the first direction X, the two second sub-areas AA42 are located on either side of the third display area AA3 along the second direction Y, and the four third sub-areas AA43 are located at the four corners of the fourth display area AA4. The second sub-pixels P2 in the two first sub-areas AA41 are electrically connected to the second voltage signal line VDD2 and the first initial voltage signal line VINIT1, respectively. The second sub-pixels P2 in the two second sub-areas AA42 are electrically connected to the first voltage signal line VDD1 and the second initial voltage signal line VINIT2, respectively. The second sub-pixels P2 in the four third sub-areas AA43 are electrically connected to both the second positive voltage signal line VDD2 and the second initial voltage signal line VINIT2. This minimizes the number of conductive layers 20, reducing the thickness and manufacturing cost of the display panel 1100.

[0100] Of course, it is understandable that the above-mentioned embodiments of the present disclosure can also be combined in other forms. For example, all the second sub-pixels P2 are electrically connected to the second positive voltage signal line VDD2 and the second initial voltage signal line VINIT2 at the same time. The embodiments of the present disclosure are not limited to this, as long as the same technical ideas of this application are applied.

[0101] In some embodiments, referring to FIG. 13 , the first signal line 30 further includes a first negative voltage signal line VSS1, which is configured to transmit a first negative voltage signal Vss1 and is electrically connected to the cathode of the first light-emitting device 210. The second signal line 40 further includes a second negative voltage signal line VSS2, which is configured to transmit a second negative voltage signal Vss2 and is electrically connected to the cathode of the second light-emitting device 220. The current of the light-emitting device 200 is negatively correlated with the voltage value of the cathode. That is, the lower the cathode voltage of the light-emitting device 200, the greater the current of the light-emitting device 200, and the higher the brightness of the light-emitting device 200. Therefore, the voltage value of the first negative voltage signal Vss1 is greater than the voltage value of the second negative voltage signal Vss2. This is beneficial to increasing the luminous brightness of the second light-emitting device 220, thereby increasing the overall brightness of the second display area AA2 in the display device 1000, reducing the brightness difference between the second display area AA2 and the first display area AA1, and improving the brightness uniformity of the entire display area of ​​the display device 1000. It is also beneficial to improving the maximum brightness within the first display area AA1, and thus the maximum luminous brightness of the first sub-pixel P1, thereby improving the display effect of the display device 1000.

[0102] In some embodiments, as shown in FIG13 , the first negative voltage signal line VSS1 and the second negative voltage signal line VSS2 are disposed on the same layer, with a gap between the first negative voltage signal line VSS1 and the second negative voltage signal line VSS. For example, as shown in FIG13 , the second negative voltage signal line VSS2 can be disposed around the first negative voltage signal line VSS1.

[0103] In some embodiments, the display panel 1100 includes a first negative voltage signal bus and a second negative voltage signal bus. The first negative voltage signal bus is used to transmit a first negative voltage signal Vss1, and the second negative voltage signal bus is used to transmit a second negative voltage signal Vss2. The first negative voltage signal line VSS1 is electrically connected to the first negative voltage signal bus, and the second negative voltage signal line VSS2 is electrically connected to the second negative voltage signal bus.

[0104] It is understandable that the first negative voltage signal line VSS1 and the second negative voltage signal line VSS can be electrically connected to the first negative voltage signal bus and a second negative voltage signal bus of the peripheral area BB through jumpers provided on other conductive layers.

[0105] As shown in FIG14 , in some embodiments, the first signal line 30 includes a first data signal line DL1, and the second signal line 40 includes a second data signal line DL2. The resistance of the first data signal line DL1 is less than the resistance of the second data signal line DL2. The luminance formula of the sub-pixel P in the OLED panel is: Lum∝1 / 2*μ*Cox*W / L*(V data -V th )^2 (1)

[0106] In the above formula (1), “Lum” is the brightness of the light-emitting device, “Cox” is the capacitance of the capacitor in the pixel circuit, “W / L” is the width-to-length ratio of the channel structure of the driving transistor, and “V data " is the voltage value of the data signal. From formula (1), it can be seen that the brightness of the light-emitting device is negatively correlated with the voltage value of the data signal, that is, V data The smaller (V data -V th ), the greater the difference, the greater the brightness of the light-emitting device.

[0107] For the above reasons, in the embodiment of the present disclosure, the resistance of the first data signal line DL1 is smaller than the resistance of the second data signal line DL2. This helps reduce the data signal transmitted by the second data signal line DL. That is, when the driver chip sends the same data signal Data, the voltage value of the data signal transmitted to the second sub-pixel P2 via the second data signal line DL2 is smaller than the voltage value of the data signal transmitted to the first sub-pixel P1 via the first data signal line DL1. This allows the second sub-pixel P2 to display a higher brightness (compared to the first sub-pixel P1), thereby increasing the overall brightness of the second display area AA2 in the display device 1000, reducing the brightness difference between the second display area AA2 and the first display area AA1, and improving the brightness uniformity of the entire display area of ​​the display device 1000. It also helps to increase the maximum brightness in the first display area AA1, and thus the maximum luminous brightness of the first sub-pixel P1, thereby improving the display effect of the display device 1000.

[0108] Referring to Figure 14, in the case where a plurality of second sub-pixels P2 surround a plurality of first sub-pixels P1, and all second sub-pixels P2 are electrically connected to the second data signal line DL2. The first data signal line DL1 and the second data signal line DL2 can be located in different conductive layers to avoid signal interference between the first data signal line DL1 and the second data signal line DL2, and to increase the wiring space of the first data signal line DL1 and the second data signal line DL2. The resistivity of the material of the first data signal line is lower than the resistivity of the material of the second data signal line, so that the resistance of the first data signal line DL1 is lower than the resistance of the second data signal line DL2. Exemplarily, the material of the first data line DL1 can be a metal material such as copper or a copper alloy; the second data line DL2 can be made of indium tin oxide (English: Indium Tin Oxides; abbreviated as: ITO).

[0109] In some other embodiments, as shown in FIG15 , at least a portion of the plurality of second sub-pixels P2 are arranged in multiple columns, and at least one column of second sub-pixels P2 is provided on both sides of the plurality of first sub-pixels P1 along the first direction X. A column of second sub-pixels P2 includes a plurality of second sub-pixels P2 arranged along the second direction Y.

[0110] Each second data line DL2 is electrically connected to a column of second subpixels P2. That is, the second data line DL2 is electrically connected only to the second subpixels P2 on both sides of the third display area AA3 along the first direction X. In this case, the first data signal line DL1 and the second data signal line DL2 can be located on the same conductive layer, and the line width of the first data signal line DL1 is greater than the line width of the second data signal line DL2. This helps reduce the number of conductive layers 20 in the display panel 1100, lowering the manufacturing cost and thickness of the display panel 1100. Furthermore, the line width of the first data signal line DL1 is greater than the line width of the second data signal line DL2. This allows the resistance of the first data signal line DL1 to be lower than that of the second data signal line DL2, resulting in a lower brightness of the first subpixel P1 than the second subpixel P2 when the first subpixel P1 and the second subpixel P2 display the same grayscale.

[0111] In some embodiments, the first subpixel P includes a first drive transistor DT10 and a first capacitor Cst1, wherein one plate of the first capacitor Cst1 is electrically connected to the gate of the first drive transistor DF1. The second subpixel P2 includes a second drive transistor DT20 and a second capacitor Cst2, wherein one plate of the second capacitor Cst2 is electrically connected to the gate of the second drive transistor DT20. As can be seen from the above formula (1), the brightness of the light-emitting device 200 is also positively correlated with the capacitance of the capacitor Cst. The larger the capacitance of the capacitor Cst, the more charge stored in the capacitor plate, the more stable the capacitor voltage, and the more stable the pixel's ability to emit light. Based on this, the capacitance of the second capacitor Cst2 is greater than the capacitance of the first capacitor Cst1, which is beneficial to improving the luminous brightness of the second sub-pixel P2, and can increase the overall brightness of the second display area AA2 in the display device 1000, reduce the brightness difference between the second display area AA2 and the first display area AA1, and improve the brightness uniformity of the entire display area of ​​the display device 1000. It is also beneficial to improve the maximum brightness in the first display area AA1, and thus the maximum luminous brightness of the first sub-pixel P1, thereby improving the display effect of the display device 1000.

[0112] In some embodiments, the facing area between the at least two plates included in the second capacitor Cst2 is larger than the facing area between the at least two plates included in the first capacitor Cst1. In this way, the capacitance of the second capacitor Cst2 can be greater than the capacitance of the first capacitor Cst1, which is beneficial to reducing the number of conductive layers 20 of the display panel 1100 and reducing the thickness and preparation cost of the display panel 1100.

[0113] In other embodiments, the number of plates included in the second capacitor Cst2 is greater than the number of plates included in the first capacitor Cst1. In this way, the capacitance of the second capacitor Cst2 can be greater than the capacitance of the first capacitor Cst1, and the area of ​​the second capacitor Cst2 can be reduced, which is beneficial to improving the pixel density of the second sub-pixel P2.

[0114] In some embodiments, the first subpixel P1 includes a first driving transistor DT10, and the second subpixel P2 includes a second driving transistor DT20. The width-to-length ratio of the channel structure of the first driving transistor DT10 is smaller than the width-to-length ratio of the channel structure of the second driving transistor DT20. As can be seen from the above formula (1), the luminance of the subpixel P is positively correlated with the width-to-length ratio of the channel structure of the driving transistor. Increasing the width-to-length ratio of the channel structure of the second driving transistor DT20 of the second subpixel P2 (compared to the first subpixel P1) can increase the display brightness of the second subpixel P2, increase the overall brightness of the second display area AA2 in the display device 1000, reduce the brightness difference between the second display area AA2 and the first display area AA1, improve the brightness uniformity of the entire display area of ​​the display device 1000, and help increase the maximum brightness in the first display area AA1, thereby increasing the maximum luminance of the first subpixel P1 and improving the display effect of the display device 1000.

[0115] For example, the purpose of increasing the aspect ratio of the channel structure of the second driving transistor DT20 can be achieved by increasing the width of the channel structure of the second driving transistor DT20 or by reducing the length of the channel structure of the second driving transistor DT20.

[0116] In some embodiments, the display panel 1100 includes a display area AA and a binding area BB1 located on one side of the display area AA. The binding area BB1 is provided with a connecting pin and a dummy pin. The first signal line 30 is electrically connected to the connecting pin, and the second signal line 40 is electrically connected to the connecting pin and / or the dummy pin.

[0117] For example, when the display panel 1100 includes a positive voltage signal bus VL, and both the first positive voltage signal line VDD1 and the second positive voltage signal line VDD2 are electrically connected to the positive voltage signal bus VL, the second positive voltage signal line VDD2 in the second signal lines 40 is electrically connected to the connection pin via the positive voltage signal bus VL. When the display panel further includes a first positive voltage signal bus VL1 and a second positive voltage signal bus VL2, the second positive voltage signal line VDD2 in the second signal lines 40 is electrically connected to the dummy pin via the second positive voltage signal bus VL2. Similarly, the second initial voltage signal line VINIT2 and the second negative voltage signal line VSS2 in the second signal lines 40 can be electrically connected to the connection pin or the dummy pin.

[0118] It is understood that the display device 1000 includes a driver chip, which is provided with multiple pins for transmitting control signals and power signals, as well as multiple dummy pins (Dummy Pins). Dummy pins refer to pins that are not used for signal transmission in the original driver chip. The solution provided in the embodiments of the present application can generate various different voltage signals (such as the first positive voltage signal Vdd1 and the second positive voltage signal Vdd2) through the above-mentioned dummy pins, which is conducive to simplifying the control difficulty of the display device and thus reducing the cost of the display device.

[0119] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any variation, combination, split, or replacement conceived by a person skilled in the art within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, comprising: a plurality of first sub-pixels and a plurality of second sub-pixels, wherein the plurality of second sub-pixels at least partially surround the plurality of first sub-pixels; a first signal line, electrically connected to the first sub-pixel, and configured to transmit at least one of a first positive voltage signal, a first negative voltage signal, a first initial voltage signal, and a data signal to the first sub-pixel; a second signal line, electrically connected to the second sub-pixel, and configured to transmit at least one of a second positive voltage signal, a second negative voltage signal, a second initial voltage signal, and a data signal to the second sub-pixel; Wherein, when displaying the same gray scale, the brightness of the first sub-pixel is smaller than the brightness of the second sub-pixel.

2. The display panel according to claim 1, wherein: The first signal line comprises a first positive voltage signal line, and the first positive voltage signal line is configured to transmit a first positive voltage signal; The second signal line includes a second positive voltage signal line, and the second positive voltage signal line is configured to transmit a second positive voltage signal; Wherein, the voltage value of the first positive voltage signal is smaller than the voltage value of the second positive voltage signal.

3. The display panel according to claim 2, wherein: The plurality of second sub-pixels surround the plurality of first sub-pixels; The second positive voltage signal line extends along the peripheral edge of the plurality of first sub-pixels and is electrically connected to the plurality of second sub-pixels; The display panel includes a plurality of conductive layers, and the first positive voltage signal line and the second positive voltage signal line are located in different conductive layers.

4. The display panel according to claim 2, wherein: At least part of the plurality of second sub-pixels are arranged in a plurality of columns, at least one column of second sub-pixels is provided on both sides of the plurality of first sub-pixels along the first direction, and the column of second sub-pixels includes a plurality of second sub-pixels arranged along the second direction; the first direction intersects the second direction; The display panel comprises a plurality of the second positive voltage signal lines, each of the second positive voltage signal lines being electrically connected to a column of second sub-pixels; The display panel includes a plurality of conductive layers, and the first positive voltage signal line and the second positive voltage signal line are arranged in the same layer.

5. The display panel according to claim 3 or 4, wherein: The display panel has a display area and a peripheral area, and the plurality of first sub-pixels and the plurality of second sub-pixels are located in the display area; The peripheral area surrounds the display area; The display panel further includes: A positive voltage signal bus is arranged in the peripheral area and surrounds the display area; The first positive voltage signal line and the second positive voltage signal line are both electrically connected to the positive voltage signal bus, and the line width of the first positive voltage signal line is smaller than the line width of the second positive voltage signal line.

6. The display panel according to claim 3 or 4, wherein: The display panel has a display area and a peripheral area, and the plurality of first sub-pixels and the plurality of second sub-pixels are located in the display area; The peripheral area surrounds the display area; The display panel further includes: A first positive voltage signal bus, disposed in the peripheral area, surrounding the display area, and configured to transmit the first positive voltage signal; A second positive voltage signal bus, disposed in the peripheral area, surrounding the display area, and configured to transmit the second positive voltage signal; The first positive voltage signal line is electrically connected to the first positive voltage signal bus, and the second positive voltage signal line is electrically connected to the second positive voltage signal bus.

7. The display panel according to any one of claims 1 to 6, wherein: The first sub-pixel includes a first pixel circuit and a first light-emitting device, the first pixel circuit includes a first node, and the first node is electrically connected to the first light-emitting device; the second sub-pixel includes a second pixel circuit and a second light-emitting device, the second pixel circuit includes a second node, and the second node is electrically connected to the second light-emitting device; The first signal line further includes a first initial voltage signal line, the first initial voltage signal line is configured to transmit a first initial voltage signal and is configured to initialize the first node; The second signal line further includes a second initial voltage signal line, the second initial voltage signal line is configured to transmit a second initial voltage signal and is configured to initialize the second node; Wherein, a voltage value of the first initial voltage signal is greater than a voltage value of the second initial voltage signal.

8. The display panel according to claim 7, wherein: The plurality of second sub-pixels surround the plurality of first sub-pixels; The second initial voltage signal line extends along the peripheral edge of the plurality of first sub-pixels and is electrically connected to the plurality of second sub-pixels; The display panel includes a plurality of conductive layers, and the first initial voltage signal line and the second initial voltage signal line are located in different conductive layers.

9. The display panel according to claim 7, wherein: At least part of the plurality of second sub-pixels are arranged in a plurality of rows, each side of the plurality of first sub-pixels along the second direction includes at least one row of second sub-pixels, and the row of second sub-pixels includes a plurality of second sub-pixels arranged along the first direction; the first direction intersects the second direction; The display panel comprises a plurality of the second initial voltage signal lines, each of which is electrically connected to a row of second sub-pixels; The display panel includes a plurality of conductive layers, the first initial voltage signal line and the second initial voltage signal line Same layer settings.

10. The display panel according to any one of claims 1 to 9, wherein: The first sub-pixel includes a first light emitting device; the second sub-pixel includes a second light emitting device; The first signal line further includes a first cathode voltage signal line, the first cathode voltage signal line is configured to transmit the first cathode voltage signal, and is configured to be electrically connected to the cathode of the first light emitting device; The second signal line further includes a second cathode voltage signal line, the second cathode voltage signal line is configured to transmit the second cathode voltage signal, and is configured to be electrically connected to the cathode of the second light emitting device; Wherein, the voltage value of the first negative voltage signal is greater than the voltage value of the second negative voltage signal.

11. The display panel according to claim 10, wherein: The first negative voltage signal line and the second negative voltage signal line are arranged in the same layer, and there is a gap between the first negative voltage signal line and the second negative voltage signal line.

12. The display panel according to any one of claims 1 to 11, wherein: The first signal line includes a first data signal line, and the second signal line includes a second data signal line; The resistance of the first data signal line is smaller than the resistance of the second data signal line.

13. The display panel according to claim 12, wherein: The plurality of second sub-pixels surround the plurality of first sub-pixels; The display panel includes a plurality of conductive layers; the first data signal line and the second data signal line are located in different conductive layers, and the resistivity of the material of the first data signal line is smaller than the resistivity of the material of the second data signal line.

14. The display panel according to claim 12, wherein: At least part of the plurality of second sub-pixels are arranged in a plurality of columns, at least one column of second sub-pixels is provided on both sides of the plurality of first sub-pixels along the first direction, and the column of second sub-pixels includes a plurality of second sub-pixels arranged along the second direction; the first direction intersects the second direction; Each second data line is electrically connected to a column of second sub-pixels; The display panel includes a plurality of conductive layers; the first data signal line and the second data signal line are located in the same conductive layer, and the line width of the first data signal line is greater than the line width of the second data signal line.

15. The display panel according to any one of claims 1 to 14, wherein: The first sub-pixel includes a first driving transistor and a first capacitor, one plate of the first capacitor is electrically connected to the gate of the first driving transistor; the second sub-pixel includes a second driving transistor and a second capacitor, one plate of the second capacitor is electrically connected to the gate of the second driving transistor; The capacitance of the second capacitor is greater than the capacitance of the first capacitor.

16. The display panel according to claim 15, wherein: The facing area between the at least two plates included in the second capacitor is greater than the facing area between the at least two plates included in the first capacitor.

17. The display panel according to claim 15 or 16, wherein: The number of plates included in the second capacitor is greater than the number of plates included in the first capacitor.

18. The display panel according to any one of claims 1 to 17, wherein: The first sub-pixel includes a first driving transistor, and the second sub-pixel includes a second driving transistor; The width-to-length ratio of the channel structure of the first driving transistor is smaller than the width-to-length ratio of the channel structure of the second driving transistor.

19. The display panel according to any one of claims 1 to 18, wherein: The display panel comprises a display area and a binding area located at one side of the display area, wherein the binding area is provided with connecting pins and dummy pins; The first signal line is electrically connected to the connection pin, and the second signal line is electrically connected to the connection pin and / or the dummy pin.

20. A display device comprising a plurality of display panels according to any one of claims 1 to 19, wherein a joint seam is provided between two adjacent display panels, the display panel comprises a first side edge close to the joint seam, and a second sub-pixel in the display panel is closer to the first side edge than the first sub-pixel.

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