A DDIC power supply system and a method for reducing DDIC power consumption

Abstract

The present invention provides a DDIC power supply system and a method for reducing DDIC power consumption. The power supply system includes an LDO unit, a digital circuit unit, a VDD unit, a VDDI unit, and a determination and control unit. The present invention uses the operating status of the entire device as the basis for turning the LDO unit on and off. Compared to existing technologies, this avoids the problem of setting values ​​too high or too low, thereby reducing power consumption. Furthermore, the present invention dynamically adjusts the output value of the LDO unit based on the operating status of the entire device, achieving even lower power consumption.

Description

Technical Field

[0001] The present application relates to the field of OLED displays, and in particular to the technical field of reducing the power consumption of display driver chips. Background Art

[0002] In the fiercely competitive OLED display market, including displays for mid- to high-end consumer products like mobile phones, wearable devices, and handheld game consoles, low power consumption has become a major selling point for many companies. The reason for this is quite intuitive: low power consumption means less power consumption, meaning that various consumer electronics products don't need to be frequently charged, greatly improving user convenience. Furthermore, power consumption often generates heat, so if power consumption is high, the product will easily overheat during use. Low power consumption can effectively reduce heat generation, making the overheating less noticeable and creating a more comfortable user experience.

[0003] Currently, display driver ICs (DDICs) generally use a 4-powermode power supply method. The motherboard directly provides all four power supplies required by the DDIC, namely VDDI, VCI, AVDD, and VDD.

[0004] However, in the actual application of 4powermode, a significant problem arises. While the external VDD power supply to the DDIC remains constant, certain unusual display usage scenarios can cause a sharp increase in VDD current. Due to the trace resistance between the motherboard and the DDIC, Ohm's law states that any current flowing through this resistance inevitably generates a voltage drop. Consequently, the VDD voltage ultimately reaching the DDIC is likely to be lower than the voltage required for proper operation of its internal digital circuitry. This can cause anomalies within the DDIC, ultimately manifesting as display anomalies. This is clearly undesirable for both product designers and users.

[0005] To address the aforementioned technical issues, an internal compensation function, namely an LDO unit, was introduced based on 4powermode. The specific principle is that when the external voltage falls below a set value A, an operating mode similar to 3powermode is activated, using the output value of the LDO unit (typically with a 1.8V input and the desired output value at the Vset terminal) to compensate for the insufficient VDD voltage entering the DDIC caused by the voltage drop. However, the set value A and the parameters of the LDO unit are fixed at the factory. Once set by the relevant application personnel at the assembly plant, they cannot be changed after the product is shipped to the user unless the product is returned to the factory for resetting. Setting the set value A and the LDO unit parameters too high or too low can lead to increased power consumption or abnormal operating conditions. Therefore, how to properly set these two parameters has become a key issue that needs to be addressed. Summary of the Invention

[0006] The present application provides a DDIC power supply system and a method for reducing DDIC power consumption, which turns on / off the LDO unit according to the working status of the entire device and dynamically adjusts the output value of the LDO unit.

[0007] The present application provides a DDIC power supply system, comprising: an LDO unit, a digital circuit unit, a VDD unit, a VDDI unit, and a judgment control unit;

[0008] The LDO unit includes a Vset terminal and an enable terminal; one end of the LDO module is connected to the VDDI unit, and the other end is connected to the digital circuit;

[0009] The digital circuit unit includes a digital module, an SRAM module, and a PHY module, one end of which is directly connected to the VDD unit;

[0010] A judgment control unit includes a first end, a second end, and a third end; the first end is connected to the interface unit and is used to judge the working state of the interface unit; the second end is connected to the enable end and is used to turn on or off the LDO unit according to the working state; the third end is connected to the Vset end of the LDO unit and is used to adjust the input value of the Vset end according to the working state;

[0011] A VDD unit is directly connected to the digital module, the SRAM module and the PHY module, and is used to provide a first voltage to the digital module, the SRAM module and the PHY module;

[0012] The VDDI module is used to provide a second voltage to the LDO module.

[0013] Furthermore, the first voltage is 1.2V.

[0014] Furthermore, the second voltage is 1.8V.

[0015] On the other hand, based on the above power supply system, the present application also provides a method for reducing DDIC power consumption, comprising the following steps:

[0016] Step 1: DDIC receives a frame of data transmitted by AP through the interface unit.

[0017] Step 2: Determine the working status of the interface unit and the read status of the SRAM module according to the transmitted data, and adjust the parameters of the LDO unit.

[0018] Furthermore, step 2 is specifically as follows:

[0019] Step 2.1 determines the working state of the interface unit based on the transmitted data and controls whether to turn on the LDO unit; if the interface state is in high-speed mode, turn on the LDO unit, input the first value to the Vset terminal, and jump to step 1; if the interface unit is in low-speed mode, jump to step 2.2;

[0020] Step 2.2: further determine whether the SRAM module needs to be read. If so, turn on the LDO unit, input the second value to the Vset terminal, and jump to step 1; if not, turn off the LDO unit and jump to step 1;

[0021] The first value is greater than the second value.

[0022] Furthermore, the first value is a higher level value.

[0023] Furthermore, the second value is a lower level value.

[0024] Compared with the prior art, the present invention has the following advantages:

[0025] (1) This application uses the working status of the entire machine as the basis for turning the LDO unit on and off. Compared with the existing technology, it avoids the problem of setting the value too high or too low and reduces power consumption.

[0026] (2) This application further dynamically adjusts the output value of the LDO unit according to the working state of the entire machine, which achieves lower power consumption compared to the single output value of the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 This is a schematic diagram of the principle of this embodiment;

[0029] Figure 2 A schematic diagram of the power supply system implemented in this paper;

[0030] Figure 3 FIG. 4 is a flow chart of the method for reducing DDIC power consumption according to this embodiment. DETAILED DESCRIPTION

[0031] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0032] See also Figure 1 The horizontal axis represents the DDIC working state, which are state A, state B and state C respectively; the vertical axis represents VDDD (i.e., the output value of the LDO unit 10). Figure 1 As shown, the lower limit for ensuring the normal operation of the DDIC is 0.99V. However, in practice, due to the existence of internal voltage drop, the voltage output to the VDD module of the DDIC in each state is different (the voltage drop in state A is the largest, state B is the second, and state C is the smallest, showing a step-by-step distribution). Even in some states (such as state A and state B), the minimum of 0.99V cannot be met, that is, the normal operation of the DDIC cannot be guaranteed. At this time, in order to ensure the normal operation of the DDIC, the value required for internal compensation is also different (the compensation value required for state A is the largest, state B is the second, and state C does not require compensation, showing a step-by-step distribution). However, in the prior art, the internal compensation value is set at the factory (that is, it remains unchanged after leaving the factory). When the compensation value meets state A, power consumption is wasted in state B (the voltage provided is greater than the voltage provided after compensation in state A) and state C (no compensation is required to ensure the normal operation of the DDIC). This implementation dynamically adjusts the compensation value for different states, so that the final voltage provided is slightly higher than 0.99V (under the condition of ensuring normal operation). Figure 1 In the figure, after compensation, it becomes a straight line, and the voltage values ​​provided by the three states are equal), thereby achieving the effect of saving power consumption.

[0033] Figure 2 FIG. 1 shows a schematic diagram of the structure of the DDIC power supply system of this embodiment. Figure 2 As shown, the power supply system includes an LDO unit 10 , a digital circuit unit 20 , a determination control unit 30 , a VDDI unit 40 , a VDD unit 50 and an interface unit 60 .

[0034] The LDO unit 10 includes a Vset terminal 101 and an enable terminal 102 ; the enable terminal 102 is used to control the on and off of the LDO unit 10 , and the value of the Vset terminal 101 is used to control the output value of the LDO unit 10 .

[0035] The digital circuit unit 20 includes a digital module, an SRAM module, and a PHY module.

[0036] The first end of the judgment control unit 30 is connected to the Vset end 101 for dynamically adjusting the output value of the LDO unit; the second end is connected to the enable end 102 for controlling the opening and closing of the LDO unit 10; the third end is connected to the interface unit 60 for obtaining the working status of the interface unit 60 and the reading status of the SRAM module.

[0037] The VDD unit 50 is connected to the digital circuit unit 20 and directly connected to the digital module, SRAM module and PHY module;

[0038] The VDDI unit 40 is connected to the LDO unit 10 and is configured to provide an input voltage to the LDO unit 10 .

[0039] Optionally, the VDD unit provides a 1.2V voltage.

[0040] Optionally, the VDDI unit provides a 1.8V voltage.

[0041] On the other hand, based on the above power supply system, the present application also provides a method for reducing DDIC power consumption, comprising the following steps:

[0042] Step 1: DDIC receives a frame of data transmitted by AP through the interface unit.

[0043] Step 2: Determine the working status of the interface unit and the read status of the SRAM module according to the transmitted data, and adjust the parameters of the LDO unit.

[0044] Step 2 is as follows:

[0045] Step 2.1 determines the working state of the interface unit based on the transmitted data and controls whether to turn on the LDO unit; if the interface state is in high-speed mode, turn on the LDO unit, input the first value to the Vset terminal, and jump to step 1; if the interface unit is in low-speed mode, jump to step 2.2;

[0046] Step 2.2: further determine whether the SRAM module needs to be read. If so, turn on the LDO unit, input the second value to the Vset terminal, and jump to step 1; if not, turn off the LDO unit and jump to step 1;

[0047] The first value is greater than the second value, the first value is a higher level value, and the second value is a lower level value.

[0048] Figure 3 The interface unit is a MIPI working sequence diagram. Figure 3 As shown, in Vedio mode, a detection mechanism is added at a fixed position after each frame of MIPI_VS to determine whether the MIPI data lane has a high-speed signal. If it does, it means the interface is transmitting data. At this time, VDD operation requires higher current consumption, so a higher compensation value is required. If it is determined that the lane has entered low-speed mode, it means the interface is not in use and does not require a large amount of power consumption, so the compensation value is set to a small value or turned off. When entering display mode, the LDO unit 10 is turned off, or Vset is set to a smaller value.

[0049] Preferably, in no-refresh mode, if the source does not update data to the panel, the LDO unit 10 can be turned off. If an update is required, data needs to be read from the SRAM module, which will also consume power, but it is much smaller than the refresh frame, so Vset can be set to a smaller value.

[0050] In summary, for devices with MIPI interface:

[0051] In Video mode, as shown in Table 1:

[0052] A) Screen off state (sleep in): At this time, power consumption is the lowest and the LDO unit 10 is turned off;

[0053] B) After waking up, refresh frame (normal display): the LDO unit 10 is turned on for compensation and inputs a first value to the Vset terminal 101 , ie, sets a higher potential value.

[0054] C) After waking up, during a non-refresh frame (normal display): If the AP is not updating data and the panel refresh frame rate is consistent with the overall device (i.e., no SRAM reading is required; during the skip frame, the AP is not sending data and the DDIC source does not provide voltage to the panel), the LDO unit 10 is turned off. If the AP is not updating data and the panel refresh frame rate is inconsistent with the overall device (i.e., an SRAM read is required, the AP maintains a lower frame rate, while the panel refreshes at a higher frame rate, requiring refresh frame data to be read from the SRAM), the LDO unit is turned on to compensate and a second value is input to Vset terminal 101, setting a lower potential. Optionally, if extreme power consumption reduction is not desired, the internal LDO can be turned on and set to a lower value in this case.

[0055] The three gears of this embodiment can be automatically switched according to the added status detection module

[0056] Table 1 Truth table of MIPI interface Vedio mode

[0057]

[0058] Optional, in Command mode, as shown in Table 2

[0059] A) Screen off state: At this time, power consumption is the lowest and the internal LDO unit 10 is turned off;

[0060] B) After waking up, refreshing the frame: the internal LDO unit is turned on, and a first value is input to the Vset terminal 101, that is, a higher potential value is set.

[0061] C) After wake-up, non-refresh frame: If the AP is not updating data, the panel needs to continuously output image information. At this time, it still needs to read the SRAM module and continuously output the source voltage to the panel. The internal LDO unit 10 is turned on and inputs a second value to the Vset terminal 101, that is, setting a lower potential value.

[0062] Table 2 Truth table of MIPI interface command mode

[0063]

[0064]

[0065] Optional, for EDP interface, as shown in Table 3

[0066] A) Screen off state: At this time, power consumption is the lowest and LDO unit 10 is turned off

[0067] B) After waking up, refreshing the frame: the LDO unit 10 is turned on and inputs a first value to the Vset terminal 101 , ie, sets a higher potential value.

[0068] C) After waking up, during the non-refresh frame and long v phase, the AP is not updating data, and the panel refresh frame rate is consistent with the entire device (i.e., there is no need to read the SRAM module. During long v, the AP is not sending data, and the DDIC source does not provide voltage to the panel). The LDO unit 10 is turned off. If the AP is not updating data, the panel refresh frame rate is inconsistent with the entire device (i.e., the SRAM module needs to be read, the AP maintains a lower frame rate, and the panel still refreshes at a higher frame rate, requiring the refresh frame data to be read from the SRAM module). The LDO unit 10 is then turned on and a second value is input to the Vset terminal 101, i.e., a lower potential value is set. Optionally, if extreme power consumption reduction is not desired, the internal LDO can be turned on in this case and set to a lower value.

[0069] Table 3 Truth table of EDP interface

[0070]

[0071]

[0072] In summary, Tables 1-3 can be simplified to Table 4:

[0073] Table 4 Simplified truth table

[0074]

[0075] Wherein, A is the first value, a is the second value, and A>a.

[0076] It should be noted that this embodiment uses Vset divided into three gears for illustration purposes. In fact, those skilled in the art can further divide it according to needs, that is, divide it into N gears to achieve stepless shifting.

[0077] The terms "equal," "same," or "equal" disclosed in the present invention must take into account the distribution of engineering parameters, with an error distribution within ±30%; the definition of "parallel" between two line segments or two straight lines is that the angle between the two line segments or two straight lines is less than or equal to 45 degrees; the definition of "perpendicular" between two line segments or two straight lines is that the angle between the two line segments or two straight lines is within the range of [60, 120] degrees; the definition of "phase mismatch" also needs to take into account the distribution of engineering parameters, with an error distribution within ±30% of the degree of mismatch. In addition, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article, or apparatus. Without more constraints, an element defined by the phrase "comprises a..." does not exclude the existence of additional identical elements in the process, method, article or apparatus that comprises the element.

[0078] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0079] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for reducing DDIC power consumption based on a DDIC power supply system, characterized in that: The DDIC power supply system includes: LDO unit, digital circuit unit, VDD unit, VDDI unit and judgment control unit; An LDO unit includes a Vset terminal and an enable terminal; one end of the LDO unit is connected to the VDDI unit, and the other end is connected to the digital circuit unit; The digital circuit unit includes a digital module, an SRAM module, and a PHY module, one end of which is directly connected to the VDD unit; A judgment control unit includes a first end, a second end, and a third end; the first end is connected to the interface unit and is used to judge the working state of the interface unit; the second end is connected to the enable end and is used to turn on or off the LDO unit according to the working state; the third end is connected to the Vset end of the LDO unit and is used to adjust the input value of the Vset end according to the working state; A VDD unit is directly connected to the digital module, the SRAM module and the PHY module, and is used to provide a first voltage to the digital module, the SRAM module and the PHY module; A VDDI unit, configured to provide a second voltage to the LDO unit; The method for reducing power consumption based on the DDIC power supply system includes the following steps: Step 1: DDIC receives a frame of data transmitted by AP through the interface unit; Step 2: judging the working status of the interface unit and the reading status of the SRAM module according to the transmitted data, and adjusting the parameters of the LDO unit; In step 2, the working state of the interface unit and the reading state of the SRAM module are determined according to the transmitted data, and the parameters of the LDO unit are adjusted as follows: Step 2.1 determines the working state of the interface unit based on the transmitted data and controls whether to turn on the LDO unit; if the interface state is in high-speed mode, turn on the LDO unit, input the first value to the Vset terminal, and jump to step 1; if the interface unit is in low-speed mode, jump to step 2.2; Step 2.2: further determine whether the SRAM module needs to be read. If so, turn on the LDO unit, input the second value to the Vset terminal, and jump to step 1; if not, turn off the LDO unit and jump to step 1; wherein the first value is greater than the second value.

2. The method according to claim 1, wherein The first voltage is 1.2V.

3. The method according to claim 1, wherein The second voltage is 1.8V.

Images