Latent fault detection system, method and on-board chip for register protection security mechanism

Abstract

The present application relates to a latent fault detection system, method and vehicle chip of register protection security mechanism, by adding fault mode control register, fault injection register and self-checking control module between each register related to security function and register protection security mechanism module, to realize fault self-checking of register protection security mechanism module in the way of increasing self-checking circuit module, the self-checking process does not produce destruction to the existing function circuit and does not need to reset after self-checking, and does not need to rely on DFT logic, and there is no test level requirement to module and system, the increased self-checking circuit module can be integrated in IP development stage of vehicle chip, so that latent fault detection in different modes is automatically executed according to the configured fault detection mode through self-checking control module, and a simplified and efficient latent fault detection means is provided and higher self-checking coverage is realized.

Description

Technical Field

[0001] This invention belongs to the field of chip security detection technology, and relates to a latent fault detection system, method and vehicle chip with a register protection security mechanism. Background Technology

[0002] In chips with functional safety requirements, safety mechanisms are typically implemented for critical internal registers to ensure the detection of register faults. If the implemented safety mechanism itself malfunctions, resulting in a latent fault, subsequent register faults may go undetected. Therefore, effective detection of such latent faults is necessary. The current standard ISO 26262 requires latent fault detection to be performed once per driving cycle, with coverage requirements varying depending on the functional safety level. For example, the automotive safety level ASIL D requires coverage of over 90%, while the automotive safety level ASIL B requires coverage of over 60%.

[0003] In chips meeting the ASILD safety rating for automobiles, latent fault detection measures for register protection security mechanisms are mostly implemented by applying LBIST (Logic Self-Test). This traditional technique utilizes the scan chain circuit of DFT (Design Testability) to achieve high coverage. However, after executing LBIST, the circuit state is disrupted, requiring reset and reinitialization, a time-consuming process. Furthermore, since LBIST is based on the DFT scan chain circuit, many logic circuits that don't require LBIST will also be executed, increasing execution time and affecting a wider range of circuits. LBIST implementation needs to be done on a module or subsystem basis; if most circuits in a module or subsystem do not require additional methods for latent fault detection, and only a small portion do, LBIST cannot effectively support this. Therefore, providing a streamlined and efficient latent fault detection method has become a pressing technical problem. Summary of the Invention

[0004] To address the problems existing in the above-mentioned traditional technologies, this invention proposes a latent fault detection system with register protection security mechanism, a latent fault detection method with register protection security mechanism, and an automotive chip, providing a simplified and efficient means of latent fault detection.

[0005] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a latent fault detection system with a register protection security mechanism is provided, including various registers related to security functions, a register protection security mechanism module, a fault mode control register, a fault injection register, and a self-test control module. Each register related to security functions is connected to the register protection security mechanism module, and the self-test control module is connected to the fault mode control register, the fault injection register, and the register protection security mechanism module. The fault injection register is connected to the register protection security mechanism module. The register protection security mechanism module is used to protect the registers related to the security function according to the set security mechanism. The register protection security mechanism module integrates register write error detection and register CRC check; the fault mode control register is used to store the fault detection mode, which includes latent fault self-checking of register write error detection or register CRC check. The self-test control module is used to initiate the corresponding self-test mode after receiving the fault detection mode. It controls the fault injection register to inject errors into different input positions of the register protection security mechanism module, obtains the alarm output of the register protection security mechanism module, and checks whether the alarm output meets the expectations to obtain the self-test result status. After the self-test is completed, the self-test result status is output, which includes normal or abnormal. Error injection includes writing errors to the register protection security mechanism module by replacing each register or injecting errors into the CRC check of the register protection security mechanism module.

[0006] In one embodiment, in the fault detection mode of register write error detection, the self-test control module controls the value of the fault injection register to change bit by bit and sends the changed value to replace the write value of the detected register to the register protection security mechanism module, while triggering the register write control signal of the register protection security mechanism module. The self-test control module checks whether the alarm output of the register protection security mechanism module meets the alarm expectation set in the fault detection mode of register write error detection. If it does, the self-test control module outputs a self-test result status indicating that the latent fault self-test is normal; otherwise, it outputs a self-test result status indicating that the latent fault self-test is abnormal.

[0007] In one embodiment, in the fault detection mode of the latent fault self-test of the register CRC check, the self-test control module controls the value of the fault injection register to change bit by bit and sends the changed value as CRC operation data to the register protection security mechanism module. The self-test control module detects whether the alarm output of the register protection security mechanism module in this mode meets the expected CRC operation. If it does, the self-test control module outputs the self-test result status of the latent fault self-test in the register CRC check as normal; otherwise, it outputs the self-test result status of the latent fault self-test in the register CRC check as abnormal.

[0008] On the other hand, a method for detecting latent faults in a register protection security mechanism is also provided. This method is applied to a latent fault detection system for a register protection security mechanism. The latent fault detection system includes various registers related to security functions, a register protection security mechanism module, a fault mode control register, a fault injection register, and a self-test control module. Each register related to security functions is connected to the register protection security mechanism module. The self-test control module is connected to the fault mode control register, the fault injection register, and the register protection security mechanism module. The fault injection register is connected to the register protection security mechanism module. The register protection security mechanism module is used to protect the registers related to the security function according to the set security mechanism. The register protection security mechanism module integrates register write error detection and register CRC check; the fault mode control register is used to store the fault detection mode, which includes latent fault self-checking of register write error detection or register CRC check. The method for detecting latent faults in register protection security mechanisms includes the following steps: The self-test control module controls the value of the fault injection register to change bit by bit and sends the changed value to replace the written value of the register being tested to the register protection security mechanism module; at the same time, it triggers the register write control signal of the register protection security mechanism module. The self-test control module checks whether the alarm output of the register protection security mechanism module meets the alarm expectations set in the fault detection mode of register write error detection; If the conditions are met, the self-test control module will output a self-test result indicating that the latent fault self-test is normal. If it does not meet the requirements, the self-test control module will output the self-test result status of latent fault self-test abnormality.

[0009] In one embodiment, the latent fault detection method of the above-described register protection security mechanism further includes the step of: The self-test control module controls the value of the fault injection register to change bit by bit and sends the changed value as CRC operation data to the register protection security mechanism module. The self-test control module detects whether the alarm output of the register protection security mechanism module in this mode meets the expected CRC calculation. If the conditions are met, the self-test control module outputs the CRC check register to show the status of a normal self-test result indicating a latent fault self-test. If it does not meet the requirements, the self-test control module outputs the CRC check register to indicate the status of the latent fault self-test abnormality.

[0010] On the other hand, an automotive chip is also provided, which incorporates a latent fault detection system with any of the aforementioned register protection security mechanisms.

[0011] One of the above technical solutions has the following advantages and beneficial effects: The aforementioned latent fault detection system, method, and automotive chip for register protection security mechanisms achieve fault self-testing of the register protection security mechanism module by adding fault mode control registers, fault injection registers, and self-test control modules between the registers related to safety functions and the register protection security mechanism module, thereby increasing the self-test circuit module. The self-testing process does not damage the existing functional circuits and does not require a reset after the self-test, nor does it rely on DFT logic. There are no requirements for the test level of the module and system. The aforementioned added self-test circuit module can be integrated during the IP development stage of the automotive chip. Thus, the self-test control module automatically performs latent fault detection under different modes according to the configured fault detection mode, providing a simplified and efficient latent fault detection method and achieving a high self-test coverage. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a block diagram of a latent fault detection system for a register protection security mechanism in one embodiment. Figure 2 This is a flowchart illustrating register write error detection in one embodiment; Figure 3 This is a schematic diagram of the latent fault self-testing process of register CRC check in one embodiment; Figure 4 This is a flowchart illustrating a latent fault detection method for a register protection security mechanism in one embodiment; Figure 5 This is a flowchart illustrating a latent fault detection method for a register protection security mechanism in another embodiment. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0015] It should be noted that, in this document, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items, and all possible combinations thereof.

[0016] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0017] In one embodiment, such as Figure 1 As shown, a latent fault detection system with a register protection security mechanism is provided, including various registers related to security functions, a register protection security mechanism module, a fault mode control register, a fault injection register, and a self-test control module. Each register related to security functions is connected to the register protection security mechanism module. The self-test control module is connected to the fault mode control register, the fault injection register, and the register protection security mechanism module. The fault injection register is connected to the register protection security mechanism module. The register protection security mechanism module is used to protect the registers related to security functions according to the set security mechanism. The register protection security mechanism module integrates register write error detection and register CRC verification. The fault mode control register is used to store fault detection modes, which include latent fault self-tests such as register write error detection or register CRC verification.

[0018] The self-test control module initiates the corresponding self-test mode upon receiving a fault detection mode. It controls the fault injection register to inject errors into different input positions of the register protection security mechanism module, obtains the alarm output of the module, and checks whether the alarm output meets expectations to obtain the self-test result status. After the self-test is completed, the self-test result status is output, which can be either normal or abnormal. Error injection includes writing errors to the register protection security mechanism module's inputs or injecting errors into the module's CRC checksum.

[0019] It is understood that the register protection security mechanism module integrates register write error detection (used to monitor whether the data written to the register and the data sent by the register bus are consistent when a write operation occurs in the register) and register CRC check (used to monitor whether the value of the register is illegally modified during operation). The check period of the CRC check can be set according to the application needs in the vehicle chip, for example, but not limited to, 200us. The connection between the various registers related to the safety function (such as registers 1 to register n) and the register protection security mechanism module can be understood in the same way as the connection method of the module circuit in the existing register protection security mechanism in this field, and will not be elaborated further in this specification. The output terminal of the fault mode control register is connected to the self-test control module to transmit the fault detection mode, and the control terminal of the fault injection register is connected to the self-test control module so that the self-test control module can control the value of the fault injection register to change as needed according to the fault detection mode. The self-test control module can be implemented by an independent control logic circuit, or it can be implemented by the existing control unit in the vehicle chip through software configuration, as long as it can be used to implement the above control functions.

[0020] The fault detection mode can be pre-configured according to the detection requirements of the register protection security mechanism module and stored in the fault mode control register for use by the self-test control module. The data format and bit positions of the fault injection register can be selected according to the configuration parameters of each register related to the security function and the register protection security mechanism module, as long as it can be used to accurately generate the corresponding data to the register protection security mechanism module.

[0021] The aforementioned latent fault detection system for register protection security mechanisms achieves fault self-testing of the register protection security mechanism module by adding fault mode control registers, fault injection registers, and self-test control modules between the registers related to safety functions and the register protection security mechanism module. This self-testing process does not damage existing functional circuits and does not require reset after self-testing, nor does it rely on DFT logic. It does not have test level requirements for modules and systems, and the aforementioned added self-test circuit module can be integrated during the IP development stage of automotive chips. Thus, the self-test control module automatically performs latent fault detection under different modes according to the configured fault detection mode, providing a simplified and efficient latent fault detection method and achieving a high self-test coverage.

[0022] In one embodiment, in the fault detection mode of register write error detection, the self-test control module controls the value of the fault injection register to change bit by bit and sends the changed value to replace the write value of the detected register to the register protection security mechanism module, while triggering the register write control signal of the register protection security mechanism module. The self-test control module checks whether the alarm output of the register protection security mechanism module meets the alarm expectation set in the fault detection mode of register write error detection. If it does, the self-test control module outputs a self-test result status indicating that the latent fault self-test is normal; otherwise, it outputs a self-test result status indicating that the latent fault self-test is abnormal.

[0023] Understandable, such as Figure 2 The diagram illustrates the write detection injection process in the fault detection mode of register write error detection. In this mode, the self-test control module controls the value of the fault injection register to change bit by bit and sends the changed value to replace the write value of the detected register, which is then sent to the register protection security mechanism module. Simultaneously, the register write control signal of the register protection security mechanism module is triggered to simulate a write operation to the corresponding register, causing the module to generate an alarm output. The self-test control module then checks whether the alarm output of the register protection security mechanism module meets the alarm expectations set in the fault detection mode. If it does, it outputs a self-test result indicating a normal latent fault self-test; otherwise, it outputs a self-test result indicating an abnormal latent fault self-test. By controlling the value of the fault injection register to change bit by bit through the self-test control module, write detection injection can be performed on each register channel and each bit of the register being written, thus achieving 100% coverage of latent write faults.

[0024] In one embodiment, in the fault detection mode of the latent fault self-test of register CRC check, the self-test control module controls the value of the fault injection register to change bit by bit and sends the changed value as CRC operation data to the register protection security mechanism module. The self-test control module detects whether the alarm output of the register protection security mechanism module in this mode meets the expected CRC operation. If it does, the self-test control module outputs the self-test result status of the latent fault self-test in the register CRC check as normal; otherwise, it outputs the self-test result status of the latent fault self-test in the register CRC check as abnormal.

[0025] Understandable, such as Figure 3 The diagram illustrates the detection process for CRC register protection injection in the latent fault self-test mode of register CRC checksum. The detection time parameter refers to the CRC checksum cycle. To shorten the overall detection time during latent fault detection, the CRC checksum cycle can be reduced, and then restored to its original value after detection. In this mode, the self-test control module controls the value of the fault injection register to change bit by bit and sends it as CRC calculation data to the register protection security mechanism module. By default, the register protection security mechanism module uses all-zero operations when performing CRC checks. However, in this mode, the self-test control module modifies the register bits by controlling the value of the fault injection register to change bit by bit, preventing it from using all-zero CRC calculation data. This causes a difference between the CRC calculation performed by the register protection security mechanism module and the expected CRC calculation by default, resulting in an alarm output. The self-test control module checks whether the alarm output of the register protection security mechanism module in this mode matches the expected CRC calculation. If it does, it outputs a normal self-test result for the latent fault self-test of register CRC checksum; otherwise, it outputs an abnormal self-test result for the latent fault self-test of register CRC checksum. By controlling the value of the fault injection register to change bit by bit through the self-test control module, all the error-injected bits of the CRC check can be traversed, thereby achieving a high coverage of the CRC detection logic for the register protection security mechanism module.

[0026] In one embodiment, an automotive chip is also provided, which incorporates a latent fault detection system with any of the above-mentioned register protection security mechanisms.

[0027] It is understood that the automotive chip can be any type of automotive chip used in intelligent vehicles, such as, but not limited to, sensor chips or domain controllers. A latent fault detection system employing the aforementioned register protection security mechanism for the registers related to safety functions in the automotive chip can achieve high-coverage latent fault detection, thus providing a more reliable detection method for the security of the automotive chip.

[0028] In one embodiment, a method for detecting latent faults in a register protection security mechanism is provided, which is applied to a latent fault detection system for a register protection security mechanism. The latent fault detection system includes registers related to security functions, a register protection security mechanism module, a fault mode control register, a fault injection register, and a self-test control module. Each register related to security functions is connected to the register protection security mechanism module. The self-test control module is connected to the fault mode control register, the fault injection register, and the register protection security mechanism module. The fault injection register is connected to the register protection security mechanism module. The register protection security mechanism module is used to protect the registers related to the security function according to the set security mechanism. The register protection security mechanism module integrates register write error detection and register CRC check. The fault mode control register is used to store the fault detection mode, which includes latent fault self-checking of register write error detection or register CRC check. like Figure 4 As shown, the latent fault detection method of the above-mentioned register protection security mechanism may include the following processing steps S10 to S16: S10, the self-test control module controls the value of the fault injection register to change bit by bit and sends the changed value to replace the written value of the register being tested to the register protection security mechanism module; at the same time, it triggers the register write control signal of the register protection security mechanism module; S12, the self-test control module checks whether the alarm output of the register protection safety mechanism module meets the alarm expectation set in the fault detection mode of register write error detection; S14, if it meets the requirements, then the self-test control module outputs a self-test result status indicating that the latent fault self-test is normal. S16, if not met, then the self-test control module outputs the self-test result status of latent fault self-test abnormality.

[0029] The aforementioned latent fault detection method for the register protection security mechanism adds a fault mode control register, a fault injection register, and a self-test control module between the registers related to the safety function and the register protection security mechanism module. This adds a self-test circuit module to achieve fault self-testing of the register protection security mechanism module. The self-testing process does not damage the existing functional circuits and does not require a reset after the self-test. It also does not rely on DFT logic and has no test level requirements for the module and system. The aforementioned added self-test circuit module can be integrated during the IP development stage of the automotive chip. The self-test control module automatically performs latent fault detection under different modes according to the configured fault detection mode, providing a simplified and efficient latent fault detection method and achieving a high self-test coverage.

[0030] In one embodiment, such as Figure 5 As shown, the latent fault detection method of the above-mentioned register protection security mechanism further includes the following processing steps S11 to S17: S11, the self-test control module controls the value of the fault injection register to change bit by bit and sends the changed value as CRC operation data to the register protection security mechanism module; S13, the self-test control module detects whether the alarm output of the register protection security mechanism module in this mode meets the expected CRC calculation. S15, if it meets the requirements, then the self-test control module outputs the CRC check register to show the status of the latent fault self-test as normal. S17, if not met, then the self-test control module output register CRC check of the latent fault self-test abnormality self-test result status.

[0031] For specific limitations on the latent fault detection method of the register protection security mechanism, please refer to the corresponding explanation of the latent fault detection system of the register protection security mechanism above, which will not be repeated here.

[0032] It should be understood that, although Figure 4 and Figure 5 The steps are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed; they can be performed in other orders. Figure 4 and Figure 5 At least some of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0033] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided by this invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), memory bus DRAM (RDRAM), and interface DRAM (DRDRAM), etc.

[0034] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0035] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A latent fault detection system with a register protection security mechanism, characterized in that, It includes various registers related to safety functions, a register protection safety mechanism module, a fault mode control register, a fault injection register, and a self-test control module. Each of the registers related to safety functions is connected to the register protection safety mechanism module. The self-test control module is connected to the fault mode control register, the fault injection register, and the register protection safety mechanism module. The fault injection register is connected to the register protection safety mechanism module. The register protection security mechanism module is used to protect the registers related to the security function according to the set security mechanism. The register protection security mechanism module integrates register write error detection and register CRC check. The register CRC check is used to monitor that the value of the register will not be illegally modified during the operation. The fault mode control register is used to store the fault detection mode, which includes latent fault self-checking of register write error detection or register CRC check. The self-test control module is used to start the corresponding self-test mode after receiving the fault detection mode, control the fault injection register to inject errors into different input positions of the register protection security mechanism module, obtain the alarm output of the register protection security mechanism module and detect whether the alarm output meets the expectations to obtain the self-test result status, and output the self-test result status after the self-test is completed. The self-test result status includes normal or abnormal. In the fault detection mode of latent fault self-testing for register write error detection, the self-testing control module controls the value of the fault injection register to change bit by bit and sends the changed value to the register protection security mechanism module, replacing the write value of the detected register. At the same time, it triggers the register write control signal of the register protection security mechanism module. In the fault detection mode of latent fault self-testing for register CRC check, the self-testing control module controls the value of the fault injection register to change bit by bit and sends the changed value as CRC operation data to the register protection security mechanism module. Error injection includes replacing the write error input to the register protection security mechanism module for each register or injecting the CRC check error into the register protection security mechanism module.

2. The latent fault detection system of the register protection security mechanism according to claim 1, characterized in that, The self-test control module detects whether the alarm output of the register protection security mechanism module meets the alarm expectation set in the fault detection mode of register write error detection. If it does, the self-test control module outputs a self-test result status indicating that the latent fault self-test is normal; otherwise, it outputs a self-test result status indicating that the latent fault self-test is abnormal.

3. The latent fault detection system of the register protection security mechanism according to claim 1, characterized in that, The self-test control module detects whether the alarm output of the register protection security mechanism module in the fault detection mode of the latent fault self-test of register CRC check meets the expected CRC operation. If it does, the self-test control module outputs the self-test result status of the latent fault self-test of register CRC check being normal; otherwise, it outputs the self-test result status of the latent fault self-test of register CRC check being abnormal.

4. A method for detecting latent faults in a register protection security mechanism, characterized in that, A latent fault detection system is applied to a register protection security mechanism. The latent fault detection system includes various registers related to security functions, a register protection security mechanism module, a fault mode control register, a fault injection register, and a self-test control module. Each of the registers related to security functions is connected to the register protection security mechanism module. The self-test control module is connected to the fault mode control register, the fault injection register, and the register protection security mechanism module. The fault injection register is connected to the register protection security mechanism module. The register protection security mechanism module is used to protect the registers related to the security function according to the set security mechanism. The register protection security mechanism module integrates register write error detection and register CRC check. The register CRC check is used to monitor that the value of the register will not be illegally modified during the operation. The fault mode control register is used to store the fault detection mode, which includes latent fault self-checking of register write error detection or register CRC check. The latent fault detection method of the register protection security mechanism includes the following steps: In the fault detection mode of latent fault self-testing for register write error detection, the self-testing control module controls the value of the fault injection register to change bit by bit and sends the changed value to the register protection security mechanism module, replacing the written value of the detected register. At the same time, it triggers the register write control signal of the register protection security mechanism module. In the fault detection mode of latent fault self-testing for register CRC check, the self-testing control module also controls the value of the fault injection register to change bit by bit and sends the changed value as CRC operation data to the register protection security mechanism module. The self-test control module detects whether the alarm output of the register protection security mechanism module meets the alarm expectation set in the fault detection mode of register write error detection; If the condition is met, the self-test control module outputs a self-test result indicating that the latent fault self-test is normal. If it does not meet the requirements, the self-test control module outputs the self-test result status of latent fault self-test anomaly.

5. The method for detecting latent faults in the register protection security mechanism according to claim 4, characterized in that, It also includes the following steps: The self-test control module detects whether the alarm output of the register protection security mechanism module in the fault detection mode of the latent fault self-test of register CRC check meets the CRC calculation expectation. If the condition is met, the self-test control module outputs the CRC check register to show the self-test result status of the latent fault self-test being normal. If it does not meet the requirements, then the self-test control module outputs the CRC check of the output register to indicate the status of the latent fault self-test abnormality.

6. An automotive chip, characterized in that, The vehicle-mounted chip incorporates a latent fault detection system with a register protection security mechanism as described in any one of claims 1 to 3.

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