A cache coherence maintenance method, apparatus, and multi-core system

Abstract

The present application provides a method, an apparatus, and a multi-core system for maintaining cache coherence. The method includes: obtaining a write pointer and an eviction pointer of a directory, where the directory includes cache line sharing information; configuring an emergency threshold and a normal threshold, and the emergency threshold is less than the normal threshold; if the sum of the write pointer and the emergency threshold is greater than the eviction pointer, setting it as a high priority and preferentially performing directory eviction; if the sum of the write pointer and the emergency threshold is less than or equal to the eviction pointer, and the sum of the write pointer and the normal threshold is greater than the eviction pointer, setting it as a low priority and performing directory eviction; where the directory includes the sharing information of the cache line, and directory eviction means evicting the sharing information of the least recently used cache line in the directory; repeating the above steps until the sum of the write pointer and the normal threshold is less than the eviction pointer. The present application maximally ensures that there is available space in the directory to store new data, is applicable to small systems, can also ensure directory coverage, and improves query efficiency and reduces query power consumption.

Description

Technical Field

[0001] This application belongs to the field of information technology, and particularly relates to a cache coherence maintenance method, apparatus, and multi-core system. Background Art

[0002] In a computer system, a cache is a high-speed memory that stores copies of recently accessed data. The role of the cache is to reduce the number of times the processor accesses memory (which is slower), thereby improving the running speed of the system. However, when multiple processor cores (CPU cores) or multiple processor clusters (a group of cores) share the same data, ensuring that the data seen by each core or cluster is consistent is the problem that cache coherence needs to solve.

[0003] To maintain cache coherence, the system usually adopts a snooping coherence protocol, and ensures the consistency of the same memory data in different caches through a snooping mechanism. However, as the number of processor cores increases, snooping requests will occupy a large amount of system bus bandwidth, resulting in decreased efficiency. To solve the inefficiency problem of the snooping mechanism, a coherence maintenance apparatus is designed. It records which processor cores share which data, so that it is not necessary to frequently snoop the bus, but directly query the coherence maintenance apparatus. However, if the shared information is recorded in the secondary cache, it will occupy a large amount of space, and this space is idle when not shared. Therefore, the coherence maintenance apparatus is responsible for managing the shared information. However, for a small system, the hardware resources are limited, and the design of the coherence maintenance apparatus needs to find a balance between hardware overhead and query efficiency.

[0004] Therefore, there is a problem in cache coherence management that the hardware overhead and query efficiency cannot be balanced. Summary of the Invention

[0005] This application discloses a cache coherence maintenance method, apparatus, and multi-core system. By setting dynamic thresholds and priorities for dynamic directory eviction, the available space in the directory is maximally guaranteed, and it is applicable to small systems, achieving the same query accuracy with less hardware overhead, improving query efficiency, and reducing query power consumption.

[0006] Other objects and advantages of this application can be further understood from the technical features disclosed in this application.

[0007] To achieve one or part or all of the above objects or other objects, in a first aspect, this application provides a cache coherence maintenance method, the method including: obtaining a write pointer and an eviction pointer of a directory, where the write pointer indicates the directory address currently written by the directory, the eviction pointer indicates the directory address currently evicted by the directory, and the directory includes cache line sharing information;

[0008] Configure an emergency threshold and a normal threshold, and the emergency threshold is less than the normal threshold;

[0009] If the sum of the write pointer and the emergency threshold is greater than the eviction pointer, set it to high priority and perform directory eviction first; if the sum of the write pointer and the emergency threshold is less than or equal to the eviction pointer, and the sum of the write pointer and the normal threshold is greater than the eviction pointer, set it to low priority and perform directory eviction; where directory eviction means evicting the cache line sharing information that has not been used for the longest time in the directory;

[0010] Repeat the above steps until the sum of the write pointer and the normal threshold is less than the eviction pointer.

[0011] In one implementation, the method further includes: determining the maximum value of the directory address according to the space size of the directory, and after the write pointer and the eviction pointer reach the maximum value, starting counting from 0; when the eviction pointer catches up with the write pointer, it means that the directory has been completely evicted; when the write pointer catches up with the eviction pointer, it means that the directory is completely occupied.

[0012] In one implementation, determining the cache line that has not been used for the longest time in the directory includes: defining that the recorded cache lines are before the write pointer and after the eviction pointer;

[0013] When the processor accesses a cache line, if the cache line used this time has been recorded in the directory, extract the cache line sharing information and place it at the position of the latest write pointer, and move the positions of the remaining cache line sharing information forward; if the cache line used this time has not been recorded in the directory, place the cache line sharing information at the position of the latest write pointer, and the positions of the remaining cache line sharing information remain unchanged;

[0014] Determine that the position after the eviction pointer is the cache line sharing information that has not been used for the longest time.

[0015] In one implementation, the method is used to maintain the consistency of data sharing between multi-core processors. When the processor accesses a cache line, the directory query first matches according to the index value, and then performs a tag value match after successful matching to confirm the cache line sharing information of the cache line in the directory; where the cache line sharing information includes the cache line address, expand the low n bits of the cache line address as the index value, and use the remaining high bits of the cache line address as the tag value.

[0016] In one implementation, each index value carries flag information, and the flag information includes a valid bit, a host indication bit, and a dirty data bit;

[0017] When writing cache line sharing information, raise the valid bit and the corresponding host indication bit, and write the processor number into the dirty data bit, indicating that the current processor has a cache line copy and there is a modified state;

[0018] Upon receiving a read transaction, go to the dirty data bit to instruct the processor to read the latest data;

[0019] Upon receiving an invalidate transaction, go to the host indication bit to instruct the processor to perform an invalidate operation.

[0020] In one implementation, when the sum of the write pointer and the emergency threshold is greater than the eviction pointer, prioritize eviction by pulling up the arbitration clear bit and the priority bit;

[0021] When the sum of the write pointer and the emergency threshold is less than or equal to the eviction pointer, and the sum of the write pointer and the normal threshold is greater than the eviction pointer, perform eviction by pulling up the arbitration clear bit and pulling down the priority bit.

[0022] In one implementation, during directory eviction, continue writing to the cache line and perform continuous eviction at a preset eviction speed until the sum of the write pointer and the normal threshold is less than the eviction pointer.

[0023] In a second aspect, the present application provides a cache coherence maintenance device, which maintains the coherence of shared data among multi-core processors through the cache coherence maintenance method described in any one of the first aspects above.

[0024] In a third aspect, the present application provides a multi-core system, which includes a cache coherence maintenance device as described in the second aspect and multiple processor cores. The system maintains the coherence of shared data among multi-core processors through the cache coherence maintenance method described in any one of the first aspects above;

[0025] The system further includes a secondary cache for sharing among different processor cores in the same processor cluster and a tertiary cache for sharing among multiple processor clusters; the coherence maintenance device includes an inter-core coherence maintenance device and an inter-cluster coherence maintenance device. The inter-core coherence maintenance device is used to maintain data coherence when the secondary cache is shared among multiple processor cores, and the inter-cluster coherence maintenance device is used to maintain data coherence when the tertiary cache is shared among multiple processor clusters.

[0026] In a fourth aspect, the present application provides an electronic device, which includes one or more processors; a memory; one or more application programs, where one or more application programs are stored in the memory and configured to be executed by one or more processors, and one or more application programs are configured to execute a cache coherence maintenance method as described in any one of the first aspects above.

[0027] The above cache coherence maintenance method, device, multi-core system, and electronic device can perform dynamic eviction by setting dynamic thresholds and priorities. When reading and modifying data, it can ensure that there is available space in the directory to store new data to the greatest extent, enabling the directory to listen according to the directory records, thereby improving query efficiency and reducing query power consumption. Compared with the previous large directory design at the cost of a large area, this application can be applied to small systems and can also ensure directory coverage, that is, the same query accuracy can be achieved with a smaller hardware overhead, improving query efficiency and reducing query power consumption.

[0028] To make the above and other purposes, features, and advantages of this application more obvious and understandable, the following specifically presents preferred embodiments and, in conjunction with the accompanying drawings, provides detailed descriptions as follows. Brief Description of the Drawings

[0029] To more clearly illustrate the technical solutions in the specific embodiments of this application, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the following described drawings are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0030] Figure 1 It is a schematic flowchart of the cache coherence maintenance method of this application.

[0031] Figure 2 It is a structural block diagram of the multi-core system of this application.

[0032] Figure 3 It is a structural block diagram of the cache coherence maintenance device of this application.

[0033] Figure 4 It is a schematic flowchart of the judgment process of the cache coherence maintenance method of this application. Detailed Embodiments

[0034] Regarding the foregoing and other technical contents, features, and effects of this application, they will be clearly presented in the following detailed description of a preferred embodiment in conjunction with the reference drawings. The terms "first", "second", etc. in the specification and claims of this application and the above drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances, which is only a way of distinguishing objects with the same attributes when describing the embodiments of this application.

[0035] In the related art, a coherence maintenance device marks data when a processor core reads data in a shared manner and synchronously clears the mark when the processor core evicts data. The coherence maintenance device query methods mainly include hierarchical query and grouped query. Among them, the hierarchical query matches through an index value, then finds a mark value for matching in the matched index row, preferentially fills the free space in the index row when storing, and then integrates information for the same mark value. This method requires storing a large number of indexes and mark values, has a large hardware overhead, faces the problem of reduced efficiency when the directory is full and there is no identical data, and is prone to multiple hits. The grouped query divides the query address information into multiple blocks of index values, and only when all the multiple blocks of index values match does it represent a hit. The hit information of the multiple blocks of index values is integrated as the final query information, which can represent more cache address information with a smaller hardware overhead. However, due to the reduced correlation between complete address information, there are invalid accesses caused by false hits. It can be seen that this method introduces a large number of index values at a low hardware overhead cost, improving the query efficiency but correspondingly sacrificing the query accuracy.

[0036] To find a balance between hardware overhead and query efficiency, the embodiments of the present application provide a cache coherence maintenance method. Through a directory-based coherence protocol and hierarchical query, by setting thresholds and priorities to dynamically manage the directory, preferentially evicting the least recently used or the location that most needs to reserve space, it is applicable to multiple scenarios, can ensure the query efficiency, and can also take into account the hardware overhead.

[0037] The following describes the present application in detail with reference to the accompanying drawings.

[0038] Referring to Figure 1 , a cache coherence maintenance method provided by the embodiments of the present application includes:

[0039] Step 1: Obtain the write pointer and eviction pointer of the directory. Among them, the write pointer indicates the directory address currently written in the directory, and the eviction pointer indicates the directory address currently evicted from the directory. The directory address is the position in the directory. The directory includes cache line sharing information to represent the sharing status and position of the cache line. The cache line sharing information specifically includes the cache line address, the processor host information participating in sharing, etc.

[0040] Among them, the pointer count value is not infinite but a cycle. In this embodiment, the maximum value of the directory address is determined according to the space size in the directory. After the write pointer and the eviction pointer reach the maximum value, counting starts from 0 again. As it is used, when the eviction pointer catches up with the write pointer, it is regarded that the directory is empty, indicating that the directory has been completely evicted; when the write pointer catches up with the eviction pointer, it is regarded that the directory is full, indicating that the directory is completely occupied, so that the determined write pointer and eviction pointer are more accurate.

[0041] Step 2: Configure the emergency threshold and the normal threshold, where the emergency threshold is less than the normal threshold. Herein, the emergency threshold and the normal threshold are collectively referred to as the eviction threshold in this text.

[0042] Step 3: If the sum of the write pointer and the emergency threshold is greater than the eviction pointer, set it to high priority and perform directory eviction preferentially; if the sum of the write pointer and the emergency threshold is less than or equal to the eviction pointer, and the sum of the write pointer and the normal threshold is greater than the eviction pointer, set it to low priority and perform directory eviction; wherein, the directory includes the shared information of cache lines, and directory eviction means evicting the shared information of the least recently used cache line in the directory, that is, removing the shared information of this cache line from the directory.

[0043] Step 4: Repeat the above steps until the sum of the write pointer and the normal threshold is less than the eviction pointer.

[0044] Specifically, when the processor needs to read data, it will first query whether the data is in the cache. If the data is in the cache, the data will be read from the corresponding cache line and returned to the processor. When the processor needs to write data, it also needs to first query whether the data is in the cache. If the data is in the cache, the data will be written to the cache line. When reading or writing data, the shared consistency of the data needs to be considered. If multiple processors write the same data simultaneously, it is necessary to ensure the consistency of the data among multiple processors. The directory is used to maintain the consistency state of each cache line, tracking which caches have this cache line and the state of this cache line. This method configures dynamic eviction thresholds by obtaining the write pointer and the eviction pointer of the directory, and determines the relationship among the write pointer, the eviction threshold, and the eviction pointer in real time, preferentially evicting the shared information of the cache line that has not been used for the longest time in the directory, so as to improve the performance of the cache and ensure the available space in the directory to the greatest extent.

[0045] According to the above description, the cache coherence maintenance method of the embodiments of the present application makes the directory eviction method more flexible by setting dynamic thresholds and priorities, and can ensure that there is available space in the directory to store new data to the greatest extent when reading and modifying data. Once stored in the directory, it can listen according to the directory records, thereby improving the query efficiency and reducing the query power consumption. Compared with the previous large directory design at the cost of a large area, the present application can be applied to small systems, and can also ensure directory coverage, that is, achieve the same query accuracy with less hardware overhead, improve the query efficiency and reduce the query power consumption. At the same time, the present application can optimize the dynamic management of the cache space, ensure the efficient utilization of the cache, and avoid cache overflow or data loss.

[0046] The following will describe the present application in detail in combination with the cache coherence maintenance device and the multi-core system provided by the present application.

[0047] Refer to Figure 2, which is a structural block diagram of a multi-core system to which the cache coherence maintenance device according to the embodiment of the present application is applied. Among them, the multi-core system includes multiple processor clusters, each processor cluster includes multiple processor cores, and the multi-core system adopts a multi-level cache architecture: each processor core uses a first-level cache to achieve independent caching, the same processor cluster uses a second-level cache to achieve inter-core sharing, and multiple processor clusters use a third-level cache to achieve inter-cluster sharing. In the figure, AXI, ACE, and CHI are extended interfaces for the interconnection protocol in the multi-core system.

[0048] The cache coherence maintenance device according to the embodiment of the present application includes an inter-core coherence maintenance device and an inter-cluster coherence maintenance device. The inter-core coherence maintenance device is used to ensure data coherence when the second-level cache realizes inter-core sharing among multiple processor cores, and the inter-cluster coherence maintenance device is used to ensure data coherence when the third-level cache realizes inter-cluster sharing among multiple processor clusters. It should be noted that for the convenience of description, in the following detailed description of the inter-core coherence maintenance device and the inter-cluster coherence maintenance device, if not specifically distinguished, they are uniformly abbreviated as the coherence maintenance device, and will not be elaborated below.

[0049] The coherence maintenance device of this embodiment is a device based on hierarchical query and directory-based coherence, and at the same time adopts an eviction mechanism to manage the space of the coherence maintenance device. The coherence maintenance device of the present application dynamically evicts positions that have not been used for a long time or positions that currently need to reserve space most to balance the hardware overhead and achieve efficient maintenance of the coherence maintenance device.

[0050] Specifically, during the search process of the coherence maintenance device, first perform index value matching. After success, search for the tag value in the index row for matching. If the match is successful, it is regarded as a hit, indicating that the current data has been shared and operations need to be performed on the specified processor core; if the match fails, it is regarded as a miss, indicating that the current data has not been shared. If there is data in the second-level / third-level cache, it can be directly returned. After the data response is returned, update the information of the shared processor cores of this row in the coherence maintenance device. At the same time, the coherence maintenance device of this embodiment allows users to configure the eviction threshold and eviction priority. When the space margin is less than the set threshold, eviction is performed spontaneously or preferentially evicted to adapt to different application scenarios and improve the operation efficiency.

[0051] More specifically, refer to Figure 1 , when processor core 0 in processor cluster 0 needs to read and modify data, first query its own first-level cache. If it misses, query the second-level cache and the intra-cluster coherence maintenance device to check whether it is shared among processor cores 1 to n-1.

[0052] If only the second-level cache hits, it means that the current data is not shared by the processor cores. The data will be returned from the second-level cache to processor core 0 and the exclusive core will be recorded by the intra-cluster coherence maintenance device.

[0053] If all misses occur, query the tertiary cache and the inter-cluster coherence maintenance device to check if it is shared among processor clusters 1 to n - 1.

[0054] If only the tertiary cache hits, it means the current data is not shared by the processor clusters. The data will be returned from the tertiary cache to processor cluster 0 and the exclusive cluster will be recorded by the inter-cluster coherence maintenance device.

[0055] If both the tertiary cache and the inter-cluster coherence maintenance device indicate hits, it means that some other cluster is sharing the data. First, invalidate the relevant processor cluster (such as processor cluster n - 1) and write back the cache lines in the modified state (Modified state in the MESI protocol) to the main memory. Send the invalidate request to processor cluster n - 1 as instructed. After receiving the request, query the secondary cache and the intra-cluster coherence maintenance device, invalidate the data in the secondary / primary cache as instructed, and write back the modified state data to the main memory to complete the request.

[0056] Reference Figure 3, which is the structural block diagram of the consistency maintenance device provided in this embodiment. The consistency maintenance device includes an index value, a valid bit, a tag value, and an indication. The consistency maintenance device in this embodiment queries the directory hierarchically, and after the index value matches successfully, it then matches the tag value to confirm the cache line sharing information of the cache line in the directory. In addition to carrying address information, the cache line sharing information has three flag information (valid bit, host indication bit, and dirty data bit). Among them, the index is used to locate the cache line address, and each cache line has an index, which is used to locate the line in the consistency maintenance device. Multiple index values (index 0 to index n - 1) are shown in the figure, and each index value corresponds to a cache line. The valid bit is used to indicate whether there is a hit. If there is a shared information record for the current address line, it remains high, indicating that the consistency maintenance device has a hit, that is, the valid bit can indicate whether the cache line is valid. Each cache line has a valid bit, which is used to indicate whether the line stores valid data. For example, if the valid bit is 1, it means the line is valid; if it is 0, it means the line is invalid. The tag value is used to represent the main memory block corresponding to the cache line. When the processor accesses the data in the cache line, it will use the tag part of the cache line address to match the tag value in the consistency maintenance device to determine whether the data is in the cache. The indication is used to represent the sharing state and modification state of the data. The indication includes a host indication bit and a dirty data bit. The host indication bit is used to indicate in which processor cores / clusters the hit address exists, that is, which processor cores or clusters have copies of the cache line. The dirty data bit is used to indicate in which processor core / cluster the modified state copy of the hit address exists, that is, whether the data in the cache line has been modified (i.e., dirty data). For example, if the dirty data bit is 1, it means the data in the line has been modified and the data in the main memory needs to be updated when written back to the main memory. When facing a dirty data write-back transaction, only the request needs to be forwarded to the location of the modified state copy, without forwarding to all shared processor cores.

[0057] Exemplarily, when the processor accesses data, it will use the index value to match the tag value in the consistency maintenance device. If a matching tag value is found and the valid bit is 1, it means the data is in the cache and the data can be directly read from the cache. Through the host indication bit and the dirty data bit, the consistency maintenance device can track the sharing state and modification state of the data. When a processor modifies the data in the cache line, it will set the dirty data bit to 1 and update the host indication bit to reflect the sharing state of the data. When the cache line needs to be replaced, if the dirty data bit is 1, the modified data needs to be written back to the main memory. The consistency maintenance device will indicate to write the data back to the correct location in the main memory. Through the host indication bit, the consistency maintenance device can track which processor cores or clusters have copies of the cache line. When a processor accesses data, if the host indication bit shows that other processor cores or clusters also have copies of the cache line, a consistency protocol needs to be executed to ensure that the data seen by all processor cores or clusters is consistent.

[0058] In some embodiments, the coherence maintenance device has m ways, that is, each index value can store up to m different tag values. When the system writes information to the coherence maintenance device, the lower n bits of the cache line address are expanded as the index value, and the remaining high bits are written to this line as the tag value. The valid bit and the corresponding host indication bit are set high, and the processor core number is written to the dirty data bit, indicating that the current processor core / cluster has a copy and there is a modified state. When a read transaction is received, it will go to the processor core indicated by the dirty data bit to read the latest data; when an invalidate transaction is received, it will go to the host indication bit to indicate the processor core to perform an invalidate operation.

[0059] As addresses are continuously written, the coherence maintenance device will eventually face the problem of being full. Refer to Figure 4 for the flowchart of the judgment for the coherence maintenance device to execute the maintenance method. The coherence maintenance device confirms the write position through the write pointer and confirms the eviction position through the eviction pointer. The object to be evicted is the cache line sharing information that has not been used for the longest time.

[0060] In this embodiment, the cache line sharing information used each time is placed at the position of the latest write pointer, and the remaining cache line sharing information is moved before the latest write pointer position. The cache line sharing information at the very front is determined as the one that has not been used for the longest time, so as to more quickly and accurately determine the object to be evicted and perform the eviction operation. Specifically, the sharing information of the cache line where the data exists is located before the write pointer and after the eviction pointer. Here, before and after refer to the front and back in the direction of pointer movement. Therefore, it is defined that the recorded cache line sharing information is located before the write pointer and after the eviction pointer; if the cache line sharing information used this time is recorded in the directory, this cache line sharing information is extracted and placed at the position of the latest write pointer, and the positions of the remaining cache line sharing information are moved forward; if the cache line sharing information used this time is not recorded in the directory, this cache line sharing information is placed at the position of the latest write pointer, and the positions of the remaining cache line sharing information remain unchanged; the position after the eviction pointer is determined as the cache line sharing information that has not been used for the longest time, and the position before the write pointer is determined as the cache line sharing information that has been used most recently. Exemplarily, assume that there are 10 cache line sharing information spaces in the directory: 1 - 10. If the current write pointer position is 2 and the eviction pointer position is 5, then the data exists in 5, 6, 7, 8, 9, 10, 1. The position where the next data will be stored is 2, and the position where the next data will be evicted is 5.

[0061] At the beginning of use, two thresholds are set through parameters, namely the normal threshold and the emergency threshold. When the processor core accesses the cache line, it is judged whether the sum of the write pointer and the emergency threshold exceeds the eviction pointer. If it exceeds, it means that the risk of data filling in this index line is relatively high, and it is necessary to raise the arbitration clear bit and the priority bit to give priority to eviction. The eviction quantity is 1, and the eviction process does not affect writing new data, so the actual eviction quantity may be greater than 1, that is, eviction continues until the sum of the write pointer and the emergency threshold is less than the eviction pointer. If it does not exceed, it is judged whether the sum of the write pointer and the normal threshold exceeds the eviction pointer. If it exceeds, it means that the current margin is less than the normal threshold, and it is necessary to raise the arbitration clear bit, invalidate the data copy and write the modified state data back to the main memory. At this time, the eviction does not set the priority, and similarly, the eviction quantity may be greater than 1, and eviction continues until the sum of the write pointer and the normal threshold is less than the eviction pointer.

[0062] Due to the existence of the real-time maintenance function, the consistency maintenance device can ensure the same query accuracy with relatively small hardware overhead. At the same time, the read operation only goes to the modified state processor core for monitoring, which further reduces the number of accesses. The setting of the dynamic threshold makes the eviction method of the consistency maintenance device more flexible. Therefore, while maintaining less hardware overhead, the advantages brought by maintaining the second-level / third-level cache consistency are faster query speed and lower query power consumption.

[0063] In summary, the consistency maintenance device and the multi-core system of the present application can record cache line sharing information, maintain cache consistency, and reduce query power consumption; compared with the traditional hierarchical query consistency maintenance device, it retains the advantage of accurate query while taking into account low hardware overhead, and allows adjustment of the eviction threshold and eviction priority; compared with the grouped query consistency maintenance device, it has the advantage of no false hits, has a clearer indication for read operations, and reduces unnecessary access times.

[0064] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are shown in sequence according to the arrows, these steps do not necessarily need to be executed in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps does not have a strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages do not necessarily need to be executed at the same time, but can be executed at different times. The execution order of these steps or stages does not necessarily need to be sequential, but can be executed alternately or alternately with at least a part of other steps or steps in other steps.

[0065] Based on the same inventive concept, an embodiment of the present application further provides a cache coherence maintenance device. This device maintains the coherence of shared data among multiple-core processors through the cache coherence maintenance method of any of the above embodiments. The implementation solution for the cache coherence maintenance device to solve the problem is similar to the implementation solution described in the above method. Therefore, the specific limitations in the embodiments of the cache coherence maintenance device provided below can refer to the limitations for a cache coherence maintenance method in the foregoing text and will not be elaborated herein.

[0066] In one embodiment, the present application further provides a multi-core system. This system includes a cache coherence maintenance device as in the above embodiment and multiple processor cores. The system maintains the coherence of shared data among multiple-core processors through the cache coherence maintenance method of any of the above embodiments. The system further includes a secondary cache shared among different processor cores in the same processor cluster and a tertiary cache shared among multiple processor clusters; the coherence maintenance device includes an inter-core coherence maintenance device and an inter-cluster coherence maintenance device. The inter-core coherence maintenance device is used to maintain data coherence when the secondary cache is shared among multiple processor cores to achieve inter-core sharing, and the inter-cluster coherence maintenance device is used to maintain data coherence when the tertiary cache is shared among multiple processor clusters to achieve inter-cluster sharing.

[0067] In one embodiment, the present application further provides an electronic device. The electronic device includes one or more processors; a memory; one or more application programs, where one or more application programs are stored in the memory and configured to be executed by one or more processors, and one or more application programs are configured to execute a cache coherence maintenance method as in any of the above embodiments.

[0068] It should be noted that for those of ordinary skill in the art in the technical field of the present application, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application. It should be understood that certain features of the present disclosure described in the context of separate embodiments for clarity can also be provided in a single embodiment by combination. Conversely, the various features of the present disclosure described in the context of a single embodiment for clarity can also be provided separately or in any suitable combination or as any other described embodiment of the present disclosure.

Claims

1. A cache coherence maintenance method, characterized in that, The method includes: Obtaining a write pointer and an eviction pointer of a directory, where the write pointer indicates the directory address currently written in the directory, the eviction pointer indicates the directory address currently evicted from the directory, the directory includes cache line sharing information, determining the maximum value of the directory address according to the space size of the directory, and after the write pointer and the eviction pointer reach the maximum value, starting counting from 0 again; Configuring an emergency threshold and a normal threshold, and the emergency threshold is less than the normal threshold; If the sum of the write pointer and the emergency threshold is greater than the eviction pointer, setting it to a high priority and preferentially performing directory eviction; if the sum of the write pointer and the emergency threshold is less than or equal to the eviction pointer, and the sum of the write pointer and the normal threshold is greater than the eviction pointer, setting it to a low priority and performing directory eviction; where the directory eviction means evicting the cache line sharing information that has not been used for the longest time in the directory; Repeating the above steps until the sum of the write pointer and the normal threshold is less than the eviction pointer.

2. The cache coherence maintenance method according to claim 1, wherein The method further includes: when the eviction pointer catches up with the write pointer, it means that the directory has been completely evicted; when the write pointer catches up with the eviction pointer, it means that the directory is completely occupied.

3. A cache coherence maintenance method according to claim 1, characterized in that Determining the cache line that has not been used for the longest time in the directory includes: defining that the recorded cache lines are before the write pointer and after the eviction pointer; When the processor accesses a cache line, if the cache line used this time has been recorded in the directory, extracting the cache line sharing information and placing it at the position of the latest write pointer, and moving the positions of the remaining cache line sharing information forward; if the cache line used this time has not been recorded in the directory, placing the cache line sharing information at the position of the latest write pointer, and keeping the positions of the remaining cache line sharing information unchanged; Determining the position after the eviction pointer as the cache line sharing information that has not been used for the longest time.

4. A cache coherence maintenance method according to claim 1, characterized in that The method is used to maintain the consistency of data sharing between multi-core processors. When the processor accesses a cache line, the directory query first matches according to the index value, and after successful matching, then performs tag value matching to confirm the cache line sharing information of the cache line in the directory; where the cache line sharing information includes the cache line address, expanding the lower n bits of the cache line address as the index value, and using the remaining high bits of the cache line address as the tag value.

5. A cache coherence maintenance method according to claim 4, wherein Each index value carries flag information, and the flag information includes a valid bit, a host indication bit, and a dirty data bit; When writing cache line sharing information, raising the valid bit and the corresponding host indication bit, and writing the processor number into the dirty data bit, indicating that the current processor has a cache line copy and there is a modified state; When receiving a read transaction, going to the processor indicated by the dirty data bit to read the latest data; When receiving an invalidate transaction, going to the processor indicated by the host indication bit to perform an invalidate operation.

6. A cache coherence maintenance method according to claim 1, characterized in that In the case where the sum of the write pointer and the emergency threshold is greater than the eviction pointer, preferentially evicting by raising the arbitration clear bit and the priority bit; When the sum of the write pointer and the emergency threshold is less than or equal to the eviction pointer, and the sum of the write pointer and the normal threshold is greater than the eviction pointer, eviction is performed by raising the arbitration clear bit and lowering the priority bit.

7. A cache coherence maintenance method according to claim 6, wherein During directory eviction, writing to cache lines continues, and continuous eviction is performed at a preset eviction speed until the sum of the write pointer and the normal threshold is less than the eviction pointer.

8. A cache coherence maintenance device, characterized in that, The device maintains the consistency of shared data among multi-core processors through the cache coherence maintenance method described in any one of claims 1-7 above.

9. A multi-core system, characterized in that, The system includes a cache coherence maintenance device as described in claim 8 and multiple processor cores. The system maintains the consistency of shared data among multi-core processors through the cache coherence maintenance method described in any one of claims 1-7 above. The system further includes a secondary cache shared among different processor cores in the same processor cluster and a tertiary cache shared among multiple processor clusters. The coherence maintenance device includes an inter-core coherence maintenance device and an inter-cluster coherence maintenance device. The inter-core coherence maintenance device is used to maintain data consistency when the secondary cache is shared among multiple processor cores to achieve inter-core sharing, and the inter-cluster coherence maintenance device is used to maintain data consistency when the tertiary cache is shared among multiple processor clusters to achieve inter-cluster sharing.

10. An electronic device, characterized in that, The electronic device includes one or more processors; a memory; one or more applications, where one or more applications are stored in the memory and configured to be executed by one or more processors, and one or more applications are configured to execute a cache coherence maintenance method as described in any one of claims 1-7 above.

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