Source driving circuit and display device

Abstract

The invention provides a source electrode driving circuit and a display device, the source electrode driving circuit comprises a plurality of chip-on-film bonded on a display panel side by side, each chip-on-film comprises a source electrode driving chip and a first signal line connected with the source electrode driving chip and a data line of the display panel, each source electrode driving chip judges a polarity switching mode of the source electrode driving chip, and the first signal line is connected with the first signal line. When the polarity switching modes of the first signal lines of the two adjacent chip-on-films are opposite and the polarities of the adjacent first signal lines are the same, one of the two adjacent first signal lines of the two adjacent chip-on-films is switched to point overturning, the polarity of the first signal line is switched line by line, and the polarity of the first signal line is different from that of the adjacent first signal line; therefore, dark lines are weakened, and the display effect is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of display panels, and in particular relates to a source driving circuit and a display device. Background Art

[0002] A plurality of flip-chip films are bonded in a conventional display panel. The flip-chip films include a source driver chip. The source driver chip outputs multiple data signals to multiple data lines of the display panel to realize the driving operation of the display panel.

[0003] With the development of display technology, display panels tend to develop towards larger size and higher resolution. Correspondingly, the number of chip-on-chip films in display panels has increased relatively. There are differences between data transmission and actual effects between different chip-on-chip films, resulting in adjacent output channels having the same polarity in the same frame. During the frame switching process, the pixel units between the two data lines connected to the adjacent output channels experience brightness changes, resulting in the existence of dark lines, which reduces the display effect of the display panel. Summary of the invention

[0004] The object of the present invention is to provide a source driving circuit, aiming to solve the problem of dark lines of the same polarity appearing in adjacent output channels of the traditional source driving circuit in the same frame.

[0005] A first aspect of an embodiment of the present invention provides a source driving circuit, comprising: A plurality of flip-chip films bonded to the display panel in parallel, each of the flip-chip films comprising a source driver chip and a plurality of first signal lines, the source driver chip outputting a plurality of data signals through the plurality of first signal lines, the plurality of first signal lines of each flip-chip film being connected to a group of data lines in the display panel, the plurality of groups of data lines being arranged in parallel in sequence, and each group of data lines comprising an even number of data lines; Wherein, when the polarity switching mode of the plurality of first signal lines of the 2i-1th chip-on-chip film is opposite to the polarity switching mode of the plurality of first signal lines of the 2i-th chip-on-chip film, the polarity of one of the two adjacent first signal lines of the 2i-1th chip-on-chip film and the 2i-th chip-on-chip film switches polarity row by row in a dot flipping mode when the display panel is driven row by row, wherein i is a positive integer; The polarity switching mode is a first polarity switching mode or a second polarity switching mode. The first polarity switching mode is periodically switched in the order of the first polarity to the second polarity. The second polarity switching mode is periodically switched in the order of the second polarity to the first polarity. The first polarity and the second polarity are positive and negative polarities to each other.

[0006] Optionally, the source driver chip of the 2i-1th flip chip switches the polarities of the plurality of first signal lines connected thereto in sequence according to the first polarity mode in response to the first level signal of the first polarity switching signal, or switches the polarities of the plurality of first signal lines connected thereto in sequence according to the second polarity mode in response to the second level signal of the first polarity switching signal, and the first level signal and the second level signal are opposite level signals; The 2ith source driver chip of the flip chip film switches the signals of multiple first signal lines connected thereto in sequence according to the first polarity mode in response to the third level signal of the second polarity switching signal, and switches the signals of multiple first signal lines connected thereto in sequence according to the second polarity switching signal in response to the fourth level signal of the second polarity switching signal, and the third level signal and the fourth level signal are opposite level signals.

[0007] Optionally, the chip-on-film further comprises a film body, and the film body comprises a plurality of circuit layers; The two adjacent first signal lines of the 2i-1th COF and the 2ith COF are located in different circuit layers of the film body.

[0008] Optionally, two adjacent first signal lines of the 2i-1th COF and the 2ith COF are respectively located on the surface layer of the film body and the inner layer adjacent to the surface layer of the film body; The non-adjacent first signal lines of the 2i-1th COF and the 2ith COF are located on the surface layer of the film body.

[0009] Optionally, the nth first signal line of the 2i-1th flip chip film is located in the inner layer of the film body, or the first first signal line of the 2ith flip chip film is located in the inner layer of the film body, and the nth first signal line of the 2i-1th flip chip film is arranged adjacent to the first first signal line of the 2ith flip chip film.

[0010] Optionally, the source driver chip is integrated into the film body; The source driver chip is connected to the first signal line located in the inner layer of the film body through a via hole.

[0011] Optionally, the flip chip film further comprises a plurality of second signal lines, each of which is stacked on one of the first signal lines located in the inner layer and connected to a source driver chip of the same flip chip film; When the polarity switching mode of the multiple first signal lines of the 2i-1th flip chip film is the same as the polarity switching mode of the multiple first signal lines of the 2ith flip chip film, the source driver chip corresponding to the flip chip film outputs a data signal through the second signal line, and the polarity of the data signal of the second signal line is switched according to the frame inversion mode.

[0012] Optionally, the chip-on-film further includes a plurality of switching switches; The first signal line and the second signal line which are stacked are respectively connected in series with one of the switches; The source driver chip is used for: When the polarity switching mode of the plurality of first signal lines of the 2i-1th chip-on-film is the same as the polarity switching mode of the plurality of first signal lines of the 2ith chip-on-film, controlling the switch serially connected to the second signal line to be turned on; When the polarity switching mode of the multiple first signal lines of the 2i-1th flip chip film is opposite to the polarity switching mode of the multiple first signal lines of the 2ith flip chip film, the switch serially connected to the first signal line located in the inner layer is controlled to be turned on.

[0013] Optionally, the source driver chip is further used for: When the polarity switching mode of the plurality of first signal lines of the 2i-1th chip-on-film is the same as the polarity switching mode of the plurality of first signal lines of the 2ith chip-on-film, outputting the first data signal to the second signal line; And when the polarity switching mode of the multiple first signal lines of the 2i-1th flip chip film is opposite to the polarity switching mode of the multiple first signal lines of the 2ith flip chip film, a second data signal is output to the first signal line located in the inner layer, and the second data signal is greater than the first data signal.

[0014] A second aspect of an embodiment of the present invention provides a display device, including a display panel and the source driving circuit as described above.

[0015] Compared with the prior art, the beneficial effects of the embodiments of the present invention are as follows: the above-mentioned source driving circuit includes a plurality of flip-chip films bonded to the display panel in parallel, the flip-chip films include a source driving chip and a first signal line connecting the source driving chip and the data line of the display panel, each source driving chip determines its own polarity switching mode, and when the polarity switching modes of the first signal lines of two adjacent flip-chip films are opposite, when the polarities of adjacent first signal lines are the same, one of the two adjacent first signal lines of the two adjacent flip-chip films is switched to point flipping, the polarity of the first signal line is switched row by row, and the polarity is different from that of the adjacent first signal line, thereby weakening the dark line and improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0017] Figure 1 A schematic diagram of the structure of a display panel provided in Embodiment 1 of the present invention; Figure 2 A schematic diagram of a first waveform of adjacent data lines provided in the first embodiment of the present invention; Figure 3 A schematic diagram of a second waveform of adjacent data lines provided in the first embodiment of the present invention; Figure 4 A third waveform diagram of adjacent data lines provided in the first embodiment of the present invention; Figure 5 A schematic diagram of a first structure of a chip-on-chip film provided in the second embodiment of the present invention; Figure 6 A schematic diagram of a second structure of a chip-on-chip film provided in the second embodiment of the present invention; Figure 7 A third structural schematic diagram of the chip-on-chip film provided in the second embodiment of the present invention; Figure 8 A fourth structural schematic diagram of the chip-on-film provided in the second embodiment of the present invention; Fig. 9 A schematic diagram of a first structure of a chip-on-chip film provided in Embodiment 3 of the present invention; Fig.10 A schematic diagram of a second structure of a chip-on-chip film provided in the third embodiment of the present invention; Fig.11 A third structural schematic diagram of the chip-on-film provided in the third embodiment of the present invention; Fig.12 This is a schematic diagram of the structure of a display device provided in Embodiment 4 of the present invention. DETAILED DESCRIPTION

[0018] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0019] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0020] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0021] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0022] A first aspect of an embodiment of the present invention provides a source driving circuit 100, comprising a plurality of flip-chip films 110 bonded side by side to a display panel 200, wherein the display panel 200 comprises a display area 210 and a non-display area 220, the non-display area 220 comprises a bonding area, the flip-chip film 110 is bonded to the bonding area, the display area 210 comprises a plurality of data lines, a plurality of scan lines and a pixel unit 230, the pixel unit 230 is respectively connected to a data line and a scan line, the plurality of data lines can be a plurality of groups according to the number of flip-chip films 110, the plurality of groups of data lines are arranged side by side in sequence, each group of data lines comprises an even number of data lines, for example, each group of data lines comprises 996 data lines, the plurality of data lines of each group are respectively connected to the flip-chip film 110 and input multiple data signals, the scan lines are also connected to the gate driving circuit 300 and input row scan signals to perform row-by-row scanning and data signal writing, the data signals are written to the pixel unit 230, so that the display panel 200 displays corresponding image information.

[0023] Among them, each flip chip film 110 includes a source driver chip 111 and a plurality of first signal lines L1. The source driver chip 111 outputs multiple data signals through the plurality of first signal lines L1. The plurality of first signal lines L1 of each flip chip film 110 are connected to a group of data lines in the display panel 200. Correspondingly, each flip chip film 110 includes at least the same number of first signal lines L1 as a group of data lines. For example, each flip chip film 110 includes 966 first signal lines L1.

[0024] Among them, the display panel 200's own architectural design and product principles will cause parasitic capacitance. For example, parasitic capacitance is generated between the pixel electrode of the pixel unit 230 and the adjacent data line. The parasitic capacitance will cause the original output voltage to be coupled with each other, resulting in a difference from the ideal value. This is one of the reasons for the appearance of dark lines.

[0025] Secondly, in the image display, different polarity switching signals are usually selected to control the signal polarity on the first signal line L1 of the odd-numbered flip chip films 110 and the even-numbered flip chip films 110 respectively, so as to switch the polarity of the data signal on each data line to avoid polarization problems, such as Figure 1 As shown, when the two polarity switching signals are different, the polarity switching mode of the data signals output to the corresponding data lines by the odd-numbered source driver chips 111 is different from the polarity switching mode of the data signals output to the corresponding data lines by the even-numbered source driver chips 111, the polarities of the two adjacent data lines corresponding to the two first signal lines L1 between the odd and even flip chip films 110 become incoherent, which is manifested as the polarities of the two first signal lines L1 at the junction of the flip chip films 110 being the same as the polarities of the two correspondingly connected data lines being the same, for example, the first data line D1 correspondingly connected to the first source driver chip 111 and the nth data line Dn correspondingly connected to the second source driver chip 111 having the same polarity, resulting in the coupling degree of the data lines to the pixel electrodes at the junction being different from that in other areas, ultimately presenting a problem of dark lines at the junction.

[0026] We take the 64 grayscale image as an example, and divide the coupling of the entire pixel electrode into three periods for analysis: display period, analysis of the first row, when the first pixel unit 230 between the two data lines at the junction is charged, the row scan signal is input, and the first data line D1 corresponding to the first flip chip film 110 is charged to the negative polarity L64 (V_L64N), at this time, the nth data line Dn corresponding to the second flip chip film 110 is a negative polarity 0 grayscale voltage, after charging is completed, the first row scan signal is turned off, and the data signals of the two adjacent data lines corresponding to the two adjacent flip chip films 110 continue to be transmitted to charge the pixel units 230 of the subsequent rows, such as Figure 2 Shown and Figure 3 As shown, the data changes of two adjacent data lines corresponding to two adjacent flip-chip films 110 are opposite, and in the display period, the coupling voltages on the pixel electrodes cancel each other out. Therefore, it can be known that there is no coupling voltage in the actual period.

[0027] During the data processing period, no data signal is output and the pixel unit 230 does not display. At this time, the coupling direction of the two adjacent data lines corresponding to the two adjacent flip chip films 110 to the pixel electrode is a single direction, and the coupling amount is ΔV, ΔV=V_L64N-0.

[0028] During the frame switching period, the polarity of each first signal line L1 and each first signal line L1 is switched, the positive polarity is switched to the negative polarity, and the negative polarity is switched to the positive polarity, wherein the positive polarity refers to the voltage polarity greater than the common electrode voltage Vcom, and the negative polarity refers to the voltage polarity less than the common electrode voltage Vcom, and the common electrode voltage Vcom is the reference voltage. The adjacent two data lines corresponding to the adjacent two flip chip films 110 are changed from the same polarity on the previous one to the same polarity on the next one, for example, from the "--" polarity to the "+ +” polarity, the data signal after polarity switching of the first row of pixel units 230 between the two adjacent data lines corresponding to the two adjacent flip chip films 110 is refreshed and switched fastest, and the switched data signal is output to the pixel electrode of the first row of pixel units 230, and then the coupling situation of the display period is repeated. Correspondingly, the voltage and coupling amount waveform of the image cable electrode of the last row of pixel units 230 between the two adjacent data lines corresponding to the two adjacent flip chip films 110 can be derived. Because the scanning is line-by-line scanning, before the last row of pixel units 230 is turned on, the voltage of the pixel electrode of the last row of pixel units 230 maintains the data of the previous frame, and there is a large cross-voltage with the voltage of the data signal on the data line of the current frame, resulting in a large coupling, and the coupling voltage is smaller, so it is displayed as a dark line, and the closer the pixel unit 230 is to the bottom, the more serious the coupling will be, so the dark line phenomenon is not a through line, and the closer to the top, the lighter the phenomenon.

[0029] To this end, in this embodiment, when the polarity switching mode of the plurality of first signal lines L1 of the 2i-1th COF 110 is opposite to the polarity switching mode of the plurality of first signal lines L1 of the 2i-th COF 110, the polarity of one of the two adjacent first signal lines L1 of the 2i-1th COF 110 and the 2i-th COF 110 is switched row by row in a dot flip mode when the display panel 200 is driven row by row, wherein i is a positive integer; The polarity switching mode is a first polarity switching mode or a second polarity switching mode. The first polarity switching mode is periodically switching in the order of the first polarity to the second polarity. The second polarity switching mode is periodically switching in the order of the second polarity to the first polarity. The first polarity and the second polarity are positive and negative polarities to each other.

[0030] In this embodiment, the source driver chip 111 in each flip chip film 110 determines its own polarity switching mode according to the received polarity switching signal, and judges whether it is the first polarity switching mode or the second polarity switching mode, and whether the polarity switching mode of the source driver chip 111 of the adjacent flip chip film 110 is different. In the first polarity switching mode, the polarities of the multiple first signal lines L1 and data lines corresponding to each source driver chip 111 are periodically switched in sequence according to the first polarity and the second polarity, for example, they are periodically switched in sequence of positive polarity, negative polarity, positive polarity, and negative polarity, and in the second polarity switching mode, the polarities of the multiple first signal lines L1 and data lines corresponding to each source driver chip 111 are periodically switched in sequence according to the second polarity and the first polarity, for example, they are periodically switched in sequence of negative polarity, positive polarity, negative polarity, and positive polarity.

[0031] When the polarity switching modes of the two are the same, the multiple first signal lines L1 corresponding to each flip chip film 110 are switched in sequence according to the same polarity switching method. For example, the multiple first signal lines L1 corresponding to the first flip chip film 110 are switched in sequence according to positive polarity, negative polarity, positive polarity, and negative polarity. Correspondingly, the multiple first signal lines L1 corresponding to the adjacent second flip chip film 110 are also switched in sequence according to positive polarity, negative polarity, positive polarity, and negative polarity. At this time, the polarities of the two adjacent data lines corresponding to the two adjacent flip chip films 110 are opposite, and there is no different coupling effect on the pixel unit 230 between the two adjacent data lines, and no dark lines are generated.

[0032] On the contrary, when the polarity switching modes of the two are opposite, e.g. Figure 1 As shown, the first flip chip film 110 corresponding to the plurality of first signal lines L1 connected is switched in sequence according to positive polarity, negative polarity, positive polarity, and negative polarity, and the adjacent second flip chip film 110 corresponding to the plurality of first signal lines L1 connected is switched in sequence according to negative polarity, positive polarity, negative polarity, and positive polarity. The polarities of the two adjacent data lines corresponding to the two adjacent flip chip films 110 are the same, both of which are negative polarities. Different coupling effects will appear on the pixel units 230 between the two adjacent data lines, resulting in the problem of dark lines appearing at the junction. Therefore, when it is determined that the polarity switching modes of the two are opposite, one of the two adjacent data lines corresponding to the two adjacent flip chip films 110 is switched to point flipping, such as Figure 4As shown, during line-by-line scanning, the data line of the row is periodically switched in sequence of the first polarity and the second polarity. For example, the polarity change mode on the nth data line Dn connected to the second flip chip film 110 is switched to dot flipping, or the polarity change mode on the first data line D1 connected to the first flip chip film 110 is switched to dot flipping. The polarity switching direction of other first signal lines L1 and data lines connected to the flip chip film 110 remains unchanged, and only the polarity switching mode of one of the two adjacent data lines connected to the two adjacent flip chip films 110 is changed. Since the signal polarity on the data line is no longer fixed and is different from the polarity of the adjacent data line corresponding to the adjacent flip chip film 110, the dark line is weakened and the display effect is improved.

[0033] Among them, the source driver chip 111 of each flip chip film 110 can be switched accordingly according to the received polarity switching signal. In an optional embodiment, the source driver chip 111 of the 2i-1th flip chip film 110 is subjected to the first level signal of the first polarity switching signal to switch the polarities of the multiple first signal lines L1 connected in sequence according to the first polarity mode, or is subjected to the second level signal of the first polarity switching signal to switch the polarities of the multiple first signal lines L1 connected in sequence according to the second polarity mode. The first level signal and the second level signal are opposite level signals, for example, the first level signal is a high level, and the second level signal is a low level. Therefore, after receiving the high level, the polarities of the multiple first signal lines L1 connected to the odd number of source driver chips 111 are periodically changed in sequence according to the first polarity and the second polarity, and when receiving the low level, the polarities of the multiple first signal lines L1 connected to the odd number of source driver chips 111 are periodically changed in sequence according to the second polarity and the first polarity.

[0034] The source driver chip 111 of the 2i-th flip chip 110 switches the signals of the multiple first signal lines L1 connected thereto in sequence according to the first polarity mode in response to the third level signal of the second polarity switching signal, and switches the signals of the multiple first signal lines L1 connected thereto in sequence according to the second polarity mode in response to the fourth level signal of the second polarity switching signal. The third level signal and the fourth level signal are opposite level signals. For example, the third level signal is a high level, and the fourth level signal is a low level. Therefore, after receiving a high level, the polarities of the multiple first signal lines L1 connected to an even number of source driver chips 111 change periodically in sequence according to the first polarity and the second polarity, and when receiving a low level, the polarities of the multiple first signal lines L1 connected to an even number of source driver chips 111 change periodically in sequence according to the second polarity and the first polarity.

[0035] Assuming that the first level signal and the third level signal are high levels, and the second level signal and the fourth level signal are low levels, when the source driver chips 111 of adjacent odd-numbered and even-numbered flip chip films 110 receive high levels and low levels respectively, the source driver chips 111 of two adjacent flip chip films 110 switch the polarity of one of the two adjacent first signal lines L1 of the two flip chip films 110 to point switching, thereby reducing parasitic voltage and improving dark lines.

[0036] When the source driver chips 111 of adjacent odd-numbered and even-numbered flip chip films 110 simultaneously receive a high level or a low level, the source driver chips 111 of two adjacent flip chip films 110 switch the two adjacent first signal lines L1 of the two flip chip films 110 according to the normal frame switching mode, that is, the polarity direction is switched after each frame ends.

[0037] Compared with the prior art, the embodiment of the present invention has the following beneficial effects: the above-mentioned source driving circuit 100 includes a plurality of flip-chip films 110 bonded to the display panel 200 in parallel, the flip-chip film 110 includes a source driving chip 111 and a first signal line L1 connecting the source driving chip 111 and the data line of the display panel 200, each source driving chip 111 determines its own polarity switching mode, and when the polarity switching modes of the first signal lines L1 of two adjacent flip-chip films 110 are opposite, when the polarities of the adjacent first signal lines L1 are the same, one of the two adjacent first signal lines L1 of the two adjacent flip-chip films 110 is switched to dot flipping, and the polarity of the first signal line L1 is switched row by row, and the polarity is different from that of the adjacent first signal line L1, thereby weakening the dark line and improving the display effect.

[0038] Embodiment 2 Among them, when the polarity switching modes of the source driver chips 111 of two adjacent flip-chip films 110 are opposite, when one of the two adjacent data lines corresponding to the two adjacent flip-chip films 110 is in the dot flip mode, there is still a situation where the polarity of the data line switched in the adjacent frame is the same half of the time, and there is a problem of different parasitic voltages in some pixel units 230, and there are some dark lines. Therefore, in order to further improve the dark line problem, as Figure 1 , Figure 5 and Figure 6 As shown, the flip chip 110 further includes a film body 112, on which the source driver chip 111 and the first signal line L1 are integrated, wherein the film body 112 includes a multi-layer circuit layer 1121; Two adjacent first signal lines L1 of the 2i-1th COF 110 and the 2ith COF 110 are located in different circuit layers 1121 of the film body 112 .

[0039] In this embodiment, two adjacent flip chip films 110 corresponding to two adjacent first signal lines L1 are routed in different layers, for example Figure 5 As shown, the first first signal line L1_1 corresponding to the first flip chip film 110 is set on the layer of the film body 112, and the nth first signal line L1_n corresponding to the second flip chip film 110 is set on the lower layer of the film body 112, or as shown in FIG. Figure 6 As shown, the first first signal line L1_1 corresponding to the first flip chip film 110 is set in the lower layer of the film body 112, and the nth first signal line L1_n corresponding to the second flip chip film 110 is set in the upper layer of the film body 112. The two adjacent first signal lines L1 corresponding to the two adjacent flip chip films 110 adopt different-layer routing, and there are no parallel routing and overlapping routing, which weakens the coupling of the two adjacent data lines corresponding to the two adjacent flip chip films 110, thereby eliminating dark lines.

[0040] Among them, the film body 112 can be provided with a multi-layer circuit layer 1121, and the two adjacent first signal lines L1 of the 2i-1th flip chip film 110 and the 2i-th flip chip film 110 can be respectively arranged in different layers. In an optional embodiment, the two adjacent first signal lines L1 of the 2i-1th flip chip film 110 and the 2i-th flip chip film 110 are respectively located on the surface layer of the film body 112 and the inner layer adjacent to the surface layer of the film body 112, and the non-adjacent first signal lines L1 of the 2i-1th flip chip film 110 and the 2i-th flip chip film 110 are located on the surface layer of the film body 112.

[0041] For example Figure 5 and Figure 6 As shown, the film body 112 has two layers, and two adjacent first signal lines L1 corresponding to two adjacent flip-chip films 110 are respectively arranged on the surface layer and the bottom layer of the film body 112, and the remaining non-adjacent first signal lines L1 are normally arranged on the surface layer of the film body 112, and are normally routed on the surface layer through copper foil routing.

[0042] Among them, the flip chip film 110 includes multiple, i.e., two adjacent first signal lines L1 corresponding to multiple adjacent flip chip films 110, wherein the layered arrangement of the two adjacent first signal lines L1 corresponding to each adjacent flip chip film 110 may be the same or different, for example, the first first signal line L1_1 of the first flip chip film 110 is arranged on the surface layer of the film body 112, and the nth first signal line L1_n of the second flip chip film 110 is arranged on the bottom layer, the first first signal line L1_1 of the second flip chip film 110 may be arranged on the surface layer or the bottom layer of the film body 112, and the nth first signal line L1_n of the third flip chip film 110 may be arranged on the bottom layer or the surface layer, and the specific arrangement method is not limited.

[0043] In order to unify the wiring and simplify the wiring method, in an optional embodiment, the nth first signal line L1 of the 2i-1th flip chip film 110 is located in the inner layer of the film body 112, or the first first signal line L1 of the 2i-1th flip chip film 110 is located in the inner layer of the film body 112, and the nth first signal line L1 of the 2i-1th flip chip film 110 is adjacent to the first first signal line L1 of the 2i-1th flip chip film 110, that is, the wiring method of each flip chip film 110 is the same, for example Figure 7 As shown, the nth first signal line L1 in each flip chip film 110 is located in the inner layer of the film body 112, or as shown in FIG. Figure 8 As shown, the first first signal line L1 in each COF 110 is located in the inner layer of the film body 112 .

[0044] Correspondingly, the source driver chip 111 is integrated into the surface layer of the thin film body 112, and the source driver chip 111 is directly connected to the first signal line L1 located on the surface layer, and is connected to the first signal line L1 located on the inner layer of the thin film body 112 through a via, wherein holes can be drilled downward at the corresponding signal end position of the source driver chip 111 for routing.

[0045] Embodiment 3 Furthermore, in order to simplify the routing, Fig. 9 and Fig.10 As shown, the COF 110 further includes a plurality of second signal lines L2, each of which is stacked on a first signal line L1 located in the inner layer and connected to the source driver chip 111 of the same COF 110; When the polarity switching mode of the multiple first signal lines L1 of the 2i-1th flip chip film 110 is the same as the polarity switching mode of the multiple first signal lines L1 of the 2ith flip chip film 110, the source driver chip 111 corresponding to the flip chip film 110 outputs the data signal through the second signal line L2, and the polarity of the data signal of the second signal line L2 is switched according to the frame inversion mode.

[0046] In the present embodiment, when the polarity switching modes of an odd number of chip-on-chip films 110 and an even number of chip-on-chip films 110 are the same, each chip-on-chip film 110 is periodically switched in the corresponding first polarity and second polarity sequence or periodically switched in the corresponding second polarity and first polarity sequence, and each adjacent first signal line L1 and the corresponding data line do not have the same polarity. At this time, the wiring can be normally performed according to the original structure, that is, two adjacent chip-on-chip films 110 normally output data signals corresponding to non-adjacent first signal lines L1, and the source driver chip 111 outputs data signals through the second signal line L2 located on the surface, and each first signal line L1 and data line switches polarity according to the frame flip mode.

[0047] When the polarity switching modes of an odd number of chip-on-chip films 110 and an even number of chip-on-chip films 110 are opposite, the two adjacent chip-on-chip films 110 corresponding to the non-adjacent first signal lines L1 arranged on the film body 112 output data signals normally, and the source driver chip 111 outputs data signals through the first signal line L1 located at the bottom layer of the film body 112. The first signal line L1 located at the bottom layer of the film body 112 switches polarity according to the dot flip mode, thereby weakening the coupling problem and eliminating the dark line problem.

[0048] Among them, the output ends of the second signal line L2 located on the surface of the film body 112 and the first signal line L1 located on the bottom layer of the film body 112 are connected in common, and their input ends can be connected in common to the same signal end of the source driver chip 111 or not connected in common to different signal ends of the source driver chip 111. In an optional embodiment, in order to ensure that the resources of the signal end of the source driver chip 111 are avoided from being increased, the input ends of the second signal line L2 located on the surface of the film body 112 and the first signal line L1 located on the bottom layer of the film body 112 are connected in common to the same signal end of the source driver chip 111. Therefore, in order to realize the output of data signals with different polarity switching modes, in an optional embodiment, as Fig.11 As shown, the flip chip 110 further includes a plurality of switching switches K1; The stacked first signal line L1 and the second signal line L2 are respectively connected in series with a switch K1; The source driver chip 111 is used for: When the polarity switching mode of the plurality of first signal lines L1 of the 2i-1th COF 110 is the same as the polarity switching mode of the plurality of first signal lines L1 of the 2ith COF 110, the switch K1 serially connected to the second signal line L2 is controlled to be turned on; When the polarity switching mode of the multiple first signal lines L1 of the 2i-1th COF 110 is opposite to the polarity switching mode of the multiple first signal lines L1 of the 2ith COF 110, the switch K1 serially connected to the first signal line L1 located in the inner layer is controlled to be turned on.

[0049] In this embodiment, the source driver chip 111 is also respectively connected to each switching switch K1 on the corresponding flip chip film 110. When the odd-numbered source driver chips 111 and the even-numbered source driver chips 111 both receive a high level or a low level, the polarity switching mode of the multiple first signal lines L1 of the odd-numbered flip chip films 110 is the same as the polarity switching mode of the multiple first signal lines L1 of the even-numbered flip chip films 110. At this time, there is no parasitic voltage, and the data signal with positive and negative polarity changes can be normally output through the first signal line L1 and the second signal line L2 located on the surface. At this time, the source driver chip 111 controls the switching switch K1 connected in series to the second signal line L2 to turn on, and the data signal in the frame flip mode is normally output through the first signal line L1 and the second signal line L2 located on the surface. Data signal with positive and negative polarity changes.

[0050] And when the odd-numbered source driver chips 111 and the even-numbered source driver chips 111 receive a high level and a low level respectively, the polarity switching mode of the multiple first signal lines L1 of the odd-numbered flip chip films 110 is opposite to the polarity switching mode of the multiple first signal lines L1 of the even-numbered flip chip films 110. At this time, there is a parasitic voltage that causes dark lines to be generated. At this time, data signals with positive and negative polarity changes can be output through the first signal line L1 located on the surface layer and the first signal line L1 located on the bottom layer. At this time, the source driver chip 111 controls the switching switch K1 connected in series to the first signal line L1 located on the bottom layer of the film body 112 to be turned on, and the data signal of the frame flip mode is normally output through the first signal line L1 located on the surface layer. The data signal of the point flip mode is output through the first signal line L1 located on the bottom layer.

[0051] Among them, each switching switch K1 can be connected to different signal terminals of the source driver chip 111 or to the same signal terminal. When each switching switch K1 is connected to the same signal terminal of the source driver chip 111, the switching switch K1 connected in series to the second signal line L2 and the switching switch K1 connected in series to the first signal line L1 of the bottom layer are of opposite types. For example, the switching switch K1 connected in series to the second signal line L2 is an NMOS tube, and the switching switch K1 connected in series to the first signal line L1 of the bottom layer is a PMOS tube. The control terminals of each switching switch K1 are connected. When the polarity switching mode of the multiple first signal lines L1 of the odd-numbered flip chip films 110 is the same as the polarity switching mode of the multiple first signal lines L1 of the even-numbered flip chip films 110, the source driver chip 111 outputs a high level to trigger the NMOS tube to turn on and the PMOS tube to turn off; and when the polarity switching mode of the multiple first signal lines L1 of the odd-numbered flip chip films 110 is opposite to the polarity switching mode of the multiple first signal lines L1 of the even-numbered flip chip films 110, the source driver chip 111 outputs a low level to trigger the NMOS tube to turn off and the PMOS tube to turn on.

[0052] Furthermore, the signal lines located in the inner layer are longer than the signal lines located in the surface layer, and have a larger impedance. When the source driver chip 111 outputs data signals of the same magnitude to the signal lines located in the inner layer and the signal lines located in the surface layer, there is a difference in the voltage magnitude of the data signals output to the data lines, resulting in bright and dark lines on the display panel 200. Therefore, in an optional embodiment, the source driver chip 111 is further used to: When the polarity switching mode of the plurality of first signal lines L1 of the 2i-1th COF 110 is the same as the polarity switching mode of the plurality of first signal lines L1 of the 2ith COF 110, the first data signal is output to the second signal line L2; When the polarity switching mode of the multiple first signal lines L1 of the 2i-1th flip chip film 110 is opposite to the polarity switching mode of the multiple first signal lines L1 of the 2ith flip chip film 110, a second data signal is output to the first signal line L1 located in the inner layer, and the second data signal is greater than the first data signal.

[0053] In the present embodiment, when the second data signal of the dot flip mode is output through the first signal line L1 of the bottom layer, voltage compensation is performed on the second data signal to avoid grayscale deviation caused by the offset of the column data. The voltage of the second data signal is larger than the voltage of the first data signal output to the second signal line L2 of the surface layer, and the voltage difference can be designed according to the length and impedance of the stacked first signal and second signal lines L2. Alternatively, during the test process, the size of the first data signal and the second data signal is adjusted based on the same target brightness, and data is stored. In different polarity switching modes, the data signal of corresponding size is selected to be output to ensure the stability of the display screen.

[0054] Embodiment 4 The present invention further proposes a display device, which includes a source driving circuit 100. The specific structure of the source driving circuit 100 refers to the above embodiment. Since the display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0055] In this embodiment, the display device may further include a gate driving circuit 300 , which is used to output a row scanning signal and cooperate with the row scanning signal output by the source driving circuit 100 to drive the display panel 200 to display corresponding picture information.

[0056] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A source driving circuit, characterized in that: include: A plurality of flip-chip films bonded to the display panel in parallel, each of the flip-chip films comprising a source driver chip and a plurality of first signal lines, the source driver chip outputting a plurality of data signals through the plurality of first signal lines, the plurality of first signal lines of each flip-chip film being connected to a group of data lines in the display panel, the plurality of groups of data lines being arranged in parallel in sequence, and each group of data lines comprising an even number of data lines; Wherein, when the polarity switching mode of the plurality of first signal lines of the 2i-1th chip-on-chip film is opposite to the polarity switching mode of the plurality of first signal lines of the 2i-th chip-on-chip film, the polarity of one of the two adjacent first signal lines of the 2i-1th chip-on-chip film and the 2i-th chip-on-chip film switches polarity row by row in a dot flipping mode when the display panel is driven row by row, wherein i is a positive integer; The polarity switching mode is a first polarity switching mode or a second polarity switching mode. The first polarity switching mode is periodically switched in the order of the first polarity to the second polarity. The second polarity switching mode is periodically switched in the order of the second polarity to the first polarity. The first polarity and the second polarity are positive and negative polarities to each other.

2. The source driving circuit according to claim 1, wherein: The 2i-1th source driver chip of the flip chip film sequentially switches the polarities of the plurality of first signal lines connected thereto according to the first polarity mode in response to the first level signal of the first polarity switching signal, or sequentially switches the polarities of the plurality of first signal lines connected thereto according to the second polarity mode in response to the second level signal of the first polarity switching signal, wherein the first level signal and the second level signal are opposite level signals; The 2ith source driver chip of the flip chip film switches the signals of multiple first signal lines connected thereto in sequence according to the first polarity mode in response to the third level signal of the second polarity switching signal, and switches the signals of multiple first signal lines connected thereto in sequence according to the second polarity switching signal in response to the fourth level signal of the second polarity switching signal, and the third level signal and the fourth level signal are opposite level signals.

3. The source driving circuit according to claim 2, wherein: The chip-on-film further comprises a film body, and the film body comprises a multi-layer circuit layer; The two adjacent first signal lines of the 2i-1th COF and the 2ith COF are located in different circuit layers of the film body.

4. The source driving circuit according to claim 3, characterized in that: The two adjacent first signal lines of the 2i-1th flip chip film and the 2ith flip chip film are respectively located on the surface layer of the film body and the inner layer adjacent to the surface layer of the film body; The non-adjacent first signal lines of the 2i-1th COF and the 2ith COF are located on the surface layer of the film body.

5. The source driving circuit according to claim 4, characterized in that: The nth first signal line of the 2i-1th flip chip film is located in the inner layer of the film body, or the first first signal line of the 2ith flip chip film is located in the inner layer of the film body, and the nth first signal line of the 2i-1th flip chip film is arranged adjacent to the first first signal line of the 2ith flip chip film.

6. The source driving circuit according to claim 4 or 5, characterized in that: The source driver chip is integrated into the film body; The source driver chip is connected to the first signal line located in the inner layer of the film body through a via hole.

7. The source driving circuit according to claim 6, wherein: The flip chip film further comprises a plurality of second signal lines, each of which is stacked on a first signal line located in the inner layer and connected to a source driver chip of the same flip chip film; When the polarity switching mode of the multiple first signal lines of the 2i-1th flip chip film is the same as the polarity switching mode of the multiple first signal lines of the 2ith flip chip film, the source driver chip corresponding to the flip chip film outputs a data signal through the second signal line, and the polarity of the data signal of the second signal line is switched according to the frame inversion mode.

8. The source driving circuit according to claim 7, wherein: The chip-on-film further includes a plurality of switching switches; The first signal line and the second signal line which are stacked are respectively connected in series with one of the switches; The source driver chip is used for: When the polarity switching mode of the plurality of first signal lines of the 2i-1th chip-on-film is the same as the polarity switching mode of the plurality of first signal lines of the 2ith chip-on-film, controlling the switch serially connected to the second signal line to be turned on; When the polarity switching mode of the multiple first signal lines of the 2i-1th flip chip film is opposite to the polarity switching mode of the multiple first signal lines of the 2ith flip chip film, the switch serially connected to the first signal line located in the inner layer is controlled to be turned on.

9. The source driving circuit according to claim 7, wherein: The source driver chip is also used for: When the polarity switching mode of the plurality of first signal lines of the 2i-1th chip-on-film is the same as the polarity switching mode of the plurality of first signal lines of the 2ith chip-on-film, outputting the first data signal to the second signal line; And when the polarity switching mode of the multiple first signal lines of the 2i-1th flip chip film is opposite to the polarity switching mode of the multiple first signal lines of the 2ith flip chip film, a second data signal is output to the first signal line located in the inner layer, and the second data signal is greater than the first data signal.

10. A display device, characterized in that: The invention comprises a display panel and a source driving circuit as claimed in any one of claims 1 to 9.

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