A wck2ck leveling training method and system for LPDDR5

Abstract

The purpose of the present invention is to provide a wck2ck leveling training method and system for LPDDR5, the method comprising: in high frequency mode, adjusting the delay line of the write clock to align the rising edge of the write clock with the rising edge of the differential clock; in low frequency mode, when the write clock passes tWCKENL_WR+tWCKPRE_Static time, switching begins until the timing requirement is met and stops. The present invention can change the order and method of training wck2ck, so that the fine and coarse of wck2ck can be trained after the ca and cs training is completed, and the method of fast positioning and precise search is used when fine is used, so as to get rid of the limitation of training write data, and train the phase relationship between wck and ck without training the write data path, thereby improving the training efficiency and reducing the complexity.

Description

Technical Field

[0001] The present invention relates to the field of dynamic memory technology, and in particular to a wck2ck leveling training method and system for LPDDR5. Background Art

[0002] LPDDR (Low Power Double Data Rate SDRAM) is a low-power double-data-rate dynamic random access memory with the advantages of large capacity, efficient data processing speed, and low power consumption. The main external interfaces of LPDDR5 are divided into control interface and data interface, including differential clock CK_t / c, write clock WCK_t / c, bidirectional data bus DQ, read data select signal RDQS_t / c and command / address signals CA and CS.

[0003] The write clock WCK_t / c is also called the write enable signal, which represents the write enable of data. To complete the normal LPDDR read and write function, it is necessary to ensure that the data is aligned with the input clock CK, that is, WCK and CK must be aligned, otherwise the data cannot be correctly written to the DRAM. For a single DRAM, the clock and data deviation between the DDR controller and the SRAM is generally a fixed routing deviation. This problem can be solved by adding some delay chains to ensure that the CK and WCK reaching the SRAM are aligned; however, for a system composed of multiple DRAM chips, the clock and data deviations of each DRAM are different, and for the controller, it does not know what the deviation is at the SRAM gate. In order to overcome this uncertainty on different DRAMs, it is necessary to perform wck2ck leveling for each DRAM to obtain the compensation size between the clock and data of each DRAM chip.

[0004] Before LPDDR5, the order of training wck2ck was to perform the rising edge alignment training of the write clock and the differential clock on the premise of ensuring that the ca and cs training were completed, and to increase the delay step of the write clock by 1 each time until the edge alignment of the write clock and the differential clock was found; then, after the read gate training, read training, and DFE training, the write DQ and wck2ck coarse were trained at the same time, and the coarse delay of the write clock was continuously adjusted in units of 1UI to ensure that the write clock can meet certain time parameters and the write operation is correct. The write training and wck2ck coarse training are carried out at the same time. By continuously sending write data operations, both the write clock and the read-back data must be guaranteed to be valid, and the data written to the SDRAM must be compared with the data read back. The disadvantage of this is that the training complexity is increased and the training speed is relatively low. Summary of the invention

[0005] The purpose of the present invention is to provide a wck2ck leveling training method and system for LPDDR5. The method can train the fine and coarse of wck2ck after the ca and cs training is completed by changing the order and method of training wck2ck. The method uses a fast positioning and precise search method during fine training to get rid of the limitation of training write data. The phase relationship between wck and ck is trained without training the write data path, thereby improving the training efficiency and reducing the complexity.

[0006] A wck2ck leveling training method for LPDDR5, comprising:

[0007] In high-frequency mode, adjust the delay line of the write clock to align the rising edge of the write clock with the rising edge of the differential clock;

[0008] In low-frequency mode, the write clock starts switching after tWCKENL_WR + tWCKPRE_Static time and stops when the timing requirements are met.

[0009] Preferably, in the high frequency mode, adjusting the delay line of the write clock to align the rising edge of the write clock with the rising edge of the differential clock comprises:

[0010] When the rising edge of the write clock is before the rising edge of the differential clock, the SDRAM uses the rising edge of the write clock to sample the differential clock to get 0, and feeds 0 back to DQ;

[0011] The delay line increases by 5 each time to push the write clock back until the value of DQ changes from 0 to 1.

[0012] Decrement the delay line by 1 each time and write the clock back until the DQ transition from 1 to 0 is detected.

[0013] The value of the backfilled delay line is increased by 1.

[0014] Preferably, in the high frequency mode, adjusting the delay line of the write clock to align the rising edge of the write clock with the rising edge of the differential clock comprises:

[0015] When the rising edge of the write clock is after the rising edge of the differential clock, the SDRAM uses the rising edge of the write clock to sample the differential clock to get 1, and feeds 1 back to DQ;

[0016] If the differential clock: write clock is in 1:4 mode, increase the write clock by 4UI so that the rising edge of the write clock is before the rising edge of the differential clock;

[0017] Increase the delay line by 5 each time to push back the write clock until the value of DQ jumps from 0 to 1;

[0018] Reduce the delay line by 1 each time and rewind the write clock until DQ changes from 1 to 0.

[0019] The value of the backfilled delay line is increased by 1.

[0020] Preferably, in the high frequency mode, adjusting the delay line of the write clock to align the rising edge of the write clock with the rising edge of the differential clock comprises:

[0021] When the rising edge of the write clock is aligned with the rising edge of the differential clock, the SDRAM uses the rising edge of the write clock to sample the differential clock to get 0, and feeds 0 back to DQ;

[0022] Increase the delay line by 5 each time to push back the write clock until the value of DQ jumps from 0 to 1;

[0023] Reduce the delay line by 1 each time and rewind the write clock until DQ changes from 1 to 0.

[0024] The value of the backfilled delay line is increased by 1.

[0025] Preferably, in the low frequency mode, when the write clock passes through tWCKENL_WR+tWCKPRE_Static time, switching starts until the timing requirement is met and stops, including:

[0026] Without training the read and write data paths, the coarse training of wck2ck is completed by sending the differential clock and the write clock to the SDRAM.

[0027] Preferably, in the low frequency mode, when the write clock passes through tWCKENL_WR+tWCKPRE_Static time, switching starts until the timing requirement is met and stops, including:

[0028] A frequency divider is used inside the PHY to generate a 25MHz low-frequency differential clock and send it to the SDRAM;

[0029] Generate a 50MHz write clock and send it to SDRAM, making the differential clock: write clock = 1:2;

[0030] The write clock is switched by firmware written into SRAM, and the write clock is sent out two cycles after the differential clock is switched;

[0031] In the case of slow speed, push the write clock back by 1UI;

[0032] Push the write clock at the SDRAM gate to align with the third rising edge of the differential clock.

[0033] Preferably, the step of pushing the write clock at the SDRAM gate to the third rising edge of the differential clock for alignment comprises:

[0034] In the case of slow speed, the write clock is continuously pushed back by 1UI;

[0035] Push the write clock at the SDRAM gate to align with the third rising edge of the differential clock.

[0036] Preferably, the step of pushing the write clock at the SDRAM gate to the third rising edge of the differential clock for alignment comprises:

[0037] The SDRAM uses the rising edge of the write clock to sample the value of the differential clock, and obtains 0 or 1 to be fed back to DQ;

[0038] Send the value of DQ to the register;

[0039] When the value read from the DQ register changes from 0 to 1, the rising edge of the write clock is pushed from before the rising edge of the differential clock to the rising edge of the differential clock.

[0040] A wck2ck leveling training system for LPDDR5, comprising:

[0041] The fine adjustment module is used to adjust the delay line of the write clock in the high-frequency mode to align the rising edge of the write clock with the rising edge of the differential clock;

[0042] The coarse adjustment module is used in low-frequency mode to start switching when the write clock passes the tWCKENL_WR + tWCKPRE_Static time and stop when the timing requirements are met.

[0043] An electronic device comprises: a chip, a processor and a memory, wherein the memory is used to store computer program code, the computer program code comprises computer instructions, and when the chip executes the computer instructions, the electronic device executes a wck2ck leveling training method for LPDDR5.

[0044] The beneficial effects of the present invention are: 1. The present invention trains wck2ck after CA / CS training is completed, and only needs to control the phase relationship between the write clock and the differential clock. There is no need to simultaneously train the two-dimensional situation of coarse and write data, and no attention is paid to the read and write data paths, which greatly reduces complexity; 2. In the present invention, fine training is divided into fast positioning and precise searching, and the three phase relationships between the write clock and ck at the initial time are converted into one situation, thereby reducing training time; 3. The Coarse training of the present invention is carried out closely following the Fine training, and the write clock and the differential clock are generated through the internal interface of the PHY, so as to realize the timing of the write clock and the differential clock of the SDRAM port, thereby greatly saving training time, reducing complexity, and improving training efficiency; 4. The present invention has high applicability and can be equipped with various types of SDRAM particles. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0046] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0047] Figure 1 A flow chart of a wck2ck leveling training method for LPDDR5 of the present invention;

[0048] Figure 2 A schematic diagram of the fine adjustment phase relationship of the present invention;

[0049] Figure 3 This is a schematic diagram of the internal structure of the coarse adjustment PHY of the present invention;

[0050] Figure 4 It is a schematic diagram of the adjustment result of the present invention;

[0051] Figure 5 The figure is a schematic diagram of the hardware structure of an electronic device of the present invention. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0054] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0055] Before LPDDR5, the order of training wck2ck was to perform the rising edge alignment training of the write clock and the differential clock on the premise of ensuring that the ca and cs training were completed, and to increase the delay step of the write clock by 1 each time until the edge alignment of the write clock and the differential clock was found; then, after the read gate training, read training, and DFE training, the write DQ and wck2ck coarse were trained at the same time, and the coarse delay of the write clock was continuously adjusted in units of 1UI to ensure that the write clock can meet certain time parameters and the write operation is correct. The write training and wck2ck coarse training are carried out at the same time. By continuously sending write data operations, both the write clock and the read-back data must be guaranteed to be valid, and the data written to the SDRAM must be compared with the data read back. The disadvantage of this is that the training complexity is increased and the training speed is relatively low.

[0056] The present invention trains wck2ck after CA / CS training is completed. It only needs to control the phase relationship between the write clock and the differential clock. It does not need to train the two-dimensional situation of coarse and write data at the same time, does not pay attention to the read and write data paths, and greatly reduces complexity. In the present invention, fine training is divided into fast positioning and precise search, and the three phase relationships of the write clock and ck at the initial time are converted into one situation, which reduces the training time. The Coarse training of the present invention is carried out closely following the Fine training, and the write clock and the differential clock are generated through the internal interface of the PHY to realize the timing of the write clock and the differential clock of the SDRAM port, which greatly saves training time, reduces complexity, and improves training efficiency. The present invention has high applicability and can carry various types of SDRAM particles.

[0057] Example 1

[0058] A wck2ck leveling training method for LPDDR5, reference Figure 1 ,include:

[0059] S100, in high frequency mode, adjusting the delay line of the write clock to align the rising edge of the write clock with the rising edge of the differential clock;

[0060] S200, in low frequency mode, when the write clock passes tWCKENL_WR + tWCKPRE_Static time, it starts switching and stops when the timing requirement is met.

[0061] The DFI interface implements the communication between the Memory Controller and the PHY. The differential clock, WCK and other related signals are sent to the inside of the PHY through the DFI interface, and then sent to the IO end of the differential clock and write clock through the delay line inside the PHY, and finally transmitted to the DDR. WCK2CK leveling is trained for each lane. If x8 DRAM is selected, one DRAM chip only corresponds to one lane, so it only needs to be trained once. If it is a x16 particle, then its two byte lanes need to be trained separately. The existing practice is to continuously adjust the delay line of WCK so that the PAD_CK and PAD_WCK that are finally sent out are aligned, and then the write operation is trained while continuing to push the write clock.

[0062] refer to Figure 5The present invention controls the generation of the write clock and the differential clock inside the PHY, and adjusts the wck delayline, so that the write clock and the differential clock sent to the SDRAM port are aligned and meet the timing parameter requirements of tWCKENL_WR and tWCKPRE_Static. In this way, it can be ensured that the phase relationship between the write clock and the differential clock is correct when performing a write operation, and data can be written into the SDRAM at the appropriate time.

[0063] Preferably, reference Figure 2 , S100, in high frequency mode, adjusting the delay line of the write clock to align the rising edge of the write clock with the rising edge of the differential clock includes:

[0064] When the rising edge of the write clock is before the rising edge of the differential clock, the SDRAM uses the rising edge of the write clock to sample the differential clock to get 0, and feeds 0 back to DQ;

[0065] The delay line increases by 5 each time to push the write clock back until the value of DQ changes from 0 to 1.

[0066] Decrement the delay line by 1 each time and write the clock back until the DQ transition from 1 to 0 is detected.

[0067] The value of the backfilled delay line is increased by 1.

[0068] This patent implements wck2ck leveling after training ca and cs, ensuring that the rising edges of wck and ck are aligned while also ensuring the timing relationship between tWCKENL_WR and tWCKPRE_Static. wck2ck leveling is divided into fine adjustment and coarse adjustment.

[0069] In the fine adjustment stage, the delay line of wck is continuously pushed in high-frequency mode to align the rising edge of wck with the rising edge of ck; the phase relationship between wck and ck sent to SDRAM without delay line is divided into three cases, and this embodiment is the first case: when the rising edge of the write clock is before the rising edge of the differential clock, the SDRAM uses the rising edge of the write clock to sample the differential clock to obtain 0, and feeds 0 back to DQ and can be read out through the register. First, the delay line is incremented by 5 each time to push the write clock back until the value of DQ jumps from 0 to 1, indicating that the fast read has located the right side of the rising edge of the differential clock; then, the delay line is decremented by 1 each time to move the write clock back until the jump of DQ from 1 to 0 is caught, indicating that a little bit to the left of the precise rising edge of the differential clock is found, and the value of the delay line that is finally filled back is incremented by 1, which is the delay value when the write clock and ck are precisely aligned.

[0070] Preferably, in the high frequency mode, adjusting the delay line of the write clock to align the rising edge of the write clock with the rising edge of the differential clock includes:

[0071] When the rising edge of the write clock is after the rising edge of the differential clock, the SDRAM uses the rising edge of the write clock to sample the differential clock to get 1, and feeds 1 back to DQ;

[0072] If the differential clock: write clock is in 1:4 mode, increase the write clock by 4UI so that the rising edge of the write clock is before the rising edge of the differential clock;

[0073] Increase the delay line by 5 each time to push back the write clock until the value of DQ jumps from 0 to 1;

[0074] Reduce the delay line by 1 each time and rewind the write clock until DQ changes from 1 to 0.

[0075] The value of the backfilled delay line is increased by 1.

[0076] This embodiment is the second case: when the rising edge of the write clock is after the rising edge of the differential clock, the SDRAM uses the rising edge of the write clock to sample the differential clock to obtain 1, and feeds 1 back to DQ and can be read out through the register. If the differential clock: write clock is in 1:4 mode, then the write clock is directly increased by 4UI, that is, it is converted to the first case, that is, the rising edge of the write clock is before the rising edge of the differential clock, and the following steps are the same as the first case.

[0077] Preferably, S100, in the high frequency mode, adjusting the delay line of the write clock to align the rising edge of the write clock with the rising edge of the differential clock includes:

[0078] When the rising edge of the write clock is aligned with the rising edge of the differential clock, the SDRAM uses the rising edge of the write clock to sample the differential clock to get 0, and feeds 0 back to DQ;

[0079] Increase the delay line by 5 each time to push back the write clock until the value of DQ jumps from 0 to 1;

[0080] Reduce the delay line by 1 each time and rewind the write clock until DQ changes from 1 to 0.

[0081] The value of the backfilled delay line is increased by 1.

[0082] This embodiment is the third case. The write clock and the differential clock are already in an aligned state, and the method of the first case can be directly used for alignment.

[0083] Preferably, S200, in the low frequency mode, when the write clock passes the time tWCKENL_WR+tWCKPRE_Static, the switching starts and stops until the timing requirement is met, including:

[0084] Without training the read and write data paths, the coarse training of wck2ck is completed by sending the differential clock and the write clock to the SDRAM.

[0085] ‌WCK2CK training is a technology for clock phase detection that is implemented through metadata error correction (meta-EDC) scanning and an adjustable precision voting algorithm. ‌ This training mechanism is mainly used to ensure the accuracy and stability of the clock signal, thereby improving the performance and reliability of the system. WCK2CK training consists in using metadata error correction (meta-EDC) scanning, a special technology for detecting and adjusting the phase of the clock signal. Through this scanning, the system is able to accurately determine the optimal phase of the clock signal, thereby optimizing the transmission quality and speed of the data. In addition, WCK2CK training is combined with an adjustable precision voting algorithm to further improve the accuracy of the voting and ensure the stability and reliability of the clock signal. In practical applications, WCK2CK training is essential to improving the performance of high-speed memory interfaces. For example, in high-speed memory technologies such as GDDR6, WCK2CK training can help ensure the accurate transmission of data and reduce error rates, thereby improving overall system performance. In addition, this training mechanism can also help extend the service life of the device because by optimizing the clock signal, potential damage caused by signal instability can be reduced.

[0086] ‌Coarse-to-Fine training is a progressively refined training method that is primarily used to improve the accuracy and performance of a model. ‌ This method trains the model in stages, gradually improving the performance of the model from coarse granularity to fine granularity. The basic principle of Coarse-to-Fine training is to start training the model at a coarse level and then gradually refine it to a finer level. This method typically involves multiple stages, each of which trains for a different granularity and task, thereby gradually improving the accuracy and performance of the model.

[0087] ‌LPDDR5's WCK2CK training is a process that ensures that the WCK and CK clock signals are properly aligned. ‌ To achieve error-free delay control, LPDDR5 SDRAM needs to detect or reset its alignment status through WCK2CK synchronization. When the controller issues a CAS command with a WCK2CK synchronization bit, the controller provides half-frequency WCK pulses to the SDRAM to mitigate inter-symbol interference (ISI), thereby improving the timing margin and reducing the difficulty of phase alignment. In LPDDR5, the frequency of WCK is four times or two times the frequency of the CK clock. To ensure the correct alignment of the clock signals, LPDDR5 detects or resets its alignment status through the WCK2CK synchronization process. This process involves complex clock control and signal processing to ensure accurate data transmission and stability of processing. ‌ In specific implementation, LPDDR5's WCK2CK training is completed by issuing a CAS command with a WCK2CK synchronization bit. This command provides half-frequency WCK pulses to the SDRAM to mitigate inter-symbol interference and improve the timing margin, thereby reducing the difficulty of phase alignment. This operation is critical to ensure the stable operation of LPDDR5 at high speeds. ‌

[0088] Preferably, S200, in the low frequency mode, when the write clock passes the time tWCKENL_WR+tWCKPRE_Static, the switching starts and stops until the timing requirement is met, including:

[0089] S210, uses a frequency divider inside the PHY to generate a 25MHz low-frequency differential clock and sends it to the SDRAM;

[0090] S220, generates a 50MHz write clock and sends it to SDRAM, making the differential clock: write clock = 1:2;

[0091] S230, the write clock is switched by firmware through SRAM, and the write clock is sent again two cycles after the differential clock is switched;

[0092] Firmware is a computer firmware used to write programs, which can improve device performance, enhance device security, and optimize device functions. In a solid-state drive, firmware is responsible for managing the algorithms for reading, writing, and transmitting, such as managing the storage location of data in NAND, recording defective sectors in NAND and avoiding reuse. By optimizing these algorithms, firmware can significantly improve the read and write speed and stability of the device. Firmware can protect device security by controlling the underlying operations of hardware devices. For example, in a server, firmware enables the operating system to control hardware through standard device drivers, which are usually stored in erasable ROM and can be upgraded to fix problems and improve user experience. This design enables firmware to provide higher security and prevent unauthorized access or operation. Firmware can implement specific functions of a device by controlling the underlying operations of hardware devices. For example, the BIOS (Basic Input / Output System) on a computer motherboard is a type of firmware, which is responsible for system startup and hardware configuration. By optimizing the settings of the BIOS, the performance of the hardware can be better utilized.

[0093] SRAM is a static random access memory, which can keep the data stored in it permanently as long as it is powered on. In contrast, the data stored in dynamic random access memory (DRAM) needs to be updated periodically. However, when the power supply stops, the data stored in SRAM will still disappear (called volatile memory), which is different from ROM or flash memory that can still store data after power failure. SRAM does not need a refresh circuit to save the data stored inside it. DRAM (Dynamic Random Access Memory) needs to be refreshed and charged every once in a while, otherwise the internal data will disappear, so SRAM has higher performance.

[0094] S240, push the write clock back by 1UI in the case of slow speed;

[0095] S250, pushes the write clock at the SDRAM gate to align with the third rising edge of the differential clock.

[0096] In the embodiment of the present invention, first, a frequency divider is used inside the PHY to generate a 25MHz low-frequency differential clock and send it to the SDRAM. In addition, a 50MHz write clock is generated and sent to the SDRAM to ensure that the differential clock: write clock = 1:2. The switch of the write clock is written by the firmware through the SRAM. The phase relationship between the write clock and ck must meet the protocol relationship of the SDRAM. The protocol stipulates that at 25MHz, tWCKENL_WR = 1tck, tWCKPRE_Static = 1tck. Therefore, for SDRAM, it is hoped to obtain a phase relationship of the write clock at the third rising edge position of the differential clock, so the write clock should be sent out two cycles after the differential clock is switched.

[0097] Preferably, S250, pushing the write clock at the SDRAM gate to the third rising edge of the differential clock for alignment includes:

[0098] S251, in the case of slow speed, continuously pushes back the write clock in units of 1UI;

[0099] S252, push the write clock at the SDRAM gate to align with the third rising edge of the differential clock.

[0100] In the embodiment of the present invention, in order to consider the delay effect of PCB and wiring, the time of sending the write clock on the PHY side is 2*twck ahead of ck. Therefore, as long as the uncertainty delay in the write clock transmission process is less than the margin of 2*twck, the write clock sent to the SDRAM gate must be earlier than the third rising edge of the differential clock, which simplifies the steps of adjusting coarse.

[0101] Preferably, S252, pushing the write clock at the SDRAM gate to the third rising edge of the differential clock for alignment includes:

[0102] S2521, the SDRAM uses the rising edge of the write clock to sample the value of the differential clock, and obtains 0 or 1 to feedback on DQ;

[0103] S2522, send the value of DQ to the register;

[0104] S2523, when the value of the DQ register read is changed from 0 to 1, the rising edge of the write clock is pushed from before the rising edge of the differential clock to the rising edge of the differential clock.

[0105] In the embodiment of the present invention, the write clock is pushed back continuously in units of 1UI at a slow speed, and the write clock at the SDRAM gate is pushed to the third rising edge of the differential clock for alignment. In this process, the SDRAM will use the rising edge of the write clock to sample the value of the differential clock, and get 0 or 1 to feedback on the DQ, and the value of DQ will be sent to the register. We only need to read the value of the DQ register from 0 to 1, then we know that the rising edge of the write clock is pushed from before the rising edge of the differential clock to the rising edge of the differential clock.

[0106] Example 2

[0107] A wck2ck leveling training system for LPDDR5, comprising:

[0108] The fine adjustment module is used to adjust the delay line of the write clock in the high-frequency mode to align the rising edge of the write clock with the rising edge of the differential clock;

[0109] The main function of the fine adjustment module is to ensure accurate alignment of clock signals and reduce latency. ‌ By fine-tuning the alignment between the write clock and the differential clock, LPDDR5 is able to improve the accuracy and stability of data transmission, thereby improving overall system performance. The fine adjustment of WCK2CK leveling involves fine-tuning the clock signal to ensure the alignment of the write clock with the CK state. In LPDDR5, the frequency of the write clock can be four times or two times the frequency of the differential clock. In order to achieve error-free delay control, LPDDR5 resets or detects its alignment state through a process called WCK2CK synchronization. When the controller issues a CAS command with a WCK2CK synchronization bit, the controller provides a half-frequency write clock pulse to the SDRAM to mitigate inter-symbol interference (ISI), thereby improving the timing margin and reducing the difficulty of phase alignment. ‌ LPDDR5 introduces a new clock scheme, in which the synchronization of the differential clock and the bidirectional DQS (data strobe signal) is key. By fine-tuning the alignment of the write clock and the differential clock, LPDDR5 is able to improve the accuracy and stability of data transmission, thereby improving overall system performance. This fine adjustment ensures accurate alignment of clock signals during high-speed data transmission, reducing delays and errors, and improving system reliability and efficiency.

[0110] The coarse adjustment module is used in low-frequency mode to start switching when the write clock passes the tWCKENL_WR + tWCKPRE_Static time and stop when the timing requirements are met.

[0111] The main function of the coarse adjustment module is to roughly adjust the clock of LPDDR5 so as to quickly adjust the initial position of the clock, which can greatly improve the adjustment efficiency.

[0112] Example 3

[0113] An electronic device includes: a chip, a processor and a memory, the memory is used to store computer program code, the computer program code includes computer instructions, and when the chip executes the computer instructions, the electronic device executes a wck2ck leveling training method for LPDDR5.

[0114] refer to Figure 5 , the electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, the memory 22, the input device 23, and the output device 24 are coupled via a connector, and the connector includes various interfaces, transmission lines, or buses, etc., which are not limited in the embodiments of the present invention. It should be understood that in various embodiments of the present invention, coupling refers to mutual connection in a specific manner, including direct connection or indirect connection through other devices, for example, through various interfaces, transmission lines, buses, etc.

[0115] The processor 21 may be one or more graphics processing units (GPUs). When the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Optionally, the processor 21 may be a processor group consisting of multiple GPUs, and the multiple processors are coupled to each other via one or more buses. Optionally, the processor may also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0116] The memory 22 can be used to store computer program instructions and various computer program codes including program codes for executing the scheme of the present invention. Optionally, the memory includes but is not limited to random access memory (RAM), read-only memory (ROM), erasable programmable read only memory (EPROM), or portable read only memory (CD-ROM), which is used for related instructions and data.

[0117] The input device 23 is used to input data and / or signals, and the output device 24 is used to output data and / or signals. The output device 24 and the input device 23 may be independent devices or an integrated device.

[0118] The present invention trains wck2ck after CA / CS training is completed. It only needs to control the phase relationship between the write clock and the differential clock. It does not need to train the two-dimensional situation of coarse and write data at the same time, does not pay attention to the read and write data paths, and greatly reduces complexity. In the present invention, fine training is divided into fast positioning and precise search, and the three phase relationships of the write clock and ck at the initial time are converted into one situation, which reduces the training time. The Coarse training of the present invention is carried out closely following the Fine training, and the write clock and the differential clock are generated through the internal interface of the PHY to realize the timing of the write clock and the differential clock of the SDRAM port, which greatly saves training time, reduces complexity, and improves training efficiency. The present invention has high applicability and can carry various types of SDRAM particles.

[0119] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A wck2ck leveling training method for LPDDR5, characterized in that: include: In high-frequency mode, adjust the delay line of the write clock to align the rising edge of the write clock with the rising edge of the differential clock; In the high frequency mode, adjusting the delay line of the write clock to align the rising edge of the write clock with the rising edge of the differential clock includes: When the rising edge of the write clock is before the rising edge of the differential clock, the SDRAM uses the rising edge of the write clock to sample the differential clock to get 0, and feeds 0 back to DQ; The delay line increases by 5 each time to push the write clock back until the value of DQ changes from 0 to 1. Reduce the delay line by 1 each time and rewind the write clock until DQ changes from 1 to 0. The value of the backfilled delay line is increased by 1; When the rising edge of the write clock is after the rising edge of the differential clock, the SDRAM uses the rising edge of the write clock to sample the differential clock to get 1, and feeds 1 back to DQ; If the differential clock: write clock is in 1:4 mode, increase the write clock by 4UI so that the rising edge of the write clock is before the rising edge of the differential clock; Increase the delay line by 5 each time to push back the write clock until the value of DQ jumps from 0 to 1; Reduce the delay line by 1 each time and rewind the write clock until DQ changes from 1 to 0. The value of the backfilled delay line is increased by 1; When the rising edge of the write clock is aligned with the rising edge of the differential clock, the SDRAM uses the rising edge of the write clock to sample the differential clock to get 0, and feeds 0 back to DQ; Increase the delay line by 5 each time to push back the write clock until the value of DQ jumps from 0 to 1; Reduce the delay line by 1 each time and rewind the write clock until DQ changes from 1 to 0. The value of the backfilled delay line is increased by 1; In low-frequency mode, the write clock starts switching after tWCKENL_WR + tWCKPRE_Static time and stops when the timing requirements are met.

2. A wck2ck leveling training method for LPDDR5 according to claim 1, characterized in that: In the low-frequency mode, when the write clock passes the time tWCKENL_WR+tWCKPRE_Static, the switching starts and stops until the timing requirement is met, including: Without training the read and write data paths, the coarse training of wck2ck is completed by sending the differential clock and the write clock to the SDRAM.

3. A wck2ck leveling training method for LPDDR5 according to claim 2, characterized in that: In the low-frequency mode, when the write clock passes the time tWCKENL_WR+tWCKPRE_Static, the switching starts and stops until the timing requirement is met, including: A frequency divider is used inside the PHY to generate a 25MHz low-frequency differential clock and send it to the SDRAM; Generate a 50MHz write clock and send it to SDRAM, making the differential clock: write clock = 1:2; The write clock is switched by firmware written into SRAM, and the write clock is sent out two cycles after the differential clock is switched; In the case of slow speed, push the write clock back by 1UI; Push the write clock at the SDRAM gate to align with the third rising edge of the differential clock.

4. A wck2ck leveling training method for LPDDR5 according to claim 3, characterized in that: The step of pushing the write clock at the SDRAM gate to the third rising edge of the differential clock for alignment includes: In the case of slow speed, the write clock is continuously pushed back by 1UI; Push the write clock at the SDRAM gate to align with the third rising edge of the differential clock.

5. A wck2ck leveling training method for LPDDR5 according to claim 4, characterized in that: The step of pushing the write clock at the SDRAM gate to the third rising edge of the differential clock for alignment includes: The SDRAM uses the rising edge of the write clock to sample the value of the differential clock, and obtains 0 or 1 to be fed back to DQ; Send the value of DQ to the register; When the value read from the DQ register changes from 0 to 1, the rising edge of the write clock is pushed from before the rising edge of the differential clock to the rising edge of the differential clock.

6. A wck2ck leveling training system for LPDDR5, applied to a wck2ck leveling training method for LPDDR5 as claimed in any one of claims 1 to 5, characterized in that: include: The fine adjustment module is used to adjust the delay line of the write clock in the high-frequency mode to align the rising edge of the write clock with the rising edge of the differential clock; The coarse adjustment module is used in low-frequency mode to start switching when the write clock passes the tWCKENL_WR + tWCKPRE_Static time and stop when the timing requirements are met.

7. An electronic device, characterized in that: include: A chip, a processor and a memory, wherein the memory is used to store computer program code, wherein the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device executes a wck2ckleveling training method for LPDDR5 as described in any one of claims 1 to 5.

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