Phase-locked loop circuit and corresponding operating method thereof
By introducing comparator, digital logic circuit and finite state machine into the PLL circuit, compensation for the change of control voltage Vtune is achieved, which solves the problem of unstable frequency of the PLL circuit output signal, and realizes the stability of frequency and compensation independence.
Patent Information
- Application Number
- CN202411198276.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-08-02
- Filing Date
- 2024-08-29
- Publication Date
- 2025-03-14
AI Technical Summary
When the existing PLL circuit controls the change of voltage Vtune, it is difficult to effectively compensate for unwanted changes caused by factors such as temperature changes and device aging, resulting in unstable output signal frequency.
A PLL circuit is designed, including a comparator circuit, a digital logic circuit and a finite state machine (FSM). By comparing the control voltage with the comparison signal, a detection signal and a compensation signal are generated, and the operation of the VCO circuit is iteratively adjusted to achieve the desired value of the control voltage.
It realizes simple and effective compensation for the unwanted change of the VCO control voltage. It is independent of the reasons for the change and does not require a special temperature sensor to ensure the stability of the output signal frequency.
Smart Images
Figure CN119628627A_ABST
Abstract
Description
[0001] CROSS-REFERENCE TO RELATED APPLICATIONS
[0002] This application is a translation of and claims the benefit of priority from Italian Application No. 102023000018714, filed on September 12, 2023, entitled “Phase-locked loop circuit and corresponding method of operation”, which is incorporated herein by reference to the maximum extent permitted by law. Technical Field
[0003] The present description relates to a phase-locked loop (PLL) circuit and its corresponding operating method. Such a PLL circuit may be applied, for example, to digital radios and the like. Background Art
[0004] A phase-locked loop is a control system that generates an output periodic signal whose phase is related to the phase of an input (reference) periodic signal. A conventional PLL circuit consists of a voltage-controlled oscillator (VCO) and a phase detector (PD) arranged in a feedback loop. The oscillator generates an output signal at a specific frequency, and the phase detector compares the phase of the output signal with the phase of the input (reference) signal to adjust the oscillator to maintain phase matching.
[0005] FIG1 is a circuit block diagram of an exemplary conventional charge pump phase-locked loop (CP-PLL) circuit 10. The CP-PLL circuit 10 includes a phase frequency detector circuit 11 (PFD) configured to receive a reference periodic signal Fref (e.g., generated by a local oscillator) and a feedback signal Ffb generated according to an output signal Fvco of the PLL circuit 10. The signal Fref has a reference frequency f ref And the signal Ffb has a frequency f fb The PFD circuit 11 compares the signals Fref and Ffb to generate a phase error signal θ indicating the phase error between the signals Fref and Ffb. err (For example, if the reference signal Fref lags behind the feedback signal Ffb, then θ err is positive, and if the reference signal Fref lags behind the feedback signal Ffb, then θ err is negative). The PLL circuit 10 includes a charge pump circuit 12 (CP), which receives a phase error signal θ err and depends on the phase error signal θ err Generates positive or negative current pulses (for example, if the phase error signal θ err is positive, a positive current pulse is generated, and if the phase error signal θ erris negative, a negative current pulse is generated). The PLL circuit 10 includes a low-pass filter circuit 13 (LPF), which receives the current pulse from the CP circuit 12 and converts the current pulse into a control voltage signal Vtune. The LPF circuit 13 also filters the spurious frequency of the feedback signal Ffb, which is the reference frequency f fb The PLL circuit 10 includes a voltage controlled oscillator circuit 14 (VCO), which receives a control voltage signal Vtune and generates a desired frequency f according to the control voltage signal Vtune. vco The PLL circuit 10 includes a frequency divider circuit 15 (e.g., an integer or fractional frequency divider) that receives the output signal Fvco and generates a feedback signal Ffb by dividing the signal Fvco. In some cases, the frequency division factor may be one, so that f fb =f vco (For example, divider circuit 15 may not be present in the architecture).
[0006] Conventionally, during the design of a PLL circuit, the value of the control voltage Vtune is selected to be a constant (eg, approximately 0.42 V) so that the gain K of the VCO circuit 14 can be optimized. VCO , the current output by the charge pump circuit 12, the size of the low-pass filter circuit 13, and the target voltage and target frequency of the output signal Fvco.
[0007] However, during operation of the PLL circuit, the value of the control voltage Vtune may change due to various phenomena, such as due to temperature changes, device degradation (e.g., aging), changes in the supply voltage of the VCO circuit, etc. For example, FIG. 2 illustrates a waveform of the control voltage Vtune, which is initially set to approximately 0.42 V and changes its value at a certain time T1 when the temperature changes. After a stabilization time, the control voltage Vtune stabilizes at a new value (e.g., approximately 0.32 V at time T2). Therefore, the PLL circuit 10 operates at a different operating point after the temperature changes. As a result, the frequency f of the output signal Fvco changes. vco may vary because it depends on the value of the control voltage Vtune. For example, FIG3 illustrates the frequency f vco and the control voltage Vtune, and shows the frequency f vco can be linearly dependent on the control voltage Vtune, so a decrease in the control voltage Vtune results in a frequency f vco of reduction.
[0008] In some known solutions, since the change of the control voltage Vtune may be caused by the temperature change, a temperature sensor is used to sense the temperature of the PLL circuit and adjust (e.g., compensate) the control voltage Vtune according to the sensed temperature. However, these solutions require the implementation of the temperature sensor and the calibration of the temperature sensor, and are also affected by the sensor accuracy and measurement errors.
[0009] Other known solutions compensate for variations in the control voltage Vtune applied to the VCO circuit, in particular using a control word allowing to vary the capacitance of the VCO circuit (eg selecting between different capacitors in an array of capacitors, or using variable capacitors or varactors) to reach a specification value.
[0010] Therefore, there is a need in the art to provide improved PLL circuits that facilitate compensating for unwanted variations in the VCO control voltage Vtune. Summary of the invention
[0011] It is an object of one or more embodiments to facilitate providing such an improved PLL circuit that can compensate for unwanted variations of the VCO control voltage.
[0012] According to one or more embodiments, this object may be achieved by a phase locked loop circuit having the features set out in the appended claims.
[0013] One or more embodiments may be directed to corresponding methods of operation.
[0014] The claims are an integral part of the technical teaching provided herein with respect to the exemplary embodiments.
[0015] According to one aspect of the present description, a PLL circuit includes a VCO circuit controlled by a control voltage and configured to generate an output periodic signal. The PLL circuit also includes a comparator circuit configured to compare the control voltage with a comparison signal, assert a detection signal in response to the control voltage being higher than the comparison signal, and de-assert the detection signal in response to the control voltage being lower than the comparison signal. The PLL circuit also includes a digital logic circuit configured to receive the detection signal and generate a comparison signal and a compensation signal for controlling the operation of the VCO circuit. The digital logic circuit is further configured to:
[0016] During a first stage of the VCO compensation process, determining and storing a value of a comparison signal corresponding to a current value of a control voltage, and comparing the stored value of the comparison signal to a target value to determine whether the control voltage needs to be increased or decreased; and
[0017] During the second phase of the VCO compensation process, the value of the compensation signal is iteratively changed until the control voltage reaches the desired value.
[0018] Thus, one or more embodiments provide a PLL circuit that can compensate for unwanted variations of a VCO control voltage in a simple manner, regardless of the cause of such variations, and without the need to implement a dedicated temperature sensor.
[0019] According to another aspect of the present description, a method of operating a PLL circuit according to one or more embodiments includes:
[0020] comparing the control voltage to a comparison signal at a comparator circuit, asserting a detection signal in response to the control voltage being higher than the comparison signal, and de-asserting the detection signal in response to the control voltage being lower than the comparison signal;
[0021] receiving the detection signal at the digital logic circuit and generating a comparison signal and generating a compensation signal at the digital logic circuit for controlling the operation of the VCO circuit;
[0022] During a first stage of the VCO compensation process, a value of a comparison signal corresponding to a present value of a control voltage is determined and stored by the digital logic circuit, and the stored value of the comparison signal is compared to a target value by the digital logic circuit to determine whether the control voltage needs to be increased or decreased; and
[0023] During the second phase of the VCO compensation process, the value of the compensation signal is iteratively changed by the digital logic circuit until the control voltage reaches the desired value. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] One or more embodiments will now be described by way of example with reference to the accompanying drawings, in which:
[0025] FIG1 is an exemplary circuit block diagram of a CP-PLL circuit;
[0026] FIG. 2 is an exemplary waveform of possible changes in a control voltage signal of a VCO circuit in a PLL circuit in response to a (pulse) temperature change;
[0027] 3 is an exemplary diagram of a possible (linear) relationship between the value of a control voltage signal of a VCO circuit of a PLL circuit and the frequency of an output signal of the PLL circuit;
[0028] Figure 4 is an exemplary circuit block diagram of a PLL circuit according to one or more embodiments of the present description; and
[0029] Figure 5 is an exemplary state diagram of the operation of a finite state machine (FSM) in a PLL circuit according to one or more embodiments of the present description. DETAILED DESCRIPTION
[0030] In the following description, one or more specific details will be explained in order to provide a deeper understanding of the examples of the embodiments of the present description. The embodiments can be obtained without one or more of these specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not explained or described in detail so as not to obscure certain aspects of the embodiments.
[0031] References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic associated with the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more points of this description do not necessarily refer to the same embodiment. Moreover, particular configurations, structures, or characteristics may be combined in any appropriate manner in one or more embodiments.
[0032] The headings / reference numbers used herein are provided for convenience only and do not limit the scope of protection or the scope of the embodiments.
[0033] Throughout the drawings appended hereto, similar parts or elements are denoted by similar reference numerals / numbers, unless the context indicates otherwise, and the corresponding description will not be repeated for the sake of brevity.
[0034] One or more embodiments are directed to a PLL circuit (e.g., a CP-PLL circuit) having an improved ability to compensate for unwanted variations in a control voltage Vtune that drives the operation of a VCO circuit. In particular, a PLL circuit is provided that includes a digital logic circuit that implements a finite state machine (FSM). The FSM operates to detect variations in the control voltage Vtune (independent of their cause, i.e., not simply due to temperature variations), and compensates for such variations, thereby leaving the frequency of the output signal of the VCO circuit unaffected.
[0035] In detail, Figure 4 1 is an exemplary circuit block diagram of a charge pump phase-locked loop (CP-PLL) circuit 10' according to one or more embodiments. The PLL circuit 10' may include one or more of the functional blocks of a conventional PLL circuit, for example, circuit blocks 11, 12, 13, 14, and 15 as described with reference to FIG. Otherwise, it will be appreciated that one or more embodiments as disclosed herein may be applied to any type of PLL circuit (e.g., not necessarily a CP-PLL circuit), as long as the compensation architecture is configured to sense a (e.g., analog) control voltage Vtune and generate a (e.g., digital) compensation signal VCODAC received by the VCO circuit 14 based thereon.
[0036] like Figure 4As illustrated, the PLL circuit 10' includes a comparator circuit 56 configured to compare a control voltage Vtune with a comparison signal PLLDACout and generate a detection signal DetCPVLF based on this comparison. The comparator 56 is preferably an analog comparator (i.e., it compares the analog signals Vtune and PLLDACout and generates a digital signal DetCPVLF). For example, if Vtune ≥ PLLDACout, the detection signal DetCPVLF can be asserted (e.g., set to a high logic value "1"), and if Vtune < PLLDACout, the detection signal DetCPVLF can be de-asserted (e.g., set to a low logic value "0"), as indicated below:
[0037]
[0038] As Figure 4 As illustrated, the PLL circuit 10' includes a digital logic circuit 57 that receives the detection signal DetCPVLF and generates a (e.g., digital) compensation signal VCODAC (e.g., an M-bit digital signal, such as a 9-bit signal) received by the VCO circuit 14 based on this signal. As discussed in more detail below, the logic circuit 57 increases or decreases the value of the signal VCODAC, which in turn affects the operation of the VCO circuit 14 in order to pursue (e.g., track) the expected value of the control voltage Vtune. The logic circuit 57 also generates a (e.g., digital) comparison signal PLLDAC (e.g., an N-bit digital signal, such as a 9-bit signal), as discussed in more detail below.
[0039] As Figure 4 As illustrated, the PLL circuit 10' includes a digital-to-analog converter circuit 55 (DAC) that receives the digital comparison signal PLLDAC and converts it into the aforementioned corresponding analog comparison signal PLLDACout.
[0040] In one or more embodiments, Figure 4The architecture of can be slightly modified according to different embodiments. For example, there are at least two options for controlling the operation of the VCO circuit 14 via the compensation signal VCODAC: the signal VCODAC can drive the varactor of the VCO circuit 14, and / or the signal VCODAC can drive a capacitor bank (i.e., an array of small capacitors that allows fine frequency tuning). For example, the digital word VCODAC is converted by a digital-to-analog converter into a corresponding analog voltage, and this analog voltage drives the varactor of the VCO circuit 14. Another possible change involves the comparison of the analog control voltage Vtune: instead of using the DAC circuit 55 to convert the digital comparison signal PLLDAC into the analog comparison signal PLLDACout and performing the comparison of the analog signal at the comparator 56, an ADC circuit ( Figure 4 The analog control signal Vtune is converted into a digital control signal by a DAC circuit 55 (not visible in the figure), and then a comparison of the digital signal is performed at the comparator 56 (i.e., a digital copy of Vtune is directly compared with the digital comparison signal PLLDAC without implementing the DAC circuit 55). However, embodiments that use the DAC circuit 55 and rely on the comparison of analog signals can be more advantageous because the DAC circuit 55 has a smaller area, lower power consumption, and less noise than the ADC circuit.
[0041] In one or more embodiments, the FSM 50 implemented by the logic circuit 57 may include six states, such as Figure 5 As illustrated in the block diagram of , which shows FSM states (represented by ellipses) and their transitions. The first state 61 (also called the INIT state) can be used for initialization of FSM variables. The second state 62 (also called the IDLE state) can be used to wait between one check and another (for example, wait between two consecutive compensations of the signal Vtune); the waiting time can be programmable. The third state 63 (also called the SET_PLLDAC state) can be used to search for the value of the signal PLLDAC corresponding to the current value of the signal Vtune (for example, a binary search). The fourth state 64 (also called the UPDN_SEL state) can be used to route to the UP state (to increase Vtune, that is, to compensate for an unwanted decrease in Vtune) or to the DN state (to reduce Vtune, that is, to compensate for an unwanted increase in Vtune). The fifth state 65 (also called the UP state) can be used to increase the control signal Vtune, thereby reducing the compensation signal VCODAC. The sixth state 66 (also called the DN state) can be used to reduce the control signal Vtune, thereby increasing the compensation signal VCODAC.
[0042] Basically, the operation of FSM 50 includes a first "search" phase, up to UPDN_SEL state 64, during which the digital value of signal PLLDAC corresponding to the current value of control voltage Vtune is determined and then compared to the digital target value to define whether control voltage Vtune must be increased or decreased to meet the analog target value, and a second "compensation" phase, including UP and DN states 65 and 66, during which compensation signal VCODAC is iteratively changed to compensate for undesired changes in signal Vtune until the value of signal Vtune meets the target value. During the search phase, signal PLLDAC is assigned the value of iteratively updated variable PLLDAC_test and signal DetCPVLF serves as an indicator to perform a (e.g., binary) search, while during the compensation phase, signal PLLDAC is assigned the constant value of variable PLLDAC_target and signal DetCPVLF serves as an indicator to stop performing compensation.
[0043] We will now describe Figure 5 A block diagram of the detailed operation of FSM 50.
[0044] The FSM starts in the INIT state 61. In this state, the FSM variables are initialized, as illustrated by operation block 502. The initialized variables include one or more of the following:
[0045] one or more counters for implementing a corresponding timer, as described in detail below, in particular: a first counter CNT_idle initialized to a value wait_time_track (e.g., a programmable value); a second counter CNT_halving initialized to zero; a third counter CNT_compare initialized to zero;
[0046] The variable PLLDAC_target, whose value (in the execution Figure 5 ) is initialized from an internal register of FSM 50 and represents the digital (e.g., 9-bit) value of signal PLLDAC corresponding to the analog target value of control voltage Vtune (or desired Vtune) according to the following equation:
[0047]
[0048] Where N is the number of bits of the signal PLLDAC and V tune_MAX is the maximum value of the signal Vtune (e.g., approximately 1.1 V);
[0049] a variable PLLDAC_test, which will be iteratively updated during the search operation phase of FSM 50 and represents the value of signal PLLDAC corresponding to the current value of control voltage Vtune, and is initialized with the same value as PLLDAC_target;
[0050] The variables MIN (minimum), MAX (maximum), and CENTER are used for a binary search (specifically a binary search) that the FSM will perform to iteratively refine the value of the variable PLLDAC_test, where possible initialization values are MIN = 0, MAX = 2 N -1 (for example, if the signal PLLDAC is a 9-bit signal, MAX=511) and CENTER=(2 N -1) / 2 (for example, if the signal PLLDAC is a 9-bit signal, CENTER=255).
[0051] At step 504, the FSM 50 checks whether execution of the compensation algorithm is enabled by checking whether the enable signal EN is asserted (e.g., "1") or not asserted (e.g., "0"). In response to a negative result (N) of step 504, the FSM 50 remains in the INIT state 61. In response to a positive result (Y) of step 504, the FSM 50 transitions to the IDLE state 62.
[0052] In the IDLE state 62, as illustrated by operation block 506, the digital comparison signal PLLDAC is assigned the value of the variable PLLDAC_test, and the value of the variable CENTER (binary center) is set to the value of the variable PLLDAC_target. After the operation of block 506, the FSM can wait for a certain time interval, as illustrated by operation blocks 508 and 510, which basically implement a timer. In practice, step 508 includes checking whether the first counter CNT_idle (previously initialized to the value wait_time_track) is equal to zero. In response to a negative result (N) of step 508, the counter CNT_idle is decremented (e.g., decremented by one unit) at step 510. In response to an affirmative result (Y) of step 508, the FSM 50 transitions to the SET_PLLDAC state 63. Therefore, in essence, the operations of blocks 508 and 510 provide a timer that pauses the FSM for a number of clock cycles equal to wait_time_track between the initialization of the value of the signal PLLDAC and the start of the (e.g., binary) search.
[0053] In SET_PLLDAC state 63, as illustrated by operation blocks 512 to 528, the FSM 50 performs an iterative search (e.g., a binary search, specifically a dichotomous search) to determine the value of the variable PLLDAC_test, which when assigned to the digital comparison signal PLLDAC, causes the analog comparison signal PLLDACout to have a value corresponding to the current value of the control voltage Vtune (e.g., "equal" to Vtune but considering quantization errors). After entering SET_PLLDAC state 63, the FSM waits for a certain time interval, as illustrated by operation blocks 512 and 514, which essentially implement a timer. In fact, step 512 includes checking whether a second counter CNT_halving (previously initialized to zero) is equal to a certain threshold dly_PLLDAC_halves, e.g., equal to 2. In response to a negative result (N) of step 512, the counter CNT_halving is incremented (e.g., incremented by one unit) at step 514. In response to a positive result (Y) of step 512, the FSM 50 transitions to step 516. Thus, essentially, the operation of blocks 512 and 514 provides a timer that pauses the FSM for a number of clock cycles equal to dly_PLLDAC_halves between two consecutive bisection steps of the binary search algorithm.
[0054] At step 516, the FSM checks whether the detection signal DetCPVLF is equal to zero. A positive result (Y) of step 516 indicates that the current value of the variable PLLDAC_test assigned to the signal PLLDAC produces the signal PLLDACout such that Vtune < PLLDACout, so the search algorithm searches in the lower half of the array, as illustrated by steps 518, 520, and 522. A negative result (N) of step 516 indicates that the current value of the variable PLLDAC_test assigned to the signal PLLDAC produces the signal PLLDA Cout such that Vtune ≥ PLLDACout, so the binary search algorithm searches in the upper half of the array, as illustrated by steps 524, 526, and 528.
[0055] At step 518, the bisection variables are updated as follows: MAX i+1 = CENTER i , MIN i+1 = MIN i , and CENTER i+1 =(CENTER i + MIN i ) / 2, where the subscript indicates the iteration number of the search algorithm. The variable PLLDAC_test is assigned the center value CENTER i+1. At step 520, it is checked whether the current iteration counter i of the binary search algorithm is above a certain threshold, where the threshold is above N (N is the number of bits of the signal PLLDAC). For example, it is checked whether i is equal to N+3. An affirmative result (Y) of step 520 indicates that the binary search algorithm has ended, while a negative result (N) of step 520 indicates that the binary search algorithm may still be running. Therefore, in response to an affirmative result (Y) of step 520, the FSM 50 transitions to the UPDN_SEL state 64. In response to a negative result (N) of step 520, the iteration counter i is incremented (e.g., by one unit) at step 522, and the FSM 50 transitions to state 63 for a further iteration of the search algorithm, where the signal PLLDAC is now assigned the updated value of the variable PLLDAC_test.
[0056] Steps 524, 526, and 528 are the same as steps 518, 520, and 522, but just in case, the binary search algorithm must search in the upper half of the array. At step 524, the binary variables are updated as follows: MAX i+1 =MAX i , MIN i+1 =CENTER i , and CENTER i+1 =(CENTER i +MAX i ) / 2, where the subscript indicates the number of iterations of the search algorithm. The variable PLLDAC_test is assigned the center value CENTER i+1 . At step 526, it is checked whether the current iteration counter i of the search algorithm is above a certain threshold, where the threshold is above N. For example, it is checked whether i is equal to N+3. An affirmative result (Y) of step 526 indicates that the binary search algorithm has ended, while a negative result (N) of step 526 indicates that the binary search algorithm may still be running. Therefore, in response to an affirmative result (Y) of step 526, the FSM 50 transitions to the UPDN_SEL state 64. In response to a negative result (N) of step 526, the iteration counter i is incremented (e.g., by one unit) at step 528, and the FSM 50 transitions to the state 63 for a further iteration of the search algorithm, where the signal PLLDAC is now assigned the updated value of the variable PLLDAC_test.
[0057] It should be noted that the binary search algorithm finds the correct value of the variable PLLDAC_test after at most N iterations, so in one or more embodiments, steps 520 and 526 may compare the iteration counter i with a threshold different from N+3 (e.g., any threshold higher than N). However, a certain margin provides higher reliability. In other embodiments, the search algorithm may even stop before N iterations, for example, if the correct value of the variable PLLDAC_test is found in advance (e.g., by checking whether the center of the binary range remains unchanged in two consecutive iterations).
[0058] In the UPDN_SEL state 64, as illustrated by operation blocks 530 to 534, the FSM 50 compares the variable PLLDAC_test determined at the end of the binary search with the variable PLLDAC_target to determine whether the current value of the voltage Vtune is higher or lower than the desired value. At step 530, the FSM 50 checks whether the variable PLLDAC_test is lower than the variable PLLDAC_target. A positive result (Y) of the check 530 indicates that the current value of the control voltage Vtune is lower than the desired value, and the FSM 50 transitions to the UP state 65 to compensate for this undesirable decrease in the voltage Vtune. In response to a negative result (N) of the check 530, at step 532, the FSM 50 checks whether the variable PLLDAC_test is higher than the variable PLLDAC_target. A positive result (Y) of the check 532 indicates that the current value of the control voltage Vtune is higher than the desired value, and the FSM 50 transitions to the DN state 66 to compensate for this undesirable increase in the voltage Vtune. In response to a negative result (N) of check 532, at step 534, FSM 50 checks whether variable PLLDAC_test is equal to variable PLLDAC_target (an optional step since this is the only possibility after two negative results of steps 530 and 532). Once it is determined that PLLDAC_test is equal to PLLDAC_target, FSM 50 transitions to IDLE state 62 since compensation of control voltage Vtune does not need to be activated.
[0059] In one or more embodiments, the checks of steps 530, 532, and 534 may include tolerances. In particular, to prevent small voltage spikes from altering the operation of the FSM, a parameterized tolerance UPDN_TOLL may be inserted in the comparison. Thus, the variable PLLDAC_test may be compared to PLLDAC_target±UPDN_TOLL. The tolerance value may be set via an input signal, such as a 4-bit input signal. For an N-bit signal PLLDAC, the value of the tolerance UPDN_TOLL expressed in mV may be calculated according to the following formula:
[0060]
[0061] When the FSM transitions to the UP state 65, it has thus been determined that the voltage Vtune has decreased relative to the target value and needs to be increased. As illustrated by operation blocks 536 to 544, the variable PLLDAC_target is now assigned to the digital comparison signal PLLDAC such that the initial detection signal DetCPVLF is equal to zero (since Vtune < PLLDACout). The FSM algorithm gradually (e.g., linearly) decreases the value of the compensation signal VCODAC applied to the VCO 14 until the control voltage Vtune increases to the desired value, which is detected when the signal DetCPVLF switches (i.e., switches to 1 in this case). When the signal DetCPVLF switches, the compensation is complete and the FSM transitions back to the IDLE state 62. In particular, at step 536, the digital comparison signal PLLDAC is assigned the value of the variable PLLDAC_target. At step 538, it is checked whether the detection signal DetCPVLF is equal to zero (0). In response to the negative result (N) of check 538 indicating that the voltage Vtune is still lower than the signal PLLDACout, the compensation signal VCODAC is decreased (e.g., by one unit) at step 544, possibly after waiting for a certain number of clock cycles, as illustrated by the operations of blocks 540 and 542. In fact, after block 538, the FSM can wait for a certain time interval, as illustrated by the operation blocks 540 and 542 that essentially implement a timer. In fact, step 540 includes checking whether a third counter CNT_compare (previously initialized to zero) is equal to a certain threshold VCODAC_wait_time. In response to the negative result (N) of step 540, the counter CNT_compare is incremented (e.g., by one unit) at step 542. In response to the positive result (Y) of step 540, the FSM 50 transitions to step 544. Thus, essentially, the operations of blocks 540 and 542 provide a timer that pauses the FSM for the number of clock cycles equal to VCODAC_wait_time between two consecutive decreases of the compensation signal VCODAC. In response to the positive result (Y) of check 538, the FSM transitions back to the IDLE state 62 as long as the compensation is complete.
[0062] On the other hand, when the FSM transitions to the DN state 66, it has been determined that the voltage Vtune has increased relative to the target value and needs to be reduced. As illustrated in operation blocks 546 to 554, the digital comparison signal PLLDAC is now assigned the value of the variable PLLDAC_target so that the initial detection signal DetCPVLF is equal to one (because Vtune>PLLDACout). The FSM algorithm gradually (e.g., linearly) increases the value of the compensation signal VCODAC acting on the VCO 14 until the control voltage Vtune decreases to the desired value, which is detected when the signal DetCPVLF switches (i.e., switches to 0 in this case). When the signal DetCPVLF switches, the compensation is completed and the FSM transitions to the IDLE state 62 again. In particular, at step 546, the digital comparison signal PLLDAC is assigned the value of the variable PLLDAC_target. At step 548, it is checked whether the detection signal DetCPVLF is equal to zero (0). In response to a positive result (Y) of the check 548 indicating that the voltage Vtune is still higher than the signal PLLDACout, the compensation signal VCODAC is increased (e.g., by one unit) at step 554, possibly after waiting for a certain number of clock cycles, as illustrated by the operations of blocks 550 and 552. In practice, after block 548, the FSM may wait for a certain time interval, as illustrated by the operations of blocks 550 and 552 which essentially implement the same timer as blocks 540 and 542. In response to a negative result (N) of the check 548, the FSM again transitions to the IDLE state 62, as long as the compensation has been completed.
[0063] Note that waiting between two subsequent updates of the value of compensation signal VCODAC (eg, see blocks 540, 542 and 550, 552) allows the PLL loop to stabilize, since modifications of signal VCODAC affect the operation of the PLL closed loop.
[0064] Note also that while a binary search (particularly a binary search) has been described in the examples above, different embodiments may rely on different search algorithms, such as a linear or sequential search algorithm.
[0065] Also note that although a FSM with one down counter (i.e., CNT_idle) and two up counters (i.e., CNT_halving and CNT_compare) has been described in the above example, other types of counters (e.g., all counters are down counters or all counters are up counters) may be used in different embodiments without departing from the scope of the present invention.
[0066] Therefore, one or more embodiments as illustrated herein may provide one or more of the following advantages:
[0067] The ability to compensate for unwanted variations of the control voltage Vtune without the use of (external) sensors, arrays of capacitors and / or varactors, thereby reducing area and cost and eliminating the need for sensor calibration; and / or
[0068] The ability to compensate for unwanted variations of the control voltage Vtune independently of their root cause.
[0069] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what is described by way of example, without departing from the scope of protection.
[0070] The scope of protection is determined by the appended claims.
Claims
1. A phase-locked loop (PLL) circuit, comprising: A voltage controlled oscillator (VCO) circuit is configured to be driven by a control voltage and generate an output periodic signal; The comparator circuit is configured as: comparing the control voltage with a comparison signal; asserting a detection signal in response to the control voltage being higher than the comparison signal; and de-asserting the detection signal in response to the control voltage being lower than the comparison signal; Digital logic circuits, configured as: receiving the detection signal; generating the comparison signal; generating a compensation signal for controlling the operation of the VCO circuit; During a first stage of a VCO compensation process, determining and storing a value of the comparison signal corresponding to a current value of the control voltage, and comparing the stored value of the comparison signal to a target value to determine whether the control voltage should be increased or decreased; as well as During a second phase of the VCO compensation process, the value of the compensation signal is iteratively changed until the control voltage reaches a desired value.
2. The PLL circuit according to claim 1, wherein: The comparator circuit is an analog comparator circuit, and wherein the PLL circuit includes a digital-to-analog converter circuit, which is configured to receive the comparison signal from the digital logic circuit as a digital comparison signal and convert the digital comparison signal into a corresponding analog comparison signal which is fed to the analog comparator circuit.
3. The PLL circuit according to claim 2, wherein: During a first stage of the VCO compensation process, the digital logic circuit is configured to: assigning a value of a first variable to the digital comparison signal; iteratively updating the value of the first variable according to a binary search, wherein the direction of each iteration of the binary search is selected according to the value of the detection signal; and The last updated value of the first variable is stored for subsequent comparison with the target value.
4. The PLL circuit according to claim 3, wherein: The digital logic circuit is configured to wait for expiration of a first timer between two subsequent updates of the first variable.
5. The PLL circuit according to claim 2, wherein: During a second phase of the VCO compensation process, the digital logic circuit is configured to: assigning the target value to the digital comparison signal; as well as The value of the compensation signal is gradually changed until the detection signal switches.
6. The PLL circuit according to claim 5, wherein: The digital logic circuit is configured as: In response to determining that the control voltage should be increased, gradually decreasing the value of the compensation signal until the detection signal switches to a de-asserted state; and In response to determining that the control voltage should be decreased, the value of the compensation signal is gradually increased until the detection signal switches to an asserted state.
7. The PLL circuit according to claim 1, wherein: The digital logic circuit is configured to wait for expiration of a second timer between two subsequent changes in the value of the compensation signal.
8. The PLL circuit according to claim 1, wherein: The digital logic circuit is configured to wait for expiration of a third timer between two subsequent executions of the VCO compensation process.
9. The PLL circuit according to claim 1, wherein: The VCO circuit comprises: a varactor and / or capacitor bank controlled by the compensation signal; and Another digital-to-analog converter circuit is configured to convert the compensation signal into an analog compensation signal to control the varactor and / or the capacitor bank.
10. The PLL circuit according to claim 1, further comprising: a phase frequency detector circuit configured to compare a reference periodic signal with a feedback signal generated based on the output periodic signal and generate a phase error signal indicative of a phase error between the reference periodic signal and the feedback signal; a charge pump circuit configured to receive the phase error signal and generate a positive current pulse or a negative current pulse depending on the polarity of the phase error signal; a low-pass filter circuit configured to receive the current pulse from the charge pump circuit and generate the control voltage according to the current pulse; as well as The frequency divider circuit is configured to receive the output periodic signal and generate the feedback signal by dividing the frequency of the output periodic signal.
11. A method of operating a phase-locked loop (PLL) circuit, the method comprising: driving a voltage controlled oscillator (VCO) circuit with a control voltage; The VCO circuit generates an output periodic signal; The control voltage is compared with a comparison signal by a comparator circuit; deasserting, by the comparator circuit, a detection signal in response to the control voltage being lower than the comparison signal; Receiving the detection signal by a digital logic circuit; generating the comparison signal by the digital logic circuit; generating, by the digital logic circuit, a compensation signal for controlling the operation of the VCO circuit; During the first stage of the VCO compensation process: determining and storing, by the digital logic circuit, a value of the comparison signal corresponding to a current value of the control voltage; as well as comparing, by the digital logic circuit, the stored value of the comparison signal with a target value to determine that the control voltage should be increased; as well as During a second phase of the VCO compensation process, the value of the compensation signal is iteratively reduced by the digital logic circuit until the control voltage increases to a desired value.
12. The method according to claim 11, wherein: The comparator circuit is an analog comparator circuit, and the method further comprises: receiving, by a digital-to-analog converter circuit, the comparison signal from the digital logic circuit as a digital comparison signal; and The digital comparison signal is converted by the digital-to-analog converter circuit into a corresponding analog comparison signal which is fed to the analog comparator circuit.
13. The method according to claim 12, further comprising: During the first phase of the VCO compensation process: assigning, by the digital logic circuit, a value of a first variable to the digital comparison signal; iteratively updating, by the digital logic circuit, the value of the first variable according to a binary search, wherein the direction of each iteration of the binary search is selected according to the value of the detection signal; as well as The last updated value of the first variable is stored by the digital logic circuit for subsequent comparison with the target value.
14. The method of claim 12, further comprising, during a second phase of the VCO compensation process: assigning, by the digital logic circuit, the target value to the digital comparison signal; and The value of the compensation signal is gradually reduced by the digital logic circuit until the detection signal switches to a de-asserted state.
15. The method according to claim 11, further comprising: comparing, by a phase frequency detector circuit, a reference periodic signal with a feedback signal generated based on the output periodic signal; generating, by the phase frequency detector circuit, a phase error signal indicative of a phase error between the reference periodic signal and the feedback signal; Receiving the phase error signal by a charge pump circuit; generating, by the charge pump circuit, a positive current pulse or a negative current pulse depending on the polarity of the phase error signal; receiving, by a low pass filter circuit, current pulses from the charge pump circuit; generating the control voltage by the low-pass filter circuit according to the current pulse; Receiving the output periodic signal by a frequency divider circuit; as well as The feedback signal is generated by the frequency divider circuit by dividing the frequency of the output periodic signal.
16. A method of operating a phase-locked loop (PLL) circuit, the method comprising: driving a voltage controlled oscillator (VCO) circuit with a control voltage; The VCO circuit generates an output periodic signal; The control voltage is compared with a comparison signal by a comparator circuit; asserting, by the comparator circuit, a detection signal in response to the control voltage being higher than the comparison signal; Receiving the detection signal by a digital logic circuit; generating the comparison signal by the digital logic circuit; generating, by the digital logic circuit, a compensation signal for controlling the operation of the VCO circuit; During the first stage of the VCO compensation process: determining and storing, by the digital logic circuit, a value of the comparison signal corresponding to a current value of the control voltage; as well as comparing, by the digital logic circuit, the stored value of the comparison signal with a target value to determine that the control voltage should be decreased; as well as During a second phase of the VCO compensation process, the value of the compensation signal is iteratively increased by the digital logic circuit until the control voltage decreases to a desired value.
17. The method according to claim 16, wherein: The comparator circuit is an analog comparator circuit, and the method further comprises: receiving, by a digital-to-analog converter circuit, the comparison signal from the digital logic circuit as a digital comparison signal; and The digital comparison signal is converted by the digital-to-analog converter circuit into a corresponding analog comparison signal which is fed to the analog comparator circuit.
18. The method according to claim 17, further comprising: During the first phase of the VCO compensation process: assigning, by the digital logic circuit, a value of a first variable to the digital comparison signal; iteratively updating, by the digital logic circuit, the value of the first variable according to a binary search, wherein the direction of each iteration of the binary search is selected according to the value of the detection signal; and The last updated value of the first variable is stored by the digital logic circuit for subsequent comparison with the target value.
19. The method of claim 17, further comprising, during a second phase of the VCO compensation process: assigning, by the digital logic circuit, the target value to the digital comparison signal; and The value of the compensation signal is gradually increased by the digital logic circuit until the detection signal switches to an asserted state.
20. The method of claim 16, further comprising: comparing, by a phase frequency detector circuit, a reference periodic signal with a feedback signal generated based on the output periodic signal; generating, by the phase frequency detector circuit, a phase error signal indicative of a phase error between the reference periodic signal and the feedback signal; Receiving the phase error signal by a charge pump circuit; generating, by the charge pump circuit, a positive current pulse or a negative current pulse depending on the polarity of the phase error signal; receiving, by a low pass filter circuit, current pulses from the charge pump circuit; generating the control voltage by the low-pass filter circuit according to the current pulse; Receiving the output periodic signal by a frequency divider circuit; as well as The feedback signal is generated by the frequency divider circuit by dividing the frequency of the output periodic signal.