A cluster dynamic scheduling method, system and medium for FPGA channel simulation

Abstract

The present invention provides a cluster dynamic scheduling method, system and medium for FPGA channel simulation, which belongs to the field of information and communication technology. The method includes: obtaining a data stream to be scheduled in a cluster; using the real-time information age as the timeliness index of the data stream, and calculating the priority weight between the data stream and the scheduling node using the real-time load of the scheduling node to be assigned; prioritizing a pre-constructed directed acyclic graph to obtain a task priority; assigning the data stream to the scheduling node according to the task priority and the priority weight to obtain the data stream on the scheduling node; updating the load of the scheduling node and updating the information age; optimizing the data resources of the scheduling node according to the timeliness index of the data stream and the preset timeliness threshold to obtain the scheduled data stream.

Description

Technical Field

[0001] The present invention relates to the field of information communication technology, and in particular to a cluster dynamic scheduling method, system and medium for FPGA channel simulation. Background Art

[0002] In large-scale wireless channel simulation, with the rapid development of communication technology, especially in high-time-sensitive application fields such as 5G / 6G networks, intelligent transportation systems, unmanned driving, satellite communications, etc., the timeliness and accuracy of channel modeling are increasingly required. Channel simulation requires real-time processing of large amounts of data streams and accurate prediction and adjustment of signal propagation characteristics under different environmental conditions. Especially in complex environments, such as high-reliability and low-latency scenarios such as Internet of Vehicles, industrial automation, and telemedicine, any delay may affect the stability and performance of the system. Therefore, how to effectively regulate the computing tasks in large-scale wireless channel simulation to meet the requirements of real-time and accuracy is a key challenge facing current technology.

[0003] However, existing channel simulation technologies lack dynamic scheduling and load balancing methods for large-scale distributed computing environments. Especially in FPGA cluster environments, how to effectively allocate tasks among computing nodes based on real-time load and timeliness remains an urgent problem to be solved. Summary of the invention

[0004] The purpose of the present invention is to overcome the deficiencies in the prior art and to provide a cluster dynamic scheduling method, system and medium for FPGA channel simulation, which can solve the problems of unreasonable task scheduling, computing node timeliness and uneven load distribution in the existing wireless channel simulation technology.

[0005] To achieve the above object, the present invention is implemented by adopting the following technical solutions:

[0006] On the one hand, the present invention provides a cluster dynamic scheduling method for FPGA channel simulation, comprising:

[0007] Get the data stream to be scheduled in the cluster;

[0008] The real-time information age is used as the timeliness index of the data flow, and the priority weight between the data flow and the scheduling node is calculated using the real-time load of the scheduling node to be assigned;

[0009] Prioritize a directed acyclic graph constructed in advance based on each task in the channel simulation task cluster as a task node to obtain a task priority; allocate the data flow to a scheduling node according to the task priority and the priority weight to obtain a data flow on the scheduling node;

[0010] The data flow on the scheduling node executes the corresponding task, calculates the time consumed by the data flow on the scheduling node to execute the corresponding task, and updates the load of the scheduling node;

[0011] Update the information age according to the initial timestamp of the data stream on the scheduling node, the timestamp before executing the corresponding task, and the time consumed in executing the corresponding task;

[0012] According to the timeliness index of the data flow and a preset timeliness threshold, the data resources of the scheduling node are optimized to obtain the scheduled data flow.

[0013] Optionally, the construction of the directed acyclic graph includes:

[0014] Each task in the channel simulation task cluster is taken as a task node, and the dependency relationship between tasks is taken as directed edges to establish a directed acyclic graph.

[0015] Optionally, each task in the channel simulation task cluster is expressed as:

[0016] ;

[0017] The dependencies between the tasks are expressed as:

[0018] ;

[0019] in, Indicates tasks; Indicates signal acquisition; represents signal preprocessing; Represents multipath propagation modeling; Indicates channel gain calculation; Representation delay modeling; Indicates signal attenuation and interference processing; Indicates output calculation or signal recovery; Indicates result storage; Indicates that tasks are executed in the order of arrows.

[0020] Optionally, the pre-constructed directed acyclic graph is prioritized to obtain task priorities; and the data flow is allocated to a scheduling node according to the task priorities and the priority weights to obtain a data flow on the scheduling node, including:

[0021] The task nodes of the directed acyclic graph are divided into 7 task priorities to obtain task priorities; wherein the first-level tasks include , the second level tasks include , the third level tasks include , , the fourth level tasks include , the fifth level tasks include , the sixth level tasks include , the seventh level tasks include ;

[0022] Allocate the data stream to the scheduling node according to the task priority from small to large, and obtain the data stream on the scheduling node;

[0023] For tasks with the same priority, the data stream is allocated to the scheduling node according to the priority weight from large to small, so as to obtain the data stream on the scheduling node.

[0024] Optionally, the priority weight between the data flow and the scheduling node is calculated using the real-time load of the scheduling node to be allocated, and the calculation formula of the priority weight is:

[0025] ;

[0026] ;

[0027] in, represents the priority weight of the kth data flow executing the ith task at the jth scheduling node; It represents the information age of the kth data flow when it completes the i-1th task before the jth scheduling node executes the i-th task; represents the computing capacity of the jth scheduling node; represents the updated load of the jth scheduling node; represents the load of the jth scheduling node before updating.

[0028] Optionally, the time consumed by the data flow on the scheduling node to execute the corresponding task is calculated, including:

[0029] ;

[0030] ;

[0031] ;

[0032] ;

[0033] in, It represents the time consumed by the kth data flow to complete the ith task at the jth scheduling node; It indicates the waiting time of the kth data flow waiting for the execution of the ith task at the jth scheduling node; It represents the running time of the kth data flow executing the ith task at the jth scheduling node; Indicates the queuing time of the kth data flow waiting in the task queue at the jth scheduling node; represents the communication delay from the front scheduling node to the jth scheduling node required for the kth data flow to execute the ith task; represents the communication delay required for the kth data stream to execute the predecessor task s of the i-th task; Represents the computing power of the jth scheduling node.

[0034] Optionally, the information age is updated according to the initial timestamp of the data flow on the scheduling node, the timestamp before the execution of the corresponding task, and the time consumed for the execution of the corresponding task, including:

[0035] ;

[0036] ;

[0037] in, represents the information age of the kth data stream when it completes the i-th task at the j-th scheduling node; Indicates the initial timestamp when the kth data stream arrives at the jth scheduling node and the ith task is not executed; It represents the time taken by the kth data flow to complete the ith task at the jth scheduling node; Indicates the generation timestamp of the kth data stream; The timestamp indicating the time when the k-th data stream arrives at the predecessor task l required to execute the i-th task; It represents the time consumed by the predecessor task l required for the kth data stream to execute the i-th task; It represents the communication delay from the front scheduling node to the j-th scheduling node required for the k-th data flow to execute the i-th task.

[0038] Optionally, optimizing data resources of a scheduling node according to a timeliness index of the data flow and a preset timeliness threshold to obtain a scheduled data flow includes:

[0039] If the timeliness index of the data flow is greater than or equal to the preset timeliness threshold, the data flow on the scheduling node is removed from the corresponding scheduling node and the corresponding scheduling node resources are reset; otherwise, the data flows on all scheduling nodes execute the corresponding tasks and generate the scheduled data flow according to the dependency relationship between the tasks.

[0040] In a second aspect, the present invention provides a cluster dynamic scheduling system for FPGA channel simulation, comprising:

[0041] The data stream acquisition module is used to: acquire the data stream to be scheduled in the cluster;

[0042] A weight calculation module, used to: use the real-time information age as the timeliness index of the data flow, and use the real-time load of the scheduling node to be assigned to calculate the priority weight between the data flow and the scheduling node;

[0043] The scheduling node allocation module is used to: prioritize the pre-built directed acyclic graph to obtain task priorities; allocate the data flow to the scheduling node according to the task priorities and the priority weights to obtain the data flow on the scheduling node;

[0044] The load update module is used to: schedule the data flow on the node to execute the corresponding task, calculate the time consumed by the data flow on the node to execute the corresponding task, and update the load of the scheduling node;

[0045] The information age updating module is used to update the information age according to the initial timestamp of the data stream on the scheduling node, the timestamp before the execution of the corresponding task, and the time consumed in executing the corresponding task;

[0046] The data scheduling module is used to optimize the data resources of the scheduling node according to the timeliness index of the data flow and the preset timeliness threshold to obtain the scheduled data flow.

[0047] In a third aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implement the steps of the cluster dynamic scheduling method for FPGA channel simulation described in the first aspect.

[0048] Compared with the prior art, the present invention has the following beneficial effects:

[0049] 1. Improve the timeliness of channel simulation: By introducing the age of information (AoI) as a timeliness indicator, the present invention can monitor the timeliness of the simulation data stream in real time and dynamically adjust the task allocation, which can effectively reduce the simulation error caused by delay, especially in high-timeliness application scenarios such as 5G / 6G networks, unmanned driving, satellite communications, etc., to ensure that the results of channel modeling can meet strict real-time requirements.

[0050] 2. Optimize resource utilization: The present invention avoids overload or idleness of computing nodes by reasonably allocating tasks according to the real-time load of the scheduling nodes, thereby greatly improving the resource utilization of the FPGA cluster.

[0051] 3. Improve simulation accuracy and reliability: The present invention ensures the sequentiality and logical integrity of task execution by constructing a directed acyclic graph of task dependencies and refining task priorities. Even in complex scenarios (such as Internet of Vehicles or industrial automation), it can accurately predict channel characteristics and improve the accuracy and reliability of simulation results.

[0052] 4. Support large-scale distributed computing: The present invention provides a solution adapted to the distributed computing environment for large-scale channel simulation. The dynamic scheduling mechanism can adjust the task allocation of each node according to the real-time load, and clean up the low-timeliness data stream in combination with the information age, thereby supporting efficient large-scale simulation.

[0053] 5. Reduce dependence on hardware resources: While fully utilizing the computing power of the scheduling nodes, the present invention effectively reduces dependence on foreign high-end devices, reduces costs by optimizing hardware resource allocation, and provides technical support for domestic independent and controllable large-scale channel simulation.

[0054] 6. Expand the application field of efficient simulation technology: This invention provides technical support for high reliability and low latency scenarios (such as telemedicine, intelligent transportation, etc.), and also provides a new technical path for the automatic scheduling and optimization of large-scale simulation tasks in the future. Its dynamic scheduling and load balancing method has good scalability and can adapt to simulation needs in more complex environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 FIG. 1 is a flow chart of a cluster dynamic scheduling method for FPGA channel simulation in an embodiment of the present invention;

[0056] Figure 2 Shown is a schematic structural diagram of a directed acyclic graph of the present invention in an embodiment;

[0057] Figure 3 The figure is a schematic diagram of a flow chart of allocating data streams to scheduling nodes in one embodiment of the present invention;

[0058] In the figure: -Signal acquisition; -Signal preprocessing; -Multipath propagation modeling; - Channel gain calculation; -Time delay modeling; -Signal attenuation and interference processing; - Output calculation or signal recovery; -Result storage. DETAILED DESCRIPTION

[0059] The technical solution of the present invention is described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present invention, rather than limitations on the technical solution of the present invention. The embodiments of the present invention and the technical features in the embodiments may be combined with each other unless there is a conflict.

[0060] The term "and / or" is only a description of the association relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " generally indicates that the related objects are in an "or" relationship.

[0061] Example 1

[0062] like Figure 1 As shown, this embodiment introduces a cluster dynamic scheduling method for FPGA channel simulation, which dynamically adjusts the allocation of simulation tasks by real-time monitoring of the real-time information age of the scheduling data stream and the real-time load of each scheduling node to ensure the timeliness and computing efficiency of the simulation process.

[0063] The method specifically comprises the following steps:

[0064] Step 1: Task dependency analysis and DAG graph generation, specifically including: taking each task in the channel simulation task cluster as a task node, taking the dependency relationship between tasks as directed edges, and establishing a directed acyclic graph (DAG). Each task in the channel simulation task cluster is represented as:

[0065] ;

[0066] The dependencies between the tasks are expressed as:

[0067] ;

[0068] in, Indicates tasks; Indicates signal acquisition; represents signal preprocessing; Represents multipath propagation modeling; Indicates channel gain calculation; Representation delay modeling; Indicates signal attenuation and interference processing; Indicates output calculation or signal recovery; Indicates result storage; Indicates that tasks are executed in the order of arrows.

[0069] In a specific embodiment, the dependency relationship between the tasks is as follows: the original signal data of signal acquisition is used as the input of signal preprocessing; the output of signal preprocessing is used as the input of multipath propagation modeling and as the input of delay modeling; the output of multipath propagation modeling is used as the input of channel gain calculation; the output of channel gain calculation and the output of delay modeling are used together as the input of signal attenuation and interference processing; the output of signal attenuation and interference processing is used as the input of output calculation or signal recovery; the output of output calculation or signal recovery is used as the input of result storage; according to the above dependency relationship, the corresponding DAG diagram is generated as shown in Figure 2 As shown in FIG. 1 , the entire process of data stream channel simulation processing is divided into 8 tasks. According to whether the tasks can be processed in parallel, the wireless channel simulation task is represented as a wireless channel simulation directed acyclic graph.

[0070] Step 2: FPGA node capacity evaluation and initialization; specifically including: initializing all scheduling nodes to be assigned in the FPGA cluster, evaluating the computing capacity of each scheduling node, initializing the load of all scheduling nodes, and counting the communication delay of the scheduling nodes. The computing capacity of the jth scheduling node It is expressed as:

[0071] ;

[0072] in, , , The weight coefficient representing the computing power; represents the number of DSP units of the jth scheduling node; represents the storage capacity of the jth scheduling node; Represents the operating frequency of the jth scheduling node.

[0073] The load of the jth scheduling node The initial value of is set to 0; the communication delay of the jth scheduling node It is expressed as:

[0074] ;

[0075] in, Indicates the average amount of data that needs to be transmitted for each task (unit: bit); Indicates the transmission rate between scheduling nodes (unit: bit / second); represents the physical distance between the qth scheduling node and the jth scheduling node (unit: meter); represents the total number of all neighboring scheduling nodes topologically linked to the jth scheduling node; Indicates the signal propagation speed, which is the speed of light in this embodiment: 3×10 8 m / s.

[0076] Step 3: Define the timeliness of data flows and prioritize tasks, including: obtaining the data flows to be scheduled in the cluster; using the age of information (AoI) as the timeliness indicator of the data flows, and using the real-time load of the scheduling node to be assigned to calculate the priority weight between the data flows and the scheduling nodes, specifically:

[0077] The age of information (AoI) is defined as the timeliness index of the channel simulation data stream, which is used to measure the time from the generation of the data stream to the completion of the eight tasks. At the initial moment, the timestamp of the kth data stream generated before the T1 signal acquisition is performed is recorded as the generation timestamp of the kth data stream: ; During the task scheduling process, the AoI value corresponding to the data stream is updated after each task is completed; the real-time information age of the kth can be expressed as:

[0078] ;

[0079] in, Indicates the real time timestamp.

[0080] The calculation of the priority weight is expressed as:

[0081] ;

[0082] ;

[0083] in, represents the priority weight of the kth data flow executing the ith task at the jth scheduling node; It represents the information age of the kth data flow when it completes the i-1th task before the jth scheduling node executes the i-th task; represents the updated load of the jth scheduling node; represents the load of the jth scheduling node before updating.

[0084] Step 4: Data flow priority calculation and dynamic node allocation; specifically includes: prioritizing the pre-built directed acyclic graph to obtain task priority; allocating the data flow to the scheduling node according to the task priority and the priority weight to obtain the data flow on the scheduling node, specifically:

[0085] According to the dependencies between tasks, the task nodes of the directed acyclic graph are divided into 7 task priorities using the topological structure generated by the DAG graph to obtain the task priorities; among which, the first-level tasks include , the second level tasks include , the third level tasks include , , the fourth level tasks include , the fifth level tasks include , the sixth level tasks include , the seventh level tasks include ;

[0086] At the same time, different data flows are assigned to the scheduling nodes according to the task priority from small to large, so as to obtain the data flow on the scheduling node; this can maximize the cluster efficiency while ensuring that the task execution order meets the dependency relationship;

[0087] Under the same task priority, data streams are allocated to scheduling nodes according to the priority weight from large to small to obtain data streams on the scheduling nodes. In this way, the scheduling node resource scheduling can be optimized while considering the timeliness of data streams, the load of scheduling nodes, and the computing power of scheduling nodes, thereby improving the efficiency of data stream transmission.

[0088] Step 5: Task execution and information age update, specifically including: scheduling the data flow on the node to execute the corresponding task, calculating the time consumed by the data flow on the scheduling node to execute the corresponding task, and updating the load of the scheduling node, specifically:

[0089] After the scheduling node receives the data stream for processing, the state information of the scheduling node will change accordingly. After each task is executed, the load of the scheduling node will be updated. The load update formula of the jth scheduling node is:

[0090] ;

[0091] Among them, the load of the jth scheduling node The initial value of is set to 0. When calculating the priority weight of data streams with the same timestamp and the same task priority, the load update situation needs to be considered.

[0092] The time it takes for the kth data flow to complete the ith task at the jth scheduling node It is expressed as:

[0093] ;

[0094] in,

[0095] ;

[0096] ;

[0097] ;

[0098] in, It indicates the waiting time of the kth data flow waiting for the execution of the ith task at the jth scheduling node; It represents the running time of the kth data flow executing the ith task at the jth scheduling node; Indicates the queuing time of the kth data flow waiting in the task queue at the jth scheduling node; represents the communication delay from the front scheduling node to the jth scheduling node required for the kth data flow to execute the ith task; It represents the communication delay required for the k-th data stream to execute the predecessor task s of the i-th task. If the predecessor task 1 is assigned to node o for execution, then:

[0099] .

[0100] Step 6: Clear low-timeliness data streams and optimize resource allocation; specifically, update the information age according to the initial timestamp of the data stream on the scheduling node, the timestamp before executing the corresponding task, and the time consumed in executing the corresponding task, specifically:

[0101] After the data stream is processed by the scheduling node to complete the corresponding task, the information age of the data stream will also increase accordingly. The information age of the kth data stream when it completes the i-th task at the j-th scheduling node is It is expressed as:

[0102] ;

[0103] in,

[0104] ;

[0105] in, Indicates the initial timestamp when the kth data stream arrives at the jth scheduling node and the ith task is not executed; It represents the time taken by the kth data flow to complete the ith task at the jth scheduling node; The timestamp indicating the time when the k-th data stream arrives at the predecessor task l required to execute the i-th task; It represents the time consumed by the predecessor task l required for the k-th data stream to execute the i-th task.

[0106] Step 7: According to the timeliness index of the data flow and the preset timeliness threshold, the data resources of the scheduling node are optimized to obtain the scheduled data flow, specifically:

[0107] Real-time monitoring of the information age of each data stream at the current moment, that is, the timeliness index of the data stream, and comparing the timeliness index of the data stream with the preset threshold Make comparisons;

[0108] If the timeliness index of the data flow is greater than or equal to the preset timeliness threshold, the data flow on the scheduling node is immediately removed from the corresponding scheduling node, and the corresponding scheduling node resources are reset to avoid affecting the overall efficiency of the channel simulation system due to the old data flow occupying system resources; otherwise, the data flows on all scheduling nodes execute the corresponding tasks and generate the scheduled data flow according to the dependency relationship between the tasks. The scheduled data flow is the scheduled wireless channel simulation result.

[0109] Example 2

[0110] like Figure 3 As shown, this embodiment introduces a specific example of a cluster dynamic scheduling method for FPGA channel simulation, including:

[0111] like Figure 3 The figure shows the allocation of scheduling nodes when the data flow has completed the 7th task and is about to carry out the 8th task. There are 4 data flows and 4 scheduling nodes in total. The computing power and initial information of the four scheduling nodes are shown in Table 1:

[0112] Table 1 Schedule node initial information statistics

[0113] ;

[0114] in, represents the jth scheduling node. From Table 1, we can see the computing capabilities of the four scheduling nodes, the initial load of the scheduling nodes and the corresponding communication delays.

[0115] According to Example 1, the real-time information age of the data stream is calculated. The generation timestamps of the four data streams are 14:27:58, 14:28:12, 14:28:05 and 14:28:07 respectively. The current real-time timestamps are all 14:28:20. The real-time information ages of the four data streams are 22s, 8s, 15s and 13s respectively. The real-time information age reflects the timeliness of the data stream. Obviously, among the four data streams, the first data stream has the worst timeliness and the second data stream has the best timeliness.

[0116] Presets ; The four data streams complete the seventh task at the same time, and now need to be allocated to different scheduling nodes to complete the eighth task. According to Example 1, the priority weights and the corresponding real-time information of the scheduling nodes are calculated, and the corresponding scheduling node allocation can be obtained. The node real-time information is shown in Table 2, and the scheduling node allocation is shown in Table 3.

[0117] Table 2 Statistics of real-time information of scheduling nodes

[0118] ;

[0119] Table 3 Statistics of scheduling node allocation

[0120] ;

[0121] As can be seen from Table 2 and Table 3, this embodiment first considers whether the timeliness of the data stream exceeds the timeliness threshold. Since the timeliness of data stream 1 has exceeded the timeliness threshold, data stream 1 is first removed from the task queue and the resources of the corresponding adjustment node are released to avoid affecting the overall efficiency of the channel simulation system due to the old data stream occupying system resources;

[0122] Then, according to the timeliness of the data flow, the data flow with poor timeliness first selects the adjustment node according to the priority weight. The adjustment node with the highest weight is the adjustment node assigned to the current data flow, and the load of the adjustment node is changed accordingly;

[0123] Then, the remaining data streams with poor timeliness are selected to continue matching the corresponding adjustment nodes according to the above method. It can be seen that the first adjustment node with poor computing power and high load is not assigned any data stream; the corresponding third adjustment node has a lower computing power than the fourth adjustment node, but the load of the third adjustment node is smaller, so it is assigned to process data streams 2 and 3;

[0124] When this embodiment is applied, it can very effectively and dynamically complete the allocation of adjustment nodes according to the timeliness of data flow and the load of adjustment nodes, thereby greatly improving the overall resource utilization and system efficiency.

[0125] Example 3

[0126] This embodiment introduces a cluster dynamic scheduling system for FPGA channel simulation, including:

[0127] The data stream acquisition module is used to: acquire the data stream to be scheduled in the cluster;

[0128] A weight calculation module, used to: use the real-time information age as the timeliness index of the data flow, and use the real-time load of the scheduling node to be assigned to calculate the priority weight between the data flow and the scheduling node;

[0129] The scheduling node allocation module is used to: prioritize the pre-built directed acyclic graph to obtain task priorities; allocate the data flow to the scheduling node according to the task priorities and the priority weights to obtain the data flow on the scheduling node;

[0130] The load update module is used to: schedule the data flow on the node to execute the corresponding task, calculate the time consumed by the data flow on the node to execute the corresponding task, and update the load of the scheduling node;

[0131] The information age updating module is used to update the information age according to the initial timestamp of the data stream on the scheduling node, the timestamp before the execution of the corresponding task, and the time consumed in executing the corresponding task;

[0132] The data scheduling module is used to optimize the data resources of the scheduling node according to the timeliness index of the data flow and the preset timeliness threshold to obtain the scheduled data flow.

[0133] Example 4

[0134] This embodiment introduces a computer-readable storage medium on which computer instructions are stored, characterized in that when the computer instructions are executed by a processor, the steps of the cluster dynamic scheduling method for FPGA channel simulation described in Example 1 or 2 are implemented.

[0135] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0136] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0137] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0138] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0139] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which all fall within the protection of the present invention.

Claims

1. A cluster dynamic scheduling method for FPGA channel simulation, characterized in that: include: Get the data stream to be scheduled in the cluster; The real-time information age is used as the timeliness index of the data flow, and the priority weight between the data flow and the scheduling node is calculated using the real-time load of the scheduling node to be assigned; Prioritize a directed acyclic graph constructed in advance based on each task in the channel simulation task cluster as a task node to obtain a task priority; allocate the data flow to a scheduling node according to the task priority and the priority weight to obtain a data flow on the scheduling node; The data flow on the scheduling node executes the corresponding task, calculates the time consumed by the data flow on the scheduling node to execute the corresponding task, and updates the load of the scheduling node; Update the information age according to the initial timestamp of the data stream on the scheduling node, the timestamp before executing the corresponding task, and the time consumed in executing the corresponding task; According to the timeliness index of the data flow and the preset timeliness threshold, the data resources of the scheduling node are optimized to obtain the scheduled data flow; The construction of the directed acyclic graph includes: Each task in the channel simulation task cluster is taken as a task node, and the dependency relationship between tasks is taken as directed edges to establish a directed acyclic graph.

2. The cluster dynamic scheduling method for FPGA channel simulation according to claim 1 is characterized in that: Each task in the channel simulation task cluster is represented as: ； The dependencies between the tasks are expressed as: ； in, Indicates tasks; Indicates signal acquisition; represents signal preprocessing; Represents multipath propagation modeling; Indicates channel gain calculation; Representation delay modeling; Indicates signal attenuation and interference processing; Indicates output calculation or signal recovery; Indicates result storage; Indicates that tasks are executed in the order of arrows.

3. The cluster dynamic scheduling method for FPGA channel simulation according to claim 2 is characterized in that: Prioritize the pre-built directed acyclic graph to obtain the task priority; Allocating the data flow to the scheduling node according to the task priority and the priority weight to obtain the data flow on the scheduling node includes: The task nodes of the directed acyclic graph are divided into 7 task priorities to obtain task priorities; wherein the first-level tasks include , the second level tasks include , the third level tasks include , , the fourth level tasks include , the fifth level tasks include , the sixth level tasks include , the seventh level tasks include ; Allocate the data stream to the scheduling node according to the task priority from small to large, and obtain the data stream on the scheduling node; For tasks with the same priority, the data stream is allocated to the scheduling node according to the priority weight from large to small, so as to obtain the data stream on the scheduling node.

4. The cluster dynamic scheduling method for FPGA channel simulation according to claim 1 or 3, characterized in that: The priority weight between the data flow and the scheduling node is calculated using the real-time load of the scheduling node to be allocated. The calculation formula of the priority weight is: ； ； in, represents the priority weight of the kth data flow executing the ith task at the jth scheduling node; It represents the information age of the kth data flow when it completes the i-1th task before the jth scheduling node executes the i-th task; represents the computing capacity of the jth scheduling node; represents the updated load of the jth scheduling node; represents the load of the jth scheduling node before updating.

5. The cluster dynamic scheduling method for FPGA channel simulation according to claim 1, characterized in that: Calculate the time consumed by the data flow on the scheduling node to execute the corresponding task, including: ； ； ； ； in, It represents the time consumed by the kth data flow to complete the ith task at the jth scheduling node; It indicates the waiting time of the kth data flow waiting for the execution of the ith task at the jth scheduling node; It represents the running time of the kth data flow executing the ith task at the jth scheduling node; Indicates the queuing time of the kth data flow waiting in the task queue at the jth scheduling node; represents the communication delay from the front scheduling node to the jth scheduling node required for the kth data flow to execute the ith task; represents the communication delay required for the kth data stream to execute the predecessor task s of the i-th task; Represents the computing power of the jth scheduling node.

6. The cluster dynamic scheduling method for FPGA channel simulation according to claim 1, characterized in that: According to the initial timestamp of the data flow on the scheduling node, the timestamp before executing the corresponding task, and the time consumed in executing the corresponding task, the information age is updated, including: ； ； in, represents the information age of the kth data stream when it completes the i-th task at the j-th scheduling node; Indicates the initial timestamp when the kth data stream arrives at the jth scheduling node and the ith task is not executed; It represents the time taken by the kth data flow to complete the ith task at the jth scheduling node; Indicates the generation timestamp of the kth data stream; The timestamp indicating the time when the k-th data stream arrives at the predecessor task l required to execute the i-th task; It represents the time consumed by the predecessor task l required for the kth data stream to execute the i-th task; It represents the communication delay from the front scheduling node to the j-th scheduling node required for the k-th data flow to execute the i-th task.

7. The cluster dynamic scheduling method for FPGA channel simulation according to claim 1, characterized in that: According to the timeliness index and the preset timeliness threshold, the data resources of the scheduling node are optimized to obtain the scheduled data stream, including: If the timeliness index of the data flow is greater than or equal to the preset timeliness threshold, the data flow on the scheduling node is removed from the corresponding scheduling node and the corresponding scheduling node resources are reset; otherwise, the data flows on all scheduling nodes execute the corresponding tasks and generate the scheduled data flow according to the dependency relationship between the tasks.

8. A cluster dynamic scheduling system for FPGA channel simulation, characterized in that: include: The data stream acquisition module is used to: acquire the data stream to be scheduled in the cluster; A weight calculation module, used to: use the real-time information age as the timeliness index of the data flow, and use the real-time load of the scheduling node to be assigned to calculate the priority weight between the data flow and the scheduling node; The scheduling node allocation module is used to: prioritize the pre-built directed acyclic graph to obtain task priorities; allocate the data flow to the scheduling node according to the task priorities and the priority weights to obtain the data flow on the scheduling node; The load update module is used to: schedule the data flow on the node to execute the corresponding task, calculate the time consumed by the data flow on the node to execute the corresponding task, and update the load of the scheduling node; The information age updating module is used to update the information age according to the initial timestamp of the data flow on the scheduling node, the timestamp before the execution of the corresponding task, and the time consumed in executing the corresponding task; A data scheduling module, used to: optimize the data resources of the scheduling node according to the timeliness index of the data flow and the preset timeliness threshold, and obtain the scheduled data flow; The construction of the directed acyclic graph includes: Each task in the channel simulation task cluster is taken as a task node, and the dependency relationship between tasks is taken as directed edges to establish a directed acyclic graph.

9. A computer-readable storage medium having computer instructions stored thereon, characterized in that: When the computer instruction is executed by a processor, the steps of the cluster dynamic scheduling method for FPGA channel simulation described in any one of claims 1 to 7 are implemented.

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