Display panel and display device

Abstract

The application relates to a display panel and a display device, comprising: a plurality of pixel groups arranged along a first direction; wherein each pixel group comprises N sub-pixel columns; a plurality of data signal lines; wherein each sub-pixel column is connected with M data signal lines, at least part of the sub-pixels in the same sub-pixel column are connected with different data signal lines, N>=2, M>=2; a plurality of multiplexing circuits, each multiplexing circuit comprises M multiplexing units; each multiplexing unit comprises a signal input end, N signal output ends and N shunt control ends, each shunt control end is used for receiving a shunt control signal; the i-th data signal line corresponding to each sub-pixel column in the same pixel group is connected with each signal output end in the i-th multiplexing unit of the corresponding multiplexing circuit, 1<=i<=M, and the display panel has good display performance.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Display technology, as an important component of the information industry, has played a vital role in the development of information technology. With the advancement of display technology, display panels of various types, such as organic light-emitting diode (OLED) displays, have been widely adopted.

[0003] However, the display performance of the display panel in the related technology is insufficient. Summary of the Invention

[0004] Therefore, it is necessary to provide a display panel and a display device, which aim to improve the display performance of the display panel.

[0005] In a first aspect, this application provides a display panel, comprising:

[0006] Multiple pixel groups are arranged along a first direction; wherein each pixel group includes N sub-pixel columns.

[0007] Multiple data signal lines; wherein each sub-pixel column is connected to M data signal lines respectively, and at least some sub-pixels in the same sub-pixel column are connected to different data signal lines, N≥2, M≥2;

[0008] Multiple multiplexing circuits are provided, each multiplexing circuit comprising M multiplexing units; each multiplexing unit includes one signal input terminal, N signal output terminals, and N branch control terminals; within the same multiplexing unit, each branch control terminal is used to receive different branch control signals; wherein, the i-th data signal line corresponding to each sub-pixel column in the same pixel group is connected to each signal output terminal of the i-th multiplexing unit in the corresponding multiplexing circuit, and the display panel also includes multiple fan-out lines, with the signal input terminals of each multiplexing unit connected to different fan-out lines, 1≤i≤M.

[0009] In one embodiment, the display panel further includes:

[0010] Multiple scan signal lines, each scan signal line being connected to a sub-pixel row;

[0011] The display panel has multiple driving stages, each driving stage including: N charging stages and a scanning stage, and there is no overlap between the charging stages; wherein, in the j-th charging stage of the N charging stages, the split control signal received by the j-th split control terminal of the multiplexing unit is at an effective level, 1≤j≤N; in the scanning stage, the scanning signals received by the adjacent M rows of sub-pixels are all at an effective level.

[0012] In one embodiment, the pixel group includes at least one sub-pixel unit, and the sub-pixel unit includes three sub-pixel columns.

[0013] In one embodiment, each sub-pixel column includes a plurality of light-emitting elements, and the light-emitting elements in the same sub-pixel column emit the same color, while the light-emitting colors of each sub-pixel column in the sub-pixel unit are different from each other.

[0014] In one embodiment, the emission color of the sub-pixel columns corresponding to the last charging stage in each of the driving stages is the same.

[0015] In one embodiment, the multiplexing unit further includes N switching transistors, the first terminal of each switching transistor being the signal input terminal, the second terminal of each switching transistor being the signal output terminal, and the gate of each switching transistor being the branch control terminal.

[0016] In one embodiment, the pixel group includes a first sub-pixel column, a second sub-pixel column, and a third sub-pixel column; each of the multiplexing circuits includes a first multiplexing unit and a second multiplexing unit.

[0017] In one embodiment, the first multiplexing unit and the second multiplexing unit each include three switching transistors.

[0018] In one embodiment, the first sub-pixel column, the second sub-pixel column, and the third sub-pixel column are respectively connected to two data signal lines, and are respectively the first data signal line and the second data signal line; the sub-pixels in the A-th row of the sub-pixel column are connected to the first data signal line, and the sub-pixels in the A+1-th row are connected to the second data signal line, where A≥1.

[0019] The first data signal line corresponding to the first sub-pixel column, the first data signal line corresponding to the second sub-pixel column, and the first data signal line corresponding to the third sub-pixel column are respectively connected to the second terminals of the three switching transistors of the first multiplexing unit. The second data signal line corresponding to the first sub-pixel column, the second data signal line corresponding to the second sub-pixel column, and the second data signal line corresponding to the third sub-pixel column are respectively connected to the second terminals of the three switching transistors of the second multiplexing unit.

[0020] In one embodiment, each sub-pixel column includes a plurality of light-emitting elements, and the light-emitting elements in the same sub-pixel column emit the same color. The light-emitting elements in the first sub-pixel column, the second sub-pixel column, and the third sub-pixel column emit different colors.

[0021] In one embodiment, the scan signal received by the sub-pixel in row A of the sub-pixel column is synchronized with the scan signal received by the sub-pixel in row A+1.

[0022] In one embodiment, each driving stage includes: a first charging stage, a second charging stage, a third charging stage, and a scanning stage; wherein the first charging stage, the second charging stage, and the third charging stage do not overlap, and the overlap time between the third charging stage and the scanning stage is less than or equal to a preset time threshold.

[0023] In one embodiment, the display panel has multiple driving phases. In the first charging phase, the first multiplexing unit provides a data signal to a first data signal line of the first sub-pixel column, and the second multiplexing unit provides a data signal to a second data signal line of the first sub-pixel column. In the second charging phase, the first multiplexing unit provides a data signal to a first data signal line of the second sub-pixel column, and the second multiplexing unit provides a data signal to a second data signal line of the second sub-pixel column. In the third charging phase, the first multiplexing unit provides a data signal to a first data signal line of the third sub-pixel column, and the second multiplexing unit provides a data signal to a second data signal line of the third sub-pixel column.

[0024] In one embodiment, each pixel group includes a fourth sub-pixel column, a fifth sub-pixel column, a sixth sub-pixel column, a seventh sub-pixel column, an eighth sub-pixel column, and a ninth sub-pixel column; each multiplexing circuit includes a third multiplexing unit, a fourth multiplexing unit, and a fifth multiplexing unit.

[0025] In one embodiment, the third multiplexing unit, the fourth multiplexing unit, and the fifth multiplexing unit each include six switching transistors.

[0026] In one embodiment, each sub-pixel column includes a plurality of light-emitting elements, and the light-emitting elements in the same sub-pixel column have the same light-emitting color. The light-emitting elements in the fourth, fifth, and sixth sub-pixel columns have different light-emitting colors. The light-emitting elements in the fourth and seventh sub-pixel columns have the same light-emitting color. The light-emitting elements in the fifth and eighth sub-pixel columns have the same light-emitting color. The light-emitting elements in the sixth and ninth sub-pixel columns have the same light-emitting color.

[0027] In one embodiment, each of the sub-pixel columns is connected to three data signal lines, namely the third data signal line, the fourth data signal line, and the fifth data signal line. The sub-pixels in the A-th row of the sub-pixel column are connected to the third data signal line, the sub-pixels in the (A+1)-th row are connected to the fourth data signal line, the sub-pixels in the (A+2)-th row are connected to the fourth data signal line, and A≥1.

[0028] In one embodiment, the scan signals received by the sub-pixels in row A, row A+1, and row A+2 of the sub-pixel column are synchronized.

[0029] Secondly, this application provides a display device, including the display panel of the first aspect.

[0030] The display panel provided in this application embodiment includes multiple pixel groups arranged along a first direction, multiple data signal lines, multiple multiplexing circuits, and multiple fan-out lines. Each pixel group includes N sub-pixel columns, each multiplexing circuit includes M multiplexing units, and each multiplexing unit includes a signal input terminal, N signal output terminals, and N branch control terminals. In this application, each sub-pixel column is connected to M data signal lines. At least some sub-pixels in the same sub-pixel column are connected to different data signal lines. The i-th data signal line corresponding to each sub-pixel column in the same pixel group is connected to the signal output terminal of the i-th multiplexing unit in the corresponding multiplexing circuit. Each branch control terminal is used to receive different branch control signals. The signal input terminal of each multiplexing unit is connected to different fan-out lines so that the signal input terminal of each multiplexing unit receives different data signals. Then, under the action of the branch control signal received by the branch control terminal, the signal input terminal in the multiplexing circuit is controlled to provide the corresponding data signal to the corresponding signal output terminal to charge the corresponding data signal line. This realizes that the multiplexing circuit cooperates with multiple data signal lines to charge multiple sub-pixels in a sub-pixel column, improves the charging time of the sub-pixels, and thus improves the display effect of the display panel. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of this application;

[0032] Figure 2 A schematic diagram of another display panel structure provided in an embodiment of this application;

[0033] Figure 3 A schematic diagram of another display panel structure provided in an embodiment of this application;

[0034] Figure 4 A schematic diagram of the planar structure of another display panel provided in an embodiment of this application;

[0035] Figure 5 A driving timing diagram for a display panel provided in an embodiment of this application;

[0036] Figure 6 A schematic diagram of the planar structure of another display panel provided in an embodiment of this application;

[0037] Figure 7 A driving timing diagram for another display panel provided in an embodiment of this application;

[0038] Figure 8 This is a schematic diagram of the structure of the display device provided in the embodiments of this application. Detailed Implementation

[0039] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0041] When describing positional relationships, unless otherwise specified, when an element, such as a layer, film, or substrate, is referred to as being "on" another element, it may be directly on the other element or there may be intermediate elements present. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate elements present. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate elements present.

[0042] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0043] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0044] It should also be understood that, in interpreting an element, although not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of a particular value as determined by a person skilled in the art. For example, "approximately," "about," or "substantially" can mean within one or more standard deviations, without limitation herein.

[0045] Furthermore, in the instruction manual, the phrase "planar distribution diagram" refers to the diagram when the target part is viewed from above, and the phrase "cross-sectional diagram" refers to the diagram when the target part is viewed from the side as a cross-section taken by vertically cutting the target part.

[0046] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the components are shown in the drawings only as examples and not necessarily to actual scale.

[0047] As described in the background section, the refresh rate and resolution of a display panel are key indicators for measuring its quality. With increasing user demands, high refresh rates and high resolutions have become industry trends. However, as refresh rates and resolutions increase, the pixel charging time of the display panel decreases. This can lead to insufficient pixel charging, preventing individual pixels from being fully charged. This results in suboptimal display performance at low grayscale levels, impacting the display device's overall quality and potentially causing issues such as poor display uniformity.

[0048] To resolve the above technical issues, please refer to [link / reference]. Figure 1 This application proposes a display panel, characterized in that it includes: multiple pixel groups 10, multiple data signal lines 20, and multiple multiplexing circuits 30.

[0049] In this arrangement, multiple pixel groups 10 are arranged along a first direction, which is the X-axis direction shown in the figure. Each pixel group 10 includes N sub-pixel columns PL, and each sub-pixel column PL is connected to M data signal lines 20. At least some sub-pixels P in the same sub-pixel column PL are connected to different data signal lines 20, N≥2, M≥2.

[0050] The multiplexing circuit 30 includes M multiplexing units 301. Each multiplexing unit 301 includes one signal input terminal, N signal output terminals, and N branch control terminals. Each branch control terminal is used to receive a branch control signal Demux. The i-th data signal line corresponding to each sub-pixel column PL in the same pixel group 10 is connected to the signal output terminal of the i-th multiplexing unit in the corresponding multiplexing circuit. The display panel also includes multiple fan-out lines (not shown in the figure). The signal input terminal of each multiplexing unit 301 is connected to different fan-out lines so that the signal input terminal of each multiplexing unit 301 receives different data signals source, 1≤i≤M.

[0051] In this embodiment, please refer to Figure 1 The display panel provided in this application includes multiple pixel groups 10 arranged along a first direction. Each pixel group 10 includes multiple sub-pixel columns PL, and each sub-pixel column PL includes multiple sub-pixels P arranged along a second direction, which is the Y-axis direction shown in the figure. In one example, the emission colors of each sub-pixel P in a sub-pixel column PL are the same, while the emission colors of each sub-pixel P in adjacent sub-pixel columns PL are different.

[0052] Each multiplexing circuit 30 provides data signals to each sub-pixel P in a pixel group 10, meaning the number of multiplexing circuits 30 in the display panel of this application is the same as the number of pixel groups 10. Each multiplexing circuit 30 may include M multiplexing units 301, and the number of multiplexing units 301 in a multiplexing circuit 30 is the same as the number of data signal lines connected to a sub-pixel column. Each multiplexing unit 301 may have one signal input terminal, N signal output terminals, and N branch control terminals. Each branch control terminal is used to receive different branch control signals, and the branch control signals received by different multiplexing units 301 may be the same. Under the action of the branch control signal Demux received by each branch control terminal, the signal input terminal transmits the received data signal source to the corresponding signal output terminal, thereby charging the corresponding data signal line. For example, under the action of the kth branch control signal Demux, the signal input terminals of each multiplexing unit 301 in the same multiplexing circuit 30 can transmit each data signal to the corresponding signal output terminal of each multiplexing unit 301, thereby charging each data signal line corresponding to the kth sub-pixel column in the pixel group. This enables the multiplexing unit to cooperate with multiple data signal lines to charge multiple sub-pixels in a sub-pixel column, improving the charging time of the sub-pixels and thus improving the display effect of the display panel.

[0053] In the application, a pixel group includes at least one sub-pixel unit, and each sub-pixel unit includes three sub-pixel columns. Each sub-pixel column includes multiple light-emitting elements. The light-emitting elements within the same sub-pixel column emit the same color, while the light-emitting colors of the sub-pixel columns within a sub-pixel unit are different from each other. See the example provided. Figure 1A pixel group 10 may include a sub-pixel unit, and the sub-pixel unit includes three sub-pixel columns PL. The emission colors of these three sub-pixel columns PL may be different. For example, one sub-pixel column PL emits red light, another emits green light, and yet another emits blue light. Each sub-pixel column PL is connected to two data signal lines 20 (data signal line 20-1 and data signal line 20-2). The multiplexing circuit 30 includes two multiplexing units 301 (multiplexing unit 301-1 and multiplexing unit 301-2). Multiplexing units 301-1 and 301-2 each include one signal input terminal, three signal output terminals, and three branch control terminals. The signal input terminal of multiplexing unit 301-1 is used to receive data signal source-1, and the signal input terminal of multiplexing unit 301-2 is used to receive data signal source-2. Under the action of the demultiplexing control signal Demux-1 received at the first demultiplexing control terminal, the signal input terminal of the multiplexing unit 301-1 can transmit the data signal source-1 to the data signal line 20-1 corresponding to the first sub-pixel column in the corresponding pixel group 10, and the signal input terminal of the multiplexing unit 301-2 can transmit the data signal source-2 to the data signal line 20-2 corresponding to the first sub-pixel column in the corresponding pixel group 10; under the action of the demultiplexing control signal Demux-2 received at the second demultiplexing control terminal, the signal input terminal of the multiplexing unit 301-1 can transmit the data signal source-1 to the data signal line 20-2 corresponding to the second sub-pixel column in the corresponding pixel group 10. The data signal line 20-1 corresponding to the pixel column, and the signal input terminal of the multiplexing unit 301-2 can transmit the data signal source-2 to the data signal line 20-2 corresponding to the second sub-pixel column in the corresponding pixel group 10. Under the action of the decoupling control signal Demux-3 received by the third decoupling control terminal, the signal input terminal of the multiplexing unit 301-1 can transmit the data signal source-1 to the data signal line 20-1 corresponding to the third sub-pixel column in the corresponding pixel group 10, and the signal input terminal of the multiplexing unit 301-2 can transmit the data signal source-2 to the data signal line 20-2 corresponding to the third sub-pixel column in the corresponding pixel group 10. This allows the two data signal lines corresponding to each sub-pixel column to simultaneously charge each sub-pixel P in that sub-pixel column PL, improving the charging time of the sub-pixels and thus enhancing the display effect of the display panel.

[0054] The display panel provided in this application embodiment includes multiple pixel groups arranged along a first direction, multiple data signal lines, multiple multiplexing circuits, and multiple fan-out lines. Each pixel group includes N sub-pixel columns, each multiplexing circuit includes M multiplexing units, and each multiplexing unit includes a signal input terminal, N signal output terminals, and N branch control terminals. In this application, each sub-pixel column is connected to M data signal lines. At least some sub-pixels in the same sub-pixel column are connected to different data signal lines. The i-th data signal line corresponding to each sub-pixel column in the same pixel group is connected to the signal output terminal of the i-th multiplexing unit in the corresponding multiplexing circuit. Each branch control terminal is used to receive different branch control signals. The signal input terminal of each multiplexing unit is connected to different fan-out lines so that the signal input terminal of each multiplexing unit receives different data signals. Then, under the action of the branch control signal received by the branch control terminal, the signal input terminal in the multiplexing circuit is controlled to provide the corresponding data signal to the corresponding signal output terminal to charge the corresponding data signal line. This enables the multiplexing unit to cooperate with multiple data signal lines to charge multiple sub-pixels in a sub-pixel column, improve the charging time of the sub-pixels, and thus improve the display effect of the display panel.

[0055] In one exemplary embodiment, please refer to Figure 2 The display panel also includes multiple scan signal lines 40, each scan signal line 40 being connected to a sub-pixel row.

[0056] The display panel includes multiple driving stages, each driving stage including N charging stages and a scanning stage, with no overlap between the charging stages. The overlap time between the scanning stage and the Nth charging stage is less than or equal to a preset time threshold. In the jth charging stage of the N charging stages, the split control signal received by the jth split control terminal of the multiplexing unit is at an effective level, 1≤j≤N. In the scanning stage, the scanning signals received by the adjacent M rows of sub-pixels are all at an effective level.

[0057] In the application, the scan signal line 40 provides the scan control signal Scan to the corresponding sub-pixel row to control the data writing process of the sub-pixels in the corresponding sub-pixel row. Before data writing, each multiplexing unit 301 needs to charge its corresponding data signal line. Specifically, in the first charging stage, the first branch control terminal in the multiplexing circuit receives a branch control signal at an active level, and each multiplexing unit 301 charges the data signal lines corresponding to the first sub-pixel column in the pixel group; in the second charging stage, the second branch control terminal in the multiplexing circuit receives a branch control signal at an active level, and each multiplexing unit 301 charges the data signal lines corresponding to the second sub-pixel column in the pixel group; and so on; in the Nth charging stage, the Nth branch control terminal in the multiplexing circuit receives a branch control signal at an active level, and each multiplexing unit 301 charges the data signal lines corresponding to the Nth sub-pixel column in the pixel group. Finally, during the scanning stage, each data signal line charges the corresponding sub-pixel with its data signal.

[0058] In this application, the pixel arrangement of the display panel can be a real RGB arrangement. A real RGB arrangement means that a square pixel is divided into three sub-pixels, each assigned a red (R), green (G), and blue (B) color. These three colors are independent and cannot be produced by mixing other colors. Furthermore, almost all other colors in nature can be obtained by combining these three primary colors in different proportions, thus ensuring that each pixel accurately displays the three primary colors, enabling the display panel to achieve full-color display. The pixel group in this application can include at least one sub-pixel unit. A sub-pixel unit refers to a combination of an R sub-pixel column, a G sub-pixel column, and a B sub-pixel column.

[0059] It can be understood that when the charging and scanning phases do not overlap, the data signal first charges the corresponding data signal line. When the scanning phase begins, the data signal line then charges the corresponding sub-pixel – this is pre-charging. When the charging and scanning phases overlap, the data signal directly charges the corresponding sub-pixel – this is direct charging. Given the same data signal magnitude, the gate potential of the driving transistor in a sub-pixel using direct charging is higher than the gate potential of the driving transistor in a sub-pixel using pre-charging.

[0060] Because this application uses a real RGB pixel arrangement, the color of the last sub-pixel column of each pixel group is the same, that is, the emission color of the sub-pixel column corresponding to the last charging stage in each driving stage is the same. Since there is no time overlap between the charging stages in the driving stage of this application, the overlap time between the Nth charging stage and the scanning stage is less than or equal to a preset time threshold, which can ensure that the size of the data signal written by different sub-pixel columns is different, and at least the sub-pixel columns corresponding to the first N-1 charging stages all adopt the pre-charging method. When the Nth charging stage does not overlap with the scanning stage, the last sub-pixel column of each pixel group corresponding to the Nth charging stage adopts the pre-charging method. When the Nth charging stage overlaps with the scanning stage, it can ensure that the charging method of the sub-pixel columns of the same color is the same, so as to ensure the display uniformity of the display panel.

[0061] Furthermore, in this application, adjacent M rows of sub-pixels in each pixel column are connected to different data signal lines to ensure that adjacent M rows of sub-pixels receive different data signals. This allows control over the reception of synchronous scan signals by these adjacent M rows of sub-pixels, achieving simultaneous control of these adjacent M rows of sub-pixels. The duration of the driving phase in this application is M times 1H, where 1H is the ratio of one frame time of the display panel to the number of rows of all sub-pixel lines in the display panel. In other words, 1H is the interval between the scan signal of the pixel circuit in the current sub-pixel row and the scan signal of the pixel circuit in the next sub-pixel row. By achieving simultaneous control of multiple rows of sub-pixels, the duration of the driving phase can be increased, thereby increasing the duration of each charging phase, improving the charging time of each sub-pixel, and ultimately improving the display effect of the display panel.

[0062] In one exemplary embodiment, please refer to Figure 3 The multiplexing unit 301 also includes N switching transistors T, the first terminal of each switching transistor T is the corresponding signal input terminal, the second terminal of each switching transistor T is the corresponding signal output terminal, and the gate of each switching transistor is the corresponding branch control terminal.

[0063] In this embodiment, in a multiplexing circuit 30, the first terminal of the q-th switching transistor T in each multiplexing unit 301 is connected to the corresponding fan-out line to receive data signals; the second terminal of the q-th switching transistor T in each multiplexing unit 301 is connected to each data signal line of the q-th sub-pixel column in the pixel group; and the gate of the q-th switching transistor T in each multiplexing unit 301 is connected to the same branch control terminal. Then, under the action of the branch control signal Demux received at the branch control terminal, the q-th switching transistor T in each multiplexing unit 301 is simultaneously turned on to charge each data signal line of the q-th sub-pixel column in the pixel group through each signal input terminal and the corresponding signal output terminal. The switching transistor T can be a P-type transistor or an N-type transistor.

[0064] In one exemplary embodiment, please refer to Figure 4 The pixel group 10 includes a first sub-pixel column PL1, a second sub-pixel column PL2, and a third sub-pixel column PL3. Each sub-pixel column PL includes multiple light-emitting elements. The light-emitting elements in each sub-pixel column PL have the same light-emitting color. The light-emitting elements in the first sub-pixel column PL1, the second sub-pixel column PL2, and the third sub-pixel column PL3 have different light-emitting colors. For example, the light-emitting elements in the first sub-pixel column PL1 emit red light, the light-emitting elements in the second sub-pixel column PL2 emit green light, and the light-emitting elements in the third sub-pixel column PL3 emit blue light.

[0065] Each sub-pixel column PL is connected to two data signal lines 20: a first data signal line 21 and a second data signal line 22. Specifically, the first sub-pixel column PL1 is connected to the first data signal line 21a and the second data signal line 22a, the second sub-pixel column PL2 is connected to the first data signal line 21b and the second data signal line 22b, and the third sub-pixel column PL3 is connected to the first data signal line 21c and the second data signal line 22c. Furthermore, adjacent rows of sub-pixels within a sub-pixel column are connected to different data signal lines 20. For example, please refer to [link to relevant documentation]. Figure 4 , Figure 4 The black circular pattern in each sub-pixel represents the connection relationship between the sub-pixel and the data signal line. It can be seen that in each sub-pixel column, the first row of sub-pixels is connected to the first data signal line 21, the second row of sub-pixels is connected to the second data signal line 22, the third row of sub-pixels is connected to the first data signal line 21, the fourth row of sub-pixels is connected to the second data signal line 22, and so on.

[0066] The multiplexing circuit 30 includes a first multiplexing unit 31 and a second multiplexing unit 32. Each of the first and second multiplexing units 31 includes three switching transistors; the gates of each switching transistor are three branch control terminals, the first terminals of the three switching transistors are signal input terminals, and the second terminals of the three switching transistors are three signal output terminals. The first data signal line 21a corresponding to the first sub-pixel column PL1, the first data signal line 21b corresponding to the second sub-pixel column PL2, and the first data signal line 21c corresponding to the third sub-pixel column PL3 are respectively connected to the second terminals of the three switching transistors in the first multiplexing unit 31; the second data signal lines 22a, 22b, and 22c corresponding to the first sub-pixel column PL1, the second data signal lines 22c corresponding to the second sub-pixel column PL2, and the third sub-pixel column PL3 are respectively connected to the second terminals of the three switching transistors in the second multiplexing unit 32.

[0067] Specifically, the first multiplexing unit 31 includes three switching transistors (switching transistor T1, switching transistor T2, and switching transistor T3). The first terminals of switching transistors T1, T2, and T3 are connected to the same fan-out line to receive the data signal source1. The second terminal of switching transistor T1 is connected to the first data signal line 21a, the second terminal of switching transistor T2 is connected to the first data signal line 21b, and the second terminal of switching transistor T3 is connected to the first data signal line 21c. The gate of switching transistor T1 is used to receive the split control signal Demux1, the gate of switching transistor T2 is used to receive the split control signal Demux2, and the gate of switching transistor T3 is used to receive the split control signal Demux3. The second multiplexing unit 32 includes three switching transistors (switching transistor T4, switching transistor T5, and switching transistor T6). The first terminals of switching transistors T4, T5, and T6 are connected to another outgoing line to receive the data signal source2. The second terminal of switching transistor T4 is connected to the second data signal line 22a, the second terminal of switching transistor T5 is connected to the second data signal line 22b, and the second terminal of switching transistor T6 is connected to the second data signal line 22c. The gate of switching transistor T4 is used to receive the split control signal Demux1, the gate of switching transistor T5 is used to receive the split control signal Demux2, and the gate of switching transistor T6 is used to receive the split control signal Demux3.

[0068] In the application, the scan signal received by the sub-pixel in row A of the sub-pixel column is synchronized with the scan signal received by the sub-pixel in row A+1. For an example, please refer to [link to documentation]. Figure 4 The scan signal line 40 includes multiple scan signal lines such as scan signal line 41, scan signal line 42, scan signal line 43, and scan signal line 44. Scan signal line 41 provides scan signal scan1 for the first row of sub-pixels, scan signal line 42 provides scan signal scan2 for the second row of sub-pixels, scan signal line 43 provides scan signal scan3 for the third row of sub-pixels, scan signal line 44 provides scan signal scan4 for the fourth row of sub-pixels, and so on. Scan signal scan1 is synchronized with scan signal scan2, scan signal scan3 is synchronized with scan signal scan4, and so on.

[0069] In this embodiment, please refer to Figure 5The display panel of this application has multiple driving stages, including a first charging stage t1, a second charging stage t2, a third charging stage t3, and a scanning stage t4; wherein the first charging stage t1, the second charging stage t2, and the third charging stage t3 do not overlap, and the overlap time between the third charging stage t3 and the scanning stage t4 is less than a preset time threshold. In the first charging stage, a first multiplexing unit is used to provide a data signal to the first data signal line of the first sub-pixel column, and a second multiplexing unit is used to provide a data signal to the second data signal line of the first sub-pixel column; in the second charging stage, the first multiplexing unit is used to provide a data signal to the first data signal line of the second sub-pixel column, and the second multiplexing unit is used to provide a data signal to the second data signal line of the second sub-pixel column; in the third charging stage, the first multiplexing unit is used to provide a data signal to the first data signal line of the third sub-pixel column, and the second multiplexing unit is used to provide a data signal to the second data signal line of the third sub-pixel column.

[0070] Please refer to the following: Figure 4 and Figure 5In this example, the duration of the driving phase is 2H. To increase the charging time of sub-pixels, adjacent rows of sub-pixels are set to charge simultaneously and receive different data signals. For example, in the first charging phase t1, the gates of switching transistors T1 and T4 simultaneously receive a low-level shunt control signal Demux1. Under the action of the shunt control signal Demux1, switching transistors T1 and T4 are turned on, thereby charging the first data signal line 21a with data signal source1 and charging the second data signal line 22a with data signal source2. After the first charging phase t1 ends, the second charging phase t2 begins, where the gates of switching transistors T2 and T5 simultaneously receive a low-level shunt control signal Demux2. Under the action of the shunt control signal Demux2... In the second charging stage t2, switching transistors T2 and T5 are turned on, thereby charging the first data signal line 21b with data signal source1 and charging the second data signal line 22b with data signal source2. After the second charging stage t2 ends, the third charging stage t3 begins. The gates of switching transistors T3 and T6 simultaneously receive a low-level branch control signal Demux3. Under the action of Demux3, switching transistors T3 and T6 are turned on, thereby charging the first data signal line 21c with data signal source1 and charging the second data signal line 22c with data signal source2. The third charging stage t3 may overlap with the scanning stage t4. In the scanning stage t4, the first data signal line 21a and the second data signal line 22a charge the corresponding sub-pixels in the first sub-pixel column, the first data signal line 21b and the second data signal line 22b charge the corresponding sub-pixels in the second sub-pixel column, and the first data signal line 21c, the second data signal line 22c, and the two signal input terminals together charge the corresponding sub-pixels in the third sub-pixel column. Since the third sub-pixel column in each pixel group emits the same light color, which is blue, this application can ensure that sub-pixel columns of the same color have the same charging method, thereby ensuring the uniformity of the display panel.

[0071] Meanwhile, since the first and second data signal lines of adjacent rows of sub-pixels in the sub-pixel column are charged synchronously and receive different data signals, this application can synchronously control the circuits of adjacent rows of pixels. For example, for the first and second rows of sub-pixels in the first sub-pixel column, during the first charging stage, the first data signal line 21a corresponding to the first row of sub-pixels in the first sub-pixel column receives data signal source1, and the second data signal line 22a corresponding to the second row of sub-pixels in the first sub-pixel column receives data signal source2. Therefore, during the scanning stage, the scanning signals scan1 and scan2 can be controlled to be low-level valid signals so that data signals source1 and source2 are simultaneously written into the first and second rows of sub-pixels in the first sub-pixel column, respectively. The charging time of the sub-pixels is increased by controlling multiple rows of sub-pixels simultaneously.

[0072] It is understandable that at any given moment, the magnitude of the data signal received at the signal input terminal of the first multiplexing unit may differ from the magnitude of the data signal received at the signal input terminal of the second multiplexing unit. Furthermore, at different charging stages, the magnitude of the data signal received at the signal input terminal of both the first and second multiplexing units may also differ.

[0073] In one exemplary embodiment, please refer to Figure 6 Each pixel group 30 includes a fourth sub-pixel column PL4, a fifth sub-pixel column PL5, a sixth sub-pixel column PL6, a seventh sub-pixel column PL7, an eighth sub-pixel column PL8, and a ninth sub-pixel column PL9. The light-emitting elements in each sub-pixel column PL have the same emission color. The light-emitting elements in the fourth, fifth, and sixth sub-pixel columns PL4, PL5, and PL6 have different emission colors. The light-emitting elements in the fourth and seventh sub-pixel columns PL4 and PL7 have the same emission color, the light-emitting elements in the fifth and eighth sub-pixel columns PL5 and PL8 have the same emission color, and the light-emitting elements in the sixth and ninth sub-pixel columns PL6 and PL9 have the same emission color. For example, the light-emitting elements in the fourth and seventh sub-pixel columns PL4 and PL7 emit red, the light-emitting elements in the fifth and eighth sub-pixel columns PL5 and PL8 emit green, and the light-emitting elements in the sixth and ninth sub-pixel columns PL6 emit blue.

[0074] Each sub-pixel column PL is connected to three data signal lines 20: the third data signal line 23, the fourth data signal line 24, and the fifth data signal line 25. Specifically, the fourth sub-pixel column PL4 is connected to the third data signal line 23a, the fourth data signal line 24a, and the fifth data signal line 25a; the fifth sub-pixel column PL5 is connected to the third data signal line 23b, the fourth data signal line 24b, and the fifth data signal line 25b; the sixth sub-pixel column PL6 is connected to the third data signal line 23c, the fourth data signal line 24c, and the fifth data signal line 25c; the seventh sub-pixel column PL7 is connected to the third data signal line 23d, the fourth data signal line 24d, and the fifth data signal line 25d; the eighth sub-pixel column PL8 is connected to the third data signal line 23e, the fourth data signal line 24e, and the fifth data signal line 25e; and the ninth sub-pixel column PL9 is connected to the third data signal line 23f, the fourth data signal line 24f, and the fifth data signal line 25f. In this sub-pixel column, the data signal lines 20 connecting three adjacent rows of sub-pixels are different. For example, please refer to... Figure 6 , Figure 6 The black circular patterns in each sub-pixel represent the connection relationship between that sub-pixel and the data signal line. It can be seen that in each sub-pixel column, the first row of sub-pixels is connected to the third data signal line 23, the second row of sub-pixels is connected to the fourth data signal line 24, the third row of sub-pixels is connected to the fifth data signal line 25, the fourth row of sub-pixels is connected to the third data signal line 23, the fifth row of sub-pixels is connected to the fourth data signal line 24, and the sixth row of sub-pixels is connected to the fifth data signal line 25.

[0075] The multiplexing circuit 30 includes a third multiplexing unit 33, a fourth multiplexing unit 34, and a fifth multiplexing unit 35. Each of the three multiplexing units includes six switching transistors; the gates of the six switching transistors are six branch control terminals, the first terminals of the six switching transistors are signal input terminals, and the second terminals of the six switching transistors are six signal output terminals.

[0076] In this embodiment, the third multiplexing unit 33 is the first multiplexing unit in the multiplexing circuit 30, the fourth multiplexing unit 34 is the second multiplexing unit in the multiplexing circuit 30, and the fifth multiplexing unit 35 is the third multiplexing unit in the multiplexing circuit 30. The third data signal line 23 is the first data signal line corresponding to the sub-pixel column, the fourth data signal line 24 is the second data signal line corresponding to the sub-pixel column, and the fifth data signal line 25 is the third data signal line corresponding to the sub-pixel column.

[0077] The third data signal lines 23a, 23b, 23c, 23d, 23e, 23f corresponding to the fourth sub-pixel column PL4, 23c, 23d, 23e, and 23f corresponding to the fifth sub-pixel column PL5, 23c, 23d, 23e, and 23f of the sixth sub-pixel column PL6, 23e, 23f, 23c, 23d, 23e, 23e, and 23f of the ninth sub-pixel column PL9 are respectively connected to the second terminals of the six switching transistors of the third multiplexing unit 33; the third data signal lines 23a, 23b, 23c, 23e, 23d, 23e, 23f of the fifth sub-pixel column PL5, 23e, 23f of the sixth sub-pixel column PL6, 23e, 23f of the seventh sub-pixel column PL7 are respectively connected to the second terminals of the six switching transistors of the third multiplexing unit 33; the third data signal lines 23a, 23b, 23c, 23e, 23e, 23f of the eighth sub-pixel column PL8, and 23f of the ninth sub-pixel column PL9 are respectively connected to the second terminals of the six switching transistors of the third multiplexing unit 33. The fourth data signal line 24d, the fourth data signal line 24e connected to the eighth sub-pixel column PL8, and the fourth data signal line 24f connected to the ninth sub-pixel column PL9 are respectively connected to the second pole of the six switching transistors of the fourth multiplexing unit 34; the fifth data signal line 25a connected to the fourth sub-pixel column PL4, the fifth data signal line 25b connected to the fifth sub-pixel column PL5, the fifth data signal line 25c connected to the sixth sub-pixel column PL6, the fifth data signal line 25d connected to the seventh sub-pixel column PL7, the fifth data signal line 25e connected to the eighth sub-pixel column PL8, and the fifth data signal line 25f connected to the ninth sub-pixel column PL9 are respectively connected to the second pole of the six switching transistors of the fifth multiplexing unit 35.

[0078] Specifically, the third multiplexing unit 33 includes six switching transistors (switching transistor T7, switching transistor T8, switching transistor T9, switching transistor T10, switching transistor T11, and switching transistor T12). The first terminals of switching transistors T7, T8, T9, T10, T11, and T12 are connected to the same fan-out line to receive the data signal source3. The second terminal of switching transistor T7 is connected to the third data signal line 23a, the second terminal of switching transistor T8 is connected to the third data signal line 23b, and the second terminal of switching transistor T9 is connected to the third data signal line 23c. The second terminal of transistor T10 is connected to the third data signal line 23d; the second terminal of switching transistor T11 is connected to the third data signal line 23e; the second terminal of switching transistor T12 is connected to the third data signal line 23f; the gate of switching transistor T7 is used to receive the shunt control signal Demux4; the gate of switching transistor T8 is used to receive the shunt control signal Demux5; the gate of switching transistor T9 is used to receive the shunt control signal Demux6; the gate of switching transistor T10 is used to receive the shunt control signal Demux7; the gate of switching transistor T11 is used to receive the shunt control signal Demux8; and the gate of switching transistor T12 is used to receive the shunt control signal Demux9.

[0079] The fourth multiplexing unit 34 includes six switching transistors (switching transistor T13, switching transistor T14, switching transistor T15, switching transistor T16, switching transistor T17, and switching transistor T18). The first terminals of switching transistors T13, T14, T15, T16, T17, and T18 are connected to another output line to receive the data signal source4. The second terminal of switching transistor T13 is connected to the fourth data signal line 24a, the second terminal of switching transistor T14 is connected to the fourth data signal line 24b, and the second terminal of switching transistor T15 is connected to the fourth data signal line 24c. The second terminal of transistor T16 is connected to the fourth data signal line 24d, the second terminal of switching transistor T17 is connected to the fourth data signal line 24e, the second terminal of switching transistor T18 is connected to the fourth data signal line 24f, the gate of switching transistor T13 is used to receive the shunt control signal Demux4, the gate of switching transistor T14 is used to receive the shunt control signal Demux5, the gate of switching transistor T15 is used to receive the shunt control signal Demux6, the gate of switching transistor T16 is used to receive the shunt control signal Demux7, the gate of switching transistor T17 is used to receive the shunt control signal Demux8, and the gate of switching transistor T18 is used to receive the shunt control signal Demux9.

[0080] The fifth multiplexing unit 35 includes six switching transistors (switching transistor T19, switching transistor T20, switching transistor T21, switching transistor T22, switching transistor T23, and switching transistor T24). The first terminals of switching transistors T19, T20, T21, T22, T23, and T24 are connected to a common outgoing line to receive data signal source5. The second terminal of switching transistor T19 is connected to the fifth data signal line 25a, the second terminal of switching transistor T20 is connected to the fifth data signal line 25b, and the second terminal of switching transistor T21 is connected to the fifth data signal line 25c. The second terminal of transistor T22 is connected to the fifth data signal line 25d, the second terminal of switching transistor T23 is connected to the fifth data signal line 25e, the second terminal of switching transistor T24 is connected to the fifth data signal line 25f, the gate of switching transistor T19 is used to receive the shunt control signal Demux4, the gate of switching transistor T20 is used to receive the shunt control signal Demux5, the gate of switching transistor T21 is used to receive the shunt control signal Demux6, the gate of switching transistor T22 is used to receive the shunt control signal Demux7, the gate of switching transistor T23 is used to receive the shunt control signal Demux8, and the gate of switching transistor T24 is used to receive the shunt control signal Demux9.

[0081] In the application, the scan signals received by the sub-pixels in row A, row A+1, and row A+2 of the sub-pixel column are synchronized. For an example, please refer to [link to documentation]. Figure 6 The scan signal line 40 includes multiple scan signal lines such as scan signal line 41, scan signal line 42, scan signal line 43, scan signal line 44, scan signal line 45, and scan signal line 46. Scan signal line 41 provides scan signal scan1 for the first row of sub-pixels; scan signal line 42 provides scan signal scan2 for the second row of sub-pixels; scan signal line 43 provides scan signal scan3 for the third row of sub-pixels; scan signal line 44 provides scan signal scan4 for the fourth row of sub-pixels; scan signal line 45 provides scan signal scan5 for the fifth row of sub-pixels; scan signal line 46 provides scan signal scan6 for the sixth row of sub-pixels, and so on. Scan signals scan1, scan2, and scan3 are identical; scan signals scan4, scan5, and scan6 are identical, and so on.

[0082] In this embodiment, please refer to Figure 7The driving phase of the display panel in this application includes a fourth charging phase t5, a fifth charging phase t6, a sixth charging phase t7, a seventh charging phase t8, an eighth charging phase t9, a ninth charging phase t10, and a scanning phase t11; there is no overlap between the fourth charging phase t5, the fifth charging phase t6, the sixth charging phase t7, the seventh charging phase t8, the eighth charging phase t9, and the ninth charging phase t10, and the overlap time between the ninth charging phase t10 and the scanning phase t11 is less than a preset time threshold.

[0083] In the fourth charging stage, the third multiplexing unit 33 provides data signals to the third data signal line of the fourth sub-pixel column PL4, the fourth multiplexing unit 34 provides data signals to the fourth data signal line of the fourth sub-pixel column, and the fifth multiplexing unit 35 provides data signals to the fifth data signal line of the fourth sub-pixel column; in the fifth charging stage, the third multiplexing unit 33 provides data signals to the third data signal line of the fifth sub-pixel column PL5, the fourth multiplexing unit 34 provides data signals to the fourth data signal line of the fifth sub-pixel column PL5, and the fifth multiplexing unit 35 provides data signals to the fifth data signal line of the fifth sub-pixel column PL5; in the sixth charging stage, the third multiplexing unit 33 provides data signals to the third data signal line of the sixth sub-pixel column PL6, the fourth multiplexing unit 34 provides data signals to the fourth data signal line of the sixth sub-pixel column PL6, and the fifth multiplexing unit 35 provides data signals to the fifth data signal line of the sixth sub-pixel column PL6; in the seventh During the charging phase, the third multiplexing unit 33 provides a data signal to the third data signal line of the seventh sub-pixel column PL7, the fourth multiplexing unit 34 provides a data signal to the fourth data signal line of the seventh sub-pixel column PL7, and the fifth multiplexing unit 35 provides a data signal to the fifth data signal line of the seventh sub-pixel column PL7; during the eighth charging phase, the third multiplexing unit 33 provides a data signal to the third data signal line of the eighth sub-pixel column PL8, the fourth multiplexing unit 34 provides a data signal to the fourth data signal line of the eighth sub-pixel column PL8, and the fifth multiplexing unit 35 provides a data signal to the fifth data signal line of the eighth sub-pixel column PL8; during the ninth charging phase, the third multiplexing unit 33 provides a data signal to the third data signal line of the ninth sub-pixel column PL9, the fourth multiplexing unit 34 provides a data signal to the fourth data signal line of the ninth sub-pixel column PL9, and the fifth multiplexing unit 35 provides a data signal to the fifth data signal line of the ninth sub-pixel column PL9.

[0084] Please refer to the following: Figure 6 and Figure 7In this example, the duration of the driving phase is 3 hours. To increase the charging time of the sub-pixels, this application sets three adjacent rows of sub-pixels to charge simultaneously and receive different data signals. For example, in the fourth charging phase t5, the gates of switching transistors T7, T13, and T19 simultaneously receive a low-level shunt control signal Demux4. Under the action of the shunt control signal Demux4, switching transistors T7, T13, and T19 are turned on, thereby charging the third data signal line 23a with data signal source3, charging the fourth data signal line 24a with data signal source4, and charging the fifth data signal line 25a with data signal source5; then the fourth charging phase... At the end of t5, the fifth charging stage t6 begins. The gates of switching transistors T8, T14, and T20 simultaneously receive a low-level shunt control signal Demux5. Under the action of Demux5, switching transistors T8, T14, and T20 are turned on, thereby charging the third data signal line 23b with data signal source3, the fourth data signal line 24b with data signal source4, and the fifth data signal line 25b with data signal source5. Then, the fifth charging... Phase t6 ends, and the sixth charging phase t7 begins. The gates of switching transistors T9, T15, and T21 simultaneously receive a low-level shunt control signal Demux6. Under the action of Demux6, switching transistors T9, T15, and T21 are turned on, thereby charging data signal source3 for the third data signal line 23c, data signal source4 for the fourth data signal line 24c, and data signal source5 for the fifth data signal line 25c. Then, the sixth... After charging phase t7 ends, the seventh charging phase t8 begins. The gates of switching transistors T10, T16, and T22 simultaneously receive a low-level shunt control signal Demux7. Under the action of the shunt control signal Demux7, switching transistors T10, T16, and T22 are turned on, thereby charging the third data signal line 23d for data signal source3, charging the fourth data signal line 24d for data signal source4, and charging the fifth data signal line 25d for data signal source5.After the seventh charging stage t8 ends, the eighth charging stage t9 begins. The gates of switching transistors T11, T17, and T23 simultaneously receive a low-level shunt control signal Demux8. Under the action of Demux8, switching transistors T11, T17, and T23 are turned on, thus charging data signal source3 for the third data signal line 23e, data signal source4 for the fourth data signal line 24e, and data signal source5 for the fifth data signal line 25e. After the eighth charging stage t9 ends, the ninth charging stage t10 begins. The gates of switching transistors T12, T18, and T24 simultaneously receive a low-level shunt control signal Demux9. Under the action of Demux98, switching transistors T12, T18, and T24 are turned on, thus charging data signal source3 for the third data signal line 23f, and data signal source4 for the fourth data line 25e. Signal line 24f is charged, and data signal source5 charges the fifth data signal line 25f; during scanning phase t11, the third data signal line 23a, the fourth data signal line 24a, and the fifth data signal line 25a charge the corresponding sub-pixels in the fourth sub-pixel column PL4; the third data signal line 23b, the fourth data signal line 24b, and the fifth data signal line 25b charge the corresponding sub-pixels in the fifth sub-pixel column PL5; the third data signal line 23c, the fourth data signal line 24c, and the fifth data signal line 25c charge the sixth... The sub-pixels in sub-pixel column PL6 are charged; the third data signal line 23d, the fourth data signal line 24d, and the fifth data signal line 25d charge the sub-pixels in the seventh sub-pixel column PL7; the third data signal line 23e, the fourth data signal line 24e, and the fifth data signal line 25e charge the sub-pixels in the eighth sub-pixel column PL8; the third data signal line 23f, the fourth data signal line 24f, and the fifth data signal line 25f, along with the three signal input terminals, charge the sub-pixels in the ninth sub-pixel column PL9. Since the emission color of the ninth sub-pixel column PL9 in each pixel group is the same, all being blue, this application can ensure that at least some sub-pixel columns of the same color have the same charging method, thus ensuring the uniformity of the display panel.

[0085] Meanwhile, since the third, fourth, and fifth data signal lines of adjacent three rows of sub-pixels in the sub-pixel column are charged synchronously and receive different data signals, this application can synchronously control the circuits of adjacent three rows of pixels. For example, for the first, second, and third sub-pixels in the fourth sub-pixel column, during the fourth charging stage, the third data signal line 23a corresponding to the first row of sub-pixels in the fourth sub-pixel column PL4 receives data signal source3, the fourth data signal line 24a corresponding to the second row of sub-pixels in the fourth sub-pixel column PL4 receives data signal source4, and the fifth data signal line 25a corresponding to the third row of sub-pixels in the fourth sub-pixel column PL4 receives data signal source5. Therefore, during the scanning stage, the scanning signals scan1, scan2, and scan3 can be controlled to be low-level valid signals, so that data signals source3, source4, and source5 are simultaneously written into the first, second, and third rows of sub-pixels in the fourth sub-pixel column PL4, thereby increasing the charging time of the sub-pixels by controlling multiple rows of sub-pixels simultaneously.

[0086] It is understandable that at any given moment, the magnitudes of the data signals received at the signal input terminals of the third, fourth, and fifth multiplexing units can be different. Furthermore, at different charging stages, the magnitudes of the data signals received at the signal input terminals of the third, fourth, and fifth multiplexing units can be different.

[0087] Based on the same concept, this application also provides a display device. Figure 8 This is a schematic diagram of the structure of the display device 200 provided in the embodiments of this application, as shown below. Figure 8 As shown, the display device 200 includes the display panel 100 in any of the above embodiments. Exemplarily, as... Figure 8 As shown, the display device 200 includes a display panel 100. Therefore, the display device 200 also has the beneficial effects of the display panel 100 in the above embodiments. The similarities can be understood with reference to the explanation of the display panel 100 above, and will not be repeated below.

[0088] The display device 200 provided in this application embodiment can be a Figure 8The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet, digital camera, smart bracelet, smart glasses, vehicle display, industrial control equipment, medical display, touch interactive terminal, etc. This application embodiment does not make any special limitation in this regard.

[0089] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A display panel, characterized in that, include: Multiple pixel groups are arranged along a first direction; wherein each pixel group includes N sub-pixel columns, each pixel group includes at least one sub-pixel unit, each sub-pixel unit includes three sub-pixel columns, each sub-pixel column includes multiple light-emitting elements, the light-emitting elements in the same sub-pixel column have the same light-emitting color, and the light-emitting colors of each sub-pixel column in the sub-pixel unit are different from each other. Multiple data signal lines; wherein each sub-pixel column is connected to M data signal lines respectively, and at least some sub-pixels in the same sub-pixel column are connected to different data signal lines, N≥2, M≥2; Multiple multiplexing circuits are provided, each multiplexing circuit comprising M multiplexing units; each multiplexing unit includes one signal input terminal, N signal output terminals, and N branch control terminals; within the same multiplexing unit, each branch control terminal is used to receive different branch control signals; wherein, the i-th data signal line corresponding to each sub-pixel column in the same pixel group is connected to each signal output terminal of the i-th multiplexing unit in the corresponding multiplexing circuit, and the display panel also includes multiple fan-out lines, with the signal input terminals of each multiplexing unit connected to different fan-out lines, 1≤i≤M.

2. The display panel according to claim 1, characterized in that, The display panel also includes: Multiple scan signal lines, each scan signal line being connected to a sub-pixel row; The display panel has multiple driving stages, each driving stage including: N charging stages and a scanning stage, and there is no overlap between the charging stages; wherein, in the j-th charging stage of the N charging stages, the split control signal received by the j-th split control terminal of the multiplexing unit is at an effective level, 1≤j≤N, and in the scanning stage, the scanning signals received by the adjacent M rows of sub-pixels are all at an effective level.

3. The display panel according to claim 2, characterized in that, The emission color of the sub-pixel column corresponding to the last charging stage in each of the driving stages is the same.

4. The display panel according to claim 1, characterized in that, The multiplexing unit also includes N switching transistors, the first terminal of each switching transistor is the signal input terminal, the second terminal of each switching transistor is the signal output terminal, and the gate of each switching transistor is the branch control terminal.

5. The display panel according to claim 4, characterized in that, The pixel group includes a first sub-pixel column, a second sub-pixel column, and a third sub-pixel column; each of the multiplexing circuits includes a first multiplexing unit and a second multiplexing unit. Both the first multiplexing unit and the second multiplexing unit include three switching transistors.

6. The display panel according to claim 5, characterized in that, The first sub-pixel column, the second sub-pixel column, and the third sub-pixel column are respectively connected to two data signal lines, and are respectively the first data signal line and the second data signal line; the sub-pixels in the A-th row of the sub-pixel column are connected to the first data signal line, and the sub-pixels in the (A+1)-th row are connected to the second data signal line, where A≥1; The first data signal line corresponding to the first sub-pixel column, the first data signal line corresponding to the second sub-pixel column, and the first data signal line corresponding to the third sub-pixel column are respectively connected to the second terminals of the three switching transistors of the first multiplexing unit. The second data signal line corresponding to the first sub-pixel column, the second data signal line corresponding to the second sub-pixel column, and the second data signal line corresponding to the third sub-pixel column are respectively connected to the second terminals of the three switching transistors of the second multiplexing unit.

7. The display panel according to claim 5, characterized in that, Each sub-pixel column includes multiple light-emitting elements, and the light-emitting elements in the same sub-pixel column emit the same color. The light-emitting elements in the first sub-pixel column, the second sub-pixel column, and the third sub-pixel column emit different colors.

8. The display panel according to claim 5, characterized in that, The scan signal received by the sub-pixel in row A of the sub-pixel column is synchronized with the scan signal received by the sub-pixel in row A+1, where A≥1.

9. The display panel according to claim 6, characterized in that, The display panel has multiple driving stages, each driving stage including: a first charging stage, a second charging stage, a third charging stage and a scanning stage; wherein, the first charging stage, the second charging stage and the third charging stage do not overlap, and the overlap time between the third charging stage and the scanning stage is less than or equal to a preset time threshold.

10. The display panel according to claim 9, characterized in that, In the first charging phase, the first multiplexing unit is used to transmit data signals to the first data signal line of the first sub-pixel column, and the second multiplexing unit is used to transmit data signals to the second data signal line of the first sub-pixel column; in the second charging phase, the first multiplexing unit is used to transmit data signals to the first data signal line of the second sub-pixel column, and the second multiplexing unit is used to transmit data signals to the second data signal line of the second sub-pixel column; in the third charging phase, the first multiplexing unit is used to transmit data signals to the first data signal line of the third sub-pixel column, and the second multiplexing unit is used to transmit data signals to the second data signal line of the third sub-pixel column.

11. The display panel according to claim 4, characterized in that, Each pixel group includes a fourth sub-pixel column, a fifth sub-pixel column, a sixth sub-pixel column, a seventh sub-pixel column, an eighth sub-pixel column, and a ninth sub-pixel column; each multiplexing circuit includes a third multiplexing unit, a fourth multiplexing unit, and a fifth multiplexing unit.

12. The display panel according to claim 11, characterized in that, The third, fourth, and fifth multiplexing units each include six switching transistors.

13. The display panel according to claim 11, characterized in that, Each of the sub-pixel columns includes multiple light-emitting elements. The light-emitting elements in the same sub-pixel column have the same light-emitting color. The light-emitting elements in the fourth, fifth, and sixth sub-pixel columns have different light-emitting colors. The light-emitting elements in the fourth and seventh sub-pixel columns have the same light-emitting color. The light-emitting elements in the fifth and eighth sub-pixel columns have the same light-emitting color. The light-emitting elements in the sixth and ninth sub-pixel columns have the same light-emitting color.

14. The display panel according to claim 11, characterized in that, Each of the sub-pixel columns is connected to three data signal lines, namely the third data signal line, the fourth data signal line, and the fifth data signal line. The sub-pixels in the A-th row of the sub-pixel column are connected to the third data signal line, the sub-pixels in the A+1-th row are connected to the fourth data signal line, the sub-pixels in the A+2-th row are connected to the fourth data signal line, and A≥1; The scanning signals received by the sub-pixels in row A, row A+1, and row A+2 of the sub-pixel column are synchronized.

15. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 14.

Images